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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1039 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.291652838 Jul 21 05:03:22 PM PDT 24 Jul 21 05:03:23 PM PDT 24 14057131 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1894623472 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:21 PM PDT 24 1292789980 ps
T113 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.585741078 Jul 21 05:03:20 PM PDT 24 Jul 21 05:03:22 PM PDT 24 37037757 ps
T1040 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2687852020 Jul 21 05:03:35 PM PDT 24 Jul 21 05:03:37 PM PDT 24 162095897 ps
T1041 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1834672415 Jul 21 05:03:42 PM PDT 24 Jul 21 05:03:44 PM PDT 24 58356553 ps
T114 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.474472809 Jul 21 05:03:20 PM PDT 24 Jul 21 05:03:24 PM PDT 24 175175379 ps
T1042 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1933618527 Jul 21 05:03:45 PM PDT 24 Jul 21 05:03:47 PM PDT 24 49653526 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.479215956 Jul 21 05:03:13 PM PDT 24 Jul 21 05:03:36 PM PDT 24 8542537441 ps
T107 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1243800730 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:39 PM PDT 24 64749953 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1376802970 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:13 PM PDT 24 82639159 ps
T143 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.993730131 Jul 21 05:03:20 PM PDT 24 Jul 21 05:03:24 PM PDT 24 139265360 ps
T99 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1706879891 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:34 PM PDT 24 191137474 ps
T100 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4207369409 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:24 PM PDT 24 656112428 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1972224648 Jul 21 05:03:37 PM PDT 24 Jul 21 05:03:38 PM PDT 24 14319490 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3611792378 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:33 PM PDT 24 129972198 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3197181382 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:11 PM PDT 24 308051189 ps
T116 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2139711515 Jul 21 05:03:30 PM PDT 24 Jul 21 05:03:32 PM PDT 24 77439001 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4129460322 Jul 21 05:03:14 PM PDT 24 Jul 21 05:03:16 PM PDT 24 51081726 ps
T144 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1825555140 Jul 21 05:03:32 PM PDT 24 Jul 21 05:03:40 PM PDT 24 1357930472 ps
T162 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2868039578 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:27 PM PDT 24 413168257 ps
T1047 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3742134201 Jul 21 05:03:41 PM PDT 24 Jul 21 05:03:43 PM PDT 24 50985656 ps
T109 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2557192116 Jul 21 05:03:16 PM PDT 24 Jul 21 05:03:33 PM PDT 24 1408805207 ps
T1048 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1838569142 Jul 21 05:03:44 PM PDT 24 Jul 21 05:03:45 PM PDT 24 14649145 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4089277027 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:36 PM PDT 24 232157895 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2983438796 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:14 PM PDT 24 29072431 ps
T101 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.306798957 Jul 21 05:03:10 PM PDT 24 Jul 21 05:03:15 PM PDT 24 333166021 ps
T1051 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2573544323 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 629819644 ps
T1052 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3551896808 Jul 21 05:03:39 PM PDT 24 Jul 21 05:03:41 PM PDT 24 37251368 ps
T117 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1684309875 Jul 21 05:03:22 PM PDT 24 Jul 21 05:03:25 PM PDT 24 112573321 ps
T118 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.102834302 Jul 21 05:03:30 PM PDT 24 Jul 21 05:03:33 PM PDT 24 37301753 ps
T103 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1663665521 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:17 PM PDT 24 117271578 ps
T1053 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2902629716 Jul 21 05:03:45 PM PDT 24 Jul 21 05:03:47 PM PDT 24 17926444 ps
T104 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.801784315 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:09 PM PDT 24 557862701 ps
T119 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3696947963 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:28 PM PDT 24 2502917768 ps
T1054 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2986574472 Jul 21 05:03:40 PM PDT 24 Jul 21 05:03:42 PM PDT 24 16517887 ps
T106 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4090802306 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:23 PM PDT 24 188662032 ps
T1055 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.948483597 Jul 21 05:03:06 PM PDT 24 Jul 21 05:03:07 PM PDT 24 14813132 ps
T120 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1904671152 Jul 21 05:03:18 PM PDT 24 Jul 21 05:03:20 PM PDT 24 45586995 ps
T167 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3136231695 Jul 21 05:03:32 PM PDT 24 Jul 21 05:03:51 PM PDT 24 1143379041 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.878301636 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:28 PM PDT 24 126948948 ps
T165 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3968205639 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:46 PM PDT 24 3294233577 ps
T1057 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3850873265 Jul 21 05:03:45 PM PDT 24 Jul 21 05:03:47 PM PDT 24 14419949 ps
T1058 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4024595307 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:26 PM PDT 24 218898876 ps
T1059 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3497287728 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:12 PM PDT 24 34996370 ps
T160 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1402415351 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:24 PM PDT 24 158358447 ps
T164 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3399446631 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:40 PM PDT 24 944516163 ps
T1060 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3389983378 Jul 21 05:03:35 PM PDT 24 Jul 21 05:03:38 PM PDT 24 49468762 ps
T1061 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2480150098 Jul 21 05:03:40 PM PDT 24 Jul 21 05:03:41 PM PDT 24 74412112 ps
T1062 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2521912999 Jul 21 05:03:27 PM PDT 24 Jul 21 05:03:29 PM PDT 24 30219840 ps
T1063 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.532746948 Jul 21 05:03:28 PM PDT 24 Jul 21 05:03:31 PM PDT 24 695729364 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2050328051 Jul 21 05:03:15 PM PDT 24 Jul 21 05:03:19 PM PDT 24 337290203 ps
T121 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4164131709 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 105595615 ps
T1065 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4134323859 Jul 21 05:03:13 PM PDT 24 Jul 21 05:03:17 PM PDT 24 241392074 ps
T1066 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4006122845 Jul 21 05:03:47 PM PDT 24 Jul 21 05:03:48 PM PDT 24 167398087 ps
T1067 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.47634394 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:23 PM PDT 24 1571069522 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1876304 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 133655413 ps
T82 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.252708200 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:14 PM PDT 24 99629627 ps
T1069 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3520442791 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:28 PM PDT 24 105991404 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2176243594 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:33 PM PDT 24 15838488 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.562276061 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:37 PM PDT 24 1301196385 ps
T83 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2377410658 Jul 21 05:03:04 PM PDT 24 Jul 21 05:03:06 PM PDT 24 373643593 ps
T1072 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2004380560 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:22 PM PDT 24 15372502 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.609003333 Jul 21 05:03:28 PM PDT 24 Jul 21 05:03:32 PM PDT 24 125043048 ps
T122 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2270642621 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:40 PM PDT 24 150316248 ps
T166 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3832932667 Jul 21 05:03:27 PM PDT 24 Jul 21 05:03:47 PM PDT 24 1064397973 ps
T102 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3487238645 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:17 PM PDT 24 2614853992 ps
T1074 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.541434467 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:06 PM PDT 24 12129404 ps
T123 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.31950133 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:15 PM PDT 24 158026157 ps
T1075 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1386745668 Jul 21 05:03:34 PM PDT 24 Jul 21 05:03:37 PM PDT 24 49398267 ps
T1076 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3852075512 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:33 PM PDT 24 43385856 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2658887243 Jul 21 05:03:30 PM PDT 24 Jul 21 05:03:33 PM PDT 24 86511030 ps
T163 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.168212818 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:40 PM PDT 24 4871465669 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.559349353 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:16 PM PDT 24 128404052 ps
T1079 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2870190271 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:23 PM PDT 24 248200230 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2912218790 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:25 PM PDT 24 1355495071 ps
T1081 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1662018009 Jul 21 05:03:34 PM PDT 24 Jul 21 05:03:35 PM PDT 24 32140754 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1845861857 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:15 PM PDT 24 81947042 ps
T105 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.427523657 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:34 PM PDT 24 136347922 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3750692519 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:13 PM PDT 24 22354338 ps
T1084 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2403803482 Jul 21 05:03:06 PM PDT 24 Jul 21 05:03:48 PM PDT 24 3481197464 ps
T1085 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1563150413 Jul 21 05:03:13 PM PDT 24 Jul 21 05:03:29 PM PDT 24 744629437 ps
T1086 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2659021033 Jul 21 05:03:28 PM PDT 24 Jul 21 05:03:30 PM PDT 24 90167971 ps
T1087 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3641644850 Jul 21 05:03:20 PM PDT 24 Jul 21 05:03:25 PM PDT 24 303134799 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.271723251 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:28 PM PDT 24 616134174 ps
T1089 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.645743503 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:40 PM PDT 24 163763085 ps
T1090 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4018067323 Jul 21 05:03:41 PM PDT 24 Jul 21 05:03:42 PM PDT 24 18631497 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1228199678 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:14 PM PDT 24 408100702 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1309384258 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:14 PM PDT 24 189665980 ps
T1093 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.689601647 Jul 21 05:03:20 PM PDT 24 Jul 21 05:03:22 PM PDT 24 179588276 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1292473973 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:14 PM PDT 24 90115316 ps
T1095 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1407905433 Jul 21 05:03:41 PM PDT 24 Jul 21 05:03:42 PM PDT 24 32156890 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2182110342 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:27 PM PDT 24 1452236592 ps
T1097 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3421218378 Jul 21 05:03:39 PM PDT 24 Jul 21 05:03:40 PM PDT 24 13056033 ps
T1098 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2347806174 Jul 21 05:03:37 PM PDT 24 Jul 21 05:03:38 PM PDT 24 78572672 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2571146885 Jul 21 05:03:30 PM PDT 24 Jul 21 05:03:33 PM PDT 24 101339334 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3767020287 Jul 21 05:03:28 PM PDT 24 Jul 21 05:03:30 PM PDT 24 828066206 ps
T1101 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2134207773 Jul 21 05:03:29 PM PDT 24 Jul 21 05:03:34 PM PDT 24 364855367 ps
T1102 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1646678368 Jul 21 05:03:40 PM PDT 24 Jul 21 05:03:41 PM PDT 24 53779743 ps
T161 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1404621601 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:35 PM PDT 24 488989123 ps
T169 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3447052767 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:14 PM PDT 24 3236401479 ps
T1103 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.918966911 Jul 21 05:03:41 PM PDT 24 Jul 21 05:03:42 PM PDT 24 43642913 ps
T1104 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.944578398 Jul 21 05:03:46 PM PDT 24 Jul 21 05:03:48 PM PDT 24 16418449 ps
T1105 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1980729996 Jul 21 05:03:14 PM PDT 24 Jul 21 05:03:19 PM PDT 24 307930661 ps
T1106 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2882749481 Jul 21 05:03:27 PM PDT 24 Jul 21 05:03:29 PM PDT 24 24012069 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1377678301 Jul 21 05:03:15 PM PDT 24 Jul 21 05:03:16 PM PDT 24 31268686 ps
T1108 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3833679523 Jul 21 05:03:33 PM PDT 24 Jul 21 05:03:37 PM PDT 24 99234241 ps
T1109 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3415731719 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:53 PM PDT 24 722181804 ps
T1110 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3089237102 Jul 21 05:03:18 PM PDT 24 Jul 21 05:03:40 PM PDT 24 819312383 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1626280390 Jul 21 05:03:13 PM PDT 24 Jul 21 05:03:31 PM PDT 24 2711891977 ps
T168 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.442387943 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:51 PM PDT 24 8501325003 ps
T1112 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1590814387 Jul 21 05:03:45 PM PDT 24 Jul 21 05:03:47 PM PDT 24 37732734 ps
T1113 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.621590403 Jul 21 05:03:10 PM PDT 24 Jul 21 05:03:11 PM PDT 24 63605247 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3297636074 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:48 PM PDT 24 7454345754 ps
T1115 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2188661191 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:23 PM PDT 24 12728778 ps
T1116 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1564900103 Jul 21 05:03:46 PM PDT 24 Jul 21 05:03:48 PM PDT 24 60333507 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3192566737 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:26 PM PDT 24 1374930292 ps
T1118 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1274261681 Jul 21 05:03:07 PM PDT 24 Jul 21 05:03:09 PM PDT 24 24056374 ps
T1119 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2728305706 Jul 21 05:03:44 PM PDT 24 Jul 21 05:03:45 PM PDT 24 58040391 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.869906704 Jul 21 05:03:14 PM PDT 24 Jul 21 05:03:16 PM PDT 24 42148610 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.102019487 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:15 PM PDT 24 84881572 ps
T1122 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3422913437 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:09 PM PDT 24 121323663 ps
T1123 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.526669376 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 428064156 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3766580589 Jul 21 05:03:04 PM PDT 24 Jul 21 05:03:08 PM PDT 24 116727351 ps
T1125 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3859495472 Jul 21 05:03:40 PM PDT 24 Jul 21 05:03:41 PM PDT 24 15783454 ps
T84 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.404443290 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:14 PM PDT 24 294001465 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.150180937 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:17 PM PDT 24 606672203 ps
T1127 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.618084218 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:36 PM PDT 24 2573652718 ps
T1128 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.655750434 Jul 21 05:03:32 PM PDT 24 Jul 21 05:03:33 PM PDT 24 25682036 ps
T1129 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1125596104 Jul 21 05:03:38 PM PDT 24 Jul 21 05:03:40 PM PDT 24 33116207 ps
T1130 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3118329466 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:32 PM PDT 24 111243402 ps
T1131 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2101541025 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:35 PM PDT 24 78156030 ps
T1132 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3076407897 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:39 PM PDT 24 6234103991 ps
T1133 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1872354787 Jul 21 05:03:23 PM PDT 24 Jul 21 05:03:25 PM PDT 24 60578811 ps
T1134 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1474146472 Jul 21 05:03:27 PM PDT 24 Jul 21 05:03:29 PM PDT 24 32747248 ps
T1135 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1131354861 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:36 PM PDT 24 1576162634 ps
T1136 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2670066979 Jul 21 05:03:29 PM PDT 24 Jul 21 05:03:50 PM PDT 24 811637173 ps
T1137 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.513394858 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:34 PM PDT 24 68717629 ps
T1138 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3963182218 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 92974746 ps
T1139 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2662658009 Jul 21 05:03:44 PM PDT 24 Jul 21 05:03:45 PM PDT 24 29574760 ps
T1140 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2484790842 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:37 PM PDT 24 13039325 ps
T1141 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3585854679 Jul 21 05:03:36 PM PDT 24 Jul 21 05:03:42 PM PDT 24 110706897 ps
T1142 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1135282832 Jul 21 05:03:45 PM PDT 24 Jul 21 05:03:47 PM PDT 24 17767571 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3682450815 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:13 PM PDT 24 37809749 ps
T1144 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3133052867 Jul 21 05:03:12 PM PDT 24 Jul 21 05:03:15 PM PDT 24 26822518 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.989019333 Jul 21 05:03:11 PM PDT 24 Jul 21 05:03:52 PM PDT 24 11253750711 ps
T1146 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2700382994 Jul 21 05:03:05 PM PDT 24 Jul 21 05:03:08 PM PDT 24 109110685 ps
T1147 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.407022283 Jul 21 05:03:21 PM PDT 24 Jul 21 05:03:23 PM PDT 24 13747955 ps
T1148 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2685528302 Jul 21 05:03:14 PM PDT 24 Jul 21 05:03:18 PM PDT 24 129019880 ps
T1149 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3665908703 Jul 21 05:03:31 PM PDT 24 Jul 21 05:03:34 PM PDT 24 132933115 ps
T1150 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2202206848 Jul 21 05:03:19 PM PDT 24 Jul 21 05:03:21 PM PDT 24 27735603 ps
T1151 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2068492491 Jul 21 05:03:26 PM PDT 24 Jul 21 05:03:29 PM PDT 24 109405078 ps

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1159613721
Short name T2
Test name
Test status
Simulation time 159786773 ps
CPU time 3.45 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 233192 kb
Host smart-f976e14a-90f5-48f0-bfe9-7a161babe90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159613721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1159613721
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2017058003
Short name T12
Test name
Test status
Simulation time 7050309093 ps
CPU time 105.19 seconds
Started Jul 21 07:05:13 PM PDT 24
Finished Jul 21 07:06:58 PM PDT 24
Peak memory 249932 kb
Host smart-3f1d1108-0fdd-4413-823d-c8fd363c32c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017058003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2017058003
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.31554977
Short name T28
Test name
Test status
Simulation time 47918857878 ps
CPU time 300.11 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:10:03 PM PDT 24
Peak memory 269004 kb
Host smart-4d85e160-a45c-4c62-8866-7aed61162ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31554977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.31554977
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.184509258
Short name T20
Test name
Test status
Simulation time 45119475719 ps
CPU time 444.43 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:12:27 PM PDT 24
Peak memory 270052 kb
Host smart-6a085927-a733-4e96-bfde-6aa2e40b7555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184509258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.184509258
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1727781124
Short name T95
Test name
Test status
Simulation time 327951453 ps
CPU time 3.79 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 217840 kb
Host smart-fe3562cf-d722-40ce-87d1-c2fa518e777f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727781124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1727781124
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3684595144
Short name T196
Test name
Test status
Simulation time 673806897880 ps
CPU time 1597.19 seconds
Started Jul 21 07:03:23 PM PDT 24
Finished Jul 21 07:30:01 PM PDT 24
Peak memory 298944 kb
Host smart-b5821bf8-152e-4282-9106-9d5bdbcbdaa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684595144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3684595144
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1786086609
Short name T66
Test name
Test status
Simulation time 16966856 ps
CPU time 0.74 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:15 PM PDT 24
Peak memory 216504 kb
Host smart-af9acf5a-99e6-4ed4-a421-456b6ebd3187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786086609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1786086609
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2791015319
Short name T80
Test name
Test status
Simulation time 41132518814 ps
CPU time 195.3 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:08:52 PM PDT 24
Peak memory 289624 kb
Host smart-08751412-e9f5-4869-a414-f61a009bb6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791015319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2791015319
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1045963043
Short name T23
Test name
Test status
Simulation time 12116555 ps
CPU time 0.72 seconds
Started Jul 21 07:04:31 PM PDT 24
Finished Jul 21 07:04:32 PM PDT 24
Peak memory 205760 kb
Host smart-0ee2dc86-cd00-4091-9e8e-03dd26553d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045963043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1045963043
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2692765335
Short name T31
Test name
Test status
Simulation time 28983244832 ps
CPU time 257.04 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:08:11 PM PDT 24
Peak memory 266064 kb
Host smart-89b5dba8-2ef7-4b86-8514-bf08ffaa54a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692765335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2692765335
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4140183235
Short name T94
Test name
Test status
Simulation time 568550967 ps
CPU time 15.9 seconds
Started Jul 21 05:03:28 PM PDT 24
Finished Jul 21 05:03:44 PM PDT 24
Peak memory 215896 kb
Host smart-0e267056-5b8e-487e-a976-4a720ea48ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140183235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4140183235
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.26358026
Short name T179
Test name
Test status
Simulation time 80478339068 ps
CPU time 713.79 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:15:49 PM PDT 24
Peak memory 274312 kb
Host smart-f9b5784c-3985-4f0e-93ed-54a958e19744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26358026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.26358026
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1390012070
Short name T26
Test name
Test status
Simulation time 5630526989 ps
CPU time 12.95 seconds
Started Jul 21 07:05:21 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 233232 kb
Host smart-762b74b8-8f58-439c-b239-09f22dc629f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390012070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1390012070
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.404025315
Short name T199
Test name
Test status
Simulation time 104197357747 ps
CPU time 526.93 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:12:40 PM PDT 24
Peak memory 269056 kb
Host smart-b38279fe-e711-462f-971d-b57814ffd3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404025315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.404025315
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2720492874
Short name T128
Test name
Test status
Simulation time 280929848715 ps
CPU time 640.97 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:16:14 PM PDT 24
Peak memory 256560 kb
Host smart-afc1f5db-09bd-4076-ba9a-27359f532ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720492874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2720492874
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.995350647
Short name T171
Test name
Test status
Simulation time 55820128827 ps
CPU time 392.76 seconds
Started Jul 21 07:05:42 PM PDT 24
Finished Jul 21 07:12:16 PM PDT 24
Peak memory 266076 kb
Host smart-b15b6c21-4a2b-45df-8f27-43f21dccde6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995350647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.995350647
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3790770363
Short name T21
Test name
Test status
Simulation time 199912437522 ps
CPU time 424.79 seconds
Started Jul 21 07:05:04 PM PDT 24
Finished Jul 21 07:12:09 PM PDT 24
Peak memory 255020 kb
Host smart-c7d66292-fbef-4e8d-990a-30e5cd8a3100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790770363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3790770363
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.306798957
Short name T101
Test name
Test status
Simulation time 333166021 ps
CPU time 4.64 seconds
Started Jul 21 05:03:10 PM PDT 24
Finished Jul 21 05:03:15 PM PDT 24
Peak memory 216220 kb
Host smart-9ef335ee-4b9d-4cfc-8622-ad8b499939f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306798957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.306798957
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2139711515
Short name T116
Test name
Test status
Simulation time 77439001 ps
CPU time 2.2 seconds
Started Jul 21 05:03:30 PM PDT 24
Finished Jul 21 05:03:32 PM PDT 24
Peak memory 215880 kb
Host smart-74fa4492-70c0-4e53-95b0-8a92cfddbf44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139711515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2139711515
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.279387994
Short name T36
Test name
Test status
Simulation time 22338514 ps
CPU time 1.04 seconds
Started Jul 21 07:03:21 PM PDT 24
Finished Jul 21 07:03:23 PM PDT 24
Peak memory 217152 kb
Host smart-eaba4432-f890-4048-a43c-b7a7967417af
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279387994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.279387994
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3684457662
Short name T35
Test name
Test status
Simulation time 4458549373 ps
CPU time 103.83 seconds
Started Jul 21 07:05:39 PM PDT 24
Finished Jul 21 07:07:25 PM PDT 24
Peak memory 265400 kb
Host smart-e114b9fd-d84d-424a-87da-8a34f35b5d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684457662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3684457662
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2269344154
Short name T70
Test name
Test status
Simulation time 482353783 ps
CPU time 1.31 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 235804 kb
Host smart-0d492222-2bf6-489c-9a7a-34f6fe02c5e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269344154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2269344154
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3488176022
Short name T201
Test name
Test status
Simulation time 40424187377 ps
CPU time 135.26 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:07:49 PM PDT 24
Peak memory 265576 kb
Host smart-4b93ce59-a5c3-45eb-bf2a-68cd77b52e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488176022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3488176022
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.256561991
Short name T170
Test name
Test status
Simulation time 55784218523 ps
CPU time 398.95 seconds
Started Jul 21 07:04:03 PM PDT 24
Finished Jul 21 07:10:43 PM PDT 24
Peak memory 262676 kb
Host smart-ba49370a-e0b2-4083-a754-08b072386996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256561991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.256561991
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2239534778
Short name T79
Test name
Test status
Simulation time 30471213712 ps
CPU time 206.54 seconds
Started Jul 21 07:04:50 PM PDT 24
Finished Jul 21 07:08:17 PM PDT 24
Peak memory 257308 kb
Host smart-43b2089e-86c8-44e6-a22f-07319deb1add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239534778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2239534778
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.525782484
Short name T223
Test name
Test status
Simulation time 16391420633 ps
CPU time 115.04 seconds
Started Jul 21 07:05:00 PM PDT 24
Finished Jul 21 07:06:56 PM PDT 24
Peak memory 260984 kb
Host smart-c5ecf42a-3c77-424c-bc39-c758e440a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525782484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.525782484
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1511048199
Short name T51
Test name
Test status
Simulation time 12604125723 ps
CPU time 104.3 seconds
Started Jul 21 07:04:31 PM PDT 24
Finished Jul 21 07:06:15 PM PDT 24
Peak memory 234008 kb
Host smart-7288fa8b-0e69-48a9-b4f1-c3995a116c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511048199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1511048199
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.442387943
Short name T168
Test name
Test status
Simulation time 8501325003 ps
CPU time 24.63 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:51 PM PDT 24
Peak memory 216008 kb
Host smart-e56550c8-8ad0-435b-af14-086b28879b33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442387943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.442387943
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2955223563
Short name T175
Test name
Test status
Simulation time 28063427258 ps
CPU time 144.41 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 265288 kb
Host smart-91852a6b-0c1e-44fe-baff-9228c1345fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955223563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2955223563
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2200780578
Short name T158
Test name
Test status
Simulation time 79272161102 ps
CPU time 284.63 seconds
Started Jul 21 07:04:56 PM PDT 24
Finished Jul 21 07:09:42 PM PDT 24
Peak memory 254240 kb
Host smart-296ff120-5165-4c3c-b67b-1c582d158441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200780578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2200780578
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1808525078
Short name T8
Test name
Test status
Simulation time 843366808 ps
CPU time 4.07 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:32 PM PDT 24
Peak memory 224916 kb
Host smart-ec0008b2-a847-4da5-84c6-38555b040f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808525078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1808525078
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3205894867
Short name T140
Test name
Test status
Simulation time 19792121290 ps
CPU time 55.46 seconds
Started Jul 21 07:03:12 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 250880 kb
Host smart-74d0a1fa-b6e1-40cf-9744-debf34f86766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205894867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3205894867
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.641412073
Short name T275
Test name
Test status
Simulation time 74691168781 ps
CPU time 411.65 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:10:54 PM PDT 24
Peak memory 256020 kb
Host smart-7f31d7eb-054f-454d-9f3a-10aa0d23f4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641412073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.641412073
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3157079438
Short name T268
Test name
Test status
Simulation time 18258147477 ps
CPU time 146.54 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:06:05 PM PDT 24
Peak memory 257884 kb
Host smart-559289ea-2c3b-4601-a4ed-ce48a324512f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157079438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3157079438
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1404621601
Short name T161
Test name
Test status
Simulation time 488989123 ps
CPU time 3.37 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:35 PM PDT 24
Peak memory 216252 kb
Host smart-15ab122b-0016-4939-9757-64eca1cbc040
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404621601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1404621601
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3154009108
Short name T9
Test name
Test status
Simulation time 48365789 ps
CPU time 0.82 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 206100 kb
Host smart-b49b2ae3-c753-4a64-871c-8331041f1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154009108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3154009108
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2989149950
Short name T129
Test name
Test status
Simulation time 11814824340 ps
CPU time 187.79 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:07:06 PM PDT 24
Peak memory 270424 kb
Host smart-710c75c5-ff8f-4a10-a2c1-04e706cc5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989149950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2989149950
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2661296400
Short name T881
Test name
Test status
Simulation time 576272204762 ps
CPU time 390.51 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:10:06 PM PDT 24
Peak memory 266148 kb
Host smart-7b76a6aa-73fd-47af-878d-2bb18d051878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661296400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2661296400
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2722177499
Short name T278
Test name
Test status
Simulation time 309240633 ps
CPU time 11.57 seconds
Started Jul 21 07:05:37 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 249500 kb
Host smart-a8357c8c-ea28-467d-97b6-883fbb57624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722177499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2722177499
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.4174209467
Short name T89
Test name
Test status
Simulation time 73474251 ps
CPU time 2.89 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:33 PM PDT 24
Peak memory 233128 kb
Host smart-a6319bec-8149-4e57-97ba-2ffe7f1bc299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174209467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.4174209467
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.673660833
Short name T182
Test name
Test status
Simulation time 41679453892 ps
CPU time 144.45 seconds
Started Jul 21 07:04:00 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 259484 kb
Host smart-25843a25-2210-43df-9398-fc77dbc0739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673660833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.673660833
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3702516751
Short name T272
Test name
Test status
Simulation time 36008282132 ps
CPU time 356.86 seconds
Started Jul 21 07:04:16 PM PDT 24
Finished Jul 21 07:10:13 PM PDT 24
Peak memory 255492 kb
Host smart-6e3dc774-fa37-49d0-87f9-1f11d38e33b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702516751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3702516751
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4190101704
Short name T234
Test name
Test status
Simulation time 256300467 ps
CPU time 4.22 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:54 PM PDT 24
Peak memory 233072 kb
Host smart-d1875289-40a2-42e9-9c32-0dabd04e672e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190101704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4190101704
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2377410658
Short name T83
Test name
Test status
Simulation time 373643593 ps
CPU time 1.36 seconds
Started Jul 21 05:03:04 PM PDT 24
Finished Jul 21 05:03:06 PM PDT 24
Peak memory 207620 kb
Host smart-adbe53d3-d49b-44d3-8060-a1ac82229d20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377410658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2377410658
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.801784315
Short name T104
Test name
Test status
Simulation time 557862701 ps
CPU time 3.84 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:09 PM PDT 24
Peak memory 216192 kb
Host smart-0590f70c-7088-43df-8d80-b4adf6a9b1a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801784315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.801784315
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1228199678
Short name T1091
Test name
Test status
Simulation time 408100702 ps
CPU time 8.09 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 215924 kb
Host smart-d40ae8e0-fe3f-4b26-add4-52ebc11339f4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228199678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1228199678
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2403803482
Short name T1084
Test name
Test status
Simulation time 3481197464 ps
CPU time 41.06 seconds
Started Jul 21 05:03:06 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 207696 kb
Host smart-8e7d3b86-429a-40ed-b644-fc84dee54a03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403803482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2403803482
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3766580589
Short name T1124
Test name
Test status
Simulation time 116727351 ps
CPU time 3.05 seconds
Started Jul 21 05:03:04 PM PDT 24
Finished Jul 21 05:03:08 PM PDT 24
Peak memory 217396 kb
Host smart-e6eb84c4-760e-4c38-8df4-25739857553a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766580589 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3766580589
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4258012773
Short name T1032
Test name
Test status
Simulation time 41038940 ps
CPU time 1.68 seconds
Started Jul 21 05:03:04 PM PDT 24
Finished Jul 21 05:03:07 PM PDT 24
Peak memory 215996 kb
Host smart-76d8f663-36a8-409e-8c9e-58da803e5c55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258012773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
258012773
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.948483597
Short name T1055
Test name
Test status
Simulation time 14813132 ps
CPU time 0.83 seconds
Started Jul 21 05:03:06 PM PDT 24
Finished Jul 21 05:03:07 PM PDT 24
Peak memory 204224 kb
Host smart-4e7c6aea-ecff-4fac-8879-f668a6815ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948483597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.948483597
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2700382994
Short name T1146
Test name
Test status
Simulation time 109110685 ps
CPU time 2.12 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:08 PM PDT 24
Peak memory 215852 kb
Host smart-3e5e0516-5ad2-434f-9663-25dbc4974221
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700382994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2700382994
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3858253665
Short name T1033
Test name
Test status
Simulation time 28640141 ps
CPU time 0.67 seconds
Started Jul 21 05:03:06 PM PDT 24
Finished Jul 21 05:03:07 PM PDT 24
Peak memory 204660 kb
Host smart-ca8cec4a-1ecb-401f-bc9b-fefecaed10a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858253665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3858253665
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3197181382
Short name T1045
Test name
Test status
Simulation time 308051189 ps
CPU time 4.37 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:11 PM PDT 24
Peak memory 215968 kb
Host smart-c6de2d97-1898-457c-bf78-f7305a1e41e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197181382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3197181382
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3192566737
Short name T1117
Test name
Test status
Simulation time 1374930292 ps
CPU time 19.46 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:26 PM PDT 24
Peak memory 223968 kb
Host smart-05055ea3-ed86-4485-be8e-b791f50a1ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192566737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3192566737
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.479215956
Short name T115
Test name
Test status
Simulation time 8542537441 ps
CPU time 21.8 seconds
Started Jul 21 05:03:13 PM PDT 24
Finished Jul 21 05:03:36 PM PDT 24
Peak memory 215912 kb
Host smart-05ef14ce-510a-4769-bc57-03a145b84669
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479215956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.479215956
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.562276061
Short name T1071
Test name
Test status
Simulation time 1301196385 ps
CPU time 23.7 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 207724 kb
Host smart-25864f0a-2869-4968-800c-eb55734fd77b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562276061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.562276061
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1854788695
Short name T81
Test name
Test status
Simulation time 13814607 ps
CPU time 0.97 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:12 PM PDT 24
Peak memory 207532 kb
Host smart-722e71dc-634d-4180-8fb9-f9654fc11bf7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854788695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1854788695
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2050328051
Short name T1064
Test name
Test status
Simulation time 337290203 ps
CPU time 4.03 seconds
Started Jul 21 05:03:15 PM PDT 24
Finished Jul 21 05:03:19 PM PDT 24
Peak memory 219200 kb
Host smart-3f6f4b26-9fe5-45dc-a3b9-2663c7e7d070
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050328051 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2050328051
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1292473973
Short name T1094
Test name
Test status
Simulation time 90115316 ps
CPU time 1.95 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 215892 kb
Host smart-9480ab31-4fc7-48c1-b822-2fdd39823ace
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292473973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
292473973
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3200799032
Short name T1038
Test name
Test status
Simulation time 19646680 ps
CPU time 0.8 seconds
Started Jul 21 05:03:03 PM PDT 24
Finished Jul 21 05:03:04 PM PDT 24
Peak memory 204304 kb
Host smart-71651ed2-112c-48cb-8eb4-923f68e5ce1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200799032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
200799032
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1274261681
Short name T1118
Test name
Test status
Simulation time 24056374 ps
CPU time 1.72 seconds
Started Jul 21 05:03:07 PM PDT 24
Finished Jul 21 05:03:09 PM PDT 24
Peak memory 215900 kb
Host smart-4cd53057-5ae4-4a51-9298-9f3131b2d9e3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274261681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1274261681
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.541434467
Short name T1074
Test name
Test status
Simulation time 12129404 ps
CPU time 0.69 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:06 PM PDT 24
Peak memory 204264 kb
Host smart-101b4c41-f233-4d9f-b72e-c61af86ec24c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541434467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.541434467
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4134323859
Short name T1065
Test name
Test status
Simulation time 241392074 ps
CPU time 3.21 seconds
Started Jul 21 05:03:13 PM PDT 24
Finished Jul 21 05:03:17 PM PDT 24
Peak memory 215896 kb
Host smart-3f3cd27a-40c8-4a2b-8574-a430288e8540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134323859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4134323859
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3422913437
Short name T1122
Test name
Test status
Simulation time 121323663 ps
CPU time 3.42 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:09 PM PDT 24
Peak memory 216196 kb
Host smart-291271fb-879e-4b38-a100-1a61f368155e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422913437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
422913437
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3447052767
Short name T169
Test name
Test status
Simulation time 3236401479 ps
CPU time 8.66 seconds
Started Jul 21 05:03:05 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 215920 kb
Host smart-84b179e9-5cc5-4a58-a0e2-e43fe639347d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447052767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3447052767
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3767020287
Short name T1100
Test name
Test status
Simulation time 828066206 ps
CPU time 1.96 seconds
Started Jul 21 05:03:28 PM PDT 24
Finished Jul 21 05:03:30 PM PDT 24
Peak memory 215948 kb
Host smart-19d56a38-c55f-40ae-b640-59ffa055d952
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767020287 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3767020287
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2870190271
Short name T1079
Test name
Test status
Simulation time 248200230 ps
CPU time 1.9 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 215964 kb
Host smart-0c159c13-cb29-45ab-808a-d9133edc0301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870190271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2870190271
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.291652838
Short name T1039
Test name
Test status
Simulation time 14057131 ps
CPU time 0.74 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 204604 kb
Host smart-60d42618-4362-439a-b0b0-59906c15ff44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291652838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.291652838
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2573544323
Short name T1051
Test name
Test status
Simulation time 629819644 ps
CPU time 2.63 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 215884 kb
Host smart-c24deac9-98c8-4b2b-9dab-c2e9d10fc60d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573544323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2573544323
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4207369409
Short name T100
Test name
Test status
Simulation time 656112428 ps
CPU time 4.44 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 216240 kb
Host smart-a0dcb375-e319-41b9-b54a-db7d5edec23d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207369409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4207369409
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2182110342
Short name T1096
Test name
Test status
Simulation time 1452236592 ps
CPU time 8.2 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:27 PM PDT 24
Peak memory 215996 kb
Host smart-c78ba75c-689a-42d7-b556-b79c7875d033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182110342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2182110342
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2659021033
Short name T1086
Test name
Test status
Simulation time 90167971 ps
CPU time 1.69 seconds
Started Jul 21 05:03:28 PM PDT 24
Finished Jul 21 05:03:30 PM PDT 24
Peak memory 216036 kb
Host smart-4b85942f-9892-4051-8886-37c9f32194ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659021033 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2659021033
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1474146472
Short name T1134
Test name
Test status
Simulation time 32747248 ps
CPU time 0.76 seconds
Started Jul 21 05:03:27 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 204368 kb
Host smart-cf211422-10f8-4be6-9896-9b2f37ea0752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474146472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1474146472
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3389983378
Short name T1060
Test name
Test status
Simulation time 49468762 ps
CPU time 1.79 seconds
Started Jul 21 05:03:35 PM PDT 24
Finished Jul 21 05:03:38 PM PDT 24
Peak memory 215800 kb
Host smart-cbcf1915-8245-4e2a-af2a-d597f0fd5d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389983378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3389983378
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.878301636
Short name T1056
Test name
Test status
Simulation time 126948948 ps
CPU time 1.7 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:28 PM PDT 24
Peak memory 216200 kb
Host smart-5f5734e2-c071-48ed-962a-ff3e96467424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878301636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.878301636
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2382372685
Short name T93
Test name
Test status
Simulation time 240860551 ps
CPU time 7.13 seconds
Started Jul 21 05:03:32 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 215816 kb
Host smart-4560161e-2118-4354-b0d9-90f3e32caaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382372685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2382372685
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3520442791
Short name T1069
Test name
Test status
Simulation time 105991404 ps
CPU time 1.72 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:28 PM PDT 24
Peak memory 215912 kb
Host smart-0115a726-31cd-4359-b702-cbe69242bc8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520442791 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3520442791
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2571146885
Short name T1099
Test name
Test status
Simulation time 101339334 ps
CPU time 2.74 seconds
Started Jul 21 05:03:30 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215912 kb
Host smart-eda3534e-0194-4f55-9be7-f006f6494320
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571146885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2571146885
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3118329466
Short name T1130
Test name
Test status
Simulation time 111243402 ps
CPU time 0.73 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:32 PM PDT 24
Peak memory 204172 kb
Host smart-1f30f44e-0acb-4432-b817-2d6f31600abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118329466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3118329466
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.532746948
Short name T1063
Test name
Test status
Simulation time 695729364 ps
CPU time 2.08 seconds
Started Jul 21 05:03:28 PM PDT 24
Finished Jul 21 05:03:31 PM PDT 24
Peak memory 215960 kb
Host smart-01d2abe7-463d-4aff-abfe-16e84199668d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532746948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.532746948
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3963182218
Short name T1138
Test name
Test status
Simulation time 92974746 ps
CPU time 3.16 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 216192 kb
Host smart-f9849d6f-ecfb-4a08-9bcf-008f9fb18155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963182218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3963182218
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2882749481
Short name T1106
Test name
Test status
Simulation time 24012069 ps
CPU time 1.55 seconds
Started Jul 21 05:03:27 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 215984 kb
Host smart-84e66c7f-f05b-4714-9e95-9d1ab6dfe8ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882749481 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2882749481
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3611792378
Short name T1044
Test name
Test status
Simulation time 129972198 ps
CPU time 1.93 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215004 kb
Host smart-09403a06-8335-4542-8c77-e95fd0db658f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611792378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3611792378
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2484790842
Short name T1140
Test name
Test status
Simulation time 13039325 ps
CPU time 0.7 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 204312 kb
Host smart-0b75c136-c7fc-43d0-991f-c4732c95e623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484790842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2484790842
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2068492491
Short name T1151
Test name
Test status
Simulation time 109405078 ps
CPU time 1.95 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 215820 kb
Host smart-2798e677-0218-4b81-8a68-a71ebd635e35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068492491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2068492491
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1706879891
Short name T99
Test name
Test status
Simulation time 191137474 ps
CPU time 2.56 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:34 PM PDT 24
Peak memory 216080 kb
Host smart-4059b096-e850-4ce3-8957-89786421477b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706879891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1706879891
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1825555140
Short name T144
Test name
Test status
Simulation time 1357930472 ps
CPU time 7.31 seconds
Started Jul 21 05:03:32 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 216024 kb
Host smart-0db66f4d-407b-4661-9604-0b3ea65fbc8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825555140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1825555140
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1876304
Short name T1068
Test name
Test status
Simulation time 133655413 ps
CPU time 2.62 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 218520 kb
Host smart-5a540120-4aae-47b0-9aa3-9996db30f270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876304 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1876304
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2687852020
Short name T1040
Test name
Test status
Simulation time 162095897 ps
CPU time 1.33 seconds
Started Jul 21 05:03:35 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 215764 kb
Host smart-a49a0fdb-f5b6-4610-8175-e09fb0c14bd8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687852020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2687852020
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1905050294
Short name T1037
Test name
Test status
Simulation time 122256790 ps
CPU time 0.7 seconds
Started Jul 21 05:03:27 PM PDT 24
Finished Jul 21 05:03:28 PM PDT 24
Peak memory 204436 kb
Host smart-b799ab83-d227-4bfd-aaf5-6cf5e90bc140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905050294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1905050294
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4089277027
Short name T1049
Test name
Test status
Simulation time 232157895 ps
CPU time 3.97 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:36 PM PDT 24
Peak memory 215148 kb
Host smart-71444286-c2fd-47ca-8f2a-ba8b578d6d1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089277027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4089277027
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2101541025
Short name T1131
Test name
Test status
Simulation time 78156030 ps
CPU time 2.99 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:35 PM PDT 24
Peak memory 216044 kb
Host smart-c432412b-8a2a-4c7f-9623-17433bf00c48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101541025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2101541025
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.609003333
Short name T1073
Test name
Test status
Simulation time 125043048 ps
CPU time 3.73 seconds
Started Jul 21 05:03:28 PM PDT 24
Finished Jul 21 05:03:32 PM PDT 24
Peak memory 218136 kb
Host smart-31e51541-e82b-4b56-90dd-79b029ce0843
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609003333 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.609003333
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4164131709
Short name T121
Test name
Test status
Simulation time 105595615 ps
CPU time 2.64 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 216052 kb
Host smart-339f93d2-6571-4c98-ab7e-552e6f26ef1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164131709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4164131709
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3852075512
Short name T1076
Test name
Test status
Simulation time 43385856 ps
CPU time 0.68 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 204408 kb
Host smart-ab8684b8-9553-4d4a-a372-35a5e52150da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852075512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3852075512
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2521912999
Short name T1062
Test name
Test status
Simulation time 30219840 ps
CPU time 1.78 seconds
Started Jul 21 05:03:27 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 207684 kb
Host smart-3e06d5de-5dfa-4a73-998c-d8589dd164a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521912999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2521912999
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2134207773
Short name T1101
Test name
Test status
Simulation time 364855367 ps
CPU time 4.25 seconds
Started Jul 21 05:03:29 PM PDT 24
Finished Jul 21 05:03:34 PM PDT 24
Peak memory 216144 kb
Host smart-20d14e94-ed06-4d0d-9664-33ba14811651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134207773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2134207773
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3832932667
Short name T166
Test name
Test status
Simulation time 1064397973 ps
CPU time 19.41 seconds
Started Jul 21 05:03:27 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 216296 kb
Host smart-3d2b01fa-fb2c-4e6b-8b96-f3418dce63b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832932667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3832932667
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.618084218
Short name T1127
Test name
Test status
Simulation time 2573652718 ps
CPU time 3.89 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:36 PM PDT 24
Peak memory 218532 kb
Host smart-3142eb87-fc38-4796-8444-f566c4ce3b2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618084218 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.618084218
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.513394858
Short name T1137
Test name
Test status
Simulation time 68717629 ps
CPU time 2.01 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:34 PM PDT 24
Peak memory 207764 kb
Host smart-488d9732-0433-433f-a31f-67563dac01a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513394858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.513394858
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3152164453
Short name T1028
Test name
Test status
Simulation time 17301176 ps
CPU time 0.78 seconds
Started Jul 21 05:03:29 PM PDT 24
Finished Jul 21 05:03:30 PM PDT 24
Peak memory 204412 kb
Host smart-666df51b-6c46-454b-8e68-67e58dfd6898
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152164453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3152164453
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4086679822
Short name T132
Test name
Test status
Simulation time 157643750 ps
CPU time 1.76 seconds
Started Jul 21 05:03:34 PM PDT 24
Finished Jul 21 05:03:36 PM PDT 24
Peak memory 216020 kb
Host smart-cb833320-8c84-47ea-8c33-f7b2c4a7a01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086679822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4086679822
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.526669376
Short name T1123
Test name
Test status
Simulation time 428064156 ps
CPU time 2.82 seconds
Started Jul 21 05:03:26 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 216220 kb
Host smart-aff1b192-699e-4a6d-8496-11b40ee81f97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526669376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.526669376
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2670066979
Short name T1136
Test name
Test status
Simulation time 811637173 ps
CPU time 20.95 seconds
Started Jul 21 05:03:29 PM PDT 24
Finished Jul 21 05:03:50 PM PDT 24
Peak memory 215964 kb
Host smart-28e1d0d1-9fce-4f94-8f3a-0ae1148cb4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670066979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2670066979
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3833679523
Short name T1108
Test name
Test status
Simulation time 99234241 ps
CPU time 3.01 seconds
Started Jul 21 05:03:33 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 217504 kb
Host smart-733dcd27-b54f-4d7d-a29f-105b41ccfad1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833679523 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3833679523
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.102834302
Short name T118
Test name
Test status
Simulation time 37301753 ps
CPU time 2.55 seconds
Started Jul 21 05:03:30 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215968 kb
Host smart-143f485a-75f9-40a4-b183-f89d17df181f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102834302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.102834302
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2176243594
Short name T1070
Test name
Test status
Simulation time 15838488 ps
CPU time 0.81 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 204348 kb
Host smart-8f40cb59-cbbd-4867-9d5d-6d5d38e61428
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176243594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2176243594
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1740789376
Short name T131
Test name
Test status
Simulation time 28587125 ps
CPU time 1.71 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215908 kb
Host smart-8d272b8c-33ac-4167-80db-3d68cb629b35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740789376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1740789376
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3665908703
Short name T1149
Test name
Test status
Simulation time 132933115 ps
CPU time 2.43 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:34 PM PDT 24
Peak memory 217116 kb
Host smart-62918199-7619-4799-b951-a9c7ccaed5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665908703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3665908703
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3136231695
Short name T167
Test name
Test status
Simulation time 1143379041 ps
CPU time 18.85 seconds
Started Jul 21 05:03:32 PM PDT 24
Finished Jul 21 05:03:51 PM PDT 24
Peak memory 216380 kb
Host smart-5ef987b1-0640-4e75-a851-af12a3f1fbb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136231695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3136231695
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1243800730
Short name T107
Test name
Test status
Simulation time 64749953 ps
CPU time 2.09 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:39 PM PDT 24
Peak memory 215888 kb
Host smart-3b605453-40da-4bd8-aa80-254b7f2d8060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243800730 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1243800730
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2658887243
Short name T1077
Test name
Test status
Simulation time 86511030 ps
CPU time 2.55 seconds
Started Jul 21 05:03:30 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215844 kb
Host smart-9cb85e4c-afeb-4b07-87b3-e15c6d2172a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658887243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2658887243
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1714049443
Short name T1030
Test name
Test status
Simulation time 16944190 ps
CPU time 0.77 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:32 PM PDT 24
Peak memory 204352 kb
Host smart-60176c3c-d8e6-4c64-baf8-61e57eb72005
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714049443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1714049443
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1131354861
Short name T1135
Test name
Test status
Simulation time 1576162634 ps
CPU time 4.58 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:36 PM PDT 24
Peak memory 215980 kb
Host smart-ead3c91b-39bb-43c6-84ce-6fa5c81e30e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131354861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1131354861
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3585854679
Short name T1141
Test name
Test status
Simulation time 110706897 ps
CPU time 6.61 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:42 PM PDT 24
Peak memory 215820 kb
Host smart-2925fae5-84aa-4669-9be5-b9653509c046
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585854679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3585854679
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.645743503
Short name T1089
Test name
Test status
Simulation time 163763085 ps
CPU time 2.71 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 217412 kb
Host smart-46837ac3-655c-4cfb-abbc-98b0d8e83ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645743503 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.645743503
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2270642621
Short name T122
Test name
Test status
Simulation time 150316248 ps
CPU time 3 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 215764 kb
Host smart-aa82852b-7008-4d75-8006-e2800920f06c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270642621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2270642621
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1972224648
Short name T1043
Test name
Test status
Simulation time 14319490 ps
CPU time 0.77 seconds
Started Jul 21 05:03:37 PM PDT 24
Finished Jul 21 05:03:38 PM PDT 24
Peak memory 204296 kb
Host smart-730a755b-a4d1-44f1-bbc4-114856b45add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972224648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1972224648
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1386745668
Short name T1075
Test name
Test status
Simulation time 49398267 ps
CPU time 2.93 seconds
Started Jul 21 05:03:34 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 215888 kb
Host smart-59ed4cf4-4e3d-47b7-a532-bd69850cb53c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386745668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1386745668
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.427523657
Short name T105
Test name
Test status
Simulation time 136347922 ps
CPU time 2.42 seconds
Started Jul 21 05:03:31 PM PDT 24
Finished Jul 21 05:03:34 PM PDT 24
Peak memory 217152 kb
Host smart-d169dee3-c41b-498a-8ec3-0c2f0958f07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427523657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.427523657
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3415731719
Short name T1109
Test name
Test status
Simulation time 722181804 ps
CPU time 15.89 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:53 PM PDT 24
Peak memory 215988 kb
Host smart-25abc000-1ab9-4463-bd85-6836f8fce0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415731719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3415731719
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1563150413
Short name T1085
Test name
Test status
Simulation time 744629437 ps
CPU time 14.7 seconds
Started Jul 21 05:03:13 PM PDT 24
Finished Jul 21 05:03:29 PM PDT 24
Peak memory 207764 kb
Host smart-82f45ba6-95c4-4cc1-81e1-b13e38927f55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563150413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1563150413
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.989019333
Short name T1145
Test name
Test status
Simulation time 11253750711 ps
CPU time 40.87 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:52 PM PDT 24
Peak memory 207652 kb
Host smart-065d9bbd-0b63-4f72-a8e7-453dcf5f7b7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989019333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.989019333
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.252708200
Short name T82
Test name
Test status
Simulation time 99629627 ps
CPU time 1.17 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 207660 kb
Host smart-22f0e6a5-5c38-404f-92b0-e6ef8ee13dd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252708200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.252708200
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1376802970
Short name T108
Test name
Test status
Simulation time 82639159 ps
CPU time 1.85 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:13 PM PDT 24
Peak memory 217004 kb
Host smart-6bbefcc0-2667-438d-bd9c-402d2e02066b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376802970 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1376802970
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3976680514
Short name T112
Test name
Test status
Simulation time 31581809 ps
CPU time 2.21 seconds
Started Jul 21 05:03:13 PM PDT 24
Finished Jul 21 05:03:16 PM PDT 24
Peak memory 215912 kb
Host smart-92a2e969-6299-4f94-b6be-2c80a9ad0c93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976680514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
976680514
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3682450815
Short name T1143
Test name
Test status
Simulation time 37809749 ps
CPU time 0.77 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:13 PM PDT 24
Peak memory 204428 kb
Host smart-b93e55f4-4dda-4ede-a02b-2059b6fed251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682450815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
682450815
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1845861857
Short name T1082
Test name
Test status
Simulation time 81947042 ps
CPU time 1.65 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:15 PM PDT 24
Peak memory 215892 kb
Host smart-0da3e8f2-0b0d-44d1-849d-1d5623db2c3e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845861857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1845861857
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3750692519
Short name T1083
Test name
Test status
Simulation time 22354338 ps
CPU time 0.69 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:13 PM PDT 24
Peak memory 204252 kb
Host smart-8d314f85-35a8-40b8-a2cf-ad8a703220ab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750692519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3750692519
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3133052867
Short name T1144
Test name
Test status
Simulation time 26822518 ps
CPU time 1.9 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:15 PM PDT 24
Peak memory 207676 kb
Host smart-ee59f4e0-dfc8-42e3-ab3a-4f184ba557aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133052867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3133052867
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3487238645
Short name T102
Test name
Test status
Simulation time 2614853992 ps
CPU time 4.76 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:17 PM PDT 24
Peak memory 216280 kb
Host smart-f234f5f4-96b3-428c-9eaf-2fadd74f14de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487238645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
487238645
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1894623472
Short name T98
Test name
Test status
Simulation time 1292789980 ps
CPU time 9.2 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:21 PM PDT 24
Peak memory 216344 kb
Host smart-3210096a-6c61-461b-be32-fc3abf7bf765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894623472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1894623472
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2347806174
Short name T1098
Test name
Test status
Simulation time 78572672 ps
CPU time 0.75 seconds
Started Jul 21 05:03:37 PM PDT 24
Finished Jul 21 05:03:38 PM PDT 24
Peak memory 204312 kb
Host smart-28c8f955-ccf6-45e3-adbe-8b9420edfd47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347806174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2347806174
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1662018009
Short name T1081
Test name
Test status
Simulation time 32140754 ps
CPU time 0.76 seconds
Started Jul 21 05:03:34 PM PDT 24
Finished Jul 21 05:03:35 PM PDT 24
Peak memory 204360 kb
Host smart-7f44fb00-838c-4021-b6ec-d96c55cfc268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662018009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1662018009
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.981954913
Short name T1027
Test name
Test status
Simulation time 182152619 ps
CPU time 0.7 seconds
Started Jul 21 05:03:36 PM PDT 24
Finished Jul 21 05:03:37 PM PDT 24
Peak memory 204308 kb
Host smart-ee87e8f9-2a94-4d81-997d-47168c5d9094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981954913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.981954913
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.655750434
Short name T1128
Test name
Test status
Simulation time 25682036 ps
CPU time 0.72 seconds
Started Jul 21 05:03:32 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 204776 kb
Host smart-3bb26230-c60e-413e-9d62-54fa76aba26a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655750434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.655750434
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2480150098
Short name T1061
Test name
Test status
Simulation time 74412112 ps
CPU time 0.75 seconds
Started Jul 21 05:03:40 PM PDT 24
Finished Jul 21 05:03:41 PM PDT 24
Peak memory 204308 kb
Host smart-5c37a561-5254-48d2-b6c0-67f6e03d488b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480150098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2480150098
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2986574472
Short name T1054
Test name
Test status
Simulation time 16517887 ps
CPU time 0.68 seconds
Started Jul 21 05:03:40 PM PDT 24
Finished Jul 21 05:03:42 PM PDT 24
Peak memory 204708 kb
Host smart-3743bbd2-b75b-4870-91a2-3348581a88e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986574472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2986574472
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1125596104
Short name T1129
Test name
Test status
Simulation time 33116207 ps
CPU time 0.84 seconds
Started Jul 21 05:03:38 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 204332 kb
Host smart-e786a943-3545-4baa-8247-ee84665421ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125596104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1125596104
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1407905433
Short name T1095
Test name
Test status
Simulation time 32156890 ps
CPU time 0.69 seconds
Started Jul 21 05:03:41 PM PDT 24
Finished Jul 21 05:03:42 PM PDT 24
Peak memory 204364 kb
Host smart-581ff1a1-9f16-45d2-a57d-8c035304a948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407905433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1407905433
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3742134201
Short name T1047
Test name
Test status
Simulation time 50985656 ps
CPU time 0.75 seconds
Started Jul 21 05:03:41 PM PDT 24
Finished Jul 21 05:03:43 PM PDT 24
Peak memory 204672 kb
Host smart-6f4d778c-e8e5-4248-8b8a-b1afc087b906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742134201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3742134201
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3421218378
Short name T1097
Test name
Test status
Simulation time 13056033 ps
CPU time 0.73 seconds
Started Jul 21 05:03:39 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 204428 kb
Host smart-78bd8431-e3ea-491e-90e8-aaa255f8a93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421218378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3421218378
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.271723251
Short name T1088
Test name
Test status
Simulation time 616134174 ps
CPU time 15.67 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:28 PM PDT 24
Peak memory 215928 kb
Host smart-3e98ac5e-d25b-4cd9-891f-0d3bfdec46a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271723251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.271723251
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3076407897
Short name T1132
Test name
Test status
Simulation time 6234103991 ps
CPU time 25.13 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:39 PM PDT 24
Peak memory 215996 kb
Host smart-8e93b8f5-94f4-4300-b87c-cddd4d427bd5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076407897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3076407897
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1309384258
Short name T1092
Test name
Test status
Simulation time 189665980 ps
CPU time 1.53 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 207788 kb
Host smart-f1a86f98-d0cb-4d5b-9fa3-19b12d04f673
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309384258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1309384258
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1980729996
Short name T1105
Test name
Test status
Simulation time 307930661 ps
CPU time 4.04 seconds
Started Jul 21 05:03:14 PM PDT 24
Finished Jul 21 05:03:19 PM PDT 24
Peak memory 218728 kb
Host smart-5df7b282-32a0-4cb2-a81b-cdbc4557e6d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980729996 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1980729996
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.102019487
Short name T1121
Test name
Test status
Simulation time 84881572 ps
CPU time 2.58 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:15 PM PDT 24
Peak memory 207796 kb
Host smart-19096628-d46d-4d21-af29-0e41b1ec6397
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102019487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.102019487
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3497287728
Short name T1059
Test name
Test status
Simulation time 34996370 ps
CPU time 0.69 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:12 PM PDT 24
Peak memory 204424 kb
Host smart-7b0f18a1-4b7c-4c02-86c6-2de4da4ef57b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497287728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
497287728
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.559349353
Short name T1078
Test name
Test status
Simulation time 128404052 ps
CPU time 2.33 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:16 PM PDT 24
Peak memory 215824 kb
Host smart-bd811c65-7d7d-4ef4-9ad0-fa7e2be55eb2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559349353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.559349353
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1377678301
Short name T1107
Test name
Test status
Simulation time 31268686 ps
CPU time 0.69 seconds
Started Jul 21 05:03:15 PM PDT 24
Finished Jul 21 05:03:16 PM PDT 24
Peak memory 204252 kb
Host smart-93a008d2-2286-4364-958f-851137cd8802
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377678301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1377678301
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.150180937
Short name T1126
Test name
Test status
Simulation time 606672203 ps
CPU time 4.05 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:17 PM PDT 24
Peak memory 215836 kb
Host smart-1a1a02b3-7e6e-4c30-aa8e-ff1af5e6fec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150180937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.150180937
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2557192116
Short name T109
Test name
Test status
Simulation time 1408805207 ps
CPU time 15.84 seconds
Started Jul 21 05:03:16 PM PDT 24
Finished Jul 21 05:03:33 PM PDT 24
Peak memory 215908 kb
Host smart-c7b7cb9e-9826-4291-a178-00bc439b3468
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557192116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2557192116
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3551896808
Short name T1052
Test name
Test status
Simulation time 37251368 ps
CPU time 0.78 seconds
Started Jul 21 05:03:39 PM PDT 24
Finished Jul 21 05:03:41 PM PDT 24
Peak memory 204628 kb
Host smart-9886042a-4adc-43b9-9b68-f532c1215dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551896808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3551896808
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.918966911
Short name T1103
Test name
Test status
Simulation time 43642913 ps
CPU time 0.73 seconds
Started Jul 21 05:03:41 PM PDT 24
Finished Jul 21 05:03:42 PM PDT 24
Peak memory 204700 kb
Host smart-62e4bfc7-04bb-4a12-9e07-0283957981e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918966911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.918966911
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1834672415
Short name T1041
Test name
Test status
Simulation time 58356553 ps
CPU time 0.73 seconds
Started Jul 21 05:03:42 PM PDT 24
Finished Jul 21 05:03:44 PM PDT 24
Peak memory 204676 kb
Host smart-c7aab359-00ef-4c7d-85f1-33bbd66071dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834672415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1834672415
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4018067323
Short name T1090
Test name
Test status
Simulation time 18631497 ps
CPU time 0.84 seconds
Started Jul 21 05:03:41 PM PDT 24
Finished Jul 21 05:03:42 PM PDT 24
Peak memory 204384 kb
Host smart-305426ce-1d31-4fb6-a220-6b816324f29e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018067323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4018067323
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3859495472
Short name T1125
Test name
Test status
Simulation time 15783454 ps
CPU time 0.77 seconds
Started Jul 21 05:03:40 PM PDT 24
Finished Jul 21 05:03:41 PM PDT 24
Peak memory 204304 kb
Host smart-6fa5fd61-abc3-47ee-adcf-a09786926ae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859495472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3859495472
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4054241027
Short name T1036
Test name
Test status
Simulation time 56250074 ps
CPU time 0.72 seconds
Started Jul 21 05:03:40 PM PDT 24
Finished Jul 21 05:03:41 PM PDT 24
Peak memory 204952 kb
Host smart-20e94bf2-7541-4188-95bc-68d821c014ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054241027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4054241027
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1646678368
Short name T1102
Test name
Test status
Simulation time 53779743 ps
CPU time 0.75 seconds
Started Jul 21 05:03:40 PM PDT 24
Finished Jul 21 05:03:41 PM PDT 24
Peak memory 204748 kb
Host smart-a43f4b03-dddc-41f2-9146-ff5aea647880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646678368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1646678368
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2902629716
Short name T1053
Test name
Test status
Simulation time 17926444 ps
CPU time 0.78 seconds
Started Jul 21 05:03:45 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 204768 kb
Host smart-75f0402c-925b-48c9-9016-0f3936d240de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902629716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2902629716
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1590814387
Short name T1112
Test name
Test status
Simulation time 37732734 ps
CPU time 0.77 seconds
Started Jul 21 05:03:45 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 204412 kb
Host smart-873c19f9-8fef-4d1c-8189-918662c1ed06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590814387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1590814387
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2662658009
Short name T1139
Test name
Test status
Simulation time 29574760 ps
CPU time 0.72 seconds
Started Jul 21 05:03:44 PM PDT 24
Finished Jul 21 05:03:45 PM PDT 24
Peak memory 204408 kb
Host smart-b9821947-90a9-4137-a0de-d3fc7a28236e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662658009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2662658009
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3696947963
Short name T119
Test name
Test status
Simulation time 2502917768 ps
CPU time 16.09 seconds
Started Jul 21 05:03:11 PM PDT 24
Finished Jul 21 05:03:28 PM PDT 24
Peak memory 216044 kb
Host smart-3d53443d-563a-4169-9ae0-c7a8d96693a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696947963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3696947963
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3297636074
Short name T1114
Test name
Test status
Simulation time 7454345754 ps
CPU time 35.08 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 208052 kb
Host smart-b003c0a2-4cd8-48aa-9ce8-bd50b6e4f496
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297636074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3297636074
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.404443290
Short name T84
Test name
Test status
Simulation time 294001465 ps
CPU time 1.44 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 207720 kb
Host smart-669c83b5-4495-4d4f-b4a4-f94d7c4213c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404443290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.404443290
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2685528302
Short name T1148
Test name
Test status
Simulation time 129019880 ps
CPU time 3.63 seconds
Started Jul 21 05:03:14 PM PDT 24
Finished Jul 21 05:03:18 PM PDT 24
Peak memory 217760 kb
Host smart-2c15ebe3-6be1-46b4-838c-97f6c1476675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685528302 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2685528302
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.869906704
Short name T1120
Test name
Test status
Simulation time 42148610 ps
CPU time 1.28 seconds
Started Jul 21 05:03:14 PM PDT 24
Finished Jul 21 05:03:16 PM PDT 24
Peak memory 215872 kb
Host smart-0e8c749a-60ca-4c6f-bdc3-41c424bf2236
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869906704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.869906704
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2983438796
Short name T1050
Test name
Test status
Simulation time 29072431 ps
CPU time 0.79 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:14 PM PDT 24
Peak memory 204436 kb
Host smart-7b39c4eb-16f5-4804-bcad-20f0d12f58a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983438796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
983438796
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.31950133
Short name T123
Test name
Test status
Simulation time 158026157 ps
CPU time 1.41 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:15 PM PDT 24
Peak memory 216036 kb
Host smart-f1525f30-787e-4798-a753-ee4de4bc014a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31950133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.31950133
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.621590403
Short name T1113
Test name
Test status
Simulation time 63605247 ps
CPU time 0.66 seconds
Started Jul 21 05:03:10 PM PDT 24
Finished Jul 21 05:03:11 PM PDT 24
Peak memory 204556 kb
Host smart-2abc0459-a7e2-4397-8697-f93ce73f54a9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621590403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.621590403
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4129460322
Short name T1046
Test name
Test status
Simulation time 51081726 ps
CPU time 1.73 seconds
Started Jul 21 05:03:14 PM PDT 24
Finished Jul 21 05:03:16 PM PDT 24
Peak memory 215984 kb
Host smart-ae4df41a-90a3-4b7c-bde7-56ef1e076cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129460322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4129460322
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2722491757
Short name T92
Test name
Test status
Simulation time 152936339 ps
CPU time 3.94 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:18 PM PDT 24
Peak memory 216096 kb
Host smart-4ec45e24-a5e7-4eda-937e-de55504629a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722491757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
722491757
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1626280390
Short name T1111
Test name
Test status
Simulation time 2711891977 ps
CPU time 16.45 seconds
Started Jul 21 05:03:13 PM PDT 24
Finished Jul 21 05:03:31 PM PDT 24
Peak memory 216084 kb
Host smart-699e3611-ec2e-47e8-82c9-2ed9484840a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626280390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1626280390
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.101367855
Short name T1031
Test name
Test status
Simulation time 77847342 ps
CPU time 0.73 seconds
Started Jul 21 05:03:44 PM PDT 24
Finished Jul 21 05:03:45 PM PDT 24
Peak memory 204676 kb
Host smart-9392cd46-1118-420d-ad44-b336579cc3c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101367855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.101367855
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3850873265
Short name T1057
Test name
Test status
Simulation time 14419949 ps
CPU time 0.76 seconds
Started Jul 21 05:03:45 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 204440 kb
Host smart-d5265481-382b-4759-ac15-4b8c073fb93e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850873265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3850873265
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1838569142
Short name T1048
Test name
Test status
Simulation time 14649145 ps
CPU time 0.74 seconds
Started Jul 21 05:03:44 PM PDT 24
Finished Jul 21 05:03:45 PM PDT 24
Peak memory 204764 kb
Host smart-a973ccfa-51e1-43c4-a1be-4af951b4acb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838569142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1838569142
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.944578398
Short name T1104
Test name
Test status
Simulation time 16418449 ps
CPU time 0.79 seconds
Started Jul 21 05:03:46 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 204776 kb
Host smart-9bcf2eb9-e1bc-41b6-b32a-1e8b40241129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944578398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.944578398
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1564900103
Short name T1116
Test name
Test status
Simulation time 60333507 ps
CPU time 0.79 seconds
Started Jul 21 05:03:46 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 204308 kb
Host smart-f060a979-4a83-4fec-bea0-a6c2988e11dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564900103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1564900103
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4060825101
Short name T1029
Test name
Test status
Simulation time 20857371 ps
CPU time 0.7 seconds
Started Jul 21 05:03:46 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 204784 kb
Host smart-7f933fbe-8cf3-460b-a97d-a390bdce9dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060825101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4060825101
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1933618527
Short name T1042
Test name
Test status
Simulation time 49653526 ps
CPU time 0.72 seconds
Started Jul 21 05:03:45 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 204372 kb
Host smart-de664a69-0c8b-4047-92af-d3721aff596c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933618527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1933618527
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1135282832
Short name T1142
Test name
Test status
Simulation time 17767571 ps
CPU time 0.77 seconds
Started Jul 21 05:03:45 PM PDT 24
Finished Jul 21 05:03:47 PM PDT 24
Peak memory 204412 kb
Host smart-9037d770-d7e8-4e1d-9816-04613ebfc20d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135282832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1135282832
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2728305706
Short name T1119
Test name
Test status
Simulation time 58040391 ps
CPU time 0.76 seconds
Started Jul 21 05:03:44 PM PDT 24
Finished Jul 21 05:03:45 PM PDT 24
Peak memory 204720 kb
Host smart-ba72298a-073c-4b1e-88d1-740447320494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728305706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2728305706
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4006122845
Short name T1066
Test name
Test status
Simulation time 167398087 ps
CPU time 0.75 seconds
Started Jul 21 05:03:47 PM PDT 24
Finished Jul 21 05:03:48 PM PDT 24
Peak memory 204480 kb
Host smart-15760751-7431-4bdb-8bad-6e954f2ab2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006122845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4006122845
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3641644850
Short name T1087
Test name
Test status
Simulation time 303134799 ps
CPU time 3.89 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 218808 kb
Host smart-cbdcafc5-97cd-4f3a-9153-9b4a5540d741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641644850 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3641644850
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.474472809
Short name T114
Test name
Test status
Simulation time 175175379 ps
CPU time 3.09 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 215828 kb
Host smart-89e766c9-91b2-479d-8e64-b3ec76c9e379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474472809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.474472809
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2230766073
Short name T1035
Test name
Test status
Simulation time 43416467 ps
CPU time 0.72 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 204368 kb
Host smart-1b916a64-2f10-45e7-8dc1-14db3c9df561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230766073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
230766073
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.474288432
Short name T133
Test name
Test status
Simulation time 83102442 ps
CPU time 2.91 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 215952 kb
Host smart-2db77cad-135b-48a4-bddb-30be0f2201a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474288432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.474288432
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1663665521
Short name T103
Test name
Test status
Simulation time 117271578 ps
CPU time 3.45 seconds
Started Jul 21 05:03:12 PM PDT 24
Finished Jul 21 05:03:17 PM PDT 24
Peak memory 216036 kb
Host smart-e1e0056c-18fc-4b68-a59e-526529764a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663665521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
663665521
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3089237102
Short name T1110
Test name
Test status
Simulation time 819312383 ps
CPU time 21.64 seconds
Started Jul 21 05:03:18 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 215924 kb
Host smart-fc7a8cf3-88b0-4609-bfa3-f34969c2de3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089237102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3089237102
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1904671152
Short name T120
Test name
Test status
Simulation time 45586995 ps
CPU time 1.33 seconds
Started Jul 21 05:03:18 PM PDT 24
Finished Jul 21 05:03:20 PM PDT 24
Peak memory 207632 kb
Host smart-94ce5623-b074-4176-90be-1b0063726ab3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904671152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
904671152
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2004380560
Short name T1072
Test name
Test status
Simulation time 15372502 ps
CPU time 0.78 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:22 PM PDT 24
Peak memory 204664 kb
Host smart-631e7f7a-e4c1-47e7-b705-aeb5d7ec0744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004380560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
004380560
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.993730131
Short name T143
Test name
Test status
Simulation time 139265360 ps
CPU time 3.25 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 215984 kb
Host smart-8fa10ae4-0484-4d20-a9eb-c64a3d4f9e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993730131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.993730131
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4090802306
Short name T106
Test name
Test status
Simulation time 188662032 ps
CPU time 3.42 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 216016 kb
Host smart-7170de6d-66f2-4c44-a6e7-c7cb1965630a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090802306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
090802306
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3399446631
Short name T164
Test name
Test status
Simulation time 944516163 ps
CPU time 20.54 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 215748 kb
Host smart-538bca5a-37ba-42c3-b7dc-f9963cfa5767
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399446631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3399446631
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.47634394
Short name T1067
Test name
Test status
Simulation time 1571069522 ps
CPU time 3.37 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 217356 kb
Host smart-bea9b362-4550-44f3-a11b-14e1bc7097de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47634394 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.47634394
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4209454222
Short name T111
Test name
Test status
Simulation time 27233975 ps
CPU time 1.96 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:22 PM PDT 24
Peak memory 216000 kb
Host smart-192d4c9b-41c4-4e2d-88b7-16a6ee0e381f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209454222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
209454222
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3406550678
Short name T1034
Test name
Test status
Simulation time 35782964 ps
CPU time 0.76 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 204428 kb
Host smart-84460178-8284-4b76-b524-d5f884ccb187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406550678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
406550678
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.689601647
Short name T1093
Test name
Test status
Simulation time 179588276 ps
CPU time 1.85 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:22 PM PDT 24
Peak memory 207696 kb
Host smart-7dddf07c-641c-415d-b8f8-6fe3ed46a49c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689601647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.689601647
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1872354787
Short name T1133
Test name
Test status
Simulation time 60578811 ps
CPU time 1.98 seconds
Started Jul 21 05:03:23 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 216128 kb
Host smart-0d5409cb-b739-42eb-aaf4-f75c7eb4b0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872354787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
872354787
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2868039578
Short name T162
Test name
Test status
Simulation time 413168257 ps
CPU time 6.83 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:27 PM PDT 24
Peak memory 215964 kb
Host smart-68cd0445-007f-4181-8e15-8a018723c5e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868039578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2868039578
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.482883867
Short name T96
Test name
Test status
Simulation time 341868147 ps
CPU time 2.67 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 218016 kb
Host smart-c65081a9-e1f6-4b99-9ca5-95815f82066b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482883867 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.482883867
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1684309875
Short name T117
Test name
Test status
Simulation time 112573321 ps
CPU time 1.83 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 215972 kb
Host smart-183b08d0-c1f4-42c4-abd5-2a11d25ef164
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684309875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
684309875
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.407022283
Short name T1147
Test name
Test status
Simulation time 13747955 ps
CPU time 0.72 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 204932 kb
Host smart-83bc0d5c-0268-4b41-8b66-5451f6561a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407022283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.407022283
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2202206848
Short name T1150
Test name
Test status
Simulation time 27735603 ps
CPU time 1.95 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:21 PM PDT 24
Peak memory 215904 kb
Host smart-81b31e8f-65e7-41e4-a075-e204d88e9948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202206848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2202206848
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1402415351
Short name T160
Test name
Test status
Simulation time 158358447 ps
CPU time 3.96 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:24 PM PDT 24
Peak memory 216320 kb
Host smart-baf0083f-3189-4322-b666-2c2303c3ffb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402415351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
402415351
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3968205639
Short name T165
Test name
Test status
Simulation time 3294233577 ps
CPU time 23.85 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:46 PM PDT 24
Peak memory 216424 kb
Host smart-80ae6f89-ee9b-4ca0-bf0f-e00078f31689
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968205639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3968205639
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2912218790
Short name T1080
Test name
Test status
Simulation time 1355495071 ps
CPU time 3.51 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:25 PM PDT 24
Peak memory 218468 kb
Host smart-d84ac92d-d0da-456b-8367-04f27cd8ec23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912218790 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2912218790
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.585741078
Short name T113
Test name
Test status
Simulation time 37037757 ps
CPU time 1.34 seconds
Started Jul 21 05:03:20 PM PDT 24
Finished Jul 21 05:03:22 PM PDT 24
Peak memory 207704 kb
Host smart-3d546851-29af-40e5-bada-fa3b84fc5ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585741078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.585741078
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2188661191
Short name T1115
Test name
Test status
Simulation time 12728778 ps
CPU time 0.73 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:23 PM PDT 24
Peak memory 204364 kb
Host smart-35aad2a4-8283-4839-bd4b-83f3b0cb256e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188661191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
188661191
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4024595307
Short name T1058
Test name
Test status
Simulation time 218898876 ps
CPU time 4.56 seconds
Started Jul 21 05:03:21 PM PDT 24
Finished Jul 21 05:03:26 PM PDT 24
Peak memory 215872 kb
Host smart-79d7ff7d-cc57-4437-aae5-d6a3324ee047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024595307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4024595307
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2189798700
Short name T97
Test name
Test status
Simulation time 175699210 ps
CPU time 2.76 seconds
Started Jul 21 05:03:22 PM PDT 24
Finished Jul 21 05:03:26 PM PDT 24
Peak memory 217176 kb
Host smart-a5708183-5f8f-481c-b78a-d906d4e5564d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189798700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
189798700
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.168212818
Short name T163
Test name
Test status
Simulation time 4871465669 ps
CPU time 20.3 seconds
Started Jul 21 05:03:19 PM PDT 24
Finished Jul 21 05:03:40 PM PDT 24
Peak memory 216612 kb
Host smart-39524551-367c-4372-8b94-b23ba05fe45c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168212818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.168212818
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3293768396
Short name T584
Test name
Test status
Simulation time 43840943 ps
CPU time 0.74 seconds
Started Jul 21 07:03:15 PM PDT 24
Finished Jul 21 07:03:16 PM PDT 24
Peak memory 205196 kb
Host smart-966c0fe5-b712-4487-a587-93a31fd9adb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293768396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
293768396
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3415662921
Short name T538
Test name
Test status
Simulation time 1948075316 ps
CPU time 7.4 seconds
Started Jul 21 07:03:27 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 224960 kb
Host smart-3d315701-1665-48dc-b5d1-c9ec53361f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415662921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3415662921
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2890643042
Short name T947
Test name
Test status
Simulation time 38251532 ps
CPU time 0.77 seconds
Started Jul 21 07:03:21 PM PDT 24
Finished Jul 21 07:03:22 PM PDT 24
Peak memory 206904 kb
Host smart-3cb2c5ba-8a0f-418d-a84e-f449e3c4082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890643042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2890643042
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.336048476
Short name T950
Test name
Test status
Simulation time 3149666742 ps
CPU time 27.23 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 241456 kb
Host smart-e9a655bf-f8fa-4d54-bc19-9c5503dc8f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336048476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.336048476
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2659639760
Short name T739
Test name
Test status
Simulation time 30925179449 ps
CPU time 62.3 seconds
Started Jul 21 07:03:25 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 249684 kb
Host smart-21a59cc6-4b7d-40c2-bdec-1f67f89c5721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659639760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2659639760
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2532814964
Short name T1016
Test name
Test status
Simulation time 27219512440 ps
CPU time 31.14 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 251092 kb
Host smart-34bfdca6-ef3b-4ace-8f36-cce121d34d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532814964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2532814964
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1366920386
Short name T430
Test name
Test status
Simulation time 1976692535 ps
CPU time 22.47 seconds
Started Jul 21 07:03:13 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 224996 kb
Host smart-ac9fa89e-7d47-4598-addb-6248d159261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366920386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1366920386
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3392222814
Short name T226
Test name
Test status
Simulation time 1456677717 ps
CPU time 10.63 seconds
Started Jul 21 07:03:29 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 234088 kb
Host smart-af679f49-6f80-4ea4-aa8f-34df13f5e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392222814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3392222814
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1382376179
Short name T714
Test name
Test status
Simulation time 1570070328 ps
CPU time 4.52 seconds
Started Jul 21 07:03:17 PM PDT 24
Finished Jul 21 07:03:22 PM PDT 24
Peak memory 224984 kb
Host smart-c3e5b2b5-2346-44ae-b5bf-2feda2bec692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382376179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1382376179
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1332724295
Short name T236
Test name
Test status
Simulation time 4365822630 ps
CPU time 13.79 seconds
Started Jul 21 07:03:15 PM PDT 24
Finished Jul 21 07:03:29 PM PDT 24
Peak memory 233276 kb
Host smart-fca8caae-5e59-41fb-b878-300fee19edaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332724295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1332724295
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2424943077
Short name T929
Test name
Test status
Simulation time 4252402583 ps
CPU time 13.73 seconds
Started Jul 21 07:03:26 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 219780 kb
Host smart-9e43e6da-9835-470e-8b47-c37e09d7673a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2424943077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2424943077
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.403176855
Short name T806
Test name
Test status
Simulation time 4775187514 ps
CPU time 73.94 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 250736 kb
Host smart-c1372efb-a118-4a2f-a966-bb2ae45884e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403176855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.403176855
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3518768120
Short name T583
Test name
Test status
Simulation time 5993029547 ps
CPU time 13.01 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 216696 kb
Host smart-2f51de94-32fc-4fca-99a4-4a9b63cbaa61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518768120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3518768120
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2055584575
Short name T786
Test name
Test status
Simulation time 13486501 ps
CPU time 0.72 seconds
Started Jul 21 07:03:20 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 206024 kb
Host smart-b3e343f1-f545-483e-97b9-c6b77b925ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055584575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2055584575
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.334719152
Short name T474
Test name
Test status
Simulation time 157641492 ps
CPU time 2.41 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:21 PM PDT 24
Peak memory 216708 kb
Host smart-624e32de-6fdc-4719-8606-0a8504e6052f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334719152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.334719152
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3899940338
Short name T298
Test name
Test status
Simulation time 101990940 ps
CPU time 0.88 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:31 PM PDT 24
Peak memory 206560 kb
Host smart-8b311780-7f40-4f40-b852-a28a3c6a03e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899940338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3899940338
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1932755169
Short name T503
Test name
Test status
Simulation time 274221908 ps
CPU time 2.55 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 232904 kb
Host smart-95e43af7-44b2-4c76-b0cb-4d608d2521e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932755169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1932755169
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3989230594
Short name T717
Test name
Test status
Simulation time 14729350 ps
CPU time 0.73 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 205232 kb
Host smart-8cd7717e-56c0-4caf-8f40-b892e8358fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989230594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
989230594
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1980235408
Short name T10
Test name
Test status
Simulation time 18044906 ps
CPU time 0.75 seconds
Started Jul 21 07:03:25 PM PDT 24
Finished Jul 21 07:03:26 PM PDT 24
Peak memory 205884 kb
Host smart-ea5b707b-ef8f-4190-8f27-b6785a7fbfd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980235408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1980235408
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3920057471
Short name T805
Test name
Test status
Simulation time 844805962 ps
CPU time 17.01 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 253484 kb
Host smart-c654b790-1cdd-41ae-b3e8-dbdf7579fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920057471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3920057471
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3140492432
Short name T832
Test name
Test status
Simulation time 26936148553 ps
CPU time 108.71 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 264996 kb
Host smart-6268faa6-a218-41de-8fdd-0e27493754cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140492432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3140492432
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2875846113
Short name T34
Test name
Test status
Simulation time 36202402827 ps
CPU time 234.65 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:07:25 PM PDT 24
Peak memory 253024 kb
Host smart-f892c003-bafc-43f2-adf9-37e4d180e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875846113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2875846113
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2424651148
Short name T794
Test name
Test status
Simulation time 1274106382 ps
CPU time 8.87 seconds
Started Jul 21 07:03:17 PM PDT 24
Finished Jul 21 07:03:26 PM PDT 24
Peak memory 237032 kb
Host smart-49e5e62a-b853-473e-a5b3-d8598552c44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424651148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2424651148
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1712336737
Short name T88
Test name
Test status
Simulation time 6667917227 ps
CPU time 71.4 seconds
Started Jul 21 07:03:15 PM PDT 24
Finished Jul 21 07:04:26 PM PDT 24
Peak memory 257768 kb
Host smart-d2d84c59-56ae-4bba-906c-137ce06d3cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712336737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1712336737
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1188214623
Short name T1005
Test name
Test status
Simulation time 557913470 ps
CPU time 9.07 seconds
Started Jul 21 07:03:25 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 233108 kb
Host smart-bacf2d22-43b8-432f-95ef-c2e9a801c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188214623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1188214623
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1956533347
Short name T335
Test name
Test status
Simulation time 1401948403 ps
CPU time 16.53 seconds
Started Jul 21 07:03:13 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 234892 kb
Host smart-6cb8ec8b-7614-438d-bb55-ab5063edd975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956533347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1956533347
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.972699919
Short name T427
Test name
Test status
Simulation time 49882828 ps
CPU time 1.05 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:03:33 PM PDT 24
Peak memory 217156 kb
Host smart-f2a6f352-9f8f-4eb6-974b-082ff2785cab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972699919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.972699919
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1363055845
Short name T239
Test name
Test status
Simulation time 1816102450 ps
CPU time 6.37 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:25 PM PDT 24
Peak memory 224996 kb
Host smart-33481068-1f4e-4f6b-9b57-b2e0c529a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363055845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1363055845
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3651779777
Short name T765
Test name
Test status
Simulation time 968187268 ps
CPU time 6.09 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 233220 kb
Host smart-269a22e6-6ef0-4cab-aba7-487a6724d3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651779777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3651779777
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4028370934
Short name T817
Test name
Test status
Simulation time 313373597 ps
CPU time 5.23 seconds
Started Jul 21 07:03:23 PM PDT 24
Finished Jul 21 07:03:29 PM PDT 24
Peak memory 223588 kb
Host smart-787f5ef0-8048-4c58-a229-f86dbe76a4db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4028370934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4028370934
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2206590771
Short name T68
Test name
Test status
Simulation time 333468058 ps
CPU time 1.23 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 236856 kb
Host smart-bec7b88d-4543-4803-94b8-89a2f5814837
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206590771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2206590771
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1162316089
Short name T29
Test name
Test status
Simulation time 79788220 ps
CPU time 0.96 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 207844 kb
Host smart-55b46386-d4ca-41af-82af-63784cc2d471
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162316089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1162316089
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1517225286
Short name T74
Test name
Test status
Simulation time 1754880057 ps
CPU time 11.19 seconds
Started Jul 21 07:03:28 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 216620 kb
Host smart-9a485210-6231-4b16-adb9-85d0cd87dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517225286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1517225286
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1767442760
Short name T482
Test name
Test status
Simulation time 14997536620 ps
CPU time 8.95 seconds
Started Jul 21 07:03:20 PM PDT 24
Finished Jul 21 07:03:29 PM PDT 24
Peak memory 218000 kb
Host smart-f7581fda-e34b-434b-9f2a-1be6530a1d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767442760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1767442760
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2682492373
Short name T610
Test name
Test status
Simulation time 38043880 ps
CPU time 1.36 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 216688 kb
Host smart-80a1599e-25c9-4dde-981c-00d3fc466f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682492373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2682492373
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3104387169
Short name T520
Test name
Test status
Simulation time 202069789 ps
CPU time 0.93 seconds
Started Jul 21 07:03:26 PM PDT 24
Finished Jul 21 07:03:27 PM PDT 24
Peak memory 206512 kb
Host smart-c2ce2624-9c41-4781-8a87-23a72b779d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104387169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3104387169
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3454306247
Short name T620
Test name
Test status
Simulation time 5325140048 ps
CPU time 4.78 seconds
Started Jul 21 07:03:13 PM PDT 24
Finished Jul 21 07:03:19 PM PDT 24
Peak memory 225064 kb
Host smart-c4b04538-0a17-42ab-8ebc-49cf6c959ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454306247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3454306247
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4250399183
Short name T818
Test name
Test status
Simulation time 11298605 ps
CPU time 0.73 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 206084 kb
Host smart-2fde01fb-73f9-4ddb-adb3-4c8feb9b469a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250399183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4250399183
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.222687259
Short name T361
Test name
Test status
Simulation time 46180933 ps
CPU time 2.54 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 232392 kb
Host smart-fbe0158b-02f5-4f00-ac29-228fa167daa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222687259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.222687259
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3457982972
Short name T329
Test name
Test status
Simulation time 17693537 ps
CPU time 0.79 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 206880 kb
Host smart-2652e102-55d1-4c7a-b779-d4a6d9df5107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457982972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3457982972
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1900778050
Short name T151
Test name
Test status
Simulation time 33159184253 ps
CPU time 15.07 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 234488 kb
Host smart-8c85f042-3ad8-4fa7-bce5-5899944be14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900778050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1900778050
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4263589000
Short name T1007
Test name
Test status
Simulation time 112493801922 ps
CPU time 160.05 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 249664 kb
Host smart-1423886f-1ec6-40ff-b502-c968c302c21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263589000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4263589000
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1678196808
Short name T326
Test name
Test status
Simulation time 248362654 ps
CPU time 7.34 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 241308 kb
Host smart-7517c883-c7d2-4cc9-8023-2b080f41cc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678196808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1678196808
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2159223780
Short name T874
Test name
Test status
Simulation time 60719117586 ps
CPU time 113.75 seconds
Started Jul 21 07:04:00 PM PDT 24
Finished Jul 21 07:05:55 PM PDT 24
Peak memory 257444 kb
Host smart-028b29e4-77f4-440f-962b-194cda6d92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159223780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2159223780
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.17208542
Short name T381
Test name
Test status
Simulation time 980540137 ps
CPU time 3.75 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 224912 kb
Host smart-c0324887-1a14-4777-ad52-e9613f453429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17208542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.17208542
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1976746126
Short name T461
Test name
Test status
Simulation time 3699306708 ps
CPU time 38.46 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 233300 kb
Host smart-ba01cf13-f7c6-4658-9230-762d373a603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976746126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1976746126
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3432641468
Short name T853
Test name
Test status
Simulation time 16968096 ps
CPU time 1.05 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 217100 kb
Host smart-2088bd8a-7aa4-4171-be7a-5f50b86414be
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432641468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3432641468
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3186633419
Short name T576
Test name
Test status
Simulation time 4431162250 ps
CPU time 5.21 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 233220 kb
Host smart-8c0c88f6-d33a-4683-809b-ed207d7907f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186633419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3186633419
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.4143589286
Short name T880
Test name
Test status
Simulation time 148537174 ps
CPU time 4.28 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 222980 kb
Host smart-9b834b28-aa18-4276-be29-072d3d379c63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4143589286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.4143589286
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1663803964
Short name T769
Test name
Test status
Simulation time 6984284781 ps
CPU time 6.2 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 217112 kb
Host smart-b2f72521-657e-49eb-8483-07201afaf8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663803964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1663803964
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1163527993
Short name T300
Test name
Test status
Simulation time 316233728 ps
CPU time 1.14 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 207332 kb
Host smart-91141e99-9f2b-455d-97c3-77371b3093a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163527993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1163527993
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4221984831
Short name T384
Test name
Test status
Simulation time 30027272 ps
CPU time 1.02 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 207788 kb
Host smart-476ba30f-d186-4788-861a-97aaddb43635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221984831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4221984831
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3834551549
Short name T711
Test name
Test status
Simulation time 94044418 ps
CPU time 0.99 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 207216 kb
Host smart-a822c2c3-771d-427f-aa2b-4041864a4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834551549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3834551549
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1867197480
Short name T924
Test name
Test status
Simulation time 18752589518 ps
CPU time 28.07 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:19 PM PDT 24
Peak memory 234128 kb
Host smart-4dabfb1c-5bbc-43bd-83b7-abfd1d8c6473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867197480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1867197480
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1605488834
Short name T340
Test name
Test status
Simulation time 108476861 ps
CPU time 0.74 seconds
Started Jul 21 07:03:58 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 205688 kb
Host smart-0d36b069-d2a7-4952-9bc0-90d482487991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605488834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1605488834
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3027625347
Short name T504
Test name
Test status
Simulation time 4568003249 ps
CPU time 18.21 seconds
Started Jul 21 07:04:06 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 233232 kb
Host smart-da6d9755-dc68-4986-b276-1bc4d4738ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027625347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3027625347
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.61371737
Short name T406
Test name
Test status
Simulation time 21231688 ps
CPU time 0.83 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 206912 kb
Host smart-0824a0bf-f741-42ac-b4a0-b5353fe705fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61371737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.61371737
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3052782655
Short name T152
Test name
Test status
Simulation time 13582691156 ps
CPU time 100.65 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 250804 kb
Host smart-40cc603c-88a5-4c89-aec2-d664f25e001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052782655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3052782655
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2474183009
Short name T13
Test name
Test status
Simulation time 27796684403 ps
CPU time 120.98 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:05:55 PM PDT 24
Peak memory 249720 kb
Host smart-094b39c3-543f-441b-903c-bda890c31402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474183009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2474183009
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.253688033
Short name T138
Test name
Test status
Simulation time 1544015198 ps
CPU time 18.2 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:04:07 PM PDT 24
Peak memory 233156 kb
Host smart-7a39d15c-ee10-427f-8823-7f83c87ed5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253688033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.253688033
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.653797798
Short name T964
Test name
Test status
Simulation time 4166343003 ps
CPU time 9.67 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 235828 kb
Host smart-e3582500-d1b1-43b2-8532-9379f66e3eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653797798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.653797798
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.982744235
Short name T568
Test name
Test status
Simulation time 3623982524 ps
CPU time 10.66 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 233248 kb
Host smart-660cc513-6de4-4a7a-9c84-ffea4b0ceb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982744235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.982744235
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2474215127
Short name T438
Test name
Test status
Simulation time 315806728 ps
CPU time 7.22 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 233116 kb
Host smart-c5cf91c9-0b48-4ec0-bd09-f1361147a25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474215127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2474215127
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2079831236
Short name T997
Test name
Test status
Simulation time 47656293 ps
CPU time 1.08 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 217140 kb
Host smart-30039342-1ad3-43ee-b9eb-9ab352e0c9f9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079831236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2079831236
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3421163528
Short name T242
Test name
Test status
Simulation time 1197833467 ps
CPU time 5.14 seconds
Started Jul 21 07:03:58 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 224928 kb
Host smart-5f798ca6-557c-429b-87fc-b794c802e82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421163528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3421163528
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2007185348
Short name T710
Test name
Test status
Simulation time 1371052885 ps
CPU time 9.8 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 233124 kb
Host smart-da9842e5-153d-4e3f-9748-6be97c3858ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007185348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2007185348
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2435006195
Short name T451
Test name
Test status
Simulation time 79318653 ps
CPU time 4.03 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 223408 kb
Host smart-5926ff57-a13b-4ab8-9ac1-ebad1a1d6e17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2435006195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2435006195
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1800011324
Short name T468
Test name
Test status
Simulation time 29143261899 ps
CPU time 112.57 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 262656 kb
Host smart-7c33a2b1-c371-422c-85d1-539a3932e68a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800011324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1800011324
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3903637950
Short name T606
Test name
Test status
Simulation time 20181706090 ps
CPU time 22.06 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 216932 kb
Host smart-e3a60e9c-485c-4a15-ad14-a49c97902ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903637950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3903637950
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4062409096
Short name T634
Test name
Test status
Simulation time 31380229801 ps
CPU time 11.74 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 216788 kb
Host smart-70a6f447-9cd1-4280-882b-18a8b2e1837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062409096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4062409096
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.707169719
Short name T291
Test name
Test status
Simulation time 66419785 ps
CPU time 0.92 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 207624 kb
Host smart-6ccedb39-d884-4ef6-813c-6fdc4bf1849d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707169719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.707169719
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2337674125
Short name T349
Test name
Test status
Simulation time 74710862 ps
CPU time 0.83 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 206200 kb
Host smart-1cd4fe52-9e6f-4115-9592-cb20852245c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337674125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2337674125
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1777219848
Short name T57
Test name
Test status
Simulation time 16776602327 ps
CPU time 11.32 seconds
Started Jul 21 07:03:59 PM PDT 24
Finished Jul 21 07:04:11 PM PDT 24
Peak memory 239536 kb
Host smart-ebf03366-0e5d-493e-8be5-158dc2722f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777219848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1777219848
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4061287237
Short name T296
Test name
Test status
Simulation time 15074202 ps
CPU time 0.7 seconds
Started Jul 21 07:03:57 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 206116 kb
Host smart-31772875-6b25-457b-9e0f-38efc60cf41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061287237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4061287237
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2465839592
Short name T453
Test name
Test status
Simulation time 285521921 ps
CPU time 2.21 seconds
Started Jul 21 07:03:59 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 223968 kb
Host smart-8f870e66-31db-43cc-a8c7-db7d7ec5ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465839592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2465839592
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4056624692
Short name T692
Test name
Test status
Simulation time 16039342 ps
CPU time 0.77 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 207060 kb
Host smart-c4c05f04-ca8e-48e8-be40-8664499cbf63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056624692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4056624692
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1625324430
Short name T986
Test name
Test status
Simulation time 28870290374 ps
CPU time 122.47 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:05:57 PM PDT 24
Peak memory 249972 kb
Host smart-029ccad8-4cc4-4be4-9a3f-c5b21241ae68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625324430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1625324430
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1514059478
Short name T347
Test name
Test status
Simulation time 9144722166 ps
CPU time 45.61 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 233296 kb
Host smart-b16f2581-dcb3-45f2-9e39-44dbd02f55be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514059478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1514059478
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.470257459
Short name T203
Test name
Test status
Simulation time 9809698716 ps
CPU time 141.41 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:06:16 PM PDT 24
Peak memory 267620 kb
Host smart-4efac629-dd69-4008-93a9-39d8cf278187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470257459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.470257459
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3164584638
Short name T137
Test name
Test status
Simulation time 2153024309 ps
CPU time 11.76 seconds
Started Jul 21 07:04:03 PM PDT 24
Finished Jul 21 07:04:16 PM PDT 24
Peak memory 233308 kb
Host smart-0d318e3e-eabc-4245-8b06-ff4f5719a5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164584638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3164584638
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1923614775
Short name T867
Test name
Test status
Simulation time 12419754463 ps
CPU time 48.74 seconds
Started Jul 21 07:03:59 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 237904 kb
Host smart-f39ae1ba-bbe5-43d1-be96-61f5d0c68a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923614775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1923614775
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2177403616
Short name T231
Test name
Test status
Simulation time 2665641058 ps
CPU time 11 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 233348 kb
Host smart-0a109616-cfa9-470b-9d44-7366549f71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177403616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2177403616
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2897910382
Short name T779
Test name
Test status
Simulation time 5562982053 ps
CPU time 11.2 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 227716 kb
Host smart-fc6d1701-5dd8-4871-9c51-3442f829f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897910382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2897910382
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.935381883
Short name T37
Test name
Test status
Simulation time 156125294 ps
CPU time 1.1 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:03:48 PM PDT 24
Peak memory 217148 kb
Host smart-7768f8f1-4662-439d-997c-bfab20aaa28e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935381883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.935381883
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2067345703
Short name T863
Test name
Test status
Simulation time 30770483 ps
CPU time 2.23 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 232832 kb
Host smart-fc0c652f-3183-4523-b902-ec56e29196fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067345703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2067345703
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2217703297
Short name T687
Test name
Test status
Simulation time 96071349 ps
CPU time 2.73 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 233088 kb
Host smart-18dd701f-4c5d-465b-ba68-2ca2cfa84960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217703297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2217703297
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3118484197
Short name T734
Test name
Test status
Simulation time 366891006 ps
CPU time 5.61 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 219388 kb
Host smart-bf1fae57-8e3e-48fb-bb7f-f1b8823c8373
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118484197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3118484197
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.399627391
Short name T148
Test name
Test status
Simulation time 32794485840 ps
CPU time 127.47 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:06:03 PM PDT 24
Peak memory 252028 kb
Host smart-464df339-2a87-4ef7-b031-583e65f8ac78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399627391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.399627391
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.11520635
Short name T768
Test name
Test status
Simulation time 13353816802 ps
CPU time 23.27 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 216824 kb
Host smart-6be79b97-d3f5-4a8c-986d-75390c09624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11520635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.11520635
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1972229359
Short name T946
Test name
Test status
Simulation time 1098050506 ps
CPU time 5.81 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:09 PM PDT 24
Peak memory 216628 kb
Host smart-edb9e16b-f8ac-4002-a542-3b2b802df1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972229359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1972229359
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.45013242
Short name T706
Test name
Test status
Simulation time 106005021 ps
CPU time 2.82 seconds
Started Jul 21 07:03:54 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 216692 kb
Host smart-5b369797-09df-4337-8720-1f865131a8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45013242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.45013242
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_upload.3365624848
Short name T695
Test name
Test status
Simulation time 8697247339 ps
CPU time 12.74 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:04:09 PM PDT 24
Peak memory 225104 kb
Host smart-df8a91d1-713d-410f-99a8-a32d9c174ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365624848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3365624848
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4055934845
Short name T708
Test name
Test status
Simulation time 11097840 ps
CPU time 0.7 seconds
Started Jul 21 07:04:06 PM PDT 24
Finished Jul 21 07:04:07 PM PDT 24
Peak memory 205668 kb
Host smart-4b2797eb-210f-4c25-adad-00a4578fbfc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055934845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4055934845
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.711295005
Short name T937
Test name
Test status
Simulation time 1999087753 ps
CPU time 5.27 seconds
Started Jul 21 07:05:00 PM PDT 24
Finished Jul 21 07:05:06 PM PDT 24
Peak memory 232972 kb
Host smart-3fe3c70b-80a1-4e97-b107-b3bb0d0f3047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711295005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.711295005
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1190463973
Short name T466
Test name
Test status
Simulation time 41234261 ps
CPU time 0.75 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 207232 kb
Host smart-e6ecf460-cf18-4bf6-aff8-203cce81763a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190463973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1190463973
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.111880356
Short name T49
Test name
Test status
Simulation time 11183302549 ps
CPU time 110.87 seconds
Started Jul 21 07:03:58 PM PDT 24
Finished Jul 21 07:05:50 PM PDT 24
Peak memory 257804 kb
Host smart-c582a6bd-496e-4bcf-8530-03943fd70783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111880356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.111880356
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.877404726
Short name T683
Test name
Test status
Simulation time 8792061456 ps
CPU time 50.51 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 252744 kb
Host smart-6e3d0ab8-c83e-465a-8144-bf393e5ebcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877404726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.877404726
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.496362683
Short name T621
Test name
Test status
Simulation time 534656534 ps
CPU time 4.3 seconds
Started Jul 21 07:04:14 PM PDT 24
Finished Jul 21 07:04:19 PM PDT 24
Peak memory 241344 kb
Host smart-d21719d2-64e7-47a8-9b50-ce0a225b7e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496362683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.496362683
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3636424001
Short name T417
Test name
Test status
Simulation time 12402111 ps
CPU time 0.81 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 215328 kb
Host smart-72f28fe3-ba22-453e-bb36-c51d2ee2edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636424001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3636424001
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3832757986
Short name T517
Test name
Test status
Simulation time 2975467408 ps
CPU time 8.16 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 224948 kb
Host smart-70bc2ee3-cff4-4d60-8b4d-f86e35ca5975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832757986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3832757986
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.211305810
Short name T969
Test name
Test status
Simulation time 9291548408 ps
CPU time 18.73 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:13 PM PDT 24
Peak memory 249560 kb
Host smart-1b15ff9a-5d57-4aaf-adf1-186043faa98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211305810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.211305810
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1284644987
Short name T486
Test name
Test status
Simulation time 58745868 ps
CPU time 1.03 seconds
Started Jul 21 07:04:00 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 218356 kb
Host smart-f062b9e8-5ff5-4b93-b1cc-b52ca9c70e65
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284644987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1284644987
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3807442493
Short name T957
Test name
Test status
Simulation time 765427197 ps
CPU time 5.81 seconds
Started Jul 21 07:03:55 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 224984 kb
Host smart-e226ef41-3d43-4294-be74-cb3e5724d0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807442493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3807442493
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2610941530
Short name T444
Test name
Test status
Simulation time 5825814026 ps
CPU time 10.81 seconds
Started Jul 21 07:04:05 PM PDT 24
Finished Jul 21 07:04:17 PM PDT 24
Peak memory 233296 kb
Host smart-ab597db0-f210-428c-a6d6-50b18ca34189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610941530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2610941530
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1417912137
Short name T135
Test name
Test status
Simulation time 9152200409 ps
CPU time 7.28 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 219276 kb
Host smart-f33b45d3-c3c2-479b-a112-528ea5c81323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1417912137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1417912137
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1116410169
Short name T273
Test name
Test status
Simulation time 103234167167 ps
CPU time 222.93 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:07:31 PM PDT 24
Peak memory 249748 kb
Host smart-74fb3ffc-302f-4d77-b4e0-8a7b4adaacdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116410169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1116410169
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3238287797
Short name T860
Test name
Test status
Simulation time 68082492304 ps
CPU time 56.53 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 216852 kb
Host smart-9df0f0db-8237-44f3-9a5f-686c304c6a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238287797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3238287797
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2884411139
Short name T949
Test name
Test status
Simulation time 1137574299 ps
CPU time 4.65 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:07 PM PDT 24
Peak memory 216668 kb
Host smart-7de2b2af-c86c-491b-a772-beb6caa2c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884411139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2884411139
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3109045468
Short name T544
Test name
Test status
Simulation time 147843727 ps
CPU time 0.96 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 206856 kb
Host smart-5815a9c2-b26a-4d0d-9b71-eb625c70b2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109045468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3109045468
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2767518941
Short name T337
Test name
Test status
Simulation time 14534293 ps
CPU time 0.71 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 206252 kb
Host smart-b8910c1f-701c-4908-902b-f9496c157e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767518941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2767518941
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.484314950
Short name T771
Test name
Test status
Simulation time 293421357 ps
CPU time 2.9 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 233152 kb
Host smart-5530006f-08a8-4b94-98ff-a80f8319355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484314950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.484314950
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.854951697
Short name T936
Test name
Test status
Simulation time 11753576 ps
CPU time 0.72 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 205752 kb
Host smart-5e9af40e-b637-4ea8-ac14-bb83c1824771
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854951697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.854951697
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2036470929
Short name T580
Test name
Test status
Simulation time 17031521852 ps
CPU time 38.22 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 225064 kb
Host smart-2f408094-2a8e-4f11-a19f-6b1649a07c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036470929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2036470929
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2339701097
Short name T60
Test name
Test status
Simulation time 21375186 ps
CPU time 0.8 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 206896 kb
Host smart-7b49cea2-002d-4045-ac44-d0c038c9f775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339701097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2339701097
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3238268807
Short name T464
Test name
Test status
Simulation time 15512021053 ps
CPU time 65.95 seconds
Started Jul 21 07:04:09 PM PDT 24
Finished Jul 21 07:05:16 PM PDT 24
Peak memory 262080 kb
Host smart-2f9e7fac-1684-4933-bf0f-456b46a0bc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238268807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3238268807
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3325322434
Short name T585
Test name
Test status
Simulation time 47645112122 ps
CPU time 94.27 seconds
Started Jul 21 07:04:05 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 234352 kb
Host smart-633e65f8-1328-462f-8a32-27928ff8bb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325322434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3325322434
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1537544443
Short name T282
Test name
Test status
Simulation time 3849813860 ps
CPU time 13.12 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:07 PM PDT 24
Peak memory 224960 kb
Host smart-2d9712b6-fb5c-47dc-a6b0-e5e01341008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537544443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1537544443
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3468628014
Short name T788
Test name
Test status
Simulation time 13686207647 ps
CPU time 49.06 seconds
Started Jul 21 07:04:03 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 254528 kb
Host smart-c89cd5b3-4a85-4f91-b2dd-16397258f6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468628014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3468628014
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.733653875
Short name T194
Test name
Test status
Simulation time 5956406072 ps
CPU time 12.49 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 233312 kb
Host smart-5e132c3f-a8c5-4342-ab0d-33618966dd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733653875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.733653875
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3873603104
Short name T935
Test name
Test status
Simulation time 5425349428 ps
CPU time 21.36 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:16 PM PDT 24
Peak memory 233300 kb
Host smart-34f7be17-e46e-423b-a69f-03b254b2cae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873603104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3873603104
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2248921470
Short name T663
Test name
Test status
Simulation time 455991002 ps
CPU time 1.07 seconds
Started Jul 21 07:04:04 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 217180 kb
Host smart-3a8f65ff-a277-452f-9ae6-efdb094baac3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248921470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2248921470
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1282428729
Short name T241
Test name
Test status
Simulation time 67813287748 ps
CPU time 29.97 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:24 PM PDT 24
Peak memory 233080 kb
Host smart-98f8e90b-f59e-4818-b942-c3ab8dd7aada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282428729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1282428729
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.578157305
Short name T77
Test name
Test status
Simulation time 3839200141 ps
CPU time 4.7 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 225012 kb
Host smart-8b59ef76-20e3-4d5c-ad6d-0064e62dc4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578157305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.578157305
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4267794822
Short name T442
Test name
Test status
Simulation time 13744665213 ps
CPU time 15.06 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:10 PM PDT 24
Peak memory 223716 kb
Host smart-f9d5333f-0b91-4a06-9d90-92414378eb07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4267794822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4267794822
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2832243713
Short name T720
Test name
Test status
Simulation time 15613908529 ps
CPU time 115.42 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:05:49 PM PDT 24
Peak memory 267652 kb
Host smart-6df4e068-e7f0-4fd5-87d9-06b487b1dbbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832243713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2832243713
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4047304264
Short name T412
Test name
Test status
Simulation time 17167774280 ps
CPU time 44.9 seconds
Started Jul 21 07:04:05 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 220072 kb
Host smart-e9ab4725-f47a-4d4a-9227-9e9fe6b48a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047304264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4047304264
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3241025891
Short name T25
Test name
Test status
Simulation time 1275314730 ps
CPU time 6.19 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:03 PM PDT 24
Peak memory 216632 kb
Host smart-9c89930e-2d7a-4cb5-ab54-aeccf5a90ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241025891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3241025891
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.187852548
Short name T75
Test name
Test status
Simulation time 469494352 ps
CPU time 2.07 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 216588 kb
Host smart-9718bd0b-8697-4afa-8560-4b4843f224f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187852548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.187852548
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1573075926
Short name T556
Test name
Test status
Simulation time 63976137 ps
CPU time 0.86 seconds
Started Jul 21 07:03:54 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 206272 kb
Host smart-9a4bf643-fc75-4f0f-9b8f-6d724becb3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573075926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1573075926
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1780240589
Short name T73
Test name
Test status
Simulation time 25888509003 ps
CPU time 20.4 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:15 PM PDT 24
Peak memory 235760 kb
Host smart-f18d537c-1577-4540-8aff-39832c73be40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780240589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1780240589
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1982672313
Short name T516
Test name
Test status
Simulation time 33727001 ps
CPU time 0.75 seconds
Started Jul 21 07:03:57 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 205804 kb
Host smart-a1e82241-19a3-452d-9928-b6509b357e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982672313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1982672313
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4286525694
Short name T879
Test name
Test status
Simulation time 1609067397 ps
CPU time 6.25 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 233316 kb
Host smart-34f461b4-0be9-4fcd-be8f-f8468792b48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286525694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4286525694
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3386522787
Short name T443
Test name
Test status
Simulation time 117686823 ps
CPU time 0.8 seconds
Started Jul 21 07:04:01 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 207256 kb
Host smart-f137686e-dfde-4a5c-830c-d072c1080701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386522787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3386522787
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.878380673
Short name T267
Test name
Test status
Simulation time 30928705053 ps
CPU time 227.16 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:07:43 PM PDT 24
Peak memory 256532 kb
Host smart-fbf297bb-03f0-49aa-8ec1-841eb1b76bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878380673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.878380673
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.45724772
Short name T181
Test name
Test status
Simulation time 18265286379 ps
CPU time 93.79 seconds
Started Jul 21 07:04:16 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 250052 kb
Host smart-cf483968-1f73-4180-a24f-088c9504bfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45724772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.45724772
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3203063666
Short name T154
Test name
Test status
Simulation time 17722007678 ps
CPU time 165.82 seconds
Started Jul 21 07:03:55 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 250044 kb
Host smart-ab5cc363-8b0f-4ac2-bf1a-a3716a6a29e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203063666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3203063666
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1761268168
Short name T209
Test name
Test status
Simulation time 589752339 ps
CPU time 6.02 seconds
Started Jul 21 07:04:13 PM PDT 24
Finished Jul 21 07:04:19 PM PDT 24
Peak memory 224952 kb
Host smart-b7f5c027-aedf-4bec-b12b-8c8f03421a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761268168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1761268168
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2237561990
Short name T878
Test name
Test status
Simulation time 719096003 ps
CPU time 5.49 seconds
Started Jul 21 07:04:00 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 224916 kb
Host smart-7a97f6c5-07c6-49b3-9272-ae5bda1470cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237561990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2237561990
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2088510620
Short name T492
Test name
Test status
Simulation time 6397553898 ps
CPU time 22.77 seconds
Started Jul 21 07:04:04 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 237928 kb
Host smart-4aa8df99-0c49-408d-90ba-5f728701f464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088510620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2088510620
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1597064385
Short name T525
Test name
Test status
Simulation time 53020088 ps
CPU time 0.97 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 218616 kb
Host smart-f0215ebf-dc01-462c-b64b-2e9b36ecc9a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597064385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1597064385
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3002615423
Short name T243
Test name
Test status
Simulation time 3340400977 ps
CPU time 10.19 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 233268 kb
Host smart-ce039131-6ce6-4a62-a4a2-cb2d81323bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002615423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3002615423
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3914280856
Short name T397
Test name
Test status
Simulation time 2563159582 ps
CPU time 5.29 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 241084 kb
Host smart-8bfe6f35-6367-4ef4-843f-f3ab12946e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914280856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3914280856
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2575659689
Short name T784
Test name
Test status
Simulation time 1427188815 ps
CPU time 11.97 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 222816 kb
Host smart-4a8c2699-663d-4fa0-a859-44cd47d88936
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2575659689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2575659689
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2796022680
Short name T263
Test name
Test status
Simulation time 44711452145 ps
CPU time 417.4 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:10:51 PM PDT 24
Peak memory 257280 kb
Host smart-fdfff061-d683-4ab4-ae3b-84e0e6090fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796022680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2796022680
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3370942645
Short name T285
Test name
Test status
Simulation time 21714575846 ps
CPU time 13.79 seconds
Started Jul 21 07:04:08 PM PDT 24
Finished Jul 21 07:04:23 PM PDT 24
Peak memory 216764 kb
Host smart-de6d1aef-2d3a-444e-96ff-29391ce34e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370942645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3370942645
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1613830396
Short name T861
Test name
Test status
Simulation time 1203069815 ps
CPU time 4.64 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 216660 kb
Host smart-7ef78281-61ad-4661-9680-b7aee131d400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613830396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1613830396
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1306290836
Short name T344
Test name
Test status
Simulation time 87550911 ps
CPU time 1.2 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 216728 kb
Host smart-281dab6d-bf86-42a8-87e1-28ddb2226d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306290836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1306290836
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2440829275
Short name T982
Test name
Test status
Simulation time 36356744 ps
CPU time 0.68 seconds
Started Jul 21 07:03:55 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 205976 kb
Host smart-9f85295e-2b25-4a69-aa72-b24b2760f1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440829275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2440829275
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1319628808
Short name T310
Test name
Test status
Simulation time 5122553944 ps
CPU time 9.12 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 241500 kb
Host smart-7dcbd156-6708-4dd1-ab0a-62428a8c56d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319628808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1319628808
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2427877284
Short name T773
Test name
Test status
Simulation time 17083279 ps
CPU time 0.73 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 205176 kb
Host smart-362f2e6b-99ae-428d-9038-8c184252e41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427877284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2427877284
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3707031177
Short name T1026
Test name
Test status
Simulation time 164341592 ps
CPU time 2.31 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 224908 kb
Host smart-f017186b-14d0-46ce-a6f4-3a3b56fd6f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707031177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3707031177
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4202058618
Short name T983
Test name
Test status
Simulation time 72067764 ps
CPU time 0.82 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 206848 kb
Host smart-456a1995-4c73-4db1-afbd-6189c6b78b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202058618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4202058618
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3798148055
Short name T731
Test name
Test status
Simulation time 4459535307 ps
CPU time 26.01 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 249000 kb
Host smart-c9684975-84d2-4ec4-9689-cc57bb4f9348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798148055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3798148055
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4113494596
Short name T749
Test name
Test status
Simulation time 9746829743 ps
CPU time 21.57 seconds
Started Jul 21 07:04:05 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 225088 kb
Host smart-ee22d511-7889-407b-8b60-02301aa0933d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113494596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4113494596
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3250591794
Short name T224
Test name
Test status
Simulation time 34997082772 ps
CPU time 110.73 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:05:53 PM PDT 24
Peak memory 267532 kb
Host smart-48b42de9-f7c8-4c43-b8fc-1c6c20c0d4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250591794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3250591794
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.395211073
Short name T450
Test name
Test status
Simulation time 3538931119 ps
CPU time 8.04 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 241532 kb
Host smart-2f01dff3-0342-48a2-8822-2512ad38318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395211073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.395211073
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1724416177
Short name T87
Test name
Test status
Simulation time 19235188298 ps
CPU time 149.3 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 252244 kb
Host smart-5c00aa20-43af-4771-9f82-93a60b413f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724416177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1724416177
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4259605307
Short name T208
Test name
Test status
Simulation time 590842591 ps
CPU time 3.76 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 233188 kb
Host smart-a90bdcb3-1566-4153-9492-e6fdc1a95a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259605307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4259605307
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.671865139
Short name T399
Test name
Test status
Simulation time 4242925127 ps
CPU time 11.46 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 240500 kb
Host smart-7840028a-3532-4feb-88b9-b9e3d3a47ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671865139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.671865139
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1496962006
Short name T951
Test name
Test status
Simulation time 86357829 ps
CPU time 1.02 seconds
Started Jul 21 07:04:11 PM PDT 24
Finished Jul 21 07:04:12 PM PDT 24
Peak memory 218476 kb
Host smart-9e731538-baa0-4318-b445-8594e14222c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496962006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1496962006
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.37909974
Short name T961
Test name
Test status
Simulation time 947200977 ps
CPU time 11.16 seconds
Started Jul 21 07:03:54 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 249564 kb
Host smart-22c3e6d3-1364-4879-a4d8-a3c1da51ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37909974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.37909974
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.83596676
Short name T702
Test name
Test status
Simulation time 10462826013 ps
CPU time 18.93 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:22 PM PDT 24
Peak memory 249660 kb
Host smart-45e86f39-c53b-4577-bf52-f3f45cc3d0e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83596676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.83596676
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4230418893
Short name T629
Test name
Test status
Simulation time 1940827578 ps
CPU time 7.42 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:04:03 PM PDT 24
Peak memory 222460 kb
Host smart-8bf89049-92ea-4986-ac81-708928e60ebe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4230418893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4230418893
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2846061297
Short name T637
Test name
Test status
Simulation time 39410405 ps
CPU time 0.93 seconds
Started Jul 21 07:04:04 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 206012 kb
Host smart-0625d691-be04-4f84-bf7c-dd16b70048d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846061297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2846061297
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3283002599
Short name T754
Test name
Test status
Simulation time 162582049 ps
CPU time 2.12 seconds
Started Jul 21 07:03:59 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 216712 kb
Host smart-38842ae6-4323-4e37-acad-fb71b8e15c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283002599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3283002599
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.4099868325
Short name T852
Test name
Test status
Simulation time 10833949140 ps
CPU time 5.23 seconds
Started Jul 21 07:04:03 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 216796 kb
Host smart-c435ef73-0247-4caf-80ca-7f0076bcd316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099868325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.4099868325
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1081041753
Short name T601
Test name
Test status
Simulation time 33553770 ps
CPU time 0.76 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 206196 kb
Host smart-b06e528f-086b-4d73-9622-91d7ea5500d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081041753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1081041753
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2792573714
Short name T565
Test name
Test status
Simulation time 48364809 ps
CPU time 0.82 seconds
Started Jul 21 07:04:10 PM PDT 24
Finished Jul 21 07:04:11 PM PDT 24
Peak memory 206280 kb
Host smart-c10ff9d9-de91-43dd-aa2f-d0aa5c2cfd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792573714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2792573714
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.590268849
Short name T377
Test name
Test status
Simulation time 104868061 ps
CPU time 2.32 seconds
Started Jul 21 07:03:52 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 224632 kb
Host smart-2591ed1b-0860-4b82-87bd-f0c51c5207e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590268849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.590268849
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1927588150
Short name T493
Test name
Test status
Simulation time 53278495 ps
CPU time 0.71 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:08 PM PDT 24
Peak memory 205736 kb
Host smart-3ba4577f-00d2-4431-9bda-c1d608838919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927588150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1927588150
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.373448319
Short name T579
Test name
Test status
Simulation time 9176284013 ps
CPU time 6.84 seconds
Started Jul 21 07:03:57 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 233156 kb
Host smart-915bd682-2e99-4609-88f0-7c8d526a90bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373448319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.373448319
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.569561535
Short name T967
Test name
Test status
Simulation time 22256979 ps
CPU time 0.78 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 206844 kb
Host smart-6e8a4039-d8a4-41e1-87b5-a7826adf3aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569561535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.569561535
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2855018261
Short name T653
Test name
Test status
Simulation time 256271851323 ps
CPU time 216.58 seconds
Started Jul 21 07:04:14 PM PDT 24
Finished Jul 21 07:07:52 PM PDT 24
Peak memory 254848 kb
Host smart-e751637a-93a5-4010-8e8f-7ebbc9c8e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855018261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2855018261
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2745119858
Short name T802
Test name
Test status
Simulation time 15713005877 ps
CPU time 33.49 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 234392 kb
Host smart-ce4263d4-bae7-4470-8a13-29b86b1fe929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745119858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2745119858
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1535682398
Short name T462
Test name
Test status
Simulation time 128753457 ps
CPU time 6.22 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 233160 kb
Host smart-067eafde-f74d-42e9-bd39-e247354e3817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535682398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1535682398
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1984964077
Short name T230
Test name
Test status
Simulation time 15286392785 ps
CPU time 62.73 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 250700 kb
Host smart-12e50aa4-33e8-45e2-b034-1d3ddea94d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984964077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1984964077
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1025199182
Short name T228
Test name
Test status
Simulation time 1560149026 ps
CPU time 6.36 seconds
Started Jul 21 07:04:13 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 224872 kb
Host smart-3b5f9629-5022-42b5-8658-c279a83c9365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025199182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1025199182
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3994266899
Short name T306
Test name
Test status
Simulation time 1434094508 ps
CPU time 17.63 seconds
Started Jul 21 07:04:09 PM PDT 24
Finished Jul 21 07:04:27 PM PDT 24
Peak memory 233144 kb
Host smart-5633bfbb-3d60-4e41-83c7-6735e990801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994266899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3994266899
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.40664417
Short name T38
Test name
Test status
Simulation time 55733027 ps
CPU time 1 seconds
Started Jul 21 07:04:19 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 218380 kb
Host smart-2317c159-1111-4b6b-952e-5fdfa04948f5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.40664417
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3442464253
Short name T736
Test name
Test status
Simulation time 847958528 ps
CPU time 11.38 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:30 PM PDT 24
Peak memory 234184 kb
Host smart-8685fe99-1838-4618-b9ad-6682dfa512d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442464253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3442464253
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2209597107
Short name T529
Test name
Test status
Simulation time 26673125074 ps
CPU time 41.67 seconds
Started Jul 21 07:04:01 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 240608 kb
Host smart-4699be14-bb57-402c-b6a4-a57e79c36ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209597107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2209597107
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3253240879
Short name T661
Test name
Test status
Simulation time 1054387284 ps
CPU time 3.97 seconds
Started Jul 21 07:04:15 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 220680 kb
Host smart-05cb2442-7248-4223-a40f-11df49becd8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3253240879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3253240879
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3558309795
Short name T422
Test name
Test status
Simulation time 20107680557 ps
CPU time 24.09 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:04:22 PM PDT 24
Peak memory 216864 kb
Host smart-fd048004-30a8-49e9-9196-0dfbc0e05446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558309795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3558309795
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4267739589
Short name T537
Test name
Test status
Simulation time 23524680185 ps
CPU time 18.15 seconds
Started Jul 21 07:04:09 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 216820 kb
Host smart-642091f0-bcbe-437b-985e-d45101787508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267739589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4267739589
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2650889289
Short name T321
Test name
Test status
Simulation time 214401252 ps
CPU time 1.34 seconds
Started Jul 21 07:03:58 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 216752 kb
Host smart-28df0009-2d2c-4550-88d6-88182ccf406c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650889289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2650889289
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1167189911
Short name T550
Test name
Test status
Simulation time 26111264 ps
CPU time 0.76 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 206280 kb
Host smart-bdb1b036-f013-4842-abdf-d01c92d0c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167189911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1167189911
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.185249016
Short name T59
Test name
Test status
Simulation time 1163738763 ps
CPU time 4.91 seconds
Started Jul 21 07:03:54 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 224952 kb
Host smart-c56ec38b-6131-4367-821e-a9ef078cc13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185249016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.185249016
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3839373175
Short name T725
Test name
Test status
Simulation time 18978020 ps
CPU time 0.72 seconds
Started Jul 21 07:04:19 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 206132 kb
Host smart-1f2fc6f3-e414-4c99-975b-884b2407b822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839373175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3839373175
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1764400592
Short name T174
Test name
Test status
Simulation time 326156444 ps
CPU time 2.25 seconds
Started Jul 21 07:04:15 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 224900 kb
Host smart-9432b647-ffa9-401a-b65a-f486059117ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764400592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1764400592
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1362788084
Short name T561
Test name
Test status
Simulation time 33272246 ps
CPU time 0.83 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:09 PM PDT 24
Peak memory 206892 kb
Host smart-420a8e8e-94c1-4ff4-9825-d6ede219d496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362788084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1362788084
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.49365145
Short name T810
Test name
Test status
Simulation time 18088012670 ps
CPU time 128.05 seconds
Started Jul 21 07:04:11 PM PDT 24
Finished Jul 21 07:06:20 PM PDT 24
Peak memory 234512 kb
Host smart-848b59bb-615a-45d1-8fb9-569cb1217209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49365145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.49365145
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3219275376
Short name T261
Test name
Test status
Simulation time 243852021776 ps
CPU time 482.62 seconds
Started Jul 21 07:04:14 PM PDT 24
Finished Jul 21 07:12:18 PM PDT 24
Peak memory 255548 kb
Host smart-e3429269-0c26-487c-96c7-85f9e57e2144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219275376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3219275376
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2047047885
Short name T235
Test name
Test status
Simulation time 177679746591 ps
CPU time 477.38 seconds
Started Jul 21 07:04:08 PM PDT 24
Finished Jul 21 07:12:06 PM PDT 24
Peak memory 257912 kb
Host smart-8bf9aad7-f299-4870-b3ec-d9dc7b1b5a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047047885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2047047885
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1629889605
Short name T966
Test name
Test status
Simulation time 2418584346 ps
CPU time 44.44 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:05:07 PM PDT 24
Peak memory 250712 kb
Host smart-7b493e93-e6e2-4c15-9d71-86b40005f3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629889605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1629889605
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1028845233
Short name T50
Test name
Test status
Simulation time 83351531519 ps
CPU time 188.1 seconds
Started Jul 21 07:04:09 PM PDT 24
Finished Jul 21 07:07:17 PM PDT 24
Peak memory 255024 kb
Host smart-7b777291-e72f-4396-8f25-5de13664fc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028845233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1028845233
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1948249300
Short name T206
Test name
Test status
Simulation time 966362999 ps
CPU time 7 seconds
Started Jul 21 07:04:10 PM PDT 24
Finished Jul 21 07:04:17 PM PDT 24
Peak memory 233112 kb
Host smart-eb5e897d-47e3-4bb6-8191-9127eca6b78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948249300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1948249300
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3093830254
Short name T795
Test name
Test status
Simulation time 31963362965 ps
CPU time 115.16 seconds
Started Jul 21 07:04:17 PM PDT 24
Finished Jul 21 07:06:13 PM PDT 24
Peak memory 240460 kb
Host smart-dc11c4d1-157a-4313-862e-e19d2d77d5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093830254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3093830254
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3053106110
Short name T813
Test name
Test status
Simulation time 51286922 ps
CPU time 1.05 seconds
Started Jul 21 07:04:00 PM PDT 24
Finished Jul 21 07:04:07 PM PDT 24
Peak memory 217188 kb
Host smart-1d1dd8fb-4de2-4284-ac71-fbb1b73cee9a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053106110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3053106110
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1427629673
Short name T276
Test name
Test status
Simulation time 3010005385 ps
CPU time 6.08 seconds
Started Jul 21 07:04:11 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 233304 kb
Host smart-015e8754-09ab-43e4-ac7c-0a57b145f463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427629673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1427629673
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2858763489
Short name T760
Test name
Test status
Simulation time 25603649194 ps
CPU time 21.06 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 237248 kb
Host smart-e2adec53-8ad0-4cb7-9627-243fd65b35cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858763489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2858763489
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.246059411
Short name T134
Test name
Test status
Simulation time 1634305382 ps
CPU time 10.64 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 222580 kb
Host smart-b7f0a315-a6bd-43f7-aaff-20baa8e4abfc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=246059411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.246059411
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2347076467
Short name T150
Test name
Test status
Simulation time 79792542572 ps
CPU time 694.88 seconds
Started Jul 21 07:04:06 PM PDT 24
Finished Jul 21 07:15:41 PM PDT 24
Peak memory 273028 kb
Host smart-0cfea9f5-93bc-4201-9e68-fe5d1bb7ed78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347076467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2347076467
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.429625411
Short name T4
Test name
Test status
Simulation time 85030414408 ps
CPU time 28.98 seconds
Started Jul 21 07:04:04 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 216820 kb
Host smart-e526bc25-44d1-4434-88ee-dea3b8337468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429625411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.429625411
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3131087477
Short name T1022
Test name
Test status
Simulation time 13699486 ps
CPU time 0.69 seconds
Started Jul 21 07:04:01 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 206008 kb
Host smart-810c94bc-374c-41c6-95f5-1a9e42dbe2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131087477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3131087477
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2574909249
Short name T790
Test name
Test status
Simulation time 51412786 ps
CPU time 0.76 seconds
Started Jul 21 07:04:07 PM PDT 24
Finished Jul 21 07:04:09 PM PDT 24
Peak memory 206308 kb
Host smart-e5b6252f-4296-40a8-96b6-608f5f81c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574909249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2574909249
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3913515846
Short name T724
Test name
Test status
Simulation time 63634434 ps
CPU time 0.87 seconds
Started Jul 21 07:04:01 PM PDT 24
Finished Jul 21 07:04:03 PM PDT 24
Peak memory 206276 kb
Host smart-593d53ee-8d8a-4579-a440-3d023e1ff526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913515846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3913515846
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.762101779
Short name T370
Test name
Test status
Simulation time 395721527 ps
CPU time 5.48 seconds
Started Jul 21 07:04:14 PM PDT 24
Finished Jul 21 07:04:21 PM PDT 24
Peak memory 233084 kb
Host smart-7b82e563-1d42-4e4a-9df0-34d90180feda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762101779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.762101779
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3460171726
Short name T885
Test name
Test status
Simulation time 20410988 ps
CPU time 0.71 seconds
Started Jul 21 07:04:27 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 205196 kb
Host smart-f83d68c3-37de-48d3-b655-6b1f18d97622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460171726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3460171726
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1901078064
Short name T255
Test name
Test status
Simulation time 1353343770 ps
CPU time 6.44 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 224876 kb
Host smart-1b6e14fc-1995-4436-a66e-a14add0e5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901078064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1901078064
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2674412244
Short name T840
Test name
Test status
Simulation time 55591109 ps
CPU time 0.74 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:04:24 PM PDT 24
Peak memory 207256 kb
Host smart-23514e60-7e58-4020-b85d-165ff1e7802c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674412244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2674412244
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.895219627
Short name T704
Test name
Test status
Simulation time 15527743399 ps
CPU time 48.1 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 249740 kb
Host smart-599e8548-43fc-46a7-bafe-0a91711dc07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895219627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.895219627
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.112414973
Short name T865
Test name
Test status
Simulation time 18658930984 ps
CPU time 185.28 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:07:29 PM PDT 24
Peak memory 257896 kb
Host smart-6cae789d-c5be-463f-b065-b695cc289329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112414973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.112414973
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2124618423
Short name T864
Test name
Test status
Simulation time 398078327453 ps
CPU time 431.39 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:11:33 PM PDT 24
Peak memory 256924 kb
Host smart-d987401b-349a-4cdb-ba89-66d47765b482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124618423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2124618423
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1014083015
Short name T1006
Test name
Test status
Simulation time 941274110 ps
CPU time 4.59 seconds
Started Jul 21 07:04:12 PM PDT 24
Finished Jul 21 07:04:17 PM PDT 24
Peak memory 233144 kb
Host smart-6eadf291-9d83-4f82-a42e-f2dfb85f0130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014083015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1014083015
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3913907415
Short name T14
Test name
Test status
Simulation time 30581395609 ps
CPU time 114.85 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:06:17 PM PDT 24
Peak memory 241488 kb
Host smart-3101c285-6fde-4c0b-8afd-4d6586fc5298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913907415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3913907415
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1510447621
Short name T785
Test name
Test status
Simulation time 204607527 ps
CPU time 2.81 seconds
Started Jul 21 07:04:15 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 224952 kb
Host smart-ff4ffa67-cb66-4046-b2c4-577cd2a1d524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510447621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1510447621
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.811861014
Short name T90
Test name
Test status
Simulation time 4289458057 ps
CPU time 15.26 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:36 PM PDT 24
Peak memory 233312 kb
Host smart-5ce444c9-2fe2-47cd-b694-4302df083662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811861014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.811861014
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2978038232
Short name T394
Test name
Test status
Simulation time 49739574 ps
CPU time 1.06 seconds
Started Jul 21 07:04:10 PM PDT 24
Finished Jul 21 07:04:12 PM PDT 24
Peak memory 218444 kb
Host smart-4b9ca251-5e33-45ad-89bf-302c7c129ff3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978038232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2978038232
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1149727443
Short name T426
Test name
Test status
Simulation time 4101553292 ps
CPU time 7.45 seconds
Started Jul 21 07:04:16 PM PDT 24
Finished Jul 21 07:04:24 PM PDT 24
Peak memory 233200 kb
Host smart-cd9e680e-3e00-44c4-b42e-46b81a7de96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149727443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1149727443
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.619735463
Short name T1001
Test name
Test status
Simulation time 45047438170 ps
CPU time 22.23 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 241456 kb
Host smart-3dfe8e2b-1665-4136-bcfc-d61726224906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619735463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.619735463
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1136232122
Short name T931
Test name
Test status
Simulation time 1297454058 ps
CPU time 8.26 seconds
Started Jul 21 07:04:10 PM PDT 24
Finished Jul 21 07:04:19 PM PDT 24
Peak memory 219192 kb
Host smart-b0918990-8f08-4b04-93a2-50437f49f760
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1136232122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1136232122
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3473195575
Short name T52
Test name
Test status
Simulation time 88713505544 ps
CPU time 441.4 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:11:40 PM PDT 24
Peak memory 265312 kb
Host smart-85b14675-e010-49ba-acf1-8eaa030a8d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473195575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3473195575
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.443439422
Short name T540
Test name
Test status
Simulation time 588900060 ps
CPU time 4.68 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 216688 kb
Host smart-1aea0cc4-8ecd-4f13-902a-fff8c3453457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443439422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.443439422
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.283721554
Short name T862
Test name
Test status
Simulation time 1470079877 ps
CPU time 5.12 seconds
Started Jul 21 07:04:08 PM PDT 24
Finished Jul 21 07:04:14 PM PDT 24
Peak memory 216620 kb
Host smart-a7f918a7-a3ed-48ea-922a-02b0fd1df1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283721554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.283721554
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1055571969
Short name T605
Test name
Test status
Simulation time 2301532319 ps
CPU time 7.12 seconds
Started Jul 21 07:04:02 PM PDT 24
Finished Jul 21 07:04:15 PM PDT 24
Peak memory 216840 kb
Host smart-2d45ccbc-0154-4c97-839d-c96c67044996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055571969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1055571969
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4044098542
Short name T897
Test name
Test status
Simulation time 27078192 ps
CPU time 0.77 seconds
Started Jul 21 07:04:16 PM PDT 24
Finished Jul 21 07:04:18 PM PDT 24
Peak memory 206276 kb
Host smart-91262e24-dc66-4e88-a770-cb3f16cebeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044098542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4044098542
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2121889093
Short name T855
Test name
Test status
Simulation time 68699787 ps
CPU time 2.66 seconds
Started Jul 21 07:04:19 PM PDT 24
Finished Jul 21 07:04:22 PM PDT 24
Peak memory 232920 kb
Host smart-41d8b5ed-f66b-4895-a15b-d6c693a5960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121889093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2121889093
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1310900619
Short name T660
Test name
Test status
Simulation time 60270805 ps
CPU time 0.68 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 206320 kb
Host smart-f8cf64f3-b7b0-4259-b01d-22f6e4bb5f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310900619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
310900619
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3817993602
Short name T649
Test name
Test status
Simulation time 132595920 ps
CPU time 3.08 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 233180 kb
Host smart-d25c0317-011f-4829-88e4-87e59466f17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817993602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3817993602
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2646820405
Short name T787
Test name
Test status
Simulation time 27783464 ps
CPU time 0.76 seconds
Started Jul 21 07:03:29 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 205836 kb
Host smart-fcf60b81-28b9-41dc-8dc9-47b768d56944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646820405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2646820405
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.722676766
Short name T256
Test name
Test status
Simulation time 7787456445 ps
CPU time 37.36 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:04:11 PM PDT 24
Peak memory 251592 kb
Host smart-b6824a87-abbd-41fd-ac30-e1ea1c5b1ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722676766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.722676766
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1332284578
Short name T872
Test name
Test status
Simulation time 6819487521 ps
CPU time 41.38 seconds
Started Jul 21 07:03:18 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 249728 kb
Host smart-df7d74c0-27de-4932-8572-241ff61f1a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332284578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1332284578
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2018820114
Short name T54
Test name
Test status
Simulation time 4480256518 ps
CPU time 96.53 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 249652 kb
Host smart-2943688a-a0d2-40cf-b546-e88d02249a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018820114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2018820114
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1511689245
Short name T709
Test name
Test status
Simulation time 1382808791 ps
CPU time 21.33 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 241372 kb
Host smart-87cd9f32-d489-4835-9fde-912af714d29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511689245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1511689245
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.789078734
Short name T974
Test name
Test status
Simulation time 14967904961 ps
CPU time 63.34 seconds
Started Jul 21 07:03:24 PM PDT 24
Finished Jul 21 07:04:27 PM PDT 24
Peak memory 254160 kb
Host smart-b5d89ac7-9ee8-4408-b9d9-108b9a056040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789078734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
789078734
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3312775007
Short name T345
Test name
Test status
Simulation time 1245353648 ps
CPU time 6.95 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 224940 kb
Host smart-4401a028-65e4-4d5d-93cd-522684cf3d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312775007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3312775007
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3513705004
Short name T252
Test name
Test status
Simulation time 11835954763 ps
CPU time 100.3 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 233316 kb
Host smart-43aed9c0-03e2-4f1a-93db-e9fd3a0d5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513705004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3513705004
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1959713343
Short name T826
Test name
Test status
Simulation time 572991465 ps
CPU time 1.08 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 217160 kb
Host smart-ce4ce971-a011-4b33-b371-9265a276c53a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959713343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1959713343
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1167332844
Short name T910
Test name
Test status
Simulation time 76399068 ps
CPU time 2.4 seconds
Started Jul 21 07:03:14 PM PDT 24
Finished Jul 21 07:03:16 PM PDT 24
Peak memory 233152 kb
Host smart-8f4b70dd-4c23-475f-9ca5-2250219cc476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167332844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1167332844
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1932666905
Short name T1010
Test name
Test status
Simulation time 176086063 ps
CPU time 2.67 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 233072 kb
Host smart-0162abf0-06c2-4202-b301-8b3b126023cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932666905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1932666905
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.185179872
Short name T930
Test name
Test status
Simulation time 2188158541 ps
CPU time 6.46 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 219928 kb
Host smart-bfbb272c-0667-41cd-8ff8-3265c4f694b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=185179872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.185179872
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2688566124
Short name T67
Test name
Test status
Simulation time 166237518 ps
CPU time 1.27 seconds
Started Jul 21 07:03:38 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 236852 kb
Host smart-1522b399-e958-4ebc-a167-61afcdb21e44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688566124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2688566124
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3595016727
Short name T458
Test name
Test status
Simulation time 5296623351 ps
CPU time 19.32 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 216936 kb
Host smart-dd969c67-8976-4c2a-8570-6df683fee125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595016727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3595016727
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3637506868
Short name T396
Test name
Test status
Simulation time 4220966705 ps
CPU time 12.36 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 216844 kb
Host smart-6abb9e90-5f40-44a3-90b7-6ae23f4f23bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637506868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3637506868
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2551774639
Short name T518
Test name
Test status
Simulation time 86580792 ps
CPU time 1.08 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 208292 kb
Host smart-448bed2e-a0fc-4311-93c9-338f36ec895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551774639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2551774639
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3470084732
Short name T341
Test name
Test status
Simulation time 67875455 ps
CPU time 0.85 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 206312 kb
Host smart-92755d31-dce3-4d4c-bd1b-ae53afd4e5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470084732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3470084732
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1216920390
Short name T395
Test name
Test status
Simulation time 6008628393 ps
CPU time 8.62 seconds
Started Jul 21 07:03:21 PM PDT 24
Finished Jul 21 07:03:30 PM PDT 24
Peak memory 229536 kb
Host smart-0445ccfc-d55c-4c92-bbaa-cb70d4980519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216920390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1216920390
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.583648463
Short name T413
Test name
Test status
Simulation time 16718095 ps
CPU time 0.72 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:26 PM PDT 24
Peak memory 206152 kb
Host smart-404b5933-d225-44a3-b9f5-b1f99f0ea269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583648463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.583648463
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3479250295
Short name T484
Test name
Test status
Simulation time 80460231 ps
CPU time 2.25 seconds
Started Jul 21 07:04:11 PM PDT 24
Finished Jul 21 07:04:14 PM PDT 24
Peak memory 224984 kb
Host smart-c7279337-8c6f-4bd5-9e98-c2af1f9f6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479250295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3479250295
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1958653970
Short name T63
Test name
Test status
Simulation time 111195472 ps
CPU time 0.8 seconds
Started Jul 21 07:04:19 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 207232 kb
Host smart-83d97dd7-c410-41ba-8324-d88981aae48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958653970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1958653970
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.314992280
Short name T45
Test name
Test status
Simulation time 494055255 ps
CPU time 4.22 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 233184 kb
Host smart-a4d9d98d-065e-4347-8a39-ff090ae43bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314992280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.314992280
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1116525650
Short name T822
Test name
Test status
Simulation time 15362688389 ps
CPU time 70.55 seconds
Started Jul 21 07:04:14 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 256092 kb
Host smart-ccd935b1-d55c-4ee0-b968-6a3adda274b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116525650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1116525650
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3883859493
Short name T1018
Test name
Test status
Simulation time 3981997906 ps
CPU time 62.09 seconds
Started Jul 21 07:04:12 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 249772 kb
Host smart-670fe253-f475-4fc8-ab9f-0301dc039348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883859493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3883859493
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1666853661
Short name T281
Test name
Test status
Simulation time 49002254472 ps
CPU time 34.98 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 235836 kb
Host smart-8859565d-f68c-4033-9721-278f2e3527df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666853661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1666853661
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4041929564
Short name T319
Test name
Test status
Simulation time 12032606 ps
CPU time 0.8 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 216280 kb
Host smart-036d8d81-f80a-42a2-b7bc-140ac04466eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041929564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.4041929564
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3204237446
Short name T500
Test name
Test status
Simulation time 3989882258 ps
CPU time 26.97 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 225000 kb
Host smart-05f5c43a-ad98-4ebc-a32b-89f9aaee2e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204237446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3204237446
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1264563235
Short name T691
Test name
Test status
Simulation time 2329257826 ps
CPU time 20.17 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 237928 kb
Host smart-d7099846-c67b-488c-b3d4-fcc009fdc7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264563235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1264563235
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2574740996
Short name T777
Test name
Test status
Simulation time 104738110 ps
CPU time 2.3 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 223356 kb
Host smart-23cb2e3e-ddf8-49a9-be81-73e2593c5c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574740996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2574740996
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1878641175
Short name T195
Test name
Test status
Simulation time 81171823 ps
CPU time 2.77 seconds
Started Jul 21 07:04:11 PM PDT 24
Finished Jul 21 07:04:14 PM PDT 24
Peak memory 233136 kb
Host smart-768e7c1c-35ab-4a18-9832-89e45e48afb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878641175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1878641175
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2008664192
Short name T383
Test name
Test status
Simulation time 1718320294 ps
CPU time 7.13 seconds
Started Jul 21 07:04:12 PM PDT 24
Finished Jul 21 07:04:20 PM PDT 24
Peak memory 223348 kb
Host smart-62bb3aed-9688-44d9-86aa-d9f39c46739e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2008664192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2008664192
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2191035122
Short name T145
Test name
Test status
Simulation time 4459694944 ps
CPU time 83.04 seconds
Started Jul 21 07:04:26 PM PDT 24
Finished Jul 21 07:05:49 PM PDT 24
Peak memory 256996 kb
Host smart-2377c9bf-b824-4e5d-8385-18c8ef76abb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191035122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2191035122
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2547381050
Short name T807
Test name
Test status
Simulation time 3486466177 ps
CPU time 4.13 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:23 PM PDT 24
Peak memory 216796 kb
Host smart-e5fa60ce-04f2-48e8-9ddf-9bcf79c985d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547381050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2547381050
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.381889138
Short name T719
Test name
Test status
Simulation time 24132525 ps
CPU time 0.75 seconds
Started Jul 21 07:04:26 PM PDT 24
Finished Jul 21 07:04:27 PM PDT 24
Peak memory 206016 kb
Host smart-bf1e5729-2174-4385-b59f-a09fc48ee6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381889138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.381889138
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2655350721
Short name T869
Test name
Test status
Simulation time 381645830 ps
CPU time 4.81 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 216608 kb
Host smart-f56027e6-01c3-48d6-8384-2aa36afe97c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655350721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2655350721
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2408866424
Short name T496
Test name
Test status
Simulation time 51467740 ps
CPU time 0.89 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:26 PM PDT 24
Peak memory 206264 kb
Host smart-9440906b-0600-43ed-a833-a32a25191db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408866424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2408866424
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.488736241
Short name T908
Test name
Test status
Simulation time 900416873 ps
CPU time 8.11 seconds
Started Jul 21 07:04:15 PM PDT 24
Finished Jul 21 07:04:24 PM PDT 24
Peak memory 233164 kb
Host smart-71e6cedf-a367-483e-ad5c-9b8079c0c8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488736241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.488736241
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3528779153
Short name T993
Test name
Test status
Simulation time 10803279 ps
CPU time 0.68 seconds
Started Jul 21 07:04:28 PM PDT 24
Finished Jul 21 07:04:30 PM PDT 24
Peak memory 205136 kb
Host smart-f43e8d5f-7635-4df6-b4ab-14218c2e0687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528779153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3528779153
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1168983002
Short name T295
Test name
Test status
Simulation time 1066452646 ps
CPU time 3.8 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:33 PM PDT 24
Peak memory 224864 kb
Host smart-46b533ad-48d5-43de-9d1a-5e8f46e8b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168983002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1168983002
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3718037889
Short name T696
Test name
Test status
Simulation time 16095077 ps
CPU time 0.78 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:19 PM PDT 24
Peak memory 205844 kb
Host smart-f4a455c2-64eb-4b06-bfe8-1b3bddb7a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718037889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3718037889
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2930289042
Short name T659
Test name
Test status
Simulation time 16950211062 ps
CPU time 58.84 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:05:28 PM PDT 24
Peak memory 238332 kb
Host smart-4eb9aa39-8f73-4d88-af92-a411d6be296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930289042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2930289042
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2255850672
Short name T689
Test name
Test status
Simulation time 228208121537 ps
CPU time 394.66 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:11:14 PM PDT 24
Peak memory 264292 kb
Host smart-95a2bd99-4d80-435a-aca6-5535d1c9d991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255850672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2255850672
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2046167988
Short name T155
Test name
Test status
Simulation time 12550335014 ps
CPU time 137.35 seconds
Started Jul 21 07:04:26 PM PDT 24
Finished Jul 21 07:06:44 PM PDT 24
Peak memory 249772 kb
Host smart-4ba8ec8e-07ad-403b-b526-5c24688d7f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046167988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2046167988
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1820393795
Short name T662
Test name
Test status
Simulation time 337172083 ps
CPU time 7.58 seconds
Started Jul 21 07:04:25 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 224940 kb
Host smart-5f2208e2-b41d-4642-93b1-96af4b38c13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820393795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1820393795
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3625677601
Short name T803
Test name
Test status
Simulation time 20443129447 ps
CPU time 177.99 seconds
Started Jul 21 07:04:28 PM PDT 24
Finished Jul 21 07:07:26 PM PDT 24
Peak memory 257208 kb
Host smart-ef94c75d-f957-4a63-bde3-31828d54b83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625677601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3625677601
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1710124558
Short name T488
Test name
Test status
Simulation time 180747078 ps
CPU time 4.48 seconds
Started Jul 21 07:04:20 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 224956 kb
Host smart-2793fa8c-624a-4748-ad70-08d654df06c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710124558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1710124558
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1324904926
Short name T91
Test name
Test status
Simulation time 9050955322 ps
CPU time 70.33 seconds
Started Jul 21 07:04:25 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 233136 kb
Host smart-7ef740e7-b66d-4371-88d7-b907e9fb6265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324904926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1324904926
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1647006274
Short name T566
Test name
Test status
Simulation time 39690361029 ps
CPU time 9.96 seconds
Started Jul 21 07:04:25 PM PDT 24
Finished Jul 21 07:04:36 PM PDT 24
Peak memory 233228 kb
Host smart-f8264e0a-73b4-43f0-a16a-05b66fd09b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647006274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1647006274
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1263482697
Short name T390
Test name
Test status
Simulation time 1092224684 ps
CPU time 3.83 seconds
Started Jul 21 07:04:28 PM PDT 24
Finished Jul 21 07:04:32 PM PDT 24
Peak memory 224964 kb
Host smart-ec2e507b-f8be-4ac0-b5e7-d4904a8f9552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263482697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1263482697
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2807071250
Short name T439
Test name
Test status
Simulation time 9992578502 ps
CPU time 9.91 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 222724 kb
Host smart-aee734b2-09de-4fe0-9fd1-90aea36f18cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2807071250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2807071250
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.330228666
Short name T845
Test name
Test status
Simulation time 247394478 ps
CPU time 0.95 seconds
Started Jul 21 07:04:19 PM PDT 24
Finished Jul 21 07:04:21 PM PDT 24
Peak memory 206940 kb
Host smart-b9480259-5927-4480-a26b-cf3a1e86311a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330228666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.330228666
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1331876971
Short name T631
Test name
Test status
Simulation time 702149793 ps
CPU time 7.9 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 216940 kb
Host smart-4a7cc968-e86c-493e-a32d-a4ee1666eaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331876971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1331876971
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3193227382
Short name T597
Test name
Test status
Simulation time 2786799952 ps
CPU time 8.04 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:32 PM PDT 24
Peak memory 216720 kb
Host smart-6c60611e-48e9-4777-bd53-8477ded91064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193227382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3193227382
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2532266704
Short name T639
Test name
Test status
Simulation time 108380333 ps
CPU time 1.56 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:26 PM PDT 24
Peak memory 216596 kb
Host smart-0946aac3-fe92-4ded-8bd9-12596ed9aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532266704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2532266704
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.875486214
Short name T454
Test name
Test status
Simulation time 66889344 ps
CPU time 0.71 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:38 PM PDT 24
Peak memory 206320 kb
Host smart-ca14d40d-34eb-4148-9dd9-6b3384cee258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875486214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.875486214
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2930788357
Short name T907
Test name
Test status
Simulation time 13306738363 ps
CPU time 5.56 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 233212 kb
Host smart-3bb3449f-4e65-4f81-8dab-aa9276884b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930788357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2930788357
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1781093421
Short name T506
Test name
Test status
Simulation time 14642905 ps
CPU time 0.69 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 205188 kb
Host smart-76899bb9-b9ab-4db4-ac4f-824089f374b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781093421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1781093421
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4275051375
Short name T431
Test name
Test status
Simulation time 148806346 ps
CPU time 2.74 seconds
Started Jul 21 07:04:25 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 224976 kb
Host smart-f1b51ed1-fecb-43b7-9950-58b4206e569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275051375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4275051375
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1573497937
Short name T355
Test name
Test status
Simulation time 18341537 ps
CPU time 0.76 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:23 PM PDT 24
Peak memory 206876 kb
Host smart-6f427712-86c5-4a29-8265-6c44393e0dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573497937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1573497937
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1453658816
Short name T904
Test name
Test status
Simulation time 7221344397 ps
CPU time 93.3 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:05:58 PM PDT 24
Peak memory 256880 kb
Host smart-70e0b5e8-dc44-4643-a1f0-c7e70e98923c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453658816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1453658816
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3542618685
Short name T288
Test name
Test status
Simulation time 5474893205 ps
CPU time 33.89 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 218248 kb
Host smart-58594277-e810-4eae-8c04-69c2f93645fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542618685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3542618685
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1135357562
Short name T916
Test name
Test status
Simulation time 94957568421 ps
CPU time 715.68 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:16:35 PM PDT 24
Peak memory 261380 kb
Host smart-91109f8f-070e-49e8-a6cb-b62a437de643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135357562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1135357562
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1085866912
Short name T277
Test name
Test status
Simulation time 260925022 ps
CPU time 7.32 seconds
Started Jul 21 07:04:27 PM PDT 24
Finished Jul 21 07:04:35 PM PDT 24
Peak memory 234848 kb
Host smart-e64a260e-1566-4dd8-8d9d-a16eeb5329f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085866912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1085866912
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4232529846
Short name T193
Test name
Test status
Simulation time 24554523533 ps
CPU time 105.81 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:06:11 PM PDT 24
Peak memory 273616 kb
Host smart-baee1d31-4885-49bc-835f-53820bbf5800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232529846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4232529846
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.311131588
Short name T619
Test name
Test status
Simulation time 2579543895 ps
CPU time 12.42 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 233336 kb
Host smart-81b5f3b3-79a6-488e-85f5-a36841008a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311131588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.311131588
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2115439889
Short name T636
Test name
Test status
Simulation time 4045058116 ps
CPU time 17.8 seconds
Started Jul 21 07:04:15 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 241500 kb
Host smart-996f79d3-649c-41b9-b61b-d8ff54e0f2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115439889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2115439889
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3057554404
Short name T888
Test name
Test status
Simulation time 418343234 ps
CPU time 7.14 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 224984 kb
Host smart-14c84feb-9141-4c3d-83b1-6fe594ed9df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057554404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3057554404
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1148199317
Short name T365
Test name
Test status
Simulation time 12798673925 ps
CPU time 16.37 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 225288 kb
Host smart-1b3ae9a2-ca3e-4a8f-844a-3a68dae02b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148199317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1148199317
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3974652149
Short name T564
Test name
Test status
Simulation time 108872185 ps
CPU time 3.9 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 223492 kb
Host smart-c8d23aac-538e-4e17-91fb-961e7e50cc50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3974652149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3974652149
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1123011539
Short name T264
Test name
Test status
Simulation time 149996790108 ps
CPU time 1505.87 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:29:50 PM PDT 24
Peak memory 300424 kb
Host smart-0f80c50a-b40d-4dcc-8b7c-bc2aa710ab6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123011539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1123011539
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.199931755
Short name T573
Test name
Test status
Simulation time 9130377056 ps
CPU time 24.99 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 216768 kb
Host smart-b201cd01-014a-4c5b-82d5-02c7a32f6219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199931755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.199931755
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.760816256
Short name T408
Test name
Test status
Simulation time 802482050 ps
CPU time 6.57 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 216656 kb
Host smart-39447301-c5dc-459e-9321-f543a0be8f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760816256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.760816256
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.937221834
Short name T594
Test name
Test status
Simulation time 128589886 ps
CPU time 2.51 seconds
Started Jul 21 07:04:26 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 216660 kb
Host smart-8b73540b-4975-4a39-8803-945729915337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937221834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.937221834
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3950916203
Short name T338
Test name
Test status
Simulation time 87039929 ps
CPU time 0.83 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:30 PM PDT 24
Peak memory 206256 kb
Host smart-b61572f9-cf68-4aa7-ba89-ece221b5a889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950916203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3950916203
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.238913742
Short name T125
Test name
Test status
Simulation time 36830022145 ps
CPU time 44.51 seconds
Started Jul 21 07:04:25 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 233268 kb
Host smart-e64f52ef-8c8f-414a-9c39-e8b947e585b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238913742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.238913742
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2386349434
Short name T952
Test name
Test status
Simulation time 24251719 ps
CPU time 0.69 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:33 PM PDT 24
Peak memory 205804 kb
Host smart-f21e95a7-eb02-46de-ae94-df4990bea251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386349434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2386349434
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4050440525
Short name T626
Test name
Test status
Simulation time 841388403 ps
CPU time 7.65 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 233148 kb
Host smart-5796f0df-2ce1-48b2-9e21-6241d74af763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050440525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4050440525
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2844489425
Short name T401
Test name
Test status
Simulation time 54641841 ps
CPU time 0.79 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 205812 kb
Host smart-26d37846-dc23-4d00-9b49-1b6c67e475d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844489425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2844489425
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.562467004
Short name T866
Test name
Test status
Simulation time 4216066423 ps
CPU time 44.18 seconds
Started Jul 21 07:04:31 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 254736 kb
Host smart-16155350-66e4-4c73-9e26-a0b198488b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562467004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.562467004
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1999302433
Short name T651
Test name
Test status
Simulation time 75216875068 ps
CPU time 216.62 seconds
Started Jul 21 07:04:26 PM PDT 24
Finished Jul 21 07:08:03 PM PDT 24
Peak memory 253936 kb
Host smart-6437feb4-e3a3-4281-b743-4a662e948857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999302433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1999302433
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2426896970
Short name T420
Test name
Test status
Simulation time 44250904684 ps
CPU time 77.86 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 253876 kb
Host smart-cd7dd00f-b091-42c1-8912-ab97bdb72084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426896970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2426896970
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2302871909
Short name T713
Test name
Test status
Simulation time 185338327 ps
CPU time 3.04 seconds
Started Jul 21 07:04:27 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 233180 kb
Host smart-da078c06-18c9-4a06-bc26-8b00f01a10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302871909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2302871909
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1649179732
Short name T452
Test name
Test status
Simulation time 6428188538 ps
CPU time 31.77 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:54 PM PDT 24
Peak memory 241512 kb
Host smart-97a27e1f-eeb8-44f7-afd0-3fad4186b8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649179732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1649179732
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2517625202
Short name T539
Test name
Test status
Simulation time 2494480712 ps
CPU time 21.01 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 225076 kb
Host smart-80184f38-59ea-4b40-a120-2736520ae857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517625202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2517625202
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.694375036
Short name T508
Test name
Test status
Simulation time 3684724999 ps
CPU time 15.99 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 233252 kb
Host smart-03993a33-dab6-4288-9ad7-b7a52edaf1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694375036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.694375036
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2789469780
Short name T843
Test name
Test status
Simulation time 7508911288 ps
CPU time 9.13 seconds
Started Jul 21 07:04:24 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 225116 kb
Host smart-813bcfd9-977a-4cf2-8eb0-03336c7302bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789469780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2789469780
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3290300566
Short name T1025
Test name
Test status
Simulation time 9212675254 ps
CPU time 23.7 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 239340 kb
Host smart-703efae5-2cbf-4385-b692-4b3328721ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290300566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3290300566
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1768986094
Short name T995
Test name
Test status
Simulation time 1019220629 ps
CPU time 4.08 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 219348 kb
Host smart-267bb4d8-7f29-4480-b99d-c657da0e79ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1768986094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1768986094
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.86278281
Short name T960
Test name
Test status
Simulation time 15323501575 ps
CPU time 128.73 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:06:49 PM PDT 24
Peak memory 257744 kb
Host smart-d1d555ea-38bb-4111-97f0-2038d701900c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86278281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress
_all.86278281
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1681582072
Short name T701
Test name
Test status
Simulation time 7216181217 ps
CPU time 14.6 seconds
Started Jul 21 07:04:28 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 216824 kb
Host smart-470c9338-e2b6-4dc5-a2d8-0751a1c3823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681582072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1681582072
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1896928303
Short name T553
Test name
Test status
Simulation time 3078287600 ps
CPU time 6.87 seconds
Started Jul 21 07:04:23 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 216788 kb
Host smart-29be578e-f04b-4045-b05b-8825a3732c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896928303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1896928303
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1120756959
Short name T657
Test name
Test status
Simulation time 26209247 ps
CPU time 1.22 seconds
Started Jul 21 07:04:27 PM PDT 24
Finished Jul 21 07:04:28 PM PDT 24
Peak memory 216700 kb
Host smart-9962d5d7-1499-43e4-84eb-d6f30d29d016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120756959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1120756959
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3693688763
Short name T6
Test name
Test status
Simulation time 31774832 ps
CPU time 0.68 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 205924 kb
Host smart-3d92b821-6faa-4427-92cf-5b78002c9fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693688763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3693688763
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3517447870
Short name T944
Test name
Test status
Simulation time 1415772977 ps
CPU time 3.22 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:38 PM PDT 24
Peak memory 224908 kb
Host smart-69280e63-7eae-481c-9bd5-a9ace15978b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517447870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3517447870
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2099103456
Short name T1013
Test name
Test status
Simulation time 151838563 ps
CPU time 2.4 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 224920 kb
Host smart-20b3aa86-52f7-42c2-9091-c29286324852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099103456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2099103456
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.215739552
Short name T730
Test name
Test status
Simulation time 36711233 ps
CPU time 0.81 seconds
Started Jul 21 07:04:22 PM PDT 24
Finished Jul 21 07:04:24 PM PDT 24
Peak memory 206932 kb
Host smart-a77a3c2d-ae4c-4386-8970-f30c0748c0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215739552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.215739552
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.403659990
Short name T728
Test name
Test status
Simulation time 14210662451 ps
CPU time 112.42 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:06:38 PM PDT 24
Peak memory 255372 kb
Host smart-b5a0ca86-6914-452c-910d-d1a25b18a7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403659990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.403659990
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1039462234
Short name T284
Test name
Test status
Simulation time 21380009746 ps
CPU time 97.05 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:06:22 PM PDT 24
Peak memory 241504 kb
Host smart-de52f768-1524-4458-a0d2-b149d188ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039462234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1039462234
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1303758947
Short name T472
Test name
Test status
Simulation time 85987668 ps
CPU time 3.96 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 233188 kb
Host smart-4fa8c42d-3f14-460a-80de-f9f1ddbd36f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303758947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1303758947
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2868580999
Short name T761
Test name
Test status
Simulation time 12565487444 ps
CPU time 62.93 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:05:50 PM PDT 24
Peak memory 253844 kb
Host smart-fb83b484-1dc8-4ae7-b1c6-6037d1a880ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868580999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2868580999
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.987004609
Short name T680
Test name
Test status
Simulation time 7595237294 ps
CPU time 6.32 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 225000 kb
Host smart-52550288-7742-445a-9722-d984ec58c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987004609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.987004609
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3916316778
Short name T980
Test name
Test status
Simulation time 66025689647 ps
CPU time 138.68 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:06:52 PM PDT 24
Peak memory 241492 kb
Host smart-e933130d-d133-41b0-8c84-35ec958356e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916316778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3916316778
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2822162265
Short name T240
Test name
Test status
Simulation time 362963225 ps
CPU time 3.45 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 224988 kb
Host smart-b8285b97-a7f3-4d7a-b494-d72cc70a0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822162265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2822162265
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1452287082
Short name T78
Test name
Test status
Simulation time 6011669619 ps
CPU time 16.17 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 225108 kb
Host smart-92f45337-cf0f-4893-bfc8-0b554d34d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452287082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1452287082
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2485961432
Short name T62
Test name
Test status
Simulation time 4201507045 ps
CPU time 6.54 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 223568 kb
Host smart-3ed04a47-2bcb-48e9-989b-0d6e5ec3a48c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2485961432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2485961432
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2276705116
Short name T981
Test name
Test status
Simulation time 16495294808 ps
CPU time 51.78 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 252876 kb
Host smart-3fbf14ee-2e36-434c-b02d-be43879069f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276705116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2276705116
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.320711486
Short name T641
Test name
Test status
Simulation time 4681913980 ps
CPU time 23.72 seconds
Started Jul 21 07:04:18 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 216844 kb
Host smart-5327e300-55ff-4cba-ae1d-3d1de482f7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320711486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.320711486
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.501453843
Short name T915
Test name
Test status
Simulation time 283152615 ps
CPU time 2.54 seconds
Started Jul 21 07:04:33 PM PDT 24
Finished Jul 21 07:04:36 PM PDT 24
Peak memory 216672 kb
Host smart-54c8c091-a783-4d40-a27c-74b2f1e5a6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501453843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.501453843
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2760479010
Short name T632
Test name
Test status
Simulation time 96760588 ps
CPU time 1.57 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:04:35 PM PDT 24
Peak memory 216596 kb
Host smart-71828680-c753-4178-949e-70c100c66a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760479010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2760479010
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.420682194
Short name T342
Test name
Test status
Simulation time 10676093 ps
CPU time 0.68 seconds
Started Jul 21 07:04:21 PM PDT 24
Finished Jul 21 07:04:22 PM PDT 24
Peak memory 206000 kb
Host smart-9efcca48-7232-4676-868d-da8c3b9706e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420682194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.420682194
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3617257952
Short name T211
Test name
Test status
Simulation time 16099215767 ps
CPU time 27.35 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:58 PM PDT 24
Peak memory 233308 kb
Host smart-f4e0cf05-e365-4159-81c8-5b61977dfa00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617257952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3617257952
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3225107461
Short name T876
Test name
Test status
Simulation time 23762517 ps
CPU time 0.7 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 205128 kb
Host smart-fe9af060-bdad-467f-bd6e-f4b2aa945ce0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225107461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3225107461
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.503197131
Short name T404
Test name
Test status
Simulation time 405348805 ps
CPU time 2.39 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 224936 kb
Host smart-c339d38d-a8dc-4b92-a547-53a3119d3381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503197131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.503197131
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2097990914
Short name T305
Test name
Test status
Simulation time 19893812 ps
CPU time 0.77 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:35 PM PDT 24
Peak memory 206860 kb
Host smart-1ee39641-cda5-4a04-a604-ca32852bbc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097990914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2097990914
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4172097433
Short name T595
Test name
Test status
Simulation time 10181752457 ps
CPU time 60.14 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 267008 kb
Host smart-c060f22d-f69c-45f2-9e6b-d6e1a452dc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172097433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4172097433
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.559057630
Short name T48
Test name
Test status
Simulation time 4759157181 ps
CPU time 72.79 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:05:48 PM PDT 24
Peak memory 249744 kb
Host smart-e22f9334-f4ff-4024-a52b-de7419bb0393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559057630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.559057630
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2560426940
Short name T664
Test name
Test status
Simulation time 9616548044 ps
CPU time 111.31 seconds
Started Jul 21 07:04:33 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 249768 kb
Host smart-a091d8d6-a8f7-46c5-8366-1af5fa8aca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560426940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2560426940
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3694355118
Short name T994
Test name
Test status
Simulation time 444681738 ps
CPU time 5.14 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 233160 kb
Host smart-1f6a4269-b96a-4b50-bd37-88617006172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694355118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3694355118
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1249229503
Short name T586
Test name
Test status
Simulation time 67132366959 ps
CPU time 123.29 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:06:41 PM PDT 24
Peak memory 248832 kb
Host smart-c461a47d-599d-45c2-8c1a-2c5ce66c621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249229503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1249229503
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.4153626649
Short name T449
Test name
Test status
Simulation time 4138259420 ps
CPU time 10.86 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 233424 kb
Host smart-623ec00b-b0fb-4263-bc55-13307d0c615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153626649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.4153626649
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1325168257
Short name T483
Test name
Test status
Simulation time 346076548 ps
CPU time 6.89 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 224932 kb
Host smart-91b2a567-cb63-4842-843b-590ec2c1e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325168257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1325168257
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1673789668
Short name T613
Test name
Test status
Simulation time 6984666949 ps
CPU time 11.83 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 239912 kb
Host smart-afe99d4b-49a4-4dd9-bdc2-b6a31f72b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673789668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1673789668
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2247871206
Short name T207
Test name
Test status
Simulation time 2648225029 ps
CPU time 9.75 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 252284 kb
Host smart-26da3bde-747f-4916-bae6-766f5edea24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247871206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2247871206
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1755678354
Short name T647
Test name
Test status
Simulation time 144050432 ps
CPU time 3.49 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 220860 kb
Host smart-1fbd03e0-7ca9-4167-9ee6-465f3410413e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1755678354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1755678354
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1974287095
Short name T146
Test name
Test status
Simulation time 2116482823 ps
CPU time 18.39 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:54 PM PDT 24
Peak memory 241428 kb
Host smart-76399570-f691-4e53-9d87-1adbd041b012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974287095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1974287095
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1957323177
Short name T292
Test name
Test status
Simulation time 377898553 ps
CPU time 4.72 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 216684 kb
Host smart-f1d2fbeb-85ed-497b-93e0-2f8e4cc22e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957323177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1957323177
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2234920675
Short name T676
Test name
Test status
Simulation time 26462824099 ps
CPU time 18.36 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 216744 kb
Host smart-1782980c-861a-49cd-ae43-7cec7c51f8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234920675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2234920675
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.597357201
Short name T987
Test name
Test status
Simulation time 48777875 ps
CPU time 0.76 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 206460 kb
Host smart-2a5c2996-ab97-4101-bec1-ee004b1df973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597357201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.597357201
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4189770736
Short name T418
Test name
Test status
Simulation time 17761136 ps
CPU time 0.75 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 206288 kb
Host smart-f0b683d5-1977-420d-9538-6d1c865a7133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189770736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4189770736
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.515590851
Short name T549
Test name
Test status
Simulation time 897677612 ps
CPU time 8.65 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 241396 kb
Host smart-56e8329c-6439-4d70-aa88-7cfc48b348b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515590851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.515590851
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.809334845
Short name T812
Test name
Test status
Simulation time 31964895 ps
CPU time 0.7 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:04:36 PM PDT 24
Peak memory 205804 kb
Host smart-1b3d6f38-9397-4790-a9e6-565e33a7056e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809334845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.809334845
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.687676795
Short name T250
Test name
Test status
Simulation time 4505585698 ps
CPU time 10.68 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 224900 kb
Host smart-5693577b-c2e7-4d7f-893b-a392352e7272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687676795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.687676795
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2698710112
Short name T694
Test name
Test status
Simulation time 29362309 ps
CPU time 0.71 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 205900 kb
Host smart-25bb0383-b671-4eb3-b51b-094ed2e1c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698710112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2698710112
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3945301945
Short name T190
Test name
Test status
Simulation time 123684046776 ps
CPU time 275.72 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:09:20 PM PDT 24
Peak memory 256240 kb
Host smart-27d72af1-ad2b-4474-ac82-d386c6f14169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945301945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3945301945
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3152054333
Short name T658
Test name
Test status
Simulation time 10002672763 ps
CPU time 81.93 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:06:09 PM PDT 24
Peak memory 249692 kb
Host smart-76c08426-ed55-4619-8ce4-2d334285f093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152054333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3152054333
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4247869206
Short name T591
Test name
Test status
Simulation time 1865217442 ps
CPU time 5.8 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 218204 kb
Host smart-b38b857c-ab51-4349-a8d3-d1f981f4b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247869206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4247869206
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1473367666
Short name T1019
Test name
Test status
Simulation time 493891770 ps
CPU time 9.84 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 234204 kb
Host smart-19205c2e-b089-4120-9dc9-515c016300b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473367666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1473367666
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2949928274
Short name T821
Test name
Test status
Simulation time 35285691222 ps
CPU time 87.12 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:06:09 PM PDT 24
Peak memory 254432 kb
Host smart-4888cb57-cae2-40cc-8950-f93964ae6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949928274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2949928274
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1668886538
Short name T921
Test name
Test status
Simulation time 2412130060 ps
CPU time 6.74 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 225012 kb
Host smart-00094c33-bc0a-4f30-8dfe-e8b2ae3c23bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668886538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1668886538
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.695204829
Short name T729
Test name
Test status
Simulation time 3288426409 ps
CPU time 38.44 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 233140 kb
Host smart-6504e6bd-1cb5-478a-b797-d061a2a1d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695204829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.695204829
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2406975769
Short name T913
Test name
Test status
Simulation time 68717750736 ps
CPU time 31.94 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:05:12 PM PDT 24
Peak memory 233312 kb
Host smart-26a79ec3-74eb-4671-acb2-0abc7b01408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406975769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2406975769
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2006094114
Short name T604
Test name
Test status
Simulation time 16577335857 ps
CPU time 12.64 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 233240 kb
Host smart-c65e1aac-cef8-49ce-a44d-5a008828535a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006094114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2006094114
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2185678974
Short name T436
Test name
Test status
Simulation time 424429052 ps
CPU time 4.58 seconds
Started Jul 21 07:04:33 PM PDT 24
Finished Jul 21 07:04:38 PM PDT 24
Peak memory 219072 kb
Host smart-7ef3129f-8aca-4c0d-b1c4-5032c6b30c1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2185678974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2185678974
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.188880304
Short name T238
Test name
Test status
Simulation time 207235795047 ps
CPU time 175.92 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:07:29 PM PDT 24
Peak memory 266160 kb
Host smart-d2e84b37-90e5-4505-b8d9-08b2b65efbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188880304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.188880304
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3908416126
Short name T61
Test name
Test status
Simulation time 1282684877 ps
CPU time 14.64 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 216860 kb
Host smart-f1ce67a4-49db-470a-8238-7187a103b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908416126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3908416126
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2056885003
Short name T336
Test name
Test status
Simulation time 448356194 ps
CPU time 1.03 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 207396 kb
Host smart-246f75f9-a7cd-4cde-9b5f-347065edb267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056885003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2056885003
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.694960032
Short name T320
Test name
Test status
Simulation time 21688983 ps
CPU time 0.72 seconds
Started Jul 21 07:04:30 PM PDT 24
Finished Jul 21 07:04:31 PM PDT 24
Peak memory 205896 kb
Host smart-911be4e7-b09a-4ac7-b282-c7094b662346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694960032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.694960032
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.896389766
Short name T425
Test name
Test status
Simulation time 87377444 ps
CPU time 0.88 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 206140 kb
Host smart-b1d85404-bc1a-46df-9052-5e1ee2ddf429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896389766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.896389766
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.495646134
Short name T780
Test name
Test status
Simulation time 9478133254 ps
CPU time 17.99 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 233120 kb
Host smart-47e44a6e-a6ce-4689-82a9-af516a7138e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495646134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.495646134
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3459032651
Short name T563
Test name
Test status
Simulation time 31055790 ps
CPU time 0.73 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 205180 kb
Host smart-604ea991-b271-4f0b-a1b8-137738961ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459032651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3459032651
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2923307674
Short name T233
Test name
Test status
Simulation time 389245179 ps
CPU time 4.27 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 233076 kb
Host smart-10a3e2ea-2533-486e-963f-9785865d546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923307674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2923307674
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1585516843
Short name T317
Test name
Test status
Simulation time 34816984 ps
CPU time 0.78 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 205880 kb
Host smart-ad545381-e444-42d2-955f-8c079ac43264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585516843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1585516843
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.164075935
Short name T459
Test name
Test status
Simulation time 150848857651 ps
CPU time 225.61 seconds
Started Jul 21 07:04:43 PM PDT 24
Finished Jul 21 07:08:32 PM PDT 24
Peak memory 251580 kb
Host smart-31666f26-256f-4a50-8c06-1780952ebfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164075935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.164075935
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1180851822
Short name T851
Test name
Test status
Simulation time 1722524907 ps
CPU time 45.85 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 249600 kb
Host smart-a21bc61a-d106-461c-b84f-f267cf3dc054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180851822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1180851822
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3470532739
Short name T287
Test name
Test status
Simulation time 1403210250 ps
CPU time 14.4 seconds
Started Jul 21 07:04:28 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 220248 kb
Host smart-2de1ec1d-db3b-4a59-b85c-6acabc031939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470532739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3470532739
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.939703792
Short name T1023
Test name
Test status
Simulation time 2095464720 ps
CPU time 18.74 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 249564 kb
Host smart-537ecf3a-fdcb-4268-a7bc-4ec04ce2f4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939703792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.939703792
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2884126778
Short name T599
Test name
Test status
Simulation time 3294553058 ps
CPU time 46.34 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:05:27 PM PDT 24
Peak memory 249608 kb
Host smart-66cc876c-d0b0-42ff-8ac6-b9496a739cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884126778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2884126778
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2360609092
Short name T186
Test name
Test status
Simulation time 1550303952 ps
CPU time 7.35 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 233208 kb
Host smart-61679c9b-13cc-47c5-be8d-c4eaaf43133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360609092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2360609092
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2894891960
Short name T828
Test name
Test status
Simulation time 1979661924 ps
CPU time 14.16 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 233092 kb
Host smart-872fa30a-8745-47db-9aa0-915503045355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894891960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2894891960
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3712429424
Short name T748
Test name
Test status
Simulation time 11413178320 ps
CPU time 7.89 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 233172 kb
Host smart-35beae2c-9706-4137-8f40-d91cda4e0385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712429424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3712429424
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3133412596
Short name T759
Test name
Test status
Simulation time 102531675 ps
CPU time 2.28 seconds
Started Jul 21 07:04:37 PM PDT 24
Finished Jul 21 07:04:40 PM PDT 24
Peak memory 232784 kb
Host smart-a0d21180-fbc8-4d83-8242-d531229663dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133412596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3133412596
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3989829720
Short name T522
Test name
Test status
Simulation time 4863151144 ps
CPU time 8.27 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:54 PM PDT 24
Peak memory 219440 kb
Host smart-2470f4ac-0aca-4a9c-b9bb-1e5aac290384
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3989829720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3989829720
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.241984700
Short name T204
Test name
Test status
Simulation time 80771407531 ps
CPU time 382.02 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:11:06 PM PDT 24
Peak memory 268728 kb
Host smart-12858803-ac11-4eb4-895c-46ae6ea0fc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241984700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.241984700
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1904617446
Short name T346
Test name
Test status
Simulation time 20974494430 ps
CPU time 19.97 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:05:02 PM PDT 24
Peak memory 216856 kb
Host smart-b99809c9-e1a5-4bbf-8426-51fab95819cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904617446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1904617446
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2253528218
Short name T899
Test name
Test status
Simulation time 25338287918 ps
CPU time 10 seconds
Started Jul 21 07:04:34 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 216892 kb
Host smart-85c32533-9244-4936-b6c0-54e5c88eb7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253528218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2253528218
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1151194880
Short name T746
Test name
Test status
Simulation time 65516284 ps
CPU time 0.98 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 207476 kb
Host smart-d6c75534-aee2-40b7-87c1-ce915ffa5aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151194880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1151194880
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.448087466
Short name T371
Test name
Test status
Simulation time 68152175 ps
CPU time 0.73 seconds
Started Jul 21 07:04:33 PM PDT 24
Finished Jul 21 07:04:34 PM PDT 24
Peak memory 206268 kb
Host smart-fe2df0a4-eccc-463a-94a1-ef910d843f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448087466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.448087466
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1248792269
Short name T485
Test name
Test status
Simulation time 6988241063 ps
CPU time 27.4 seconds
Started Jul 21 07:04:32 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 233272 kb
Host smart-838ac941-6a93-4217-afd1-25190b86c38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248792269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1248792269
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.122970448
Short name T546
Test name
Test status
Simulation time 13340556 ps
CPU time 0.77 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 205188 kb
Host smart-f08ac558-8b2f-4355-aa9e-f6138d883f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122970448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.122970448
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3334656964
Short name T799
Test name
Test status
Simulation time 84748214 ps
CPU time 2.16 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 224752 kb
Host smart-1b5e108d-0bc4-456c-8330-504437ec3056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334656964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3334656964
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2979086829
Short name T364
Test name
Test status
Simulation time 21195288 ps
CPU time 0.81 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 206940 kb
Host smart-febfac38-6586-403f-bbaf-ee98a658d71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979086829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2979086829
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.492478774
Short name T958
Test name
Test status
Simulation time 14300648 ps
CPU time 0.75 seconds
Started Jul 21 07:04:36 PM PDT 24
Finished Jul 21 07:04:37 PM PDT 24
Peak memory 216292 kb
Host smart-70cc49be-9968-441c-98f8-d731201c368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492478774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.492478774
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1928462208
Short name T972
Test name
Test status
Simulation time 63701922447 ps
CPU time 67.71 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:05:53 PM PDT 24
Peak memory 249728 kb
Host smart-747a7e97-d4f6-4947-9108-f34c9a0a8ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928462208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1928462208
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1204257672
Short name T447
Test name
Test status
Simulation time 15378549872 ps
CPU time 62.17 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 252380 kb
Host smart-ad106c98-c4f8-4f02-9c55-27b6cab64f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204257672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1204257672
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2767984754
Short name T445
Test name
Test status
Simulation time 4724234820 ps
CPU time 7.57 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 224904 kb
Host smart-771f6d79-e813-4733-a4c1-46e43ffe7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767984754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2767984754
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.60223558
Short name T854
Test name
Test status
Simulation time 3305329033 ps
CPU time 31.17 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:05:19 PM PDT 24
Peak memory 239444 kb
Host smart-1685b8b8-e8e2-4bea-a1e9-f305be000449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60223558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.60223558
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1183985495
Short name T645
Test name
Test status
Simulation time 171060721 ps
CPU time 5.37 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 233160 kb
Host smart-7e2674ad-90ed-4851-b16e-e0e93e472e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183985495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1183985495
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4075889835
Short name T478
Test name
Test status
Simulation time 1445321609 ps
CPU time 17.35 seconds
Started Jul 21 07:04:29 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 233116 kb
Host smart-0c627f2a-8d03-464c-9e98-d0e1d1105f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075889835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4075889835
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2089390457
Short name T678
Test name
Test status
Simulation time 10028617758 ps
CPU time 10.11 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:54 PM PDT 24
Peak memory 233312 kb
Host smart-b6155d1c-040e-49e7-9e3f-047eb0c6cc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089390457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2089390457
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3461264918
Short name T142
Test name
Test status
Simulation time 294817231 ps
CPU time 2.01 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 224036 kb
Host smart-cb20a56a-f87d-4b89-a101-a4be03a65b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461264918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3461264918
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2698353268
Short name T738
Test name
Test status
Simulation time 183838147 ps
CPU time 3.36 seconds
Started Jul 21 07:04:43 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 220120 kb
Host smart-fd763f0b-5117-495a-ab72-93009a12b65a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2698353268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2698353268
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.779581835
Short name T149
Test name
Test status
Simulation time 108245072094 ps
CPU time 1140.75 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:23:51 PM PDT 24
Peak memory 284516 kb
Host smart-3c40ab8f-ab7c-4720-a0d4-df295bb3c926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779581835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.779581835
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2133384606
Short name T920
Test name
Test status
Simulation time 8008404628 ps
CPU time 21.68 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 216844 kb
Host smart-9d339b80-dcea-4768-a8ff-297db7a61ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133384606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2133384606
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3676489930
Short name T755
Test name
Test status
Simulation time 6739507051 ps
CPU time 10.37 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 216904 kb
Host smart-6c7038fe-c053-46ac-945a-209e29006ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676489930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3676489930
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3903560769
Short name T809
Test name
Test status
Simulation time 507954020 ps
CPU time 3.05 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 216708 kb
Host smart-2c7cb13b-2148-4175-8d41-6bd929223e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903560769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3903560769
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1754302954
Short name T618
Test name
Test status
Simulation time 33598971 ps
CPU time 0.79 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 206260 kb
Host smart-e41254e2-e3fc-4b2e-9617-e6e3480ee83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754302954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1754302954
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2290239741
Short name T216
Test name
Test status
Simulation time 568743980 ps
CPU time 8.53 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 233160 kb
Host smart-e4fca8fe-3e4d-44b1-ae34-4c0a19d24e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290239741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2290239741
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1362287247
Short name T64
Test name
Test status
Simulation time 20186168 ps
CPU time 0.73 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 205808 kb
Host smart-60df1461-83e9-466c-a007-5e9934b059cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362287247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1362287247
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.382653003
Short name T440
Test name
Test status
Simulation time 901608299 ps
CPU time 2.64 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 225032 kb
Host smart-143c8a62-8566-4d16-ab0b-077c068dc23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382653003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.382653003
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3279408408
Short name T602
Test name
Test status
Simulation time 86020443 ps
CPU time 0.75 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 206884 kb
Host smart-2e781b21-c89d-465d-bec0-2594ba8c2432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279408408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3279408408
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3934572628
Short name T419
Test name
Test status
Simulation time 9276552142 ps
CPU time 55.84 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:05:41 PM PDT 24
Peak memory 257436 kb
Host smart-64a688f3-f940-450d-ad53-3f92f0cabcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934572628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3934572628
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.86143412
Short name T932
Test name
Test status
Simulation time 2959140688 ps
CPU time 28.74 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:55 PM PDT 24
Peak memory 249536 kb
Host smart-47cabb76-3fc2-4244-87ce-2c4352625bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86143412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.86143412
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3431421099
Short name T421
Test name
Test status
Simulation time 210406274 ps
CPU time 3.47 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:05:07 PM PDT 24
Peak memory 224896 kb
Host smart-ce4086b7-ae4e-47b2-9054-7405826d3b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431421099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3431421099
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.4246317099
Short name T1003
Test name
Test status
Simulation time 112754272267 ps
CPU time 186.9 seconds
Started Jul 21 07:04:43 PM PDT 24
Finished Jul 21 07:07:53 PM PDT 24
Peak memory 257096 kb
Host smart-b63ba6d8-58a4-4d92-a9c2-5a79e7aea729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246317099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.4246317099
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1360015267
Short name T827
Test name
Test status
Simulation time 13033281450 ps
CPU time 14.64 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 225020 kb
Host smart-23868208-74eb-4856-8a35-2fd1d7b5a549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360015267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1360015267
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2192688349
Short name T721
Test name
Test status
Simulation time 28788192945 ps
CPU time 62.56 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 233232 kb
Host smart-8a71d48f-6518-4ad3-9a61-3f8936260f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192688349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2192688349
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3027779208
Short name T726
Test name
Test status
Simulation time 541508390 ps
CPU time 3.57 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 224924 kb
Host smart-f7c7e3e7-a816-40fe-a0d4-60d695608405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027779208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3027779208
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2158091405
Short name T487
Test name
Test status
Simulation time 28599132 ps
CPU time 2.26 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 232840 kb
Host smart-41429c18-7719-41b8-9668-3128609e3808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158091405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2158091405
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.355724829
Short name T900
Test name
Test status
Simulation time 396428131 ps
CPU time 6.26 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 221072 kb
Host smart-b12d2ce4-3d31-433b-8495-e91f2bacee55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=355724829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.355724829
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3585846112
Short name T733
Test name
Test status
Simulation time 30509276680 ps
CPU time 135.41 seconds
Started Jul 21 07:04:35 PM PDT 24
Finished Jul 21 07:06:51 PM PDT 24
Peak memory 255880 kb
Host smart-9050c452-2474-46b8-91f7-d101c48fd4f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585846112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3585846112
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2376051970
Short name T939
Test name
Test status
Simulation time 3334554629 ps
CPU time 22.6 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 217112 kb
Host smart-409c4e81-d158-43a6-a895-15fa018c5186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376051970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2376051970
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3319212000
Short name T551
Test name
Test status
Simulation time 972496432 ps
CPU time 6.42 seconds
Started Jul 21 07:04:50 PM PDT 24
Finished Jul 21 07:04:58 PM PDT 24
Peak memory 216600 kb
Host smart-5c764ab7-8a8e-4c79-b46b-16ff0165626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319212000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3319212000
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2676758908
Short name T753
Test name
Test status
Simulation time 261626202 ps
CPU time 2.12 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 216556 kb
Host smart-e6212e3b-5ba5-4848-b8df-602162223e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676758908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2676758908
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3342149233
Short name T674
Test name
Test status
Simulation time 32283831 ps
CPU time 0.86 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 207296 kb
Host smart-7df17a39-d875-40b9-95ce-b0e1f78ea8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342149233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3342149233
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3526538551
Short name T410
Test name
Test status
Simulation time 13390390342 ps
CPU time 20.61 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:05:02 PM PDT 24
Peak memory 233216 kb
Host smart-e515038b-1761-4390-a96e-842e8f37c6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526538551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3526538551
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4136696667
Short name T322
Test name
Test status
Simulation time 31341238 ps
CPU time 0.77 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:37 PM PDT 24
Peak memory 205748 kb
Host smart-634fc85f-7c90-4d84-94a4-f04709bd770a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136696667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
136696667
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.469132028
Short name T844
Test name
Test status
Simulation time 423982337 ps
CPU time 7.85 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 224896 kb
Host smart-53e8760b-13f4-488f-84f2-7a8da5e6ef9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469132028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.469132028
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.314915516
Short name T393
Test name
Test status
Simulation time 31421647 ps
CPU time 0.79 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 206928 kb
Host smart-8dca74a5-0c0d-45e1-a922-f425eb7d40f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314915516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.314915516
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.591408589
Short name T53
Test name
Test status
Simulation time 3829954784 ps
CPU time 83.32 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 252552 kb
Host smart-66fc8449-0b5d-41bf-83e9-e77b35767e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591408589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.591408589
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3445390452
Short name T918
Test name
Test status
Simulation time 18626838075 ps
CPU time 211.56 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:07:09 PM PDT 24
Peak memory 249756 kb
Host smart-8db8cec3-afae-45ab-b322-727939ae8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445390452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3445390452
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1382449911
Short name T764
Test name
Test status
Simulation time 5286552469 ps
CPU time 10.99 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 241464 kb
Host smart-387062f4-cf38-493b-bf35-2b2e47b1a1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382449911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1382449911
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2282696478
Short name T172
Test name
Test status
Simulation time 36518778607 ps
CPU time 89.14 seconds
Started Jul 21 07:03:38 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 255708 kb
Host smart-fc86475f-870c-4e84-b7cb-cc89a1c01ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282696478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2282696478
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2324881888
Short name T44
Test name
Test status
Simulation time 172314067 ps
CPU time 2.29 seconds
Started Jul 21 07:03:28 PM PDT 24
Finished Jul 21 07:03:31 PM PDT 24
Peak memory 224944 kb
Host smart-215d9f1b-8dba-430d-8312-45fdf58f4ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324881888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2324881888
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1602903447
Short name T448
Test name
Test status
Simulation time 30875691334 ps
CPU time 81.18 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 220380 kb
Host smart-aa7fbd55-b22b-41cd-9e49-56e30099a2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602903447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1602903447
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1012952169
Short name T798
Test name
Test status
Simulation time 16515115 ps
CPU time 1.04 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 217116 kb
Host smart-6b697979-b725-4d08-8102-3546f5ff3968
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012952169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1012952169
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2708491472
Short name T76
Test name
Test status
Simulation time 75111728 ps
CPU time 2.07 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 223640 kb
Host smart-7794b08f-4c7a-4410-aa56-34e1c1c27d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708491472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2708491472
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1446451950
Short name T977
Test name
Test status
Simulation time 551116948 ps
CPU time 3.97 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 224940 kb
Host smart-7c43f3d7-b90a-4056-b5fd-7bd4a11d11ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446451950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1446451950
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2514564020
Short name T363
Test name
Test status
Simulation time 221264968 ps
CPU time 3.98 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 219260 kb
Host smart-58c82daf-2e6f-490e-ba86-80597af73eab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2514564020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2514564020
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3604649182
Short name T22
Test name
Test status
Simulation time 93392108 ps
CPU time 1.16 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 235884 kb
Host smart-6948ee93-0e3f-4f17-b4eb-08e425f0a84f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604649182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3604649182
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3889263302
Short name T343
Test name
Test status
Simulation time 2302593050 ps
CPU time 17.54 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 216924 kb
Host smart-acec9110-828b-4c3c-a221-5b415ad77916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889263302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3889263302
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2981787796
Short name T541
Test name
Test status
Simulation time 14403932 ps
CPU time 0.71 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 205868 kb
Host smart-1a45219e-fa1e-4456-a42a-9a371b558d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981787796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2981787796
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3226902223
Short name T302
Test name
Test status
Simulation time 222969149 ps
CPU time 3.25 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:37 PM PDT 24
Peak memory 216632 kb
Host smart-9015a4c7-479d-4d87-9ee0-65ccb53b6cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226902223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3226902223
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1881326510
Short name T871
Test name
Test status
Simulation time 38203123 ps
CPU time 0.87 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:03:41 PM PDT 24
Peak memory 206248 kb
Host smart-15eff169-ae13-4eb6-88df-8a1aa9bc7ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881326510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1881326510
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2583024609
Short name T429
Test name
Test status
Simulation time 8209807285 ps
CPU time 20.57 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 225084 kb
Host smart-80b0c9e2-1fd0-4c12-8515-49f0911a1443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583024609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2583024609
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.686270006
Short name T65
Test name
Test status
Simulation time 47332348 ps
CPU time 0.71 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 205756 kb
Host smart-2cf95ee4-e2d5-46d0-89d2-ac2277e85186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686270006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.686270006
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3953843134
Short name T856
Test name
Test status
Simulation time 145174058 ps
CPU time 3.02 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 233120 kb
Host smart-c2a1095d-3ee7-43d2-a771-11747c914ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953843134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3953843134
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1653151491
Short name T350
Test name
Test status
Simulation time 15376861 ps
CPU time 0.75 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:41 PM PDT 24
Peak memory 205776 kb
Host smart-d6b91e85-6dcb-4885-bd17-7ac15f726fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653151491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1653151491
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3793833815
Short name T558
Test name
Test status
Simulation time 1538088586 ps
CPU time 19.68 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 224824 kb
Host smart-806d8489-7422-46ac-ab42-c9cb69b1b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793833815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3793833815
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4100398361
Short name T624
Test name
Test status
Simulation time 14684121720 ps
CPU time 105.54 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:06:29 PM PDT 24
Peak memory 256540 kb
Host smart-a367e7e9-6c60-45bf-8e96-c4f9d5761715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100398361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4100398361
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3250259317
Short name T210
Test name
Test status
Simulation time 98274919597 ps
CPU time 237.22 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:08:42 PM PDT 24
Peak memory 251208 kb
Host smart-3f9d7b1e-a5af-49f2-93a6-396cc9e4e340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250259317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3250259317
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2848254804
Short name T945
Test name
Test status
Simulation time 440730225 ps
CPU time 8.19 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 224908 kb
Host smart-25ccb9b4-74ce-48ea-a7df-464b02fd9bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848254804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2848254804
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1476858739
Short name T260
Test name
Test status
Simulation time 11636949153 ps
CPU time 150.28 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:07:23 PM PDT 24
Peak memory 256976 kb
Host smart-4705de30-13e8-48e1-a89a-e84e6f531c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476858739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1476858739
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1592078242
Short name T126
Test name
Test status
Simulation time 125633388 ps
CPU time 4.21 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 233100 kb
Host smart-676bdd8b-017f-44d2-8823-95c57f7952e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592078242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1592078242
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3606441119
Short name T681
Test name
Test status
Simulation time 121346881 ps
CPU time 2.46 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 232952 kb
Host smart-567da240-690f-44cb-b420-814118456d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606441119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3606441119
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4092429959
Short name T11
Test name
Test status
Simulation time 8926736827 ps
CPU time 27.97 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:53 PM PDT 24
Peak memory 249432 kb
Host smart-2932752e-dee0-4f08-88d5-e4f5c12ab9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092429959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4092429959
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4131622802
Short name T221
Test name
Test status
Simulation time 1004316716 ps
CPU time 8.84 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 225044 kb
Host smart-4c3cb29a-d302-425d-bd23-7e1ac140dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131622802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4131622802
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3272749162
Short name T354
Test name
Test status
Simulation time 1031865548 ps
CPU time 11.08 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:04:58 PM PDT 24
Peak memory 222072 kb
Host smart-2d7d3c46-19a9-492d-9678-4e9eb29bf73e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3272749162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3272749162
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3672061920
Short name T185
Test name
Test status
Simulation time 26203130636 ps
CPU time 232.5 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:08:37 PM PDT 24
Peak memory 249756 kb
Host smart-331f724c-7bd5-4064-83b3-c930b6f60c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672061920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3672061920
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.506592340
Short name T644
Test name
Test status
Simulation time 1671809676 ps
CPU time 13.3 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 216748 kb
Host smart-88a80d87-5e30-4050-bae3-47867782cf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506592340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.506592340
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3218972284
Short name T679
Test name
Test status
Simulation time 8730329025 ps
CPU time 18.81 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 216888 kb
Host smart-288c5848-98d3-46c0-ab02-30054daf84fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218972284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3218972284
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3078474559
Short name T648
Test name
Test status
Simulation time 26492751 ps
CPU time 1.62 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 216656 kb
Host smart-033e8b7d-d4aa-4705-ab34-53367c9ebb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078474559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3078474559
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.444875096
Short name T666
Test name
Test status
Simulation time 39692358 ps
CPU time 0.81 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 206248 kb
Host smart-d6bcdae8-45e3-4e75-bab7-6b834ee0ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444875096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.444875096
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3527892262
Short name T215
Test name
Test status
Simulation time 5709343098 ps
CPU time 13.57 seconds
Started Jul 21 07:04:56 PM PDT 24
Finished Jul 21 07:05:10 PM PDT 24
Peak memory 225012 kb
Host smart-ea82e8a3-1c92-4657-9998-96a648a4bb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527892262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3527892262
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1196780014
Short name T582
Test name
Test status
Simulation time 49553566 ps
CPU time 0.74 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 206132 kb
Host smart-4fdc840c-0fb6-4586-b139-feb3d171c24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196780014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1196780014
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2178956335
Short name T495
Test name
Test status
Simulation time 58702191 ps
CPU time 2.6 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 233148 kb
Host smart-cd23eda5-427f-47be-8288-f9338357f64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178956335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2178956335
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3345690694
Short name T490
Test name
Test status
Simulation time 56077903 ps
CPU time 0.75 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 207244 kb
Host smart-87589ee6-1d17-4e14-9422-65de85b45f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345690694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3345690694
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3300236330
Short name T774
Test name
Test status
Simulation time 36011407847 ps
CPU time 76.87 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:06:00 PM PDT 24
Peak memory 252116 kb
Host smart-342a423d-67dc-49c2-8774-e4773b28757d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300236330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3300236330
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.597817377
Short name T286
Test name
Test status
Simulation time 880733131 ps
CPU time 12.37 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:05:06 PM PDT 24
Peak memory 218020 kb
Host smart-9bc9c02a-4313-4216-adef-98eaba7ee156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597817377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.597817377
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3381512350
Short name T202
Test name
Test status
Simulation time 28651199676 ps
CPU time 260.41 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:09:06 PM PDT 24
Peak memory 256100 kb
Host smart-54d66db6-f98d-404e-953e-c75174da72b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381512350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3381512350
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1559127679
Short name T751
Test name
Test status
Simulation time 105750920 ps
CPU time 2.86 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:45 PM PDT 24
Peak memory 233088 kb
Host smart-c4d6e6a7-6fa8-4d19-9dfc-dd541a0a4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559127679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1559127679
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4206415337
Short name T959
Test name
Test status
Simulation time 62730856464 ps
CPU time 162.2 seconds
Started Jul 21 07:04:43 PM PDT 24
Finished Jul 21 07:07:29 PM PDT 24
Peak memory 249896 kb
Host smart-d503a3a4-8562-4cdd-a965-299dfa960a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206415337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4206415337
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.214826007
Short name T776
Test name
Test status
Simulation time 35706438 ps
CPU time 2.38 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:04:47 PM PDT 24
Peak memory 232872 kb
Host smart-9da26db9-6866-4591-a3b4-c1e8b0331ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214826007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.214826007
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3357682853
Short name T933
Test name
Test status
Simulation time 11642604846 ps
CPU time 92.96 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 233188 kb
Host smart-117e2edf-64b0-43fe-bc47-38d84c09f586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357682853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3357682853
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3772708521
Short name T587
Test name
Test status
Simulation time 908079281 ps
CPU time 6.11 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 233004 kb
Host smart-5dcff194-4405-4833-b6f6-419c230bda3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772708521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3772708521
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.591496079
Short name T339
Test name
Test status
Simulation time 479345549 ps
CPU time 7.43 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:05:02 PM PDT 24
Peak memory 223604 kb
Host smart-5576468c-3ace-4c8b-ba6f-131835ee52bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=591496079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.591496079
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.863529133
Short name T17
Test name
Test status
Simulation time 2578995969 ps
CPU time 30.49 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 241484 kb
Host smart-0a6d7cd0-d67a-4b3e-8459-20036c67de89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863529133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.863529133
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1515542857
Short name T409
Test name
Test status
Simulation time 1329749088 ps
CPU time 9.97 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:05:34 PM PDT 24
Peak memory 216540 kb
Host smart-3b716031-aafc-48a3-ae31-9e6897c62ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515542857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1515542857
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.224668175
Short name T555
Test name
Test status
Simulation time 21294549415 ps
CPU time 7.45 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 216808 kb
Host smart-e7c5498a-5237-4858-95c0-72e9cb586540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224668175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.224668175
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3654169170
Short name T463
Test name
Test status
Simulation time 12973462 ps
CPU time 0.73 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:40 PM PDT 24
Peak memory 205928 kb
Host smart-0df9778a-910a-4759-9188-bed28901acd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654169170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3654169170
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1328901975
Short name T625
Test name
Test status
Simulation time 81836790 ps
CPU time 0.96 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 207304 kb
Host smart-99512b49-9d72-463f-94d1-f45bc2fd0c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328901975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1328901975
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1904407102
Short name T513
Test name
Test status
Simulation time 4151271950 ps
CPU time 14.27 seconds
Started Jul 21 07:04:50 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 233272 kb
Host smart-1ffedfdd-75e2-4ead-b131-444e9577c594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904407102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1904407102
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1501452835
Short name T700
Test name
Test status
Simulation time 31440369 ps
CPU time 0.71 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 206100 kb
Host smart-3fa7fdba-2357-4488-86f0-0ef9ad4a0e4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501452835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1501452835
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3297969799
Short name T318
Test name
Test status
Simulation time 126822083 ps
CPU time 2.52 seconds
Started Jul 21 07:04:39 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 224948 kb
Host smart-0e557d39-5aee-4382-a5c9-45d45603c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297969799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3297969799
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2591890473
Short name T313
Test name
Test status
Simulation time 144680074 ps
CPU time 0.81 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 206952 kb
Host smart-03613d29-9f02-45cd-b4d7-eb85099d60ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591890473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2591890473
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3953828526
Short name T253
Test name
Test status
Simulation time 84784375365 ps
CPU time 578.79 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:14:27 PM PDT 24
Peak memory 270336 kb
Host smart-3684a452-b427-4dbf-87f2-4256c9d4490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953828526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3953828526
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3489575740
Short name T956
Test name
Test status
Simulation time 1960551699 ps
CPU time 38.92 seconds
Started Jul 21 07:04:42 PM PDT 24
Finished Jul 21 07:05:24 PM PDT 24
Peak memory 249992 kb
Host smart-8b4cccb0-8a54-4da3-8179-fbd8eb8f6bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489575740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3489575740
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.731278563
Short name T505
Test name
Test status
Simulation time 65651000506 ps
CPU time 56.51 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 240296 kb
Host smart-62005b7f-9c93-435d-8e6a-49cdf54c19b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731278563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.731278563
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1841516589
Short name T593
Test name
Test status
Simulation time 1340954573 ps
CPU time 7.85 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 241396 kb
Host smart-056a6661-ca34-4299-b754-360b2046859e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841516589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1841516589
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2107354071
Short name T271
Test name
Test status
Simulation time 1040559477 ps
CPU time 23.5 seconds
Started Jul 21 07:05:01 PM PDT 24
Finished Jul 21 07:05:25 PM PDT 24
Peak memory 249564 kb
Host smart-b7b4f447-dac6-4256-9a47-4105e648fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107354071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2107354071
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.306982502
Short name T467
Test name
Test status
Simulation time 33404294 ps
CPU time 2.49 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 232852 kb
Host smart-3cdb5c50-e783-4254-808c-14d247722ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306982502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.306982502
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3800806164
Short name T480
Test name
Test status
Simulation time 1878913717 ps
CPU time 26.16 seconds
Started Jul 21 07:04:48 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 233284 kb
Host smart-ee389290-b698-4942-b13c-b24f77f2280f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800806164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3800806164
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.966947170
Short name T743
Test name
Test status
Simulation time 15455864352 ps
CPU time 11.79 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 224984 kb
Host smart-b52d7e6b-92cb-4a6d-afbe-775809530d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966947170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.966947170
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.71258985
Short name T839
Test name
Test status
Simulation time 12970271763 ps
CPU time 6.53 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 232592 kb
Host smart-8e867bad-1d1d-4aaf-a319-aab8a58a030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71258985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.71258985
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3274133984
Short name T398
Test name
Test status
Simulation time 820177478 ps
CPU time 4.71 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 220560 kb
Host smart-87d7d753-85ff-4452-b69a-9af2137ce78b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3274133984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3274133984
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1432348867
Short name T778
Test name
Test status
Simulation time 70641304 ps
CPU time 0.85 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 206140 kb
Host smart-7f8477d5-52b3-4b5e-894e-591776bfe040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432348867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1432348867
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3759581098
Short name T1011
Test name
Test status
Simulation time 1618576130 ps
CPU time 14.37 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 216688 kb
Host smart-b893cf62-c541-46cf-bbf1-519b7caab0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759581098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3759581098
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4191650252
Short name T703
Test name
Test status
Simulation time 1326091161 ps
CPU time 7.9 seconds
Started Jul 21 07:04:55 PM PDT 24
Finished Jul 21 07:05:04 PM PDT 24
Peak memory 216660 kb
Host smart-a518c73d-ee84-49fd-9eee-2381c5ebef47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191650252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4191650252
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.547883171
Short name T543
Test name
Test status
Simulation time 91222798 ps
CPU time 1.25 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 208296 kb
Host smart-03267250-0011-4f28-9e00-ca2e6f0bbc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547883171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.547883171
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1687128248
Short name T835
Test name
Test status
Simulation time 49888202 ps
CPU time 0.81 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 206252 kb
Host smart-d3e5a65c-df2c-46ab-92f4-97db7466f00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687128248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1687128248
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3668166533
Short name T535
Test name
Test status
Simulation time 457241497 ps
CPU time 10.7 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 250860 kb
Host smart-01adddaa-2f3e-434b-8b2a-37c6263d0f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668166533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3668166533
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2615809750
Short name T476
Test name
Test status
Simulation time 11453737 ps
CPU time 0.7 seconds
Started Jul 21 07:04:48 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 205164 kb
Host smart-ef430230-c581-411a-9b80-72ec239b4a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615809750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2615809750
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2418960994
Short name T85
Test name
Test status
Simulation time 604184930 ps
CPU time 3.52 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 224928 kb
Host smart-9c6acb2b-13c5-4af1-9075-23a44e31960e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418960994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2418960994
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3611136101
Short name T723
Test name
Test status
Simulation time 26661842 ps
CPU time 0.75 seconds
Started Jul 21 07:04:38 PM PDT 24
Finished Jul 21 07:04:40 PM PDT 24
Peak memory 205860 kb
Host smart-a8014374-91b5-4980-85be-0d36fee55d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611136101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3611136101
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1384429306
Short name T465
Test name
Test status
Simulation time 14457813107 ps
CPU time 109.64 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:06:49 PM PDT 24
Peak memory 249708 kb
Host smart-eaca3955-d793-4fbb-9d2e-242ececefab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384429306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1384429306
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1909986151
Short name T217
Test name
Test status
Simulation time 16757301315 ps
CPU time 77.26 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 254968 kb
Host smart-7bd5b9cc-e2c8-4911-8c3a-c5a055d2ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909986151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1909986151
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3021612932
Short name T279
Test name
Test status
Simulation time 6299196384 ps
CPU time 23.6 seconds
Started Jul 21 07:04:50 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 241448 kb
Host smart-670c123a-a153-4eff-88a3-0faa4ee08895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021612932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3021612932
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.99462316
Short name T675
Test name
Test status
Simulation time 23758962309 ps
CPU time 95.44 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:06:24 PM PDT 24
Peak memory 269720 kb
Host smart-559fd225-4f9d-4228-8a14-f7ca8368260e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99462316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.99462316
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1479213937
Short name T1004
Test name
Test status
Simulation time 264248440 ps
CPU time 4.36 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 224888 kb
Host smart-f3c47844-4e34-4cf6-aa5a-3e7f58c75f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479213937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1479213937
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1975427501
Short name T110
Test name
Test status
Simulation time 65750880 ps
CPU time 2.44 seconds
Started Jul 21 07:04:46 PM PDT 24
Finished Jul 21 07:04:51 PM PDT 24
Peak memory 233144 kb
Host smart-7de7603d-c7c9-43b0-8a5d-a18abe0c28db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975427501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1975427501
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3289586263
Short name T811
Test name
Test status
Simulation time 4110206792 ps
CPU time 8.11 seconds
Started Jul 21 07:04:40 PM PDT 24
Finished Jul 21 07:04:50 PM PDT 24
Peak memory 225044 kb
Host smart-32f04fc7-6032-4cad-a1a4-b3efc972ea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289586263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3289586263
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1544462839
Short name T552
Test name
Test status
Simulation time 2322326642 ps
CPU time 7.34 seconds
Started Jul 21 07:04:41 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 233364 kb
Host smart-08ffdd3d-7e9b-4ad5-8af1-bdaef2d43827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544462839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1544462839
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3471938876
Short name T685
Test name
Test status
Simulation time 105586241 ps
CPU time 4.07 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 223384 kb
Host smart-cde57ce5-9978-4be3-8e10-ba89b86711c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3471938876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3471938876
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2726662808
Short name T922
Test name
Test status
Simulation time 63636223098 ps
CPU time 164.35 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:07:34 PM PDT 24
Peak memory 249764 kb
Host smart-1c812b7c-ce24-48df-94db-f5c014bae60a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726662808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2726662808
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.632825275
Short name T616
Test name
Test status
Simulation time 5662138018 ps
CPU time 10.5 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 217176 kb
Host smart-96f64ba3-fab7-4091-8f8f-f4466ae4c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632825275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.632825275
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3605896346
Short name T58
Test name
Test status
Simulation time 1953313190 ps
CPU time 7.49 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 216660 kb
Host smart-1ed67b27-f9c4-4784-a655-b2b429ea917e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605896346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3605896346
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.625708605
Short name T970
Test name
Test status
Simulation time 170316386 ps
CPU time 1.13 seconds
Started Jul 21 07:04:44 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 208236 kb
Host smart-63a11576-76ff-42e0-954c-7c47f8ce581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625708605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.625708605
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4197124044
Short name T682
Test name
Test status
Simulation time 89361419 ps
CPU time 0.84 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:49 PM PDT 24
Peak memory 206320 kb
Host smart-6d6698f2-35f5-4a0e-bcb7-fb234a2782b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197124044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4197124044
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1368102471
Short name T359
Test name
Test status
Simulation time 1969741176 ps
CPU time 10.01 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 240992 kb
Host smart-da18f4c7-61d6-44cb-8b6a-6beded1a641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368102471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1368102471
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3760138966
Short name T327
Test name
Test status
Simulation time 30091249 ps
CPU time 0.73 seconds
Started Jul 21 07:04:57 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 205808 kb
Host smart-ab773abf-bf01-47e6-8f5f-91b6a9a801a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760138966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3760138966
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1152781256
Short name T882
Test name
Test status
Simulation time 168890820 ps
CPU time 2.61 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 233132 kb
Host smart-28cde0b1-a0b0-4e0b-86b3-9d5dbfb24cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152781256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1152781256
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.257125615
Short name T446
Test name
Test status
Simulation time 34500674 ps
CPU time 0.75 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 205896 kb
Host smart-810a238b-5856-4fb1-9780-43a29bc624fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257125615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.257125615
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3372508546
Short name T747
Test name
Test status
Simulation time 5613626985 ps
CPU time 44.32 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:05:43 PM PDT 24
Peak memory 249692 kb
Host smart-a7c5f76a-018d-41d2-98fc-ec47225092cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372508546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3372508546
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1612300893
Short name T373
Test name
Test status
Simulation time 3780934225 ps
CPU time 17.07 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:05:10 PM PDT 24
Peak memory 239180 kb
Host smart-b1edab64-e06c-4d41-887a-b4cbdc87bf71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612300893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1612300893
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.256746069
Short name T976
Test name
Test status
Simulation time 5944841856 ps
CPU time 40.15 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 240480 kb
Host smart-7c888203-3687-4d8a-8081-ee8e8379e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256746069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.256746069
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1935497318
Short name T569
Test name
Test status
Simulation time 298049112 ps
CPU time 7.8 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 235792 kb
Host smart-9dda2a79-6f40-4559-ad26-85e0d1e4e893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935497318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1935497318
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1838817171
Short name T526
Test name
Test status
Simulation time 2369389871 ps
CPU time 7.34 seconds
Started Jul 21 07:04:55 PM PDT 24
Finished Jul 21 07:05:04 PM PDT 24
Peak memory 233276 kb
Host smart-fca0a44d-196f-4308-9c78-929a216d19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838817171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1838817171
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.625922659
Short name T954
Test name
Test status
Simulation time 7739103423 ps
CPU time 83.83 seconds
Started Jul 21 07:04:49 PM PDT 24
Finished Jul 21 07:06:14 PM PDT 24
Peak memory 233252 kb
Host smart-2c39f0aa-dedb-457a-9e9b-d27737d23e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625922659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.625922659
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1937067114
Short name T611
Test name
Test status
Simulation time 940801770 ps
CPU time 8.19 seconds
Started Jul 21 07:04:45 PM PDT 24
Finished Jul 21 07:04:56 PM PDT 24
Peak memory 233136 kb
Host smart-b9d8b369-2749-407a-9d56-52bca63f789f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937067114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1937067114
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1013466387
Short name T403
Test name
Test status
Simulation time 419959697 ps
CPU time 3.94 seconds
Started Jul 21 07:04:57 PM PDT 24
Finished Jul 21 07:05:02 PM PDT 24
Peak memory 224956 kb
Host smart-3fa2a56a-4635-4cf5-9718-3aafafbad701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013466387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1013466387
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3807137576
Short name T441
Test name
Test status
Simulation time 10657932155 ps
CPU time 17.48 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:05:21 PM PDT 24
Peak memory 223580 kb
Host smart-8c650944-96be-4c66-b106-c053f5e735dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3807137576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3807137576
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1011515541
Short name T18
Test name
Test status
Simulation time 106483068 ps
CPU time 0.95 seconds
Started Jul 21 07:05:06 PM PDT 24
Finished Jul 21 07:05:07 PM PDT 24
Peak memory 207172 kb
Host smart-042bfebd-2b03-4d1a-85fb-f7c652a0f72d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011515541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1011515541
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.484471454
Short name T289
Test name
Test status
Simulation time 13575427753 ps
CPU time 21.58 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:05:14 PM PDT 24
Peak memory 216732 kb
Host smart-cf1db844-95e6-48b3-9983-eeb757798df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484471454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.484471454
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2064652278
Short name T7
Test name
Test status
Simulation time 3794171008 ps
CPU time 6.06 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 216820 kb
Host smart-f1bfd36c-e112-4961-8595-469c1ea7c400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064652278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2064652278
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3089489177
Short name T299
Test name
Test status
Simulation time 690239129 ps
CPU time 2.06 seconds
Started Jul 21 07:04:48 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 216624 kb
Host smart-361023a7-9fbe-42d5-954b-c4dd93a895f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089489177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3089489177
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1260582754
Short name T847
Test name
Test status
Simulation time 136374711 ps
CPU time 0.81 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 206340 kb
Host smart-d56771ed-73cc-4e17-a248-6fe99468f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260582754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1260582754
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1293122300
Short name T16
Test name
Test status
Simulation time 2659854104 ps
CPU time 8.56 seconds
Started Jul 21 07:04:47 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 224908 kb
Host smart-2313c8aa-f187-49b4-8217-9b4a9aefd3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293122300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1293122300
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2984393523
Short name T308
Test name
Test status
Simulation time 14015276 ps
CPU time 0.71 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 205188 kb
Host smart-056c5bd5-65bf-4b10-b803-f338e9a08e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984393523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2984393523
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4279000245
Short name T312
Test name
Test status
Simulation time 1230242946 ps
CPU time 5.01 seconds
Started Jul 21 07:05:05 PM PDT 24
Finished Jul 21 07:05:10 PM PDT 24
Peak memory 224924 kb
Host smart-f3d40a7f-2f29-4819-93c0-6a3df10f13b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279000245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4279000245
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2460633819
Short name T5
Test name
Test status
Simulation time 12776679 ps
CPU time 0.73 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:04:57 PM PDT 24
Peak memory 206024 kb
Host smart-22f6f937-406b-40e2-afc5-0c8c4609d7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460633819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2460633819
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.31196117
Short name T375
Test name
Test status
Simulation time 12481452316 ps
CPU time 16.89 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:05:10 PM PDT 24
Peak memory 238560 kb
Host smart-c384aec1-a1d4-49b2-9675-1f9f5716443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31196117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.31196117
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3887549920
Short name T184
Test name
Test status
Simulation time 19561484728 ps
CPU time 71.56 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:06:07 PM PDT 24
Peak memory 250512 kb
Host smart-f61517b9-9762-436a-a12a-266004f6ed68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887549920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3887549920
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2290413917
Short name T266
Test name
Test status
Simulation time 36987018078 ps
CPU time 340.5 seconds
Started Jul 21 07:04:55 PM PDT 24
Finished Jul 21 07:10:37 PM PDT 24
Peak memory 265632 kb
Host smart-e301d17e-0c00-41f7-9b15-eee57aa9ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290413917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2290413917
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1344466333
Short name T499
Test name
Test status
Simulation time 656757087 ps
CPU time 14.47 seconds
Started Jul 21 07:05:01 PM PDT 24
Finished Jul 21 07:05:16 PM PDT 24
Peak memory 233180 kb
Host smart-7b3c3dbb-4b27-42d7-abf2-615d97a1ddd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344466333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1344466333
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2827214694
Short name T575
Test name
Test status
Simulation time 81359618516 ps
CPU time 160.57 seconds
Started Jul 21 07:04:53 PM PDT 24
Finished Jul 21 07:07:35 PM PDT 24
Peak memory 264244 kb
Host smart-4639e969-1a3e-4664-a4b9-d48c68e48537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827214694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2827214694
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.287670764
Short name T834
Test name
Test status
Simulation time 22047791656 ps
CPU time 17.86 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 225116 kb
Host smart-0820146d-bca2-44c1-9955-d069ead1abb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287670764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.287670764
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.771584924
Short name T424
Test name
Test status
Simulation time 2021507209 ps
CPU time 16.57 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:20 PM PDT 24
Peak memory 241284 kb
Host smart-3c4fab37-f4ce-4756-ab44-3f5b86718920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771584924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.771584924
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1921250813
Short name T896
Test name
Test status
Simulation time 391495912 ps
CPU time 4.77 seconds
Started Jul 21 07:04:54 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 224952 kb
Host smart-bd3ccf0c-b96b-4585-8d77-6b3d772385c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921250813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1921250813
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2156665391
Short name T159
Test name
Test status
Simulation time 2082904682 ps
CPU time 10.16 seconds
Started Jul 21 07:04:50 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 233148 kb
Host smart-b6ffcb8a-6a86-439b-a20c-707fdef19fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156665391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2156665391
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.80561320
Short name T775
Test name
Test status
Simulation time 223343357 ps
CPU time 4.21 seconds
Started Jul 21 07:05:05 PM PDT 24
Finished Jul 21 07:05:09 PM PDT 24
Peak memory 222848 kb
Host smart-7d799a78-5063-4a64-844b-37c2920450a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=80561320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direc
t.80561320
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.254830558
Short name T33
Test name
Test status
Simulation time 117748180982 ps
CPU time 613.46 seconds
Started Jul 21 07:04:57 PM PDT 24
Finished Jul 21 07:15:12 PM PDT 24
Peak memory 282512 kb
Host smart-95a2e911-7c1f-49b7-b9cd-a48c2a4d03d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254830558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.254830558
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.620368995
Short name T883
Test name
Test status
Simulation time 15485720957 ps
CPU time 30.7 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 217024 kb
Host smart-a6250992-5b16-4118-9509-20168fa863dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620368995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.620368995
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.54364577
Short name T531
Test name
Test status
Simulation time 9008983647 ps
CPU time 14.05 seconds
Started Jul 21 07:04:57 PM PDT 24
Finished Jul 21 07:05:12 PM PDT 24
Peak memory 216840 kb
Host smart-208de6e9-7052-4b0f-8f66-ec292a8afdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54364577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.54364577
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2569987968
Short name T380
Test name
Test status
Simulation time 342975243 ps
CPU time 4.56 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:05:04 PM PDT 24
Peak memory 216680 kb
Host smart-9359f4a4-c2d7-4d19-a2c0-987378dc3323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569987968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2569987968
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3959541110
Short name T328
Test name
Test status
Simulation time 73352331 ps
CPU time 0.91 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:53 PM PDT 24
Peak memory 206272 kb
Host smart-fc4cd7f4-5f4b-4a00-b0d2-240c50bee17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959541110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3959541110
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.632846973
Short name T548
Test name
Test status
Simulation time 1040248635 ps
CPU time 8.96 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:05:01 PM PDT 24
Peak memory 240912 kb
Host smart-c071f278-cc5d-40a3-9b21-aa6b5d2f94b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632846973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.632846973
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3941435703
Short name T455
Test name
Test status
Simulation time 11500189 ps
CPU time 0.7 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:05:04 PM PDT 24
Peak memory 205708 kb
Host smart-13a0ee63-3088-4129-9a79-e3500012073a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941435703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3941435703
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.64557157
Short name T360
Test name
Test status
Simulation time 404825503 ps
CPU time 4.86 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:05:03 PM PDT 24
Peak memory 224908 kb
Host smart-f593875a-696f-4c5e-bbb9-45fb594811e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64557157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.64557157
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.339271296
Short name T633
Test name
Test status
Simulation time 17321131 ps
CPU time 0.79 seconds
Started Jul 21 07:05:04 PM PDT 24
Finished Jul 21 07:05:06 PM PDT 24
Peak memory 206188 kb
Host smart-2f10dd13-8485-4d09-ba81-d251997203eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339271296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.339271296
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1906281612
Short name T270
Test name
Test status
Simulation time 7672409534 ps
CPU time 100.33 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:06:43 PM PDT 24
Peak memory 257064 kb
Host smart-17dbc9a3-1cc0-4406-85ef-a51d1facc5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906281612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1906281612
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2327100966
Short name T27
Test name
Test status
Simulation time 7502684596 ps
CPU time 40.15 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 225060 kb
Host smart-4181c4af-4275-4a4f-ad6f-39e9cef53855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327100966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2327100966
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1378883389
Short name T213
Test name
Test status
Simulation time 17945297727 ps
CPU time 141.69 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:07:24 PM PDT 24
Peak memory 237228 kb
Host smart-849215df-bbc5-48f5-b4d5-ff404a8f6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378883389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1378883389
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2706184084
Short name T978
Test name
Test status
Simulation time 232953747 ps
CPU time 3.3 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:03 PM PDT 24
Peak memory 224976 kb
Host smart-0d8b63c2-4c6f-4818-8f22-dc21e77f5beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706184084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2706184084
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4265243211
Short name T1012
Test name
Test status
Simulation time 13135275595 ps
CPU time 164.6 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:07:48 PM PDT 24
Peak memory 269580 kb
Host smart-680cff4b-76f7-4589-ad83-b7098ae1a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265243211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4265243211
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1443695588
Short name T3
Test name
Test status
Simulation time 39050229 ps
CPU time 2.34 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:05:07 PM PDT 24
Peak memory 224940 kb
Host smart-1ccfe85d-dd34-4d37-9ccd-cbf477ce8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443695588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1443695588
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2704090800
Short name T800
Test name
Test status
Simulation time 2791789423 ps
CPU time 27.67 seconds
Started Jul 21 07:04:57 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 225092 kb
Host smart-c5dc9db1-2568-4749-a33f-5b1364a2a93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704090800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2704090800
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.811809180
Short name T979
Test name
Test status
Simulation time 273352445 ps
CPU time 3.74 seconds
Started Jul 21 07:04:55 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 225084 kb
Host smart-ed7187cd-2d27-46e6-8223-75b56dd3e8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811809180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.811809180
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2184498738
Short name T846
Test name
Test status
Simulation time 5418774640 ps
CPU time 11.85 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 233180 kb
Host smart-7da76b49-38de-441e-b8b0-5f07773da824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184498738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2184498738
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.982279328
Short name T756
Test name
Test status
Simulation time 185456609 ps
CPU time 3.82 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:07 PM PDT 24
Peak memory 220924 kb
Host smart-dd34bf06-b84f-49e6-aa1c-28323390c787
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982279328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.982279328
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1051790965
Short name T814
Test name
Test status
Simulation time 7925876400 ps
CPU time 18.88 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:19 PM PDT 24
Peak memory 216820 kb
Host smart-c4ece248-2a85-4bdd-ba03-0df506d827c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051790965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1051790965
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2030019728
Short name T789
Test name
Test status
Simulation time 1803479422 ps
CPU time 5.86 seconds
Started Jul 21 07:04:51 PM PDT 24
Finished Jul 21 07:04:58 PM PDT 24
Peak memory 216656 kb
Host smart-c6efed76-d507-4acd-b914-8905b1872b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030019728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2030019728
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2140344042
Short name T646
Test name
Test status
Simulation time 38311642 ps
CPU time 2.2 seconds
Started Jul 21 07:04:52 PM PDT 24
Finished Jul 21 07:04:55 PM PDT 24
Peak memory 216620 kb
Host smart-c9594de5-e27a-44cc-af88-fae483dbe473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140344042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2140344042
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2440398768
Short name T514
Test name
Test status
Simulation time 21442365 ps
CPU time 0.85 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:05:03 PM PDT 24
Peak memory 206360 kb
Host smart-9ca3993f-95a2-412e-9ba5-b9ab615f02b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440398768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2440398768
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1178908951
Short name T984
Test name
Test status
Simulation time 276297325 ps
CPU time 2.69 seconds
Started Jul 21 07:04:56 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 232808 kb
Host smart-2073fc64-56d6-4002-9c2d-99d15953a20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178908951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1178908951
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2544013321
Short name T673
Test name
Test status
Simulation time 12936772 ps
CPU time 0.75 seconds
Started Jul 21 07:05:13 PM PDT 24
Finished Jul 21 07:05:14 PM PDT 24
Peak memory 205756 kb
Host smart-1ee1e2c6-fa88-4d26-aed9-9544f8a6eb54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544013321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2544013321
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3247693243
Short name T479
Test name
Test status
Simulation time 1247176730 ps
CPU time 7.33 seconds
Started Jul 21 07:04:55 PM PDT 24
Finished Jul 21 07:05:04 PM PDT 24
Peak memory 233188 kb
Host smart-05cb5edd-5b48-4a27-bf48-ffb269526337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247693243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3247693243
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.488618916
Short name T392
Test name
Test status
Simulation time 35457217 ps
CPU time 0.78 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:04:59 PM PDT 24
Peak memory 206884 kb
Host smart-fa389ec7-24da-431b-8ddd-b9ba35cbb1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488618916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.488618916
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2424228964
Short name T884
Test name
Test status
Simulation time 135138176807 ps
CPU time 252.89 seconds
Started Jul 21 07:05:04 PM PDT 24
Finished Jul 21 07:09:18 PM PDT 24
Peak memory 266896 kb
Host smart-42ba60b3-4513-4c30-831b-757b44d6de69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424228964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2424228964
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3673448389
Short name T560
Test name
Test status
Simulation time 15209929907 ps
CPU time 62.24 seconds
Started Jul 21 07:04:58 PM PDT 24
Finished Jul 21 07:06:01 PM PDT 24
Peak memory 253672 kb
Host smart-ae5b30c9-b6f1-493b-97cf-d8c4527b39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673448389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3673448389
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1022172673
Short name T46
Test name
Test status
Simulation time 7008189628 ps
CPU time 50.07 seconds
Started Jul 21 07:05:06 PM PDT 24
Finished Jul 21 07:05:56 PM PDT 24
Peak memory 253528 kb
Host smart-af710f42-6ebb-438b-ba8a-57c43ef7dc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022172673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1022172673
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2374194747
Short name T732
Test name
Test status
Simulation time 325477019 ps
CPU time 3.85 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 233124 kb
Host smart-4bb0a5dd-c897-4f76-ad81-37ba96137f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374194747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2374194747
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3981760732
Short name T833
Test name
Test status
Simulation time 32033375225 ps
CPU time 223.34 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:08:56 PM PDT 24
Peak memory 257232 kb
Host smart-ce8f3fe5-3a63-4617-9fea-00fb3efef9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981760732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3981760732
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2255044944
Short name T400
Test name
Test status
Simulation time 2597785131 ps
CPU time 30.95 seconds
Started Jul 21 07:05:14 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 225072 kb
Host smart-9f51f221-80be-4df1-b78d-4571681fb224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255044944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2255044944
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3553020644
Short name T570
Test name
Test status
Simulation time 3115866680 ps
CPU time 11.33 seconds
Started Jul 21 07:04:59 PM PDT 24
Finished Jul 21 07:05:12 PM PDT 24
Peak memory 225032 kb
Host smart-6df0c84d-9515-4f32-bb7c-947f6228c248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553020644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3553020644
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2058554517
Short name T533
Test name
Test status
Simulation time 27869159 ps
CPU time 2.09 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:06 PM PDT 24
Peak memory 223220 kb
Host smart-fbe0609e-f0e4-4871-aa60-303ce86fee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058554517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2058554517
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2677767006
Short name T740
Test name
Test status
Simulation time 32398803317 ps
CPU time 14.6 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 233236 kb
Host smart-12b418fd-dfd3-4ed7-850f-d30e75bc39a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677767006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2677767006
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4231895070
Short name T838
Test name
Test status
Simulation time 963802884 ps
CPU time 5.12 seconds
Started Jul 21 07:05:02 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 222780 kb
Host smart-2aef9abf-629b-4231-a979-edbd50f9a96f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4231895070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4231895070
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2136429615
Short name T130
Test name
Test status
Simulation time 80087618622 ps
CPU time 475.79 seconds
Started Jul 21 07:05:08 PM PDT 24
Finished Jul 21 07:13:04 PM PDT 24
Peak memory 282528 kb
Host smart-2227753f-f594-45d0-b49c-a755e0fcca4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136429615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2136429615
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3292695764
Short name T968
Test name
Test status
Simulation time 2314632844 ps
CPU time 12.78 seconds
Started Jul 21 07:05:08 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 216800 kb
Host smart-e1565e39-fdf3-4f0c-b9bd-0e086454a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292695764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3292695764
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3969905880
Short name T309
Test name
Test status
Simulation time 2357484185 ps
CPU time 7.57 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:12 PM PDT 24
Peak memory 216776 kb
Host smart-2d8a5555-e72e-424a-af69-e8a2ffeb8f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969905880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3969905880
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.520356646
Short name T457
Test name
Test status
Simulation time 38227689 ps
CPU time 0.78 seconds
Started Jul 21 07:05:04 PM PDT 24
Finished Jul 21 07:05:05 PM PDT 24
Peak memory 206264 kb
Host smart-21da557c-6c60-4522-af91-199c140c51c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520356646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.520356646
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2085126408
Short name T1015
Test name
Test status
Simulation time 102795366 ps
CPU time 0.81 seconds
Started Jul 21 07:05:16 PM PDT 24
Finished Jul 21 07:05:18 PM PDT 24
Peak memory 206240 kb
Host smart-8e4079ff-fbaf-4f3f-a2a3-f326581a5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085126408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2085126408
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2081613927
Short name T825
Test name
Test status
Simulation time 253413581 ps
CPU time 3.27 seconds
Started Jul 21 07:04:56 PM PDT 24
Finished Jul 21 07:05:00 PM PDT 24
Peak memory 224968 kb
Host smart-b560de01-dcd7-4e42-891e-611376001066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081613927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2081613927
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2522581897
Short name T369
Test name
Test status
Simulation time 11389542 ps
CPU time 0.74 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:14 PM PDT 24
Peak memory 205200 kb
Host smart-486652d5-6d3a-4ac8-9d54-4cb94bbfba15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522581897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2522581897
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2639389782
Short name T32
Test name
Test status
Simulation time 78822139 ps
CPU time 2.33 seconds
Started Jul 21 07:05:10 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 224824 kb
Host smart-cf7d771f-bdf7-418c-b630-1d12181a5ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639389782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2639389782
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1514450068
Short name T615
Test name
Test status
Simulation time 31129805 ps
CPU time 0.75 seconds
Started Jul 21 07:05:07 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 207160 kb
Host smart-bd911ebc-fedd-4a51-8101-8acab558fad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514450068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1514450068
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.181142006
Short name T269
Test name
Test status
Simulation time 220348999225 ps
CPU time 282.17 seconds
Started Jul 21 07:05:05 PM PDT 24
Finished Jul 21 07:09:47 PM PDT 24
Peak memory 257252 kb
Host smart-fe387870-5b11-4c18-8fe2-f18cc8542df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181142006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.181142006
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1509338407
Short name T71
Test name
Test status
Simulation time 3435205862 ps
CPU time 81.59 seconds
Started Jul 21 07:05:17 PM PDT 24
Finished Jul 21 07:06:39 PM PDT 24
Peak memory 256720 kb
Host smart-592ab0b6-70ae-4da6-8f2b-56f32ffe6bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509338407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1509338407
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2420073945
Short name T512
Test name
Test status
Simulation time 3624821879 ps
CPU time 29.02 seconds
Started Jul 21 07:05:06 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 233292 kb
Host smart-cce1d24a-c93b-44c7-bbbd-719a63c30467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420073945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2420073945
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3940237863
Short name T481
Test name
Test status
Simulation time 1898690536 ps
CPU time 25.14 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 224964 kb
Host smart-7a6ba366-d321-412c-a032-1fdabc151deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940237863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3940237863
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1018280809
Short name T411
Test name
Test status
Simulation time 18914498255 ps
CPU time 67.67 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:06:23 PM PDT 24
Peak memory 257868 kb
Host smart-1f2b403d-cac7-4faa-8c1a-b6636f4aaac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018280809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1018280809
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2609505972
Short name T914
Test name
Test status
Simulation time 246829907 ps
CPU time 5.3 seconds
Started Jul 21 07:05:03 PM PDT 24
Finished Jul 21 07:05:09 PM PDT 24
Peak memory 224876 kb
Host smart-0e5c2138-6821-40ad-803e-efc9de71b685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609505972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2609505972
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.504681975
Short name T988
Test name
Test status
Simulation time 1496090003 ps
CPU time 5.37 seconds
Started Jul 21 07:05:16 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 224904 kb
Host smart-cb0b4ba7-b673-4aac-807c-f65f70950f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504681975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.504681975
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3868241264
Short name T314
Test name
Test status
Simulation time 867685669 ps
CPU time 2.31 seconds
Started Jul 21 07:05:11 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 223620 kb
Host smart-e3da9105-e482-4ab2-a3e3-db11b001fa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868241264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3868241264
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3321743422
Short name T222
Test name
Test status
Simulation time 306523549 ps
CPU time 3.55 seconds
Started Jul 21 07:05:07 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 224968 kb
Host smart-9376d2c6-36d8-4750-8875-bbe638f4fcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321743422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3321743422
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.564545620
Short name T868
Test name
Test status
Simulation time 519244734 ps
CPU time 6.41 seconds
Started Jul 21 07:05:22 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 223500 kb
Host smart-1cb98a9e-c85c-4daf-8514-a94cae753b28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=564545620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.564545620
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3191533563
Short name T274
Test name
Test status
Simulation time 882498386949 ps
CPU time 750.42 seconds
Started Jul 21 07:05:08 PM PDT 24
Finished Jul 21 07:17:39 PM PDT 24
Peak memory 282472 kb
Host smart-1f6165da-e7bd-4958-9a81-2ade833864d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191533563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3191533563
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3754757260
Short name T925
Test name
Test status
Simulation time 2417133286 ps
CPU time 4.17 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 216740 kb
Host smart-993bd5d1-c048-46f4-aa63-621b35656104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754757260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3754757260
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3083443422
Short name T757
Test name
Test status
Simulation time 35532582475 ps
CPU time 14.58 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 216752 kb
Host smart-0547207f-2f6f-4c33-81e8-cb62eb0d47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083443422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3083443422
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3199550581
Short name T376
Test name
Test status
Simulation time 401230443 ps
CPU time 3.24 seconds
Started Jul 21 07:05:18 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 216592 kb
Host smart-8e19b15e-87f4-40aa-b00b-e28fc873225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199550581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3199550581
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.511150465
Short name T942
Test name
Test status
Simulation time 90145693 ps
CPU time 1 seconds
Started Jul 21 07:05:10 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 207300 kb
Host smart-68aa8efc-f77b-4a1c-be33-aa4965454c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511150465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.511150465
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3546638201
Short name T801
Test name
Test status
Simulation time 772400514 ps
CPU time 2.19 seconds
Started Jul 21 07:05:23 PM PDT 24
Finished Jul 21 07:05:25 PM PDT 24
Peak memory 224496 kb
Host smart-797e2493-f2b7-443d-97b2-3b24496fc40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546638201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3546638201
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.101017879
Short name T948
Test name
Test status
Simulation time 16143872 ps
CPU time 0.78 seconds
Started Jul 21 07:05:16 PM PDT 24
Finished Jul 21 07:05:17 PM PDT 24
Peak memory 206108 kb
Host smart-659722e8-f1fb-4649-8ede-569f3f4e4b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101017879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.101017879
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1148539421
Short name T86
Test name
Test status
Simulation time 234046735 ps
CPU time 2.58 seconds
Started Jul 21 07:05:22 PM PDT 24
Finished Jul 21 07:05:25 PM PDT 24
Peak memory 224788 kb
Host smart-547308c1-563f-4c70-abdf-35e523eb0b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148539421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1148539421
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3583292006
Short name T547
Test name
Test status
Simulation time 21545011 ps
CPU time 0.87 seconds
Started Jul 21 07:05:04 PM PDT 24
Finished Jul 21 07:05:06 PM PDT 24
Peak memory 206904 kb
Host smart-e0080161-5517-4f54-aadc-93af6d856972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583292006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3583292006
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3582653171
Short name T955
Test name
Test status
Simulation time 5062332940 ps
CPU time 40.24 seconds
Started Jul 21 07:05:06 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 249732 kb
Host smart-b50c9c2b-8bdc-4b2f-acbf-952ebd2535c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582653171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3582653171
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2147452598
Short name T187
Test name
Test status
Simulation time 93712936624 ps
CPU time 237.16 seconds
Started Jul 21 07:05:08 PM PDT 24
Finished Jul 21 07:09:05 PM PDT 24
Peak memory 263700 kb
Host smart-2c7b3d37-6431-4c50-ba00-d4e33bdf0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147452598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2147452598
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.682694988
Short name T716
Test name
Test status
Simulation time 8078538559 ps
CPU time 55.57 seconds
Started Jul 21 07:05:22 PM PDT 24
Finished Jul 21 07:06:18 PM PDT 24
Peak memory 250700 kb
Host smart-4f8d8526-ac27-4450-b164-2a12a17c8ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682694988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.682694988
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1407359029
Short name T598
Test name
Test status
Simulation time 32504323 ps
CPU time 2.13 seconds
Started Jul 21 07:05:09 PM PDT 24
Finished Jul 21 07:05:12 PM PDT 24
Peak memory 224468 kb
Host smart-ab50e97b-2ff7-4df6-a200-773b68813562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407359029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1407359029
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.871692397
Short name T247
Test name
Test status
Simulation time 1497935908 ps
CPU time 14.36 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:27 PM PDT 24
Peak memory 224976 kb
Host smart-1739595a-739b-4aa7-9314-567114a5c814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871692397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.871692397
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1860377050
Short name T530
Test name
Test status
Simulation time 666823090 ps
CPU time 4.85 seconds
Started Jul 21 07:05:09 PM PDT 24
Finished Jul 21 07:05:14 PM PDT 24
Peak memory 224944 kb
Host smart-b19f715d-5da3-4b0b-af46-f7cd0139186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860377050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1860377050
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.924968237
Short name T251
Test name
Test status
Simulation time 2199718003 ps
CPU time 5.92 seconds
Started Jul 21 07:05:14 PM PDT 24
Finished Jul 21 07:05:20 PM PDT 24
Peak memory 233224 kb
Host smart-e463f63a-4137-48ea-971f-9fbcfc811943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924968237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.924968237
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1866270728
Short name T762
Test name
Test status
Simulation time 1395979097 ps
CPU time 15.77 seconds
Started Jul 21 07:05:13 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 219060 kb
Host smart-4bcfff08-0015-4674-bd08-3116b99e1a9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866270728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1866270728
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1736897083
Short name T712
Test name
Test status
Simulation time 778640940 ps
CPU time 6.16 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 216680 kb
Host smart-f12c15ec-1ec5-47ee-a553-0af7597b255a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736897083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1736897083
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3050187142
Short name T894
Test name
Test status
Simulation time 2537545790 ps
CPU time 3.94 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:05:24 PM PDT 24
Peak memory 216812 kb
Host smart-ceac11a4-3884-454f-b300-fdb5653b0b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050187142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3050187142
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2888532892
Short name T475
Test name
Test status
Simulation time 50449760 ps
CPU time 2.08 seconds
Started Jul 21 07:05:21 PM PDT 24
Finished Jul 21 07:05:24 PM PDT 24
Peak memory 216728 kb
Host smart-ba8e0f47-ccc8-4504-a83b-e00459c446f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888532892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2888532892
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1169863780
Short name T612
Test name
Test status
Simulation time 141462235 ps
CPU time 0.74 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 206376 kb
Host smart-481297b2-686e-401f-9f88-dc5d6c28e15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169863780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1169863780
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.950440642
Short name T1008
Test name
Test status
Simulation time 11070400451 ps
CPU time 15.16 seconds
Started Jul 21 07:05:18 PM PDT 24
Finished Jul 21 07:05:34 PM PDT 24
Peak memory 251616 kb
Host smart-6c58f8e1-c360-406b-bd0b-3fe6ae21c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950440642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.950440642
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3234614188
Short name T655
Test name
Test status
Simulation time 13475122 ps
CPU time 0.73 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:45 PM PDT 24
Peak memory 205172 kb
Host smart-d7399851-f139-43b6-a3b5-2979b8bd51fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234614188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
234614188
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2978686956
Short name T391
Test name
Test status
Simulation time 131240697 ps
CPU time 2.13 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 224980 kb
Host smart-dc2e8dbe-5c7b-43da-9c2e-51996b868335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978686956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2978686956
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2406773401
Short name T557
Test name
Test status
Simulation time 65650010 ps
CPU time 0.8 seconds
Started Jul 21 07:03:25 PM PDT 24
Finished Jul 21 07:03:26 PM PDT 24
Peak memory 206904 kb
Host smart-99d34b27-4a8a-4de4-91e0-a64e9c310f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406773401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2406773401
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3907289908
Short name T772
Test name
Test status
Simulation time 3671548727 ps
CPU time 65.12 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:04:44 PM PDT 24
Peak memory 254768 kb
Host smart-391451c5-efd4-478e-9332-150e4393c282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907289908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3907289908
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2903456538
Short name T796
Test name
Test status
Simulation time 9715507747 ps
CPU time 118.75 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:05:41 PM PDT 24
Peak memory 266084 kb
Host smart-c7b848f7-315a-44cb-b2de-8e1a966822e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903456538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2903456538
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1273346928
Short name T698
Test name
Test status
Simulation time 21254976805 ps
CPU time 47.37 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 241488 kb
Host smart-5bcf73c4-438f-4cab-94cf-ebcdf859126a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273346928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1273346928
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.833022427
Short name T307
Test name
Test status
Simulation time 7647217566 ps
CPU time 31.88 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:04:04 PM PDT 24
Peak memory 240680 kb
Host smart-23ea75a8-08b7-4396-84e4-ca02e6901bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833022427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.833022427
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2823988871
Short name T707
Test name
Test status
Simulation time 16224944290 ps
CPU time 92.73 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 257252 kb
Host smart-f8ed31ad-6a12-4c2d-b2c8-71508f2d5e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823988871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2823988871
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3426848300
Short name T684
Test name
Test status
Simulation time 303775703 ps
CPU time 5.19 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 233132 kb
Host smart-98be5758-d658-44e1-ad39-e30127614197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426848300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3426848300
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.102065971
Short name T741
Test name
Test status
Simulation time 3253551480 ps
CPU time 14.08 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 239600 kb
Host smart-062c85c0-f2e6-4e90-9164-215d4edd4473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102065971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.102065971
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.848800914
Short name T515
Test name
Test status
Simulation time 245620614 ps
CPU time 1.1 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:39 PM PDT 24
Peak memory 217220 kb
Host smart-037c8944-dc9f-4004-bcc4-b028357cb72f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848800914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.848800914
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1280582880
Short name T315
Test name
Test status
Simulation time 136001366 ps
CPU time 2.3 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:38 PM PDT 24
Peak memory 223584 kb
Host smart-da9a3ada-57c4-4b62-913e-1a37daf3a3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280582880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1280582880
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2249504725
Short name T581
Test name
Test status
Simulation time 2196089647 ps
CPU time 8.44 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 233280 kb
Host smart-f3a82dd0-35fc-4762-9159-5815daa0bb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249504725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2249504725
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1967853414
Short name T891
Test name
Test status
Simulation time 1053657556 ps
CPU time 5.29 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 223416 kb
Host smart-12ae454c-8413-4995-aef1-54e16f493471
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1967853414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1967853414
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1412977083
Short name T69
Test name
Test status
Simulation time 134095660 ps
CPU time 1.17 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 236204 kb
Host smart-cd6f21e7-4d24-4dd0-bcc7-387ada94e7fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412977083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1412977083
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1088391438
Short name T423
Test name
Test status
Simulation time 22353036429 ps
CPU time 220.82 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:07:19 PM PDT 24
Peak memory 247856 kb
Host smart-365eb326-d819-4b64-8e17-542db58f6701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088391438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1088391438
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1329743135
Short name T672
Test name
Test status
Simulation time 4714719930 ps
CPU time 25.55 seconds
Started Jul 21 07:03:28 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 216892 kb
Host smart-16abc785-faa2-4752-b453-0228f3d5f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329743135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1329743135
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3542088741
Short name T405
Test name
Test status
Simulation time 1373063713 ps
CPU time 1.65 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:03:41 PM PDT 24
Peak memory 207452 kb
Host smart-4ff878e9-2626-48c3-aadf-801efa457301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542088741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3542088741
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2757645588
Short name T858
Test name
Test status
Simulation time 714826839 ps
CPU time 8.24 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 216680 kb
Host smart-58961d1b-8580-433c-b469-fcd7a85a5bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757645588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2757645588
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1740576932
Short name T963
Test name
Test status
Simulation time 193149980 ps
CPU time 0.86 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:38 PM PDT 24
Peak memory 207324 kb
Host smart-ba423034-05b1-4e38-b099-b9b3cc74381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740576932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1740576932
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4235985076
Short name T823
Test name
Test status
Simulation time 3900977727 ps
CPU time 15.5 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:59 PM PDT 24
Peak memory 233260 kb
Host smart-562e91bb-e0af-44a1-a91b-df929827eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235985076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4235985076
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1602026586
Short name T927
Test name
Test status
Simulation time 11637910 ps
CPU time 0.7 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 206140 kb
Host smart-4f1d181b-84f1-44f3-9f9a-8ec53f3f213c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602026586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1602026586
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.257818498
Short name T926
Test name
Test status
Simulation time 2343982053 ps
CPU time 21.15 seconds
Started Jul 21 07:05:22 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 225032 kb
Host smart-8daec055-4733-4d07-91e5-c465679da559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257818498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.257818498
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.330588800
Short name T971
Test name
Test status
Simulation time 62224368 ps
CPU time 0.78 seconds
Started Jul 21 07:05:17 PM PDT 24
Finished Jul 21 07:05:18 PM PDT 24
Peak memory 205872 kb
Host smart-db09e0de-71f8-4eeb-811e-a5c267b1ce35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330588800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.330588800
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.4008540563
Short name T200
Test name
Test status
Simulation time 2701359220 ps
CPU time 56.81 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:06:21 PM PDT 24
Peak memory 256768 kb
Host smart-fe91bacc-1d52-4061-a3dc-e382f1679728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008540563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.4008540563
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2035287129
Short name T258
Test name
Test status
Simulation time 37829130487 ps
CPU time 327.67 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:10:52 PM PDT 24
Peak memory 241528 kb
Host smart-93ba3cb8-d5b1-41e0-8c17-568350c35b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035287129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2035287129
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1935416064
Short name T72
Test name
Test status
Simulation time 1224980742 ps
CPU time 16.81 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 224948 kb
Host smart-d8222a42-2ca6-4ea3-adad-15ded70b72d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935416064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1935416064
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2878904517
Short name T938
Test name
Test status
Simulation time 6195786918 ps
CPU time 41.25 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:05:57 PM PDT 24
Peak memory 254768 kb
Host smart-af80d862-0a0d-4760-b48f-9138e80b0987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878904517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2878904517
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3601400007
Short name T428
Test name
Test status
Simulation time 265484749 ps
CPU time 5.75 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 233196 kb
Host smart-f2f47444-6791-4ae4-8db4-ee33450a35dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601400007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3601400007
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3518592714
Short name T191
Test name
Test status
Simulation time 2327700866 ps
CPU time 19.08 seconds
Started Jul 21 07:05:13 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 224976 kb
Host smart-a8c0cbfa-9559-4a30-b221-ea12cbb0fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518592714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3518592714
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.843965831
Short name T257
Test name
Test status
Simulation time 1738053498 ps
CPU time 6.88 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 233148 kb
Host smart-1fbeba2b-7d05-4f6b-90eb-a1ddeae9d462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843965831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.843965831
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.17191543
Short name T205
Test name
Test status
Simulation time 1236669510 ps
CPU time 4.91 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:05:20 PM PDT 24
Peak memory 233080 kb
Host smart-79fe267f-351d-42ff-954e-265ca8e6871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17191543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.17191543
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3319766546
Short name T469
Test name
Test status
Simulation time 3617498107 ps
CPU time 10.13 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 219384 kb
Host smart-a91c5033-fcb0-4a18-8734-9d9d9fd350bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3319766546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3319766546
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2454644278
Short name T699
Test name
Test status
Simulation time 175827238195 ps
CPU time 490.33 seconds
Started Jul 21 07:05:17 PM PDT 24
Finished Jul 21 07:13:28 PM PDT 24
Peak memory 274272 kb
Host smart-bfc6a603-9faf-4fa5-895d-988cda220c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454644278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2454644278
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2668358008
Short name T718
Test name
Test status
Simulation time 7243896340 ps
CPU time 17.38 seconds
Started Jul 21 07:05:18 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 217204 kb
Host smart-9ec21338-ad93-43c9-ace7-7ba2e1b85beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668358008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2668358008
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2887033537
Short name T509
Test name
Test status
Simulation time 5400984287 ps
CPU time 17.59 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 216832 kb
Host smart-94512393-b824-437f-912d-ed8ae571c875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887033537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2887033537
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2720910253
Short name T705
Test name
Test status
Simulation time 41815641 ps
CPU time 1.23 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 208456 kb
Host smart-183d7f02-9789-4eaf-ab8f-40cd67a5ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720910253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2720910253
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1031968861
Short name T1020
Test name
Test status
Simulation time 22444778 ps
CPU time 0.8 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 206328 kb
Host smart-46158a2b-324f-42ef-8282-ba32a309e1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031968861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1031968861
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.561269286
Short name T996
Test name
Test status
Simulation time 13771930759 ps
CPU time 12.74 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 233300 kb
Host smart-9f712a1c-0744-4d76-92b8-b486b9c5f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561269286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.561269286
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1136541714
Short name T763
Test name
Test status
Simulation time 58847022 ps
CPU time 0.73 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 205644 kb
Host smart-b26021a2-a01f-4570-9c2c-a052b5e76b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136541714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1136541714
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.172227740
Short name T56
Test name
Test status
Simulation time 863932942 ps
CPU time 9.25 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 233128 kb
Host smart-d672188b-b642-49d2-8d90-90892c70f73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172227740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.172227740
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1898614335
Short name T999
Test name
Test status
Simulation time 24075677 ps
CPU time 0.75 seconds
Started Jul 21 07:05:12 PM PDT 24
Finished Jul 21 07:05:14 PM PDT 24
Peak memory 205880 kb
Host smart-853ba98f-a542-4953-bcc8-a39f8a6bc95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898614335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1898614335
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3303279865
Short name T991
Test name
Test status
Simulation time 33449501164 ps
CPU time 96.59 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:06:52 PM PDT 24
Peak memory 254660 kb
Host smart-30687ed1-1436-4f9e-8e64-aa7dab10d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303279865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3303279865
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.218276973
Short name T244
Test name
Test status
Simulation time 69182335828 ps
CPU time 138.98 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:07:51 PM PDT 24
Peak memory 249724 kb
Host smart-66a075bf-f019-4d1b-8bf7-0cc9c6688522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218276973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.218276973
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3444377116
Short name T177
Test name
Test status
Simulation time 33688712192 ps
CPU time 349.41 seconds
Started Jul 21 07:05:16 PM PDT 24
Finished Jul 21 07:11:06 PM PDT 24
Peak memory 257156 kb
Host smart-8f231164-0b35-4fd3-a66a-88203d3d4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444377116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3444377116
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2408110733
Short name T136
Test name
Test status
Simulation time 19434949889 ps
CPU time 33.5 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:06:07 PM PDT 24
Peak memory 252600 kb
Host smart-1e495e1e-daea-4921-b37b-74954957e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408110733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2408110733
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2414857778
Short name T40
Test name
Test status
Simulation time 239290869607 ps
CPU time 93.37 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:07:00 PM PDT 24
Peak memory 254464 kb
Host smart-d5692c6d-d655-4b52-a6e5-0783dc1fcef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414857778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2414857778
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2030536040
Short name T497
Test name
Test status
Simulation time 368231314 ps
CPU time 5.93 seconds
Started Jul 21 07:05:22 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 233036 kb
Host smart-b5059f61-0187-43a5-ba76-5d1e3eab797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030536040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2030536040
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.209875486
Short name T923
Test name
Test status
Simulation time 443602034 ps
CPU time 6.35 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 233208 kb
Host smart-f0bfa95c-875c-4883-9017-6b8fdfeafc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209875486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.209875486
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3606640053
Short name T24
Test name
Test status
Simulation time 354870923 ps
CPU time 2.22 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:28 PM PDT 24
Peak memory 223268 kb
Host smart-a528d46b-0d88-4293-b6e3-86698c90d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606640053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3606640053
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.825567136
Short name T650
Test name
Test status
Simulation time 2563271004 ps
CPU time 3.15 seconds
Started Jul 21 07:05:13 PM PDT 24
Finished Jul 21 07:05:17 PM PDT 24
Peak memory 228788 kb
Host smart-eaf170ff-95e6-49f9-8f92-bc4ddf1a691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825567136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.825567136
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1365024339
Short name T139
Test name
Test status
Simulation time 2942041983 ps
CPU time 8.62 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:43 PM PDT 24
Peak memory 220720 kb
Host smart-059ecfb7-1ce7-423d-8d25-47f915182558
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1365024339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1365024339
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.320157573
Short name T1009
Test name
Test status
Simulation time 1842815286 ps
CPU time 19.55 seconds
Started Jul 21 07:05:18 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 216904 kb
Host smart-64f3bc16-a56a-4c76-927f-7f004a79d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320157573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.320157573
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1022756958
Short name T366
Test name
Test status
Simulation time 5989838517 ps
CPU time 5.12 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 216800 kb
Host smart-da8e5736-9de5-4603-9e09-b8ae94bfac6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022756958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1022756958
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1367139589
Short name T609
Test name
Test status
Simulation time 524537065 ps
CPU time 1.5 seconds
Started Jul 21 07:05:11 PM PDT 24
Finished Jul 21 07:05:13 PM PDT 24
Peak memory 216692 kb
Host smart-a70cba87-0b0d-46c7-a367-0aaba2686944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367139589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1367139589
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1563948209
Short name T600
Test name
Test status
Simulation time 31404216 ps
CPU time 0.76 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 206324 kb
Host smart-9b6f6e8e-d10f-4fe4-ad0c-63e71f9b63df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563948209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1563948209
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2708953191
Short name T770
Test name
Test status
Simulation time 31053465094 ps
CPU time 24.34 seconds
Started Jul 21 07:05:19 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 233168 kb
Host smart-9c65538f-6fdd-4d07-b6e8-cb4f6b8bbeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708953191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2708953191
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3294519135
Short name T686
Test name
Test status
Simulation time 49496337 ps
CPU time 0.7 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:32 PM PDT 24
Peak memory 205224 kb
Host smart-51e9cb03-4d5e-4837-b77e-7fc4b7208093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294519135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3294519135
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4070822074
Short name T722
Test name
Test status
Simulation time 651192659 ps
CPU time 2.27 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 233128 kb
Host smart-e055fad0-8149-4869-b801-79b21bb2f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070822074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4070822074
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.428597007
Short name T578
Test name
Test status
Simulation time 17899850 ps
CPU time 0.78 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:27 PM PDT 24
Peak memory 206868 kb
Host smart-5d2e859a-1458-487c-818d-ccd9bf9803fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428597007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.428597007
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3282436050
Short name T877
Test name
Test status
Simulation time 6681536830 ps
CPU time 22.3 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 241452 kb
Host smart-c3bf535a-7ecd-49dd-92c0-db2036c8dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282436050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3282436050
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1501468184
Short name T898
Test name
Test status
Simulation time 6651432360 ps
CPU time 145.73 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:07:55 PM PDT 24
Peak memory 265056 kb
Host smart-9276710c-b5b4-495a-8eef-111c8b25503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501468184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1501468184
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2702614155
Short name T870
Test name
Test status
Simulation time 42362856892 ps
CPU time 103.73 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:07:12 PM PDT 24
Peak memory 257096 kb
Host smart-c32cf4c6-a47e-4153-b6f1-9d314259b4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702614155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2702614155
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4213597236
Short name T542
Test name
Test status
Simulation time 573998293 ps
CPU time 3.8 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 224916 kb
Host smart-d8178406-0fbc-4862-97ab-718a3fdbce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213597236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4213597236
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.914699118
Short name T767
Test name
Test status
Simulation time 17603960026 ps
CPU time 126.47 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:07:38 PM PDT 24
Peak memory 250100 kb
Host smart-b7c88339-5f60-48f9-ab77-5773f5578dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914699118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.914699118
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1684081635
Short name T989
Test name
Test status
Simulation time 287597809 ps
CPU time 5.07 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 233180 kb
Host smart-7520c5f8-f91e-4bb9-831d-25ba8ed44b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684081635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1684081635
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1468789034
Short name T588
Test name
Test status
Simulation time 20887374183 ps
CPU time 19.16 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:47 PM PDT 24
Peak memory 251348 kb
Host smart-c070262a-cd9e-4dff-8c71-90de81bb0cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468789034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1468789034
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.180832567
Short name T873
Test name
Test status
Simulation time 1481165170 ps
CPU time 8.37 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 240932 kb
Host smart-79910142-fcd9-4651-b8bb-2f32cc8bdfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180832567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.180832567
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1077124747
Short name T628
Test name
Test status
Simulation time 5254609755 ps
CPU time 6.88 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:05:23 PM PDT 24
Peak memory 225088 kb
Host smart-d6b3a38c-5652-4ba1-8800-08ff83966c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077124747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1077124747
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2478866528
Short name T534
Test name
Test status
Simulation time 4465997017 ps
CPU time 11.97 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:48 PM PDT 24
Peak memory 223160 kb
Host smart-3fd06e77-9d74-4f1a-a1f7-4a843ee15904
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2478866528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2478866528
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3952310149
Short name T259
Test name
Test status
Simulation time 29906890702 ps
CPU time 301.97 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:10:18 PM PDT 24
Peak memory 254364 kb
Host smart-41044065-5b36-4fbf-8882-bccf27e70773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952310149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3952310149
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1470529917
Short name T290
Test name
Test status
Simulation time 3397889291 ps
CPU time 22.42 seconds
Started Jul 21 07:05:19 PM PDT 24
Finished Jul 21 07:05:41 PM PDT 24
Peak memory 217012 kb
Host smart-c76c91dc-3e34-4a89-bb0b-d7a2544d109f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470529917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1470529917
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3720162605
Short name T758
Test name
Test status
Simulation time 5419657424 ps
CPU time 8.44 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:41 PM PDT 24
Peak memory 216744 kb
Host smart-c1f0f721-6e9a-4133-a825-c25e555c4109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720162605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3720162605
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1096134538
Short name T589
Test name
Test status
Simulation time 421323006 ps
CPU time 5.32 seconds
Started Jul 21 07:05:15 PM PDT 24
Finished Jul 21 07:05:21 PM PDT 24
Peak memory 216728 kb
Host smart-390e3e5c-56f4-447e-b090-8dd06431476e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096134538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1096134538
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2944065866
Short name T875
Test name
Test status
Simulation time 316158866 ps
CPU time 0.92 seconds
Started Jul 21 07:05:16 PM PDT 24
Finished Jul 21 07:05:18 PM PDT 24
Peak memory 206260 kb
Host smart-20ad394a-ff20-45e1-b4df-6d885f41aa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944065866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2944065866
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.654446871
Short name T433
Test name
Test status
Simulation time 847402980 ps
CPU time 10.34 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:43 PM PDT 24
Peak memory 241356 kb
Host smart-f0c6c48b-617f-4810-a9c8-f844dd12667a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654446871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.654446871
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.177052851
Short name T331
Test name
Test status
Simulation time 11619515 ps
CPU time 0.72 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 206076 kb
Host smart-35acaef3-025a-4e52-941a-efdb2fad0c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177052851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.177052851
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.628102528
Short name T521
Test name
Test status
Simulation time 16608522 ps
CPU time 0.79 seconds
Started Jul 21 07:05:19 PM PDT 24
Finished Jul 21 07:05:20 PM PDT 24
Peak memory 206960 kb
Host smart-66b004f7-bf44-4cd7-8e6b-063577c2f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628102528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.628102528
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2722742626
Short name T153
Test name
Test status
Simulation time 1913208357 ps
CPU time 14.61 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:49 PM PDT 24
Peak memory 236696 kb
Host smart-e36878e7-1bc5-46cc-9d07-7b0b6b109a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722742626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2722742626
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1890132273
Short name T416
Test name
Test status
Simulation time 18832468495 ps
CPU time 180.06 seconds
Started Jul 21 07:05:21 PM PDT 24
Finished Jul 21 07:08:22 PM PDT 24
Peak memory 257596 kb
Host smart-d3362d50-d0e8-4f2c-90e2-2ae81673dd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890132273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1890132273
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3743789997
Short name T677
Test name
Test status
Simulation time 3194948443 ps
CPU time 27.45 seconds
Started Jul 21 07:05:23 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 236536 kb
Host smart-e8e9b5e6-0221-4971-844b-cc2fd9863f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743789997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3743789997
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1188241460
Short name T603
Test name
Test status
Simulation time 1743188105 ps
CPU time 7.96 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 241204 kb
Host smart-e3a824af-d0e9-4fbf-9991-f493b5d3b87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188241460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1188241460
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.992811590
Short name T665
Test name
Test status
Simulation time 7606896504 ps
CPU time 53.1 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:06:25 PM PDT 24
Peak memory 251036 kb
Host smart-d8131a55-49f8-44e1-b3a8-a9431b7679b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992811590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.992811590
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4045496600
Short name T368
Test name
Test status
Simulation time 32666233 ps
CPU time 2.37 seconds
Started Jul 21 07:05:19 PM PDT 24
Finished Jul 21 07:05:22 PM PDT 24
Peak memory 232900 kb
Host smart-68e7f921-b337-47d8-939c-a9060acb475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045496600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4045496600
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2875220821
Short name T735
Test name
Test status
Simulation time 2799447363 ps
CPU time 29.75 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:56 PM PDT 24
Peak memory 225092 kb
Host smart-104235ee-05ef-492f-bc2e-6d1ba4153156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875220821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2875220821
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.644356377
Short name T850
Test name
Test status
Simulation time 6828106506 ps
CPU time 9.97 seconds
Started Jul 21 07:05:34 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 225044 kb
Host smart-aa9ab1f7-5f16-4a07-b507-5d00f9566ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644356377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.644356377
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2717278615
Short name T477
Test name
Test status
Simulation time 106806761 ps
CPU time 2.25 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 223332 kb
Host smart-d75fc084-6e32-4a0c-bacb-890c2f807f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717278615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2717278615
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2988842045
Short name T912
Test name
Test status
Simulation time 410877660 ps
CPU time 3.84 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 223000 kb
Host smart-a78e1ecd-8d57-4bd0-9dbe-046d723c79bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2988842045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2988842045
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.61917795
Short name T147
Test name
Test status
Simulation time 16044469282 ps
CPU time 72.25 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:06:32 PM PDT 24
Peak memory 256008 kb
Host smart-933d2d60-84b0-4bee-a79b-cd6866373dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61917795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress
_all.61917795
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.22143041
Short name T934
Test name
Test status
Simulation time 6380618481 ps
CPU time 37.67 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:06:08 PM PDT 24
Peak memory 216884 kb
Host smart-375223b8-1bba-4f6f-9f5d-af1226e95a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22143041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.22143041
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3539324654
Short name T857
Test name
Test status
Simulation time 9953817529 ps
CPU time 23.02 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:59 PM PDT 24
Peak memory 216692 kb
Host smart-7d4d466a-5fc6-4226-8f73-f728eccb5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539324654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3539324654
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1080748993
Short name T627
Test name
Test status
Simulation time 21606263 ps
CPU time 1.07 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 207780 kb
Host smart-b4e2843e-0f1e-4043-9fbc-6acfc74306ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080748993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1080748993
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2724121067
Short name T975
Test name
Test status
Simulation time 281277814 ps
CPU time 0.93 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 206280 kb
Host smart-42da0647-584a-49cb-a587-44f3a44f50e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724121067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2724121067
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4135893865
Short name T909
Test name
Test status
Simulation time 475609188 ps
CPU time 2.99 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 224908 kb
Host smart-7b2512ae-3fb3-4915-8ea4-1e5e2c41cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135893865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4135893865
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2793852991
Short name T352
Test name
Test status
Simulation time 13365172 ps
CPU time 0.73 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 205764 kb
Host smart-490841cf-110f-41c3-a10f-d05ff3b4056a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793852991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2793852991
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3498660527
Short name T890
Test name
Test status
Simulation time 2580988357 ps
CPU time 17.27 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 233288 kb
Host smart-fdad57e2-3042-4272-bfd3-08b1e9e96824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498660527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3498660527
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3527639822
Short name T577
Test name
Test status
Simulation time 35022139 ps
CPU time 0.76 seconds
Started Jul 21 07:05:19 PM PDT 24
Finished Jul 21 07:05:21 PM PDT 24
Peak memory 206892 kb
Host smart-c96133cb-71a7-4774-9aa4-d10484870565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527639822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3527639822
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.188953915
Short name T262
Test name
Test status
Simulation time 9721193587 ps
CPU time 35.35 seconds
Started Jul 21 07:05:39 PM PDT 24
Finished Jul 21 07:06:16 PM PDT 24
Peak memory 254200 kb
Host smart-33c81985-77bb-485f-bf7e-f9ceb146b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188953915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.188953915
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.566909449
Short name T690
Test name
Test status
Simulation time 34675795610 ps
CPU time 414.09 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:12:20 PM PDT 24
Peak memory 284456 kb
Host smart-65661e3a-9e82-444c-a38f-ce7f0608ae53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566909449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.566909449
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3524572787
Short name T842
Test name
Test status
Simulation time 144031433230 ps
CPU time 71.23 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:06:31 PM PDT 24
Peak memory 249312 kb
Host smart-37137235-e4be-4357-ad7f-698967e20fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524572787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3524572787
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4176850149
Short name T693
Test name
Test status
Simulation time 9725513366 ps
CPU time 10.67 seconds
Started Jul 21 07:05:20 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 224996 kb
Host smart-a8b0202d-123e-4d5f-b5fe-0e3a3fd823cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176850149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4176850149
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.4024321703
Short name T197
Test name
Test status
Simulation time 940170453 ps
CPU time 23.79 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:55 PM PDT 24
Peak memory 233184 kb
Host smart-e8fe84b9-ba80-4db5-bbd3-cd400ff01d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024321703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.4024321703
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3623334914
Short name T15
Test name
Test status
Simulation time 212229544 ps
CPU time 2.51 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 224956 kb
Host smart-765a28cf-a62e-4810-9fc7-80bfffed3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623334914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3623334914
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2807946284
Short name T642
Test name
Test status
Simulation time 19614333617 ps
CPU time 13.84 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 225048 kb
Host smart-a6b54419-1611-4801-9659-1f2dd16f1991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807946284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2807946284
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.133864495
Short name T669
Test name
Test status
Simulation time 463586092 ps
CPU time 6.71 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 223408 kb
Host smart-def0c38f-8410-4d50-92c6-b2a1b3a672da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=133864495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.133864495
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2205429682
Short name T127
Test name
Test status
Simulation time 62411169055 ps
CPU time 577.2 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:15:09 PM PDT 24
Peak memory 253660 kb
Host smart-44fcc237-c626-4fcf-9892-65eeb7bfaa10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205429682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2205429682
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2864827300
Short name T737
Test name
Test status
Simulation time 247390691 ps
CPU time 2.4 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 216724 kb
Host smart-865efcb6-f340-48bc-a94b-ec85a862c963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864827300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2864827300
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1648892392
Short name T332
Test name
Test status
Simulation time 626917309 ps
CPU time 4.32 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 216656 kb
Host smart-5ca7440c-ccd2-40f2-93c1-0ceb939f1f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648892392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1648892392
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3203501600
Short name T382
Test name
Test status
Simulation time 640020068 ps
CPU time 2.36 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 216696 kb
Host smart-e0a26da5-81ba-4464-84c9-60a50c3745b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203501600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3203501600
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.20077323
Short name T437
Test name
Test status
Simulation time 92780916 ps
CPU time 0.77 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:05:25 PM PDT 24
Peak memory 206288 kb
Host smart-eb120f62-8299-47f9-ba51-07e17eee37ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20077323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.20077323
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3025050732
Short name T1014
Test name
Test status
Simulation time 2504759039 ps
CPU time 6.08 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 233208 kb
Host smart-f2210609-92f9-4070-91e8-6444e7a286ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025050732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3025050732
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1236472724
Short name T630
Test name
Test status
Simulation time 27811933 ps
CPU time 0.71 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 205200 kb
Host smart-1cca2cfe-d243-4439-b19f-2f3cf64f275d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236472724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1236472724
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.14288831
Short name T1017
Test name
Test status
Simulation time 4693308476 ps
CPU time 12.75 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 225068 kb
Host smart-b7f7f7c7-30e9-40c4-b3dd-3d13bf777d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14288831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.14288831
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1357235002
Short name T388
Test name
Test status
Simulation time 30252805 ps
CPU time 0.78 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 205912 kb
Host smart-1804d366-5883-4b5f-a58f-5f95ab7ce500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357235002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1357235002
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2974481647
Short name T188
Test name
Test status
Simulation time 52209413640 ps
CPU time 186.89 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:08:39 PM PDT 24
Peak memory 249672 kb
Host smart-39689417-8a1a-4e8f-bd77-1977db6d1b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974481647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2974481647
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3183794993
Short name T895
Test name
Test status
Simulation time 19770431904 ps
CPU time 182.24 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:08:28 PM PDT 24
Peak memory 250844 kb
Host smart-3225c308-7717-4426-9d1c-09be68ba584d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183794993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3183794993
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3073638387
Short name T507
Test name
Test status
Simulation time 4269471635 ps
CPU time 23.96 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:52 PM PDT 24
Peak memory 220196 kb
Host smart-d486e19a-ba5a-4aba-9ae0-deaadd128355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073638387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3073638387
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1942188117
Short name T414
Test name
Test status
Simulation time 1998151121 ps
CPU time 32.39 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:06:10 PM PDT 24
Peak memory 234144 kb
Host smart-c92b88df-a708-4ecb-acbd-90209cedfc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942188117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1942188117
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3036306
Short name T727
Test name
Test status
Simulation time 147906103 ps
CPU time 4.14 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:34 PM PDT 24
Peak memory 225044 kb
Host smart-5570d886-077a-41f4-bea6-aa5193c7e6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.3036306
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3285747819
Short name T501
Test name
Test status
Simulation time 1654187994 ps
CPU time 4.63 seconds
Started Jul 21 07:05:34 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 233176 kb
Host smart-4c3b7bb6-3aed-4e9f-8be4-85e9f1d6800e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285747819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3285747819
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3323179906
Short name T519
Test name
Test status
Simulation time 79235852204 ps
CPU time 126.05 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:07:36 PM PDT 24
Peak memory 234344 kb
Host smart-6e9fc00d-80b8-4fb0-a668-411eb9c4a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323179906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3323179906
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3839699195
Short name T494
Test name
Test status
Simulation time 1266345426 ps
CPU time 5.68 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 233148 kb
Host smart-897abd1b-0bf1-418c-8ba3-425f4281ef6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839699195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3839699195
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.553917680
Short name T992
Test name
Test status
Simulation time 5496392504 ps
CPU time 13.23 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:47 PM PDT 24
Peak memory 241024 kb
Host smart-76494d77-f9e5-4aee-b03e-469faf01e56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553917680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.553917680
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1393616944
Short name T808
Test name
Test status
Simulation time 1310566293 ps
CPU time 7.04 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 223432 kb
Host smart-4ba06202-9704-45ef-bd0e-e6dd9c2ffef3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1393616944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1393616944
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1719124419
Short name T640
Test name
Test status
Simulation time 5557273696 ps
CPU time 16.07 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:52 PM PDT 24
Peak memory 225060 kb
Host smart-f4b19e9c-8212-49c0-b5ec-0b1f479f651d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719124419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1719124419
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3222969901
Short name T715
Test name
Test status
Simulation time 3517999378 ps
CPU time 3.99 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 216848 kb
Host smart-12ed35bd-3344-4049-ad09-d222da79bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222969901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3222969901
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1057538480
Short name T378
Test name
Test status
Simulation time 20046028327 ps
CPU time 4.6 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:32 PM PDT 24
Peak memory 216084 kb
Host smart-d47c4c6a-e22a-4af4-b310-b8a9fee66501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057538480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1057538480
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4049346904
Short name T374
Test name
Test status
Simulation time 1114925506 ps
CPU time 4.62 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 216752 kb
Host smart-f75aa282-8f83-46f1-96b1-f50c972a3a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049346904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4049346904
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3557680080
Short name T303
Test name
Test status
Simulation time 114301529 ps
CPU time 0.79 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:28 PM PDT 24
Peak memory 206368 kb
Host smart-de586d95-e479-4159-9b4d-69f0d8371fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557680080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3557680080
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2956713970
Short name T348
Test name
Test status
Simulation time 83255077 ps
CPU time 2.29 seconds
Started Jul 21 07:05:34 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 224564 kb
Host smart-1362ac5d-f9c0-4852-9bbc-5eca51b3b548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956713970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2956713970
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.972327381
Short name T940
Test name
Test status
Simulation time 101759485 ps
CPU time 0.77 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:37 PM PDT 24
Peak memory 205252 kb
Host smart-8d5a8f22-113f-438a-8ff3-5603becc6302
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972327381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.972327381
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2163711839
Short name T688
Test name
Test status
Simulation time 12630036285 ps
CPU time 18.11 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:52 PM PDT 24
Peak memory 225000 kb
Host smart-64434f6a-ca8e-4f3a-b3d6-9b86e313c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163711839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2163711839
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2061899209
Short name T473
Test name
Test status
Simulation time 65111044 ps
CPU time 0.79 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 206924 kb
Host smart-3fe2a207-42b3-4a63-90ff-d8c6125331b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061899209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2061899209
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1339334743
Short name T39
Test name
Test status
Simulation time 9419759752 ps
CPU time 41.81 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:06:16 PM PDT 24
Peak memory 253936 kb
Host smart-62e7b42c-aff1-4ea2-b64f-781bfb530d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339334743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1339334743
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.321882774
Short name T532
Test name
Test status
Simulation time 17229645870 ps
CPU time 182.46 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:08:34 PM PDT 24
Peak memory 251388 kb
Host smart-1cdac828-2402-4f66-ac66-2f1fcdcb49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321882774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.321882774
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4081987743
Short name T906
Test name
Test status
Simulation time 216953555776 ps
CPU time 510.15 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:14:02 PM PDT 24
Peak memory 263720 kb
Host smart-cd3200aa-ae4a-416b-9e2c-3445df885715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081987743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4081987743
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1671490289
Short name T283
Test name
Test status
Simulation time 2249609703 ps
CPU time 12.83 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 225128 kb
Host smart-3ae42d35-8b4b-49f3-a5ec-dfe4cfae6b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671490289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1671490289
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2202358262
Short name T815
Test name
Test status
Simulation time 33321122131 ps
CPU time 125.62 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:07:38 PM PDT 24
Peak memory 249692 kb
Host smart-8ebb4f71-f482-4c1e-90ff-72d4ba6287a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202358262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2202358262
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1208107003
Short name T470
Test name
Test status
Simulation time 14297831231 ps
CPU time 26.15 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:06:12 PM PDT 24
Peak memory 225008 kb
Host smart-7e307d6f-a173-401d-bdce-815573d06219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208107003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1208107003
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3602596288
Short name T220
Test name
Test status
Simulation time 4609140786 ps
CPU time 6.81 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 241384 kb
Host smart-3abb5924-b962-4f0a-9b43-c601c0513161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602596288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3602596288
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2476236000
Short name T55
Test name
Test status
Simulation time 446838055 ps
CPU time 3.96 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 224896 kb
Host smart-d3dd91a0-dbc5-4f67-b9fe-f250f57a6899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476236000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2476236000
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2000565315
Short name T562
Test name
Test status
Simulation time 16363256752 ps
CPU time 13.5 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 225056 kb
Host smart-ebfbfadc-f418-4343-98c6-06f7e26251bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000565315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2000565315
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2958488551
Short name T671
Test name
Test status
Simulation time 1083189024 ps
CPU time 5.37 seconds
Started Jul 21 07:05:37 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 222072 kb
Host smart-9635e3b7-2246-4213-8433-b808a054ccd5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2958488551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2958488551
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3027124166
Short name T792
Test name
Test status
Simulation time 4004091698 ps
CPU time 20.13 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:06:00 PM PDT 24
Peak memory 216808 kb
Host smart-29c6a802-67ff-4353-8d60-710e0d9eff7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027124166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3027124166
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3694636690
Short name T1
Test name
Test status
Simulation time 805550956 ps
CPU time 3.56 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 216620 kb
Host smart-8ab82668-25fd-4ea2-a19d-beaf6c9fe59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694636690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3694636690
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2782993882
Short name T797
Test name
Test status
Simulation time 240851022 ps
CPU time 1.55 seconds
Started Jul 21 07:05:24 PM PDT 24
Finished Jul 21 07:05:26 PM PDT 24
Peak memory 216700 kb
Host smart-5dca3990-0908-48f2-b437-7c9cb4582917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782993882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2782993882
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2886247586
Short name T911
Test name
Test status
Simulation time 253913305 ps
CPU time 0.89 seconds
Started Jul 21 07:05:31 PM PDT 24
Finished Jul 21 07:05:33 PM PDT 24
Peak memory 206256 kb
Host smart-c570a7d5-4518-4991-b18c-f3716c6fcf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886247586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2886247586
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3189469764
Short name T829
Test name
Test status
Simulation time 7578945497 ps
CPU time 31.04 seconds
Started Jul 21 07:05:30 PM PDT 24
Finished Jul 21 07:06:02 PM PDT 24
Peak memory 234280 kb
Host smart-3533f100-d7d3-40f9-bdd6-e8a556ead31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189469764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3189469764
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2143804021
Short name T1002
Test name
Test status
Simulation time 13104627 ps
CPU time 0.72 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 205188 kb
Host smart-ac717c43-09cf-4558-aa71-46540822fed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143804021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2143804021
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2808071415
Short name T670
Test name
Test status
Simulation time 400471098 ps
CPU time 5.21 seconds
Started Jul 21 07:05:28 PM PDT 24
Finished Jul 21 07:05:34 PM PDT 24
Peak memory 224956 kb
Host smart-1d2c55dc-01ec-40f4-98ca-0fbdc4aa0944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808071415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2808071415
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.158712862
Short name T892
Test name
Test status
Simulation time 36327220 ps
CPU time 0.77 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:35 PM PDT 24
Peak memory 206880 kb
Host smart-a851f4ca-9208-424d-b9d1-e0847eac1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158712862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.158712862
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2279019202
Short name T1021
Test name
Test status
Simulation time 7520344793 ps
CPU time 69.59 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:06:51 PM PDT 24
Peak memory 250468 kb
Host smart-e37e4cc3-9b8c-4fc4-ad2a-6b0cac8c75fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279019202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2279019202
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4047147009
Short name T973
Test name
Test status
Simulation time 103282692797 ps
CPU time 201.94 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:09:00 PM PDT 24
Peak memory 249716 kb
Host smart-e0db55a4-2535-46da-9e90-4f308ccbcb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047147009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4047147009
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1793950396
Short name T189
Test name
Test status
Simulation time 6591565522 ps
CPU time 89 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:07:07 PM PDT 24
Peak memory 267388 kb
Host smart-b8971ce7-b8b9-4c90-915c-a90abdcc7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793950396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1793950396
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.4130692578
Short name T471
Test name
Test status
Simulation time 2090297424 ps
CPU time 25.48 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:59 PM PDT 24
Peak memory 233100 kb
Host smart-a325c61e-7f7e-4b9b-b789-7afc42e61f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130692578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.4130692578
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.4070775861
Short name T590
Test name
Test status
Simulation time 3028474879 ps
CPU time 20.88 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:48 PM PDT 24
Peak memory 239880 kb
Host smart-09c3ea2c-1184-4d13-9f2b-761936539cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070775861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.4070775861
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.865972994
Short name T214
Test name
Test status
Simulation time 311171121 ps
CPU time 4.43 seconds
Started Jul 21 07:05:27 PM PDT 24
Finished Jul 21 07:05:32 PM PDT 24
Peak memory 219172 kb
Host smart-4fe9313e-bd30-4257-a043-e16953701ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865972994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.865972994
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2055895719
Short name T523
Test name
Test status
Simulation time 37480126 ps
CPU time 2.56 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 232920 kb
Host smart-7290c041-bbf2-4cbb-9c6c-0ffde1c896f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055895719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2055895719
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3495232691
Short name T237
Test name
Test status
Simulation time 1686436144 ps
CPU time 8.12 seconds
Started Jul 21 07:05:32 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 241208 kb
Host smart-a717a253-c395-4f31-ae47-fc140fd2e9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495232691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3495232691
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4293862357
Short name T232
Test name
Test status
Simulation time 712401264 ps
CPU time 3.45 seconds
Started Jul 21 07:05:25 PM PDT 24
Finished Jul 21 07:05:29 PM PDT 24
Peak memory 233152 kb
Host smart-109b5de2-fd48-4bec-a787-80112b2408dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293862357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4293862357
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.362994601
Short name T432
Test name
Test status
Simulation time 301853049 ps
CPU time 3.76 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:31 PM PDT 24
Peak memory 220324 kb
Host smart-2ecc512a-48c8-4faa-9954-b2456611d865
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362994601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.362994601
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.527049716
Short name T697
Test name
Test status
Simulation time 15250973427 ps
CPU time 168.8 seconds
Started Jul 21 07:05:39 PM PDT 24
Finished Jul 21 07:08:29 PM PDT 24
Peak memory 265616 kb
Host smart-6e101f44-b457-4f89-a671-fd900dc18b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527049716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.527049716
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3770511911
Short name T643
Test name
Test status
Simulation time 4481753207 ps
CPU time 16.41 seconds
Started Jul 21 07:05:26 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 216928 kb
Host smart-16ebbbef-0192-4a3b-9e42-b55c086c4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770511911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3770511911
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4008137489
Short name T820
Test name
Test status
Simulation time 6562305458 ps
CPU time 16.09 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 216804 kb
Host smart-a8169df1-d58d-4ef7-adb4-b6eb874d7761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008137489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4008137489
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2234956145
Short name T524
Test name
Test status
Simulation time 50028425 ps
CPU time 0.72 seconds
Started Jul 21 07:05:34 PM PDT 24
Finished Jul 21 07:05:36 PM PDT 24
Peak memory 205904 kb
Host smart-8a110baa-11fc-4cf6-857e-241776691a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234956145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2234956145
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1496475515
Short name T998
Test name
Test status
Simulation time 19630304 ps
CPU time 0.74 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 206140 kb
Host smart-262f90bf-093d-48d5-9499-7d45925b40d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496475515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1496475515
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4173772033
Short name T903
Test name
Test status
Simulation time 12554472695 ps
CPU time 21.52 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 233316 kb
Host smart-6787bb13-27b9-4775-bb6b-4aacbac4622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173772033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4173772033
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3732648589
Short name T528
Test name
Test status
Simulation time 14734455 ps
CPU time 0.73 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 205156 kb
Host smart-7fd85c6f-cf32-4e34-8dbe-3c6eff4e712c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732648589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3732648589
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3912441543
Short name T830
Test name
Test status
Simulation time 578605544 ps
CPU time 4.12 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 224940 kb
Host smart-a3f3560f-954a-478c-87d0-a35a14864fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912441543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3912441543
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.669363717
Short name T545
Test name
Test status
Simulation time 65120789 ps
CPU time 0.79 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:40 PM PDT 24
Peak memory 206864 kb
Host smart-436ce38b-cc04-46d7-a687-3c4f8a0bc2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669363717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.669363717
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.810264448
Short name T905
Test name
Test status
Simulation time 2942094560 ps
CPU time 60.14 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:06:37 PM PDT 24
Peak memory 265592 kb
Host smart-8e6c1ab3-4d61-4f21-894b-0f689afd7001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810264448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.810264448
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.691363806
Short name T47
Test name
Test status
Simulation time 15835424535 ps
CPU time 108.74 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:07:25 PM PDT 24
Peak memory 255644 kb
Host smart-a8be8b8f-ab33-43cd-8e44-0cf43b7c7385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691363806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.691363806
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2511532157
Short name T198
Test name
Test status
Simulation time 103485227348 ps
CPU time 148.53 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:08:09 PM PDT 24
Peak memory 257412 kb
Host smart-ce350062-c111-4939-b794-e3daf7adf7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511532157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2511532157
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2348517818
Short name T280
Test name
Test status
Simulation time 5706901871 ps
CPU time 22.47 seconds
Started Jul 21 07:05:44 PM PDT 24
Finished Jul 21 07:06:08 PM PDT 24
Peak memory 235416 kb
Host smart-f3fec577-b297-4a65-ac83-861b8293e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348517818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2348517818
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2374230716
Short name T901
Test name
Test status
Simulation time 22636465 ps
CPU time 0.75 seconds
Started Jul 21 07:05:37 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 208076 kb
Host smart-5dba8812-c71c-4387-a3f5-b8af2ffdf12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374230716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2374230716
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2353411197
Short name T460
Test name
Test status
Simulation time 225633149 ps
CPU time 2.79 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 224904 kb
Host smart-83b55564-48ae-43a6-b9cb-79b70237f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353411197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2353411197
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.640106470
Short name T402
Test name
Test status
Simulation time 61400177 ps
CPU time 2.53 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 232860 kb
Host smart-8a8b0820-97b9-44dc-809e-7ada13a80a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640106470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.640106470
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4200572822
Short name T510
Test name
Test status
Simulation time 767002867 ps
CPU time 4.13 seconds
Started Jul 21 07:05:34 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 233128 kb
Host smart-93ed392b-2afc-4db5-89d8-2425fb3d7a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200572822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4200572822
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1692928090
Short name T668
Test name
Test status
Simulation time 104287869 ps
CPU time 2.3 seconds
Started Jul 21 07:05:40 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 233124 kb
Host smart-7d151cd9-be77-40f8-949f-c99c353b9409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692928090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1692928090
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2360137127
Short name T334
Test name
Test status
Simulation time 277532961 ps
CPU time 4.49 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:41 PM PDT 24
Peak memory 223532 kb
Host smart-8b66c52a-85a1-44ee-b376-7b02baacb125
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2360137127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2360137127
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.518065087
Short name T30
Test name
Test status
Simulation time 15263148614 ps
CPU time 84.29 seconds
Started Jul 21 07:05:29 PM PDT 24
Finished Jul 21 07:06:54 PM PDT 24
Peak memory 240388 kb
Host smart-3289dd18-1f8d-4f30-b786-12148820e664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518065087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.518065087
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1457074070
Short name T919
Test name
Test status
Simulation time 2188362659 ps
CPU time 10.63 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 216840 kb
Host smart-b689c6d0-6827-4d82-99d9-b82a19c5c20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457074070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1457074070
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1037766862
Short name T652
Test name
Test status
Simulation time 2036345041 ps
CPU time 6.89 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:47 PM PDT 24
Peak memory 216624 kb
Host smart-e262c83f-a1e0-4d8b-a2be-b81ac9deea41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037766862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1037766862
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2200578481
Short name T902
Test name
Test status
Simulation time 150063964 ps
CPU time 4.64 seconds
Started Jul 21 07:05:44 PM PDT 24
Finished Jul 21 07:05:50 PM PDT 24
Peak memory 216668 kb
Host smart-7d243102-444e-4aa1-bc1b-ec06c8ddf916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200578481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2200578481
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1746444232
Short name T953
Test name
Test status
Simulation time 60141576 ps
CPU time 0.74 seconds
Started Jul 21 07:05:44 PM PDT 24
Finished Jul 21 07:05:46 PM PDT 24
Peak memory 206148 kb
Host smart-907b8265-2b0b-4aa6-b2ea-54207fd718a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746444232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1746444232
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2548400005
Short name T567
Test name
Test status
Simulation time 21662458995 ps
CPU time 8.03 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 233300 kb
Host smart-f3c452e6-8a5c-4b30-9c60-6b6ce13a920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548400005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2548400005
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1940694837
Short name T304
Test name
Test status
Simulation time 34437848 ps
CPU time 0.69 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 205732 kb
Host smart-ae064583-c2a0-46a0-ae76-6b07cf29e2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940694837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1940694837
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.546989387
Short name T744
Test name
Test status
Simulation time 752787103 ps
CPU time 8.52 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 224968 kb
Host smart-996b68d0-49cc-479b-9267-7d6f6b07f92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546989387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.546989387
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4143557964
Short name T836
Test name
Test status
Simulation time 43889665 ps
CPU time 0.75 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:05:38 PM PDT 24
Peak memory 206200 kb
Host smart-76bd1146-3cc8-42b4-928e-8f911fe54f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143557964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4143557964
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3802136741
Short name T192
Test name
Test status
Simulation time 8532756036 ps
CPU time 24.37 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:06:05 PM PDT 24
Peak memory 251932 kb
Host smart-5129bf2f-a7ee-444c-8543-0465ec16bb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802136741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3802136741
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1165783753
Short name T389
Test name
Test status
Simulation time 34378166409 ps
CPU time 280.07 seconds
Started Jul 21 07:05:36 PM PDT 24
Finished Jul 21 07:10:18 PM PDT 24
Peak memory 249788 kb
Host smart-0d4181ab-1435-44d8-bafb-fca83b5a7a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165783753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1165783753
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2734669640
Short name T330
Test name
Test status
Simulation time 54646407 ps
CPU time 3.07 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 233152 kb
Host smart-3fa6163c-7e4f-4453-868b-678efe2b9546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734669640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2734669640
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1717722033
Short name T43
Test name
Test status
Simulation time 144302004 ps
CPU time 3.05 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:39 PM PDT 24
Peak memory 233140 kb
Host smart-250a259c-23a5-4e66-bff2-0c9beebf2c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717722033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1717722033
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3378439086
Short name T372
Test name
Test status
Simulation time 373025498 ps
CPU time 4.48 seconds
Started Jul 21 07:05:38 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 233112 kb
Host smart-7911e444-ec45-40b5-bc66-a06e95af205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378439086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3378439086
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2207873264
Short name T407
Test name
Test status
Simulation time 30324016718 ps
CPU time 15.47 seconds
Started Jul 21 07:05:37 PM PDT 24
Finished Jul 21 07:05:54 PM PDT 24
Peak memory 233260 kb
Host smart-c7b53c04-dce7-4fce-955e-48d42bc5c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207873264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2207873264
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3379164590
Short name T357
Test name
Test status
Simulation time 894170167 ps
CPU time 10.58 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:05:45 PM PDT 24
Peak memory 239396 kb
Host smart-e51cd250-962c-44a4-a3cd-3628025a7487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379164590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3379164590
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4276424079
Short name T41
Test name
Test status
Simulation time 811923265 ps
CPU time 9.09 seconds
Started Jul 21 07:05:41 PM PDT 24
Finished Jul 21 07:05:52 PM PDT 24
Peak memory 222884 kb
Host smart-f10d61eb-1a16-4239-8bd5-fd425a7d8697
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4276424079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4276424079
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2425619000
Short name T324
Test name
Test status
Simulation time 76445536 ps
CPU time 0.92 seconds
Started Jul 21 07:05:41 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 206896 kb
Host smart-77c85e47-0f6e-48de-93e4-f24e520bcd5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425619000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2425619000
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4136528982
Short name T294
Test name
Test status
Simulation time 10654613745 ps
CPU time 27.04 seconds
Started Jul 21 07:05:33 PM PDT 24
Finished Jul 21 07:06:02 PM PDT 24
Peak memory 216768 kb
Host smart-62e8208e-8894-4b34-a4fb-8361bd0ea007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136528982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4136528982
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.951648183
Short name T351
Test name
Test status
Simulation time 5310595275 ps
CPU time 10.63 seconds
Started Jul 21 07:05:39 PM PDT 24
Finished Jul 21 07:05:51 PM PDT 24
Peak memory 216844 kb
Host smart-b616853d-165e-4a9f-83e8-7eeae4439b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951648183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.951648183
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3678249306
Short name T297
Test name
Test status
Simulation time 18623250 ps
CPU time 0.89 seconds
Started Jul 21 07:05:39 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 207312 kb
Host smart-2d710707-8125-468c-9893-52af8b48127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678249306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3678249306
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.491031019
Short name T434
Test name
Test status
Simulation time 20896527 ps
CPU time 0.71 seconds
Started Jul 21 07:05:41 PM PDT 24
Finished Jul 21 07:05:44 PM PDT 24
Peak memory 205980 kb
Host smart-ed6e7e13-c0d8-4d29-8efb-c1b35e077d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491031019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.491031019
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.492750733
Short name T245
Test name
Test status
Simulation time 4789445772 ps
CPU time 5.17 seconds
Started Jul 21 07:05:35 PM PDT 24
Finished Jul 21 07:05:42 PM PDT 24
Peak memory 224948 kb
Host smart-1a1b8ae2-cd78-449d-a4b2-db3c116fe5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492750733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.492750733
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3833414266
Short name T574
Test name
Test status
Simulation time 66052650 ps
CPU time 0.74 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:37 PM PDT 24
Peak memory 205216 kb
Host smart-b2d8ec40-98d9-4ed5-888e-073d9e7a0c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833414266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
833414266
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3090053741
Short name T962
Test name
Test status
Simulation time 179125671 ps
CPU time 2.72 seconds
Started Jul 21 07:03:31 PM PDT 24
Finished Jul 21 07:03:35 PM PDT 24
Peak memory 233108 kb
Host smart-6d7b4a78-8602-40dc-9f1d-c263d46e40da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090053741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3090053741
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.458083716
Short name T596
Test name
Test status
Simulation time 15518842 ps
CPU time 0.78 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:36 PM PDT 24
Peak memory 206852 kb
Host smart-e994fd60-956e-4486-8737-eff449be8ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458083716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.458083716
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1570222
Short name T782
Test name
Test status
Simulation time 5651916185 ps
CPU time 15.16 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 225048 kb
Host smart-0d8d57bd-fd62-416c-acdb-a1fb408173ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1570222
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1610517140
Short name T212
Test name
Test status
Simulation time 3722361709 ps
CPU time 76.93 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:04:52 PM PDT 24
Peak memory 257164 kb
Host smart-930cac7e-0a10-4073-b81d-b2785ff17c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610517140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1610517140
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1786453726
Short name T183
Test name
Test status
Simulation time 13149567178 ps
CPU time 110.16 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 253112 kb
Host smart-1de1b03d-b4be-4935-8877-9a953a9bdb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786453726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1786453726
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1656341991
Short name T622
Test name
Test status
Simulation time 2590149031 ps
CPU time 15.9 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 241496 kb
Host smart-92a65959-2513-4d6c-97b6-f00c3f332133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656341991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1656341991
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1559563419
Short name T178
Test name
Test status
Simulation time 14620985545 ps
CPU time 115.95 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:05:30 PM PDT 24
Peak memory 253668 kb
Host smart-34dcb286-babd-4781-b022-6cabcdc4ab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559563419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1559563419
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1985483838
Short name T362
Test name
Test status
Simulation time 6187664503 ps
CPU time 13.31 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 241400 kb
Host smart-f2b4d47b-4342-4b75-b2fd-00a0e9622c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985483838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1985483838
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2374562197
Short name T227
Test name
Test status
Simulation time 4861597632 ps
CPU time 42.72 seconds
Started Jul 21 07:03:30 PM PDT 24
Finished Jul 21 07:04:13 PM PDT 24
Peak memory 241404 kb
Host smart-deff82b7-3684-4238-adc3-3945bdffba39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374562197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2374562197
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3352796300
Short name T386
Test name
Test status
Simulation time 55439536 ps
CPU time 1.01 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:44 PM PDT 24
Peak memory 218416 kb
Host smart-bbfdd5a0-b2e7-43bd-84e0-f18e81759330
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352796300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3352796300
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4257790056
Short name T356
Test name
Test status
Simulation time 66454024176 ps
CPU time 37.69 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:04:13 PM PDT 24
Peak memory 249612 kb
Host smart-12930046-8781-4981-a119-f9350dcfcf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257790056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4257790056
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4164654219
Short name T638
Test name
Test status
Simulation time 16200660177 ps
CPU time 23.92 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 240880 kb
Host smart-b9ca076a-7822-4971-bbc2-0b64efb216c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164654219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4164654219
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2491399572
Short name T42
Test name
Test status
Simulation time 142187731 ps
CPU time 3.95 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 219084 kb
Host smart-5f21cb1a-ca6f-4f1c-a6bb-54403fe9c25e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2491399572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2491399572
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2327559114
Short name T19
Test name
Test status
Simulation time 2463477183 ps
CPU time 49.28 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:04:39 PM PDT 24
Peak memory 238516 kb
Host smart-e79174f2-ad7f-43a4-987e-1dbee45f2e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327559114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2327559114
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3512321504
Short name T536
Test name
Test status
Simulation time 13600694490 ps
CPU time 15.98 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 216776 kb
Host smart-0154bc60-c0f2-492d-b7a3-b3c6f86ea4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512321504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3512321504
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1385164165
Short name T325
Test name
Test status
Simulation time 20823367087 ps
CPU time 15.8 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 216756 kb
Host smart-d45a2f03-b098-401b-bc88-fb7a71728c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385164165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1385164165
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3814006953
Short name T293
Test name
Test status
Simulation time 293133354 ps
CPU time 1.1 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:34 PM PDT 24
Peak memory 208268 kb
Host smart-914b39c8-6ad2-4e2d-a1ee-ac0561babfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814006953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3814006953
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3362613392
Short name T635
Test name
Test status
Simulation time 30280461 ps
CPU time 0.77 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 206236 kb
Host smart-bea67ff0-d4f5-4e01-a216-40728189e6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362613392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3362613392
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3569700434
Short name T229
Test name
Test status
Simulation time 245326814 ps
CPU time 3.69 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 233172 kb
Host smart-a5466d5d-9266-4333-8413-88661430fee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569700434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3569700434
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.4046225732
Short name T745
Test name
Test status
Simulation time 24100892 ps
CPU time 0.72 seconds
Started Jul 21 07:03:38 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 206096 kb
Host smart-0b3ba0b1-1205-4bad-b32f-56a7347ec013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046225732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4
046225732
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3510519100
Short name T781
Test name
Test status
Simulation time 6135402073 ps
CPU time 13.43 seconds
Started Jul 21 07:03:32 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 225084 kb
Host smart-10be8a64-103e-4462-b2a7-35bfe8e6702e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510519100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3510519100
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1259095701
Short name T571
Test name
Test status
Simulation time 15731137 ps
CPU time 0.74 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:45 PM PDT 24
Peak memory 206144 kb
Host smart-afc380d6-fed1-4181-8560-1c5fd99aa57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259095701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1259095701
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1350438880
Short name T889
Test name
Test status
Simulation time 178394850554 ps
CPU time 199.15 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:06:59 PM PDT 24
Peak memory 251576 kb
Host smart-ac6da9df-d938-41fe-82d8-ad7a52963f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350438880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1350438880
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3679658780
Short name T572
Test name
Test status
Simulation time 12435015413 ps
CPU time 168.7 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:06:27 PM PDT 24
Peak memory 266188 kb
Host smart-8f63771a-52b3-4bca-9fcf-a597c435bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679658780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3679658780
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2433186469
Short name T265
Test name
Test status
Simulation time 36666796405 ps
CPU time 422.63 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:10:39 PM PDT 24
Peak memory 264672 kb
Host smart-878b3437-41ab-4aab-b5d8-7eb7b1162687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433186469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2433186469
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3924204388
Short name T353
Test name
Test status
Simulation time 673923312 ps
CPU time 3.84 seconds
Started Jul 21 07:03:37 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 233732 kb
Host smart-ff6e57f5-5bc8-44ed-ae0e-c1f3e430d905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924204388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3924204388
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3799373613
Short name T859
Test name
Test status
Simulation time 77606722912 ps
CPU time 144.93 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:06:14 PM PDT 24
Peak memory 250704 kb
Host smart-84de9374-fa3f-4633-95cd-fe8a482ea0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799373613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3799373613
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2583439772
Short name T752
Test name
Test status
Simulation time 181079019 ps
CPU time 3.55 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:03:44 PM PDT 24
Peak memory 233144 kb
Host smart-54fb3a79-8151-403f-8ca1-f743e1b51783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583439772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2583439772
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3257840739
Short name T219
Test name
Test status
Simulation time 1055983166 ps
CPU time 8.16 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 224948 kb
Host smart-ae66d765-5a5b-4872-a76e-138ffa417802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257840739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3257840739
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2347197270
Short name T415
Test name
Test status
Simulation time 114814687 ps
CPU time 1.05 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:45 PM PDT 24
Peak memory 217124 kb
Host smart-fdc5568e-3ad2-4ea3-809f-4c5df270858e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347197270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2347197270
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.677978438
Short name T246
Test name
Test status
Simulation time 46193139 ps
CPU time 2.36 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:45 PM PDT 24
Peak memory 224920 kb
Host smart-f9b6b588-05e9-4167-bbca-d50de05cedb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677978438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
677978438
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1977085580
Short name T667
Test name
Test status
Simulation time 8415220957 ps
CPU time 8.31 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 233196 kb
Host smart-fadbb8e8-ec60-4ec9-999b-16b43fdf5673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977085580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1977085580
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3071012821
Short name T491
Test name
Test status
Simulation time 990799136 ps
CPU time 10.59 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 222756 kb
Host smart-f84ea992-eea6-4e9b-923d-51d5a1c07e2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3071012821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3071012821
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1840042793
Short name T804
Test name
Test status
Simulation time 96660570302 ps
CPU time 769.96 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:16:33 PM PDT 24
Peak memory 274280 kb
Host smart-a1ad2d36-0357-4ebf-a867-c30183d1e0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840042793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1840042793
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2775423747
Short name T559
Test name
Test status
Simulation time 774945310 ps
CPU time 11.38 seconds
Started Jul 21 07:03:36 PM PDT 24
Finished Jul 21 07:03:48 PM PDT 24
Peak memory 216880 kb
Host smart-52aad1a8-9a5c-4477-85be-1a525aba7f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775423747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2775423747
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3400571721
Short name T301
Test name
Test status
Simulation time 7831689953 ps
CPU time 8.92 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:42 PM PDT 24
Peak memory 216840 kb
Host smart-b334de4d-fcc4-444e-8b6d-8124a69dc569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400571721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3400571721
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3257664929
Short name T990
Test name
Test status
Simulation time 114896397 ps
CPU time 1.46 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 216712 kb
Host smart-0ec0b0e9-1d76-4b50-85b4-905cfec563cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257664929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3257664929
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3557736342
Short name T886
Test name
Test status
Simulation time 214186236 ps
CPU time 1.04 seconds
Started Jul 21 07:03:38 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 207344 kb
Host smart-52666000-990d-4313-95cf-aab870201c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557736342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3557736342
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.485887068
Short name T608
Test name
Test status
Simulation time 12080901717 ps
CPU time 13.49 seconds
Started Jul 21 07:03:33 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 225096 kb
Host smart-f8af627b-18fd-4dc9-9221-554982c7caf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485887068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.485887068
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2021719208
Short name T316
Test name
Test status
Simulation time 11131549 ps
CPU time 0.76 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:44 PM PDT 24
Peak memory 205728 kb
Host smart-d697441e-1cc3-4e30-b0f2-1dee0576ceeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021719208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
021719208
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3659667323
Short name T654
Test name
Test status
Simulation time 193275217 ps
CPU time 2.65 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 233120 kb
Host smart-f70eda93-c56e-4081-a53d-b3b2bea3225b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659667323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3659667323
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2818701377
Short name T1024
Test name
Test status
Simulation time 35378298 ps
CPU time 0.79 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 206800 kb
Host smart-383e25f4-638f-4d1f-b798-7b4959cce1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818701377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2818701377
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1575312144
Short name T225
Test name
Test status
Simulation time 1150915389 ps
CPU time 25.03 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:04:12 PM PDT 24
Peak memory 239280 kb
Host smart-06e2076e-2b15-4b22-b24e-6a4d315d9e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575312144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1575312144
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.283822350
Short name T527
Test name
Test status
Simulation time 35774277661 ps
CPU time 161.36 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:06:26 PM PDT 24
Peak memory 249712 kb
Host smart-cce47189-6b45-4c78-81a2-febd4429ffdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283822350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.283822350
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2208711683
Short name T511
Test name
Test status
Simulation time 3802565571 ps
CPU time 20.09 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 225128 kb
Host smart-82007cda-e7d8-4cc2-a278-44f697780ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208711683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2208711683
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1641984029
Short name T985
Test name
Test status
Simulation time 982026211 ps
CPU time 5.78 seconds
Started Jul 21 07:03:34 PM PDT 24
Finished Jul 21 07:03:40 PM PDT 24
Peak memory 234656 kb
Host smart-7853e9bb-dbe3-4345-bc02-9ae2bcb1cdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641984029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1641984029
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2435101907
Short name T173
Test name
Test status
Simulation time 41111073927 ps
CPU time 254.59 seconds
Started Jul 21 07:03:55 PM PDT 24
Finished Jul 21 07:08:12 PM PDT 24
Peak memory 251156 kb
Host smart-d53718bc-0647-4312-a905-951f7b3adad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435101907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2435101907
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.770613437
Short name T456
Test name
Test status
Simulation time 210018390 ps
CPU time 3.03 seconds
Started Jul 21 07:03:35 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 224920 kb
Host smart-6b080469-1794-4425-af79-641b771fde64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770613437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.770613437
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.802995130
Short name T254
Test name
Test status
Simulation time 6839221761 ps
CPU time 31.85 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:25 PM PDT 24
Peak memory 233312 kb
Host smart-cb977fee-755c-4538-b431-29af2e1aeeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802995130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.802995130
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4251782938
Short name T656
Test name
Test status
Simulation time 49079767 ps
CPU time 0.98 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:51 PM PDT 24
Peak memory 217152 kb
Host smart-b011e553-b0d1-4b74-b4f6-f893cf50ad32
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251782938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4251782938
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1861018307
Short name T249
Test name
Test status
Simulation time 307322649 ps
CPU time 6.46 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 233180 kb
Host smart-ea0e0b55-4295-455a-b308-1055c2c6912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861018307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1861018307
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2312989723
Short name T941
Test name
Test status
Simulation time 19933869974 ps
CPU time 9.31 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:06 PM PDT 24
Peak memory 225044 kb
Host smart-e5610222-6fe1-448d-a9f8-9e6d5d648590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312989723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2312989723
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2351723954
Short name T323
Test name
Test status
Simulation time 2092300776 ps
CPU time 3.88 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 219152 kb
Host smart-c71f47d9-b2a3-451b-9292-ece98a89788e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2351723954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2351723954
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1801633221
Short name T816
Test name
Test status
Simulation time 322114718731 ps
CPU time 326.87 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:09:08 PM PDT 24
Peak memory 268884 kb
Host smart-b8454291-fa60-4292-b5d5-927930d2214a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801633221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1801633221
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1517933244
Short name T848
Test name
Test status
Simulation time 12597783110 ps
CPU time 33.06 seconds
Started Jul 21 07:03:41 PM PDT 24
Finished Jul 21 07:04:15 PM PDT 24
Peak memory 216836 kb
Host smart-605bb62a-1c20-41e7-b084-4bd7ad5a0c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517933244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1517933244
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2371278526
Short name T311
Test name
Test status
Simulation time 3039116454 ps
CPU time 7.13 seconds
Started Jul 21 07:03:50 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 216796 kb
Host smart-9b13dbfd-0efb-4d68-a525-730882e63efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371278526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2371278526
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.942735400
Short name T554
Test name
Test status
Simulation time 59951089 ps
CPU time 1.14 seconds
Started Jul 21 07:03:47 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 208276 kb
Host smart-07d71367-e624-4921-9aa8-0a7a8e21fad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942735400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.942735400
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.498195185
Short name T824
Test name
Test status
Simulation time 49448421 ps
CPU time 0.73 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 206192 kb
Host smart-9973bc8a-8fb8-42a1-8ecf-a4b4683f1ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498195185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.498195185
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2997390679
Short name T502
Test name
Test status
Simulation time 68195849 ps
CPU time 2.65 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 232220 kb
Host smart-a25f4c3f-797e-49f8-96d7-85c36a90c690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997390679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2997390679
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.354576253
Short name T614
Test name
Test status
Simulation time 24922525 ps
CPU time 0.74 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 205728 kb
Host smart-470a1f4f-78c4-4a1d-adb5-89b66f1d112a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354576253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.354576253
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.4128887060
Short name T176
Test name
Test status
Simulation time 1799720143 ps
CPU time 7.44 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 224776 kb
Host smart-d7632b42-8a86-4174-b389-01c8ec01707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128887060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.4128887060
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3411501794
Short name T385
Test name
Test status
Simulation time 24447640 ps
CPU time 0.81 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 206888 kb
Host smart-87c93337-f287-46a0-bb72-9ebd6d907b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411501794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3411501794
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.546202626
Short name T887
Test name
Test status
Simulation time 11049112780 ps
CPU time 84.2 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:05:08 PM PDT 24
Peak memory 255804 kb
Host smart-1318ef2d-cc73-49d0-8f15-f587930cbd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546202626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.546202626
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.588739480
Short name T791
Test name
Test status
Simulation time 66572582236 ps
CPU time 347.73 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:09:41 PM PDT 24
Peak memory 266044 kb
Host smart-5ace799d-6f4a-4f83-a3a8-eabfaab0a2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588739480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.588739480
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3011457561
Short name T156
Test name
Test status
Simulation time 12678190916 ps
CPU time 59.18 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:04:43 PM PDT 24
Peak memory 249712 kb
Host smart-bbc47bf6-ccca-45a0-af1c-76bae895453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011457561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3011457561
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1335261901
Short name T333
Test name
Test status
Simulation time 1305046625 ps
CPU time 3.27 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 224916 kb
Host smart-46080247-e5cd-4673-a055-535be78be88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335261901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1335261901
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3877798891
Short name T917
Test name
Test status
Simulation time 680789263 ps
CPU time 6.44 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 234388 kb
Host smart-f7023c0a-bab8-4e6c-8ab8-2d2c3945d620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877798891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3877798891
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.993258647
Short name T928
Test name
Test status
Simulation time 817563755 ps
CPU time 3.51 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:49 PM PDT 24
Peak memory 233088 kb
Host smart-419e70cb-b103-42f1-9f00-d0cf99bf1d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993258647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.993258647
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3394244689
Short name T943
Test name
Test status
Simulation time 840629390 ps
CPU time 10.52 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 233136 kb
Host smart-eec24d38-54c4-424b-8d9d-aa7f9b113289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394244689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3394244689
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3709118244
Short name T379
Test name
Test status
Simulation time 41066783 ps
CPU time 1.03 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 217160 kb
Host smart-cc899436-3912-4ad1-897d-3db1f983a911
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709118244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3709118244
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2774104773
Short name T367
Test name
Test status
Simulation time 2991590765 ps
CPU time 5.71 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 241328 kb
Host smart-96ee9e26-49e7-4d85-90ad-460e85861fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774104773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2774104773
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4185445033
Short name T435
Test name
Test status
Simulation time 1369289362 ps
CPU time 7.93 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 233140 kb
Host smart-bb5431b7-e2c5-4700-8649-aa3f71cd4179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185445033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4185445033
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3476948868
Short name T617
Test name
Test status
Simulation time 8721207987 ps
CPU time 9.6 seconds
Started Jul 21 07:03:43 PM PDT 24
Finished Jul 21 07:03:54 PM PDT 24
Peak memory 222096 kb
Host smart-84b900f5-b885-45ba-83da-59973ee5632c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3476948868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3476948868
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.41992144
Short name T819
Test name
Test status
Simulation time 3768926436 ps
CPU time 80.7 seconds
Started Jul 21 07:03:40 PM PDT 24
Finished Jul 21 07:05:02 PM PDT 24
Peak memory 257192 kb
Host smart-88b2241f-0fb1-48ff-98af-ecaf40cc8d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41992144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_
all.41992144
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.920478302
Short name T498
Test name
Test status
Simulation time 9817707046 ps
CPU time 22.99 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:15 PM PDT 24
Peak memory 216728 kb
Host smart-5b47da07-a011-4112-ad65-6058a8e80eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920478302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.920478302
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.762413061
Short name T750
Test name
Test status
Simulation time 1177852118 ps
CPU time 6.49 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:50 PM PDT 24
Peak memory 216624 kb
Host smart-995a2223-1f06-4311-9e3f-1ba21b6fc76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762413061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.762413061
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2587869626
Short name T831
Test name
Test status
Simulation time 254653979 ps
CPU time 1.18 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:48 PM PDT 24
Peak memory 216684 kb
Host smart-0fb08eb8-ff05-4860-9cda-42fa89874eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587869626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2587869626
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2432008307
Short name T489
Test name
Test status
Simulation time 12416472 ps
CPU time 0.69 seconds
Started Jul 21 07:03:45 PM PDT 24
Finished Jul 21 07:03:47 PM PDT 24
Peak memory 205920 kb
Host smart-b8ab21c8-7734-45e1-ad96-01bab21c939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432008307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2432008307
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.372845499
Short name T387
Test name
Test status
Simulation time 91925504 ps
CPU time 2.76 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:53 PM PDT 24
Peak memory 233148 kb
Host smart-1b44d5a6-19a8-4d9f-b61c-39275ece161d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372845499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.372845499
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3775254419
Short name T1000
Test name
Test status
Simulation time 25722892 ps
CPU time 0.71 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:55 PM PDT 24
Peak memory 205740 kb
Host smart-affa0bc2-3233-4d2c-ac25-fb9811867e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775254419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
775254419
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2185167490
Short name T793
Test name
Test status
Simulation time 107575384 ps
CPU time 2.07 seconds
Started Jul 21 07:03:57 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 224448 kb
Host smart-0fd6898b-7efc-4b8c-8664-c49829039a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185167490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2185167490
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.218214979
Short name T358
Test name
Test status
Simulation time 15579240 ps
CPU time 0.74 seconds
Started Jul 21 07:03:59 PM PDT 24
Finished Jul 21 07:04:01 PM PDT 24
Peak memory 205876 kb
Host smart-ee95c80c-bcf4-4986-b476-46148a3d9bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218214979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.218214979
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3173406114
Short name T742
Test name
Test status
Simulation time 4249060358 ps
CPU time 30.5 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:04:15 PM PDT 24
Peak memory 240932 kb
Host smart-fb2ed028-258b-4f49-a7e6-419f3364811e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173406114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3173406114
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3710187092
Short name T849
Test name
Test status
Simulation time 49685709350 ps
CPU time 432.16 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:11:01 PM PDT 24
Peak memory 266080 kb
Host smart-bd65430f-2768-481c-951a-d1e0e982866d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710187092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3710187092
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1744271540
Short name T623
Test name
Test status
Simulation time 20925375407 ps
CPU time 51.6 seconds
Started Jul 21 07:03:54 PM PDT 24
Finished Jul 21 07:04:48 PM PDT 24
Peak memory 225164 kb
Host smart-fec22651-d187-4a8c-bc37-4e7b4d8efa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744271540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1744271540
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1234538456
Short name T783
Test name
Test status
Simulation time 3189020817 ps
CPU time 12.85 seconds
Started Jul 21 07:03:44 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 236024 kb
Host smart-f2989179-d6a9-4a94-be2c-2581c3a648ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234538456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1234538456
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3090865673
Short name T157
Test name
Test status
Simulation time 8860461456 ps
CPU time 44.62 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:40 PM PDT 24
Peak memory 249964 kb
Host smart-ec87bf42-da6f-4143-9d1a-98a9e9935016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090865673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3090865673
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1307950925
Short name T607
Test name
Test status
Simulation time 3132057716 ps
CPU time 8.58 seconds
Started Jul 21 07:03:53 PM PDT 24
Finished Jul 21 07:04:05 PM PDT 24
Peak memory 233240 kb
Host smart-7ac3b5ff-f548-4891-9a62-7e08a0300524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307950925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1307950925
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1448780640
Short name T124
Test name
Test status
Simulation time 205214327 ps
CPU time 3.46 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:03:43 PM PDT 24
Peak memory 224856 kb
Host smart-353302a9-61e4-4f29-9240-7a125d9df326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448780640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1448780640
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3651439968
Short name T766
Test name
Test status
Simulation time 80976716 ps
CPU time 1.07 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 217176 kb
Host smart-e270fa3c-9421-47a4-b211-061c9f343f62
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651439968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3651439968
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1744234691
Short name T248
Test name
Test status
Simulation time 450780353 ps
CPU time 5.37 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:56 PM PDT 24
Peak memory 224932 kb
Host smart-0590ca31-b8c0-413e-bc82-fb5074750180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744234691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1744234691
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2793580017
Short name T218
Test name
Test status
Simulation time 300472793 ps
CPU time 3.59 seconds
Started Jul 21 07:03:56 PM PDT 24
Finished Jul 21 07:04:02 PM PDT 24
Peak memory 233044 kb
Host smart-faf0f774-5c4c-41d4-94c2-ed9066c2385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793580017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2793580017
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2265160887
Short name T141
Test name
Test status
Simulation time 1141397092 ps
CPU time 7.64 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:04:03 PM PDT 24
Peak memory 223016 kb
Host smart-6847ddf5-2141-449a-8e09-ccc2313665eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265160887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2265160887
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.251434804
Short name T180
Test name
Test status
Simulation time 14939864084 ps
CPU time 166.23 seconds
Started Jul 21 07:03:46 PM PDT 24
Finished Jul 21 07:06:33 PM PDT 24
Peak memory 254112 kb
Host smart-2ddd2017-61ed-4b71-80df-886eafa034f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251434804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.251434804
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.784496968
Short name T893
Test name
Test status
Simulation time 11629491750 ps
CPU time 8.04 seconds
Started Jul 21 07:03:49 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 216764 kb
Host smart-e9ae21be-b31f-49ff-9f3d-164486cdec9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784496968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.784496968
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2888643159
Short name T965
Test name
Test status
Simulation time 947580264 ps
CPU time 2.79 seconds
Started Jul 21 07:03:51 PM PDT 24
Finished Jul 21 07:03:58 PM PDT 24
Peak memory 216664 kb
Host smart-8f95e825-927b-4d9b-b36e-9416787a30c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888643159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2888643159
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1731357175
Short name T837
Test name
Test status
Simulation time 114700731 ps
CPU time 1.4 seconds
Started Jul 21 07:03:42 PM PDT 24
Finished Jul 21 07:03:45 PM PDT 24
Peak memory 216612 kb
Host smart-4b2b7f2b-4f90-490b-bd06-aa487e6c179f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731357175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1731357175
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1089606841
Short name T841
Test name
Test status
Simulation time 292785471 ps
CPU time 0.85 seconds
Started Jul 21 07:03:39 PM PDT 24
Finished Jul 21 07:03:41 PM PDT 24
Peak memory 206272 kb
Host smart-c1158ce5-112d-40c7-aa2e-1ec2d5e75826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089606841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1089606841
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.647977013
Short name T592
Test name
Test status
Simulation time 1476091536 ps
CPU time 7.18 seconds
Started Jul 21 07:03:48 PM PDT 24
Finished Jul 21 07:03:57 PM PDT 24
Peak memory 233088 kb
Host smart-f7f05dbc-c56d-4569-8709-7706b8c1d714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647977013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.647977013
Directory /workspace/9.spi_device_upload/latest
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