Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2825917	1			T1	1		T2	3568		T3	53052
all_values[1]	2825917	1			T1	1		T2	3568		T3	53052
all_values[2]	2825917	1			T1	1		T2	3568		T3	53052
all_values[3]	2825917	1			T1	1		T2	3568		T3	53052
all_values[4]	2825917	1			T1	1		T2	3568		T3	53052
all_values[5]	2825917	1			T1	1		T2	3568		T3	53052
all_values[6]	2825917	1			T1	1		T2	3568		T3	53052
all_values[7]	2825917	1			T1	1		T2	3568		T3	53052

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22471871

1

T1

8

T2

28544

T3

424362

auto[1]

135465

1

T3

54

T14

12026

T16

49

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22577311

1

T1

8

T2

28544

T3

424158

auto[1]

30025

1

T3

258

T14

415

T24

378

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2811021	1			T1	1		T2	3568		T3	52920
all_values[0]	auto[0]	auto[1]	14420	1			T3	128		T14	187		T24	153
all_values[0]	auto[1]	auto[0]	276	1			T3	2		T14	1		T16	4
all_values[0]	auto[1]	auto[1]	200	1			T3	2		T14	3		T16	2
all_values[1]	auto[0]	auto[0]	2781593	1			T1	1		T2	3568		T3	52978
all_values[1]	auto[0]	auto[1]	9140	1			T3	69		T14	3		T24	115
all_values[1]	auto[1]	auto[0]	34681	1			T3	1		T14	3877		T16	5
all_values[1]	auto[1]	auto[1]	503	1			T3	4		T14	124		T16	4
all_values[2]	auto[0]	auto[0]	2814011	1			T1	1		T2	3568		T3	53011
all_values[2]	auto[0]	auto[1]	3408	1			T3	33		T14	5		T24	110
all_values[2]	auto[1]	auto[0]	8216	1			T3	4		T14	3929		T16	4
all_values[2]	auto[1]	auto[1]	282	1			T3	4		T14	73		T16	1
all_values[3]	auto[0]	auto[0]	2798482	1			T1	1		T2	3568		T3	53043
all_values[3]	auto[0]	auto[1]	206	1			T14	3		T16	4		T19	4
all_values[3]	auto[1]	auto[0]	26992	1			T3	7		T14	2		T16	1
all_values[3]	auto[1]	auto[1]	237	1			T3	2		T14	4		T16	5
all_values[4]	auto[0]	auto[0]	2801806	1			T1	1		T2	3568		T3	53041
all_values[4]	auto[0]	auto[1]	213	1			T3	3		T14	1		T16	1
all_values[4]	auto[1]	auto[0]	23685	1			T3	5		T14	4		T16	6
all_values[4]	auto[1]	auto[1]	213	1			T3	3		T16	2		T18	1
all_values[5]	auto[0]	auto[0]	2813746	1			T1	1		T2	3568		T3	53044
all_values[5]	auto[0]	auto[1]	193	1			T3	2		T14	1		T16	3
all_values[5]	auto[1]	auto[0]	11786	1			T3	4		T14	3		T16	6
all_values[5]	auto[1]	auto[1]	192	1			T3	2		T14	1		T17	1
all_values[6]	auto[0]	auto[0]	2813282	1			T1	1		T2	3568		T3	53045
all_values[6]	auto[0]	auto[1]	208	1			T3	1		T14	4		T16	1
all_values[6]	auto[1]	auto[0]	12238	1			T3	5		T16	3		T17	3
all_values[6]	auto[1]	auto[1]	189	1			T3	1		T14	1		T17	2
all_values[7]	auto[0]	auto[0]	2809931	1			T1	1		T2	3568		T3	53042
all_values[7]	auto[0]	auto[1]	211	1			T3	2		T14	1		T16	1
all_values[7]	auto[1]	auto[0]	15565	1			T3	6		T14	4000		T16	4
all_values[7]	auto[1]	auto[1]	210	1			T3	2		T14	4		T16	2