Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	37376	1			T3	117		T5	8		T8	8
auto[SpiFlashAddrCfg]	7754	1			T3	35		T13	1		T14	67
auto[SpiFlashAddr3b]	9636	1			T3	64		T4	2		T8	2
auto[SpiFlashAddr4b]	8054	1			T3	41		T4	2		T13	16

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36323

1

T3

151

T4

4

T5

8

auto[1]

26497

1

T3

106

T13

16

T14

317

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32606

1

T3

139

T5

8

T8

8

auto[1]

30214

1

T3

118

T4

4

T8

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	42295	1			T3	141		T5	8		T8	10
values[1]	1156	1			T3	5		T12	4		T14	4
values[2]	1533	1			T3	4		T13	1		T14	16
values[3]	1520	1			T3	6		T4	2		T13	1
values[4]	1405	1			T3	12		T13	1		T14	17
values[5]	1517	1			T3	9		T13	1		T14	13
values[6]	1493	1			T3	7		T13	1		T14	12
values[7]	1456	1			T3	5		T13	4		T14	7
values[8]	10445	1			T3	68		T4	2		T13	10

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31857

1

T3

62

T5

8

T8

10

auto[1]

30963

1

T3

195

T4

4

T14

449

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

59332

1

T3

243

T4

4

T5

8

write

3488

1

T3

14

T13

3

T14

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

20161

1

T3

119

T4

4

T5

8

valids[0x1]

42659

1

T3

138

T8

10

T12

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1605	1			T3	13		T8	4		T13	3
internal_process_ops[0x5a]	1676	1			T3	10		T8	2		T13	3
internal_process_ops[0x05]	22856	1			T3	26		T13	2		T14	284
internal_process_ops[0x35]	1617	1			T3	11		T8	4		T14	19
internal_process_ops[0x15]	1570	1			T3	7		T13	3		T14	7
internal_process_ops[0x03]	1106	1			T3	1		T14	8		T15	3
internal_process_ops[0x0b]	1018	1			T3	1		T13	1		T14	8
internal_process_ops[0x3b]	1039	1			T3	3		T14	6		T15	3
internal_process_ops[0x6b]	1084	1			T3	6		T4	2		T14	7
internal_process_ops[0xbb]	1090	1			T3	4		T4	2		T13	1
internal_process_ops[0xeb]	1052	1			T3	6		T13	2		T14	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

61008

1

T3

251

T4

4

T5

8

auto[1]

1812

1

T3

6

T14

11

T15

7

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

60223

1

T3

247

T4

4

T5

8

auto[1]

2597

1

T3

10

T13

3

T14

22

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11362

1

T3

22

T5

8

T8

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6337

1

T3

5

T13

3

T14

23

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2062

1

T3

3

T14

5

T38

26

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1719

1

T3

5

T13

1

T14

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2547

1

T3

9

T8

2

T12

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2120

1

T3

7

T13

3

T14

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2151

1

T3

4

T13

9

T14

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1892

1

T3

2

T13

7

T14

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

94

1

T13

1

T38

1

T58

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T14

1

T38

1

T26

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

92

1

T13

2

T38

1

T26

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

126

1

T38

2

T37

2

T41

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

112

1

T38

3

T37

1

T58

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

106

1

T3

1

T14

2

T38

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T38

2

T41

5

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T38

1

T26

1

T40

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

122

1

T14

1

T26

5

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

107

1

T38

1

T37

2

T26

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T43

1

T158

1

T166

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

114

1

T3

2

T26

2

T42

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

107

1

T3

1

T38

1

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

106

1

T3

1

T14

2

T38

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T14

2

T38

1

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T14

2

T37

4

T26

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11201

1

T3

57

T14

127

T15

323

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7624

1

T3

28

T14

187

T15

192

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1596

1

T3

16

T14

19

T15

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1514

1

T3

8

T14

27

T15

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2050

1

T3

18

T4

2

T14

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1998

1

T3

27

T14

19

T15

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1627

1

T3

13

T4

2

T14

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1532

1

T3

19

T14

17

T15

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T3

3

T167

1

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

101

1

T15

1

T24

2

T168

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

125

1

T3

2

T15

1

T24

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T15

2

T24

1

T167

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

99

1

T3

1

T31

3

T18

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

121

1

T3

1

T14

2

T15

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

121

1

T15

1

T24

1

T16

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T14

2

T15

1

T169

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

93

1

T14

3

T15

1

T24

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

128

1

T24

1

T167

2

T168

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

96

1

T3

1

T14

2

T15

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

158

1

T15

2

T24

4

T167

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

120

1

T15

1

T24

1

T170

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

102

1

T3

1

T171

2

T172

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

106

1

T15

4

T167

2

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

128

1

T24

6

T173

3

T18

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3869	1			T3	12		T5	8		T13	5
auto[0]	values[0]	valids[0x1]	16746	1			T3	19		T8	10		T13	16
auto[0]	values[1]	valids[0x1]	555	1			T3	1		T12	4		T38	10
auto[0]	values[2]	valids[0x0]	507	1			T3	2		T14	3		T38	6
auto[0]	values[2]	valids[0x1]	352	1			T13	1		T14	1		T38	2
auto[0]	values[3]	valids[0x0]	597	1			T13	1		T14	2		T38	9
auto[0]	values[3]	valids[0x1]	283	1			T14	1		T38	9		T40	2
auto[0]	values[4]	valids[0x0]	487	1			T3	2		T14	3		T38	12
auto[0]	values[4]	valids[0x1]	282	1			T13	1		T14	5		T38	1
auto[0]	values[5]	valids[0x0]	527	1			T13	1		T14	4		T38	4
auto[0]	values[5]	valids[0x1]	308	1			T14	1		T38	6		T37	1
auto[0]	values[6]	valids[0x0]	537	1			T13	1		T14	3		T38	8
auto[0]	values[6]	valids[0x1]	304	1			T3	1		T14	1		T37	3
auto[0]	values[7]	valids[0x0]	509	1			T3	1		T13	2		T14	2
auto[0]	values[7]	valids[0x1]	272	1			T13	2		T14	3		T38	3
auto[0]	values[8]	valids[0x0]	3645	1			T3	18		T13	5		T14	13
auto[0]	values[8]	valids[0x1]	2077	1			T3	6		T13	5		T14	9
auto[1]	values[0]	valids[0x0]	4308	1			T3	37		T14	54		T15	53
auto[1]	values[0]	valids[0x1]	17372	1			T3	73		T14	284		T15	495
auto[1]	values[1]	valids[0x1]	601	1			T3	4		T14	4		T15	10
auto[1]	values[2]	valids[0x0]	387	1			T14	6		T15	3		T24	2
auto[1]	values[2]	valids[0x1]	287	1			T3	2		T14	6		T15	2
auto[1]	values[3]	valids[0x0]	386	1			T3	2		T4	2		T14	1
auto[1]	values[3]	valids[0x1]	254	1			T3	4		T14	5		T24	5
auto[1]	values[4]	valids[0x0]	373	1			T3	7		T14	3		T15	1
auto[1]	values[4]	valids[0x1]	263	1			T3	3		T14	6		T15	2
auto[1]	values[5]	valids[0x0]	385	1			T3	7		T14	4		T15	1
auto[1]	values[5]	valids[0x1]	297	1			T3	2		T14	4		T15	3
auto[1]	values[6]	valids[0x0]	379	1			T3	4		T14	3		T15	8
auto[1]	values[6]	valids[0x1]	273	1			T3	2		T14	5		T15	4
auto[1]	values[7]	valids[0x0]	415	1			T3	3		T15	3		T24	6
auto[1]	values[7]	valids[0x1]	260	1			T3	1		T14	2		T15	4
auto[1]	values[8]	valids[0x0]	2850	1			T3	24		T4	2		T14	41
auto[1]	values[8]	valids[0x1]	1873	1			T3	20		T14	21		T15	13