Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3161230

1

T3

19866

T4

3024

T5

2978

auto[1]

33194

1

T3

17

T13

15

T14

271

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

844939

1

T3

81

T4

3024

T5

2978

auto[1]

2349485

1

T3

19802

T8

14

T13

3057

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	632986	1			T3	547		T4	1507		T5	2
auto[524288:1048575]	363818	1			T3	4007		T4	128		T5	12
auto[1048576:1572863]	339039	1			T3	5736		T5	1098		T8	148
auto[1572864:2097151]	387358	1			T3	2638		T4	72		T5	1109
auto[2097152:2621439]	391739	1			T3	4315		T4	119		T5	757
auto[2621440:3145727]	349072	1			T3	211		T9	65		T13	13
auto[3145728:3670015]	337500	1			T3	2		T4	914		T8	483
auto[3670016:4194303]	392912	1			T3	2427		T4	284		T8	62

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2385491

1

T3

19883

T4

21

T5

13

auto[1]

808933

1

T4

3003

T5

2965

T8

916

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2764266

1

T3

17859

T4

3024

T5

2978

auto[1]

430158

1

T3

2024

T14

1546

T15

2499

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	196501	1			T3	5		T4	1507		T5	2
auto[0]	auto[0]	auto[0:524287]	auto[1]	367374	1			T3	537		T8	5		T13	3052
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	87975	1			T3	10		T4	128		T5	12
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	229219	1			T3	2694		T15	128		T24	258
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	67440	1			T3	5		T5	1098		T8	148
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	219112	1			T3	5731		T14	1025		T15	391
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	103955	1			T3	7		T4	72		T5	1109
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	225747	1			T3	2629		T8	8		T13	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103710	1			T3	9		T4	119		T5	757
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	229415	1			T3	3788		T14	1974		T15	526
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	83139	1			T3	4		T9	65		T13	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	212204	1			T14	4529		T15	1248		T24	318
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	97637	1			T3	2		T4	914		T8	483
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	189171	1			T14	131		T15	2		T24	387
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	89425	1			T3	13		T4	284		T8	61
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	234779	1			T3	2413		T8	1		T14	783
auto[0]	auto[1]	auto[0:524287]	auto[0]	885	1			T3	4		T24	2		T37	25
auto[0]	auto[1]	auto[0:524287]	auto[1]	63996	1			T3	1		T37	2		T26	1901
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2100	1			T3	11		T15	5		T24	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	41800	1			T3	1283		T15	800		T24	2039
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1325	1			T24	8		T38	2		T41	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48128	1			T24	8		T41	2693		T167	1025
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	975	1			T14	1		T26	4		T43	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	52371	1			T14	889		T26	2712		T43	768
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1397	1			T3	1		T14	2		T15	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	52091	1			T3	512		T14	5		T44	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	872	1			T14	5		T15	6		T24	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	48321	1			T3	207		T14	385		T15	7
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2563	1			T15	12		T24	7		T38	6
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44867	1			T15	777		T24	207		T38	2312
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	741	1			T15	5		T24	3		T38	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61995	1			T14	256		T15	771		T24	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	568	1			T13	7		T14	5		T15	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2954	1			T14	28		T15	74		T24	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	422	1			T3	3		T13	2		T24	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1783	1			T3	1		T24	1		T26	21
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	383	1			T14	1		T15	2		T24	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2112	1			T14	7		T15	75		T38	36
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	422	1			T3	1		T14	2		T15	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3422	1			T3	1		T14	4		T15	33
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	436	1			T3	2		T14	3		T24	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3948	1			T3	3		T14	9		T24	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	389	1			T13	6		T14	7		T15	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3155	1			T14	189		T15	24		T24	14
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	415	1			T14	3		T15	2		T24	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2223	1			T14	10		T15	10		T24	16
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	471	1			T3	1		T15	3		T24	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	4360	1			T15	79		T24	51		T38	15
auto[1]	auto[1]	auto[0:524287]	auto[0]	99	1			T173	2		T18	2		T166	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	609	1			T173	43		T18	12		T49	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	108	1			T3	3		T15	1		T24	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	411	1			T3	2		T15	25		T24	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	77	1			T24	2		T41	1		T167	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	462	1			T24	22		T41	2		T16	53
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	59	1			T167	2		T166	3		T49	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	407	1			T167	3		T166	13		T20	8
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	117	1			T173	3		T158	2		T171	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	625	1			T173	23		T158	41		T171	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	120	1			T14	1		T15	3		T44	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	872	1			T14	2		T15	21		T44	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	95	1			T15	2		T24	2		T19	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	529	1			T15	36		T24	35		T225	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	118	1			T15	1		T24	1		T158	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1023	1			T15	26		T24	9		T158	54

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1934412	1			T3	17847		T4	21		T5	13
auto[0]	auto[0]	auto[1]	802391	1			T4	3003		T5	2965		T8	916
auto[0]	auto[1]	auto[0]	418631	1			T3	2019		T14	1543		T15	2381
auto[0]	auto[1]	auto[1]	5796	1			T15	3		T24	2		T173	1
auto[1]	auto[0]	auto[0]	26852	1			T3	12		T13	12		T14	268
auto[1]	auto[0]	auto[1]	611	1			T13	3		T24	1		T38	9
auto[1]	auto[1]	auto[0]	5596	1			T3	5		T14	3		T15	113
auto[1]	auto[1]	auto[1]	135	1			T15	2		T41	1		T173	1