Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[1]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[2]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[3]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[4]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[5]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[6]	2825917	1			T1	1		T2	3568		T3	53052
all_pins[7]	2825917	1			T1	1		T2	3568		T3	53052

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22592566	1			T1	8		T2	28544		T3	424396
values[0x1]	14770	1			T3	20		T14	228		T16	16
transitions[0x0=>0x1]	14255	1			T3	14		T14	148		T16	13
transitions[0x1=>0x0]	14267	1			T3	14		T14	148		T16	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2825717	1			T1	1		T2	3568		T3	53050
all_pins[0]	values[0x1]	200	1			T3	2		T14	3		T16	2
all_pins[0]	transitions[0x0=>0x1]	139	1			T3	1		T14	3		T16	1
all_pins[0]	transitions[0x1=>0x0]	476	1			T3	3		T14	136		T16	3
all_pins[1]	values[0x0]	2825380	1			T1	1		T2	3568		T3	53048
all_pins[1]	values[0x1]	537	1			T3	4		T14	136		T16	4
all_pins[1]	transitions[0x0=>0x1]	395	1			T3	2		T14	59		T16	4
all_pins[1]	transitions[0x1=>0x0]	148	1			T3	2		T14	2		T16	1
all_pins[2]	values[0x0]	2825627	1			T1	1		T2	3568		T3	53048
all_pins[2]	values[0x1]	290	1			T3	4		T14	79		T16	1
all_pins[2]	transitions[0x0=>0x1]	239	1			T3	4		T14	78		T18	1
all_pins[2]	transitions[0x1=>0x0]	186	1			T3	2		T14	3		T16	4
all_pins[3]	values[0x0]	2825680	1			T1	1		T2	3568		T3	53050
all_pins[3]	values[0x1]	237	1			T3	2		T14	4		T16	5
all_pins[3]	transitions[0x0=>0x1]	176	1			T3	1		T14	4		T16	4
all_pins[3]	transitions[0x1=>0x0]	152	1			T3	2		T16	1		T18	1
all_pins[4]	values[0x0]	2825704	1			T1	1		T2	3568		T3	53049
all_pins[4]	values[0x1]	213	1			T3	3		T16	2		T18	1
all_pins[4]	transitions[0x0=>0x1]	162	1			T3	3		T16	2		T19	3
all_pins[4]	transitions[0x1=>0x0]	940	1			T3	2		T14	1		T17	1
all_pins[5]	values[0x0]	2824926	1			T1	1		T2	3568		T3	53050
all_pins[5]	values[0x1]	991	1			T3	2		T14	1		T17	1
all_pins[5]	transitions[0x0=>0x1]	947	1			T3	2		T14	1		T17	1
all_pins[5]	transitions[0x1=>0x0]	12048	1			T3	1		T14	1		T17	2
all_pins[6]	values[0x0]	2813825	1			T1	1		T2	3568		T3	53051
all_pins[6]	values[0x1]	12092	1			T3	1		T14	1		T17	2
all_pins[6]	transitions[0x0=>0x1]	12042	1			T17	2		T19	4		T20	2
all_pins[6]	transitions[0x1=>0x0]	160	1			T3	1		T14	3		T16	2
all_pins[7]	values[0x0]	2825707	1			T1	1		T2	3568		T3	53050
all_pins[7]	values[0x1]	210	1			T3	2		T14	4		T16	2
all_pins[7]	transitions[0x0=>0x1]	155	1			T3	1		T14	3		T16	2
all_pins[7]	transitions[0x1=>0x0]	157	1			T3	1		T14	2		T16	2