Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18977

1

T3

41

T5

8

T8

10

auto[1]

12880

1

T3

21

T13

16

T14

63

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4586	1			T3	22		T13	20		T14	20
values[1]	3391	1			T3	20		T38	20		T26	20
values[2]	3283	1			T5	8		T14	28		T38	20
values[3]	4007	1			T3	20		T14	114		T38	150
values[4]	4128	1			T8	10		T12	4		T38	123
values[5]	5062	1			T13	20		T37	40		T26	40
values[6]	4164	1			T26	20		T224	2		T40	21
values[7]	3236	1			T37	40		T43	34		T44	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4111	1			T13	20		T55	20		T215	8
values[1]	3705	1			T38	91		T37	40		T26	20
values[2]	3162	1			T38	43		T92	2		T43	20
values[3]	4197	1			T3	20		T5	8		T38	49
values[4]	3259	1			T3	20		T14	61		T37	20
values[5]	3815	1			T8	10		T38	20		T57	2
values[6]	4487	1			T3	22		T13	20		T14	70
values[7]	5121	1			T12	4		T14	31		T38	116

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	170	1			T55	20		T41	12		T226	15
auto[0]	values[0]	values[1]	217	1			T38	14		T227	2		T44	22
auto[0]	values[0]	values[2]	249	1			T197	13		T18	4		T157	9
auto[0]	values[0]	values[3]	231	1			T228	8		T41	14		T189	16
auto[0]	values[0]	values[4]	270	1			T26	28		T101	20		T41	11
auto[0]	values[0]	values[5]	438	1			T43	19		T210	16		T19	11
auto[0]	values[0]	values[6]	532	1			T3	12		T13	12		T14	6
auto[0]	values[0]	values[7]	542	1			T26	18		T229	2		T73	55
auto[0]	values[1]	values[0]	231	1			T215	8		T19	14		T90	13
auto[0]	values[1]	values[1]	112	1			T26	9		T230	2		T50	14
auto[0]	values[1]	values[2]	224	1			T157	11		T158	11		T198	8
auto[0]	values[1]	values[3]	450	1			T38	12		T41	11		T16	14
auto[0]	values[1]	values[4]	281	1			T3	14		T50	33		T231	13
auto[0]	values[1]	values[5]	352	1			T40	46		T232	14		T190	15
auto[0]	values[1]	values[6]	241	1			T16	17		T19	12		T233	16
auto[0]	values[1]	values[7]	240	1			T49	11		T19	14		T72	49
auto[0]	values[2]	values[0]	254	1			T195	4		T234	2		T185	6
auto[0]	values[2]	values[1]	241	1			T38	15		T235	6		T166	34
auto[0]	values[2]	values[2]	107	1			T92	2		T85	14		T188	11
auto[0]	values[2]	values[3]	234	1			T5	8		T91	20		T16	41
auto[0]	values[2]	values[4]	279	1			T14	17		T44	71		T16	16
auto[0]	values[2]	values[5]	272	1			T37	23		T26	13		T49	14
auto[0]	values[2]	values[6]	254	1			T158	42		T199	10		T198	9
auto[0]	values[2]	values[7]	262	1			T198	13		T22	13		T71	14
auto[0]	values[3]	values[0]	262	1			T158	34		T166	18		T236	11
auto[0]	values[3]	values[1]	388	1			T210	97		T19	27		T88	12
auto[0]	values[3]	values[2]	227	1			T38	12		T188	12		T50	5
auto[0]	values[3]	values[3]	237	1			T3	15		T38	24		T237	2
auto[0]	values[3]	values[4]	288	1			T14	26		T197	11		T50	26
auto[0]	values[3]	values[5]	242	1			T38	13		T40	15		T157	27
auto[0]	values[3]	values[6]	313	1			T14	28		T58	110		T84	10
auto[0]	values[3]	values[7]	324	1			T14	22		T38	37		T26	113
auto[0]	values[4]	values[0]	260	1			T43	46		T238	2		T212	32
auto[0]	values[4]	values[1]	260	1			T38	42		T37	10		T239	4
auto[0]	values[4]	values[2]	293	1			T41	11		T210	11		T16	38
auto[0]	values[4]	values[3]	381	1			T93	18		T158	35		T19	6
auto[0]	values[4]	values[4]	206	1			T37	10		T187	4		T166	11
auto[0]	values[4]	values[5]	204	1			T8	10		T57	2		T157	10
auto[0]	values[4]	values[6]	327	1			T38	12		T158	20		T166	14
auto[0]	values[4]	values[7]	640	1			T12	4		T38	45		T16	14
auto[0]	values[5]	values[0]	497	1			T13	12		T83	6		T43	8
auto[0]	values[5]	values[1]	469	1			T37	13		T16	125		T19	7
auto[0]	values[5]	values[2]	223	1			T41	12		T44	15		T210	11
auto[0]	values[5]	values[3]	284	1			T158	10		T49	12		T50	13
auto[0]	values[5]	values[4]	179	1			T49	9		T22	12		T240	8
auto[0]	values[5]	values[5]	371	1			T26	10		T44	52		T49	12
auto[0]	values[5]	values[6]	405	1			T26	10		T102	4		T16	11
auto[0]	values[5]	values[7]	660	1			T37	15		T184	12		T48	58
auto[0]	values[6]	values[0]	369	1			T41	15		T44	8		T18	16
auto[0]	values[6]	values[1]	179	1			T44	10		T196	14		T189	25
auto[0]	values[6]	values[2]	289	1			T43	13		T41	11		T189	10
auto[0]	values[6]	values[3]	271	1			T49	18		T189	11		T212	12
auto[0]	values[6]	values[4]	246	1			T26	9		T82	13		T166	16
auto[0]	values[6]	values[5]	364	1			T224	2		T16	23		T158	11
auto[0]	values[6]	values[6]	419	1			T50	11		T205	11		T75	10
auto[0]	values[6]	values[7]	245	1			T40	14		T82	14		T50	19
auto[0]	values[7]	values[0]	266	1			T49	12		T198	19		T22	13
auto[0]	values[7]	values[1]	237	1			T16	14		T241	2		T242	18
auto[0]	values[7]	values[2]	191	1			T158	62		T192	14		T166	15
auto[0]	values[7]	values[3]	423	1			T44	16		T189	11		T214	8
auto[0]	values[7]	values[4]	205	1			T197	13		T158	16		T222	14
auto[0]	values[7]	values[5]	97	1			T43	10		T233	14		T243	10
auto[0]	values[7]	values[6]	253	1			T37	15		T16	12		T49	19
auto[0]	values[7]	values[7]	300	1			T37	6		T166	16		T244	172
auto[1]	values[0]	values[0]	261	1			T245	10		T41	9		T226	5
auto[1]	values[0]	values[1]	231	1			T38	12		T44	56		T16	5
auto[1]	values[0]	values[2]	188	1			T197	7		T18	30		T157	11
auto[1]	values[0]	values[3]	215	1			T41	6		T189	4		T193	8
auto[1]	values[0]	values[4]	145	1			T26	8		T41	12		T16	7
auto[1]	values[0]	values[5]	191	1			T43	11		T210	45		T19	9
auto[1]	values[0]	values[6]	345	1			T3	10		T13	8		T14	14
auto[1]	values[0]	values[7]	361	1			T26	32		T73	32		T150	13
auto[1]	values[1]	values[0]	248	1			T19	9		T90	7		T220	9
auto[1]	values[1]	values[1]	57	1			T26	11		T50	6		T198	17
auto[1]	values[1]	values[2]	163	1			T157	10		T158	46		T198	12
auto[1]	values[1]	values[3]	201	1			T38	8		T42	8		T41	9
auto[1]	values[1]	values[4]	153	1			T3	6		T50	15		T231	7
auto[1]	values[1]	values[5]	154	1			T40	9		T190	5		T150	14
auto[1]	values[1]	values[6]	149	1			T16	13		T19	8		T233	4
auto[1]	values[1]	values[7]	135	1			T49	9		T19	7		T72	6
auto[1]	values[2]	values[0]	153	1			T205	9		T212	9		T246	9
auto[1]	values[2]	values[1]	208	1			T38	5		T247	14		T166	45
auto[1]	values[2]	values[2]	63	1			T188	9		T246	11		T226	9
auto[1]	values[2]	values[3]	247	1			T16	5		T88	6		T248	8
auto[1]	values[2]	values[4]	178	1			T14	11		T44	6		T16	4
auto[1]	values[2]	values[5]	145	1			T37	17		T26	11		T49	9
auto[1]	values[2]	values[6]	210	1			T158	8		T199	26		T198	23
auto[1]	values[2]	values[7]	176	1			T198	7		T22	9		T71	6
auto[1]	values[3]	values[0]	189	1			T158	9		T166	7		T236	9
auto[1]	values[3]	values[1]	324	1			T210	15		T19	13		T88	8
auto[1]	values[3]	values[2]	207	1			T38	31		T188	8		T186	12
auto[1]	values[3]	values[3]	131	1			T3	5		T38	5		T19	6
auto[1]	values[3]	values[4]	199	1			T14	7		T197	11		T50	16
auto[1]	values[3]	values[5]	168	1			T38	7		T40	5		T157	13
auto[1]	values[3]	values[6]	273	1			T14	22		T19	7		T220	9
auto[1]	values[3]	values[7]	235	1			T14	9		T38	21		T26	13
auto[1]	values[4]	values[0]	233	1			T43	6		T212	5		T71	8
auto[1]	values[4]	values[1]	121	1			T38	3		T37	10		T88	12
auto[1]	values[4]	values[2]	263	1			T41	11		T210	14		T16	3
auto[1]	values[4]	values[3]	126	1			T158	8		T249	4		T19	17
auto[1]	values[4]	values[4]	188	1			T37	10		T166	16		T19	10
auto[1]	values[4]	values[5]	157	1			T157	10		T49	11		T199	9
auto[1]	values[4]	values[6]	204	1			T38	8		T158	6		T166	6
auto[1]	values[4]	values[7]	265	1			T38	13		T16	11		T50	6
auto[1]	values[5]	values[0]	357	1			T13	8		T43	12		T41	33
auto[1]	values[5]	values[1]	260	1			T37	7		T250	4		T16	6
auto[1]	values[5]	values[2]	217	1			T41	8		T44	76		T210	9
auto[1]	values[5]	values[3]	182	1			T158	67		T49	8		T50	7
auto[1]	values[5]	values[4]	78	1			T49	17		T22	8		T251	9
auto[1]	values[5]	values[5]	203	1			T26	10		T44	16		T49	9
auto[1]	values[5]	values[6]	232	1			T26	10		T16	9		T72	57
auto[1]	values[5]	values[7]	445	1			T37	5		T197	10		T49	7
auto[1]	values[6]	values[0]	160	1			T41	11		T44	16		T18	4
auto[1]	values[6]	values[1]	136	1			T44	18		T189	15		T198	7
auto[1]	values[6]	values[2]	184	1			T43	7		T41	9		T213	22
auto[1]	values[6]	values[3]	363	1			T49	5		T189	9		T212	8
auto[1]	values[6]	values[4]	257	1			T26	11		T82	7		T166	24
auto[1]	values[6]	values[5]	368	1			T16	17		T158	9		T199	70
auto[1]	values[6]	values[6]	125	1			T50	11		T205	15		T216	9
auto[1]	values[6]	values[7]	189	1			T40	7		T82	8		T50	1
auto[1]	values[7]	values[0]	201	1			T49	8		T198	2		T22	7
auto[1]	values[7]	values[1]	265	1			T16	6		T22	7		T190	8
auto[1]	values[7]	values[2]	74	1			T158	7		T166	5		T199	7
auto[1]	values[7]	values[3]	221	1			T44	4		T189	9		T214	12
auto[1]	values[7]	values[4]	107	1			T197	7		T158	28		T50	7
auto[1]	values[7]	values[5]	89	1			T43	24		T233	6		T32	9
auto[1]	values[7]	values[6]	205	1			T37	5		T16	8		T49	1
auto[1]	values[7]	values[7]	102	1			T37	14		T166	4		T88	7