Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	401	1			T14	1		T37	4		T26	1
auto[ReadAddrCrossIntoMailbox]	313	1			T14	2		T38	4		T101	4
auto[ReadAddrCrossOutOfMailbox]	291	1			T14	3		T38	3		T37	1
auto[ReadAddrCrossAllMailbox]	219	1			T3	1		T38	3		T37	2
auto[ReadAddrOutsideMailbox]	3480	1			T3	9		T13	4		T14	16

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2268

1

T3

5

T13

4

T14

13

auto[1]

2436

1

T3

5

T14

9

T38

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	813	1			T3	1		T14	5		T38	5
read_ops[0x0b]	774	1			T3	1		T13	1		T14	2
read_ops[0x3b]	728	1			T14	3		T38	9		T37	6
read_ops[0x6b]	784	1			T3	4		T14	4		T38	8
read_ops[0xbb]	803	1			T13	1		T14	2		T38	9
read_ops[0xeb]	802	1			T3	4		T13	2		T14	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T101	1		T43	1		T16	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T101	1		T41	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T101	2		T16	1		T157	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T101	2		T197	1		T252	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T101	1		T157	1		T253	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T38	1		T101	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T3	1		T101	1		T157	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T101	1		T41	1		T253	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	308	1			T14	5		T38	3		T91	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	304	1			T38	1		T37	1		T91	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T215	1		T101	1		T102	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T215	1		T101	1		T102	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T38	2		T16	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	32	1			T40	1		T210	1		T197	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T214	1		T220	2		T233	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T40	1		T41	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T37	1		T16	1		T236	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T40	2		T41	1		T16	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	266	1			T13	1		T38	6		T37	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T3	1		T14	2		T38	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T101	1		T210	1		T197	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T37	1		T101	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T82	1		T16	1		T165	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T40	1		T16	1		T157	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T158	1		T88	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T157	1		T49	1		T198	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T101	1		T43	1		T16	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T101	1		T16	1		T238	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T14	2		T38	4		T37	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T14	1		T38	5		T37	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T14	1		T215	1		T82	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T37	2		T26	1		T215	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T38	1		T18	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T14	1		T197	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T82	1		T41	1		T158	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T41	1		T157	1		T19	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T38	1		T212	1		T88	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T16	1		T199	1		T189	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	278	1			T38	2		T37	1		T26	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	310	1			T3	4		T14	2		T38	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T37	1		T41	1		T16	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T41	2		T166	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T16	1		T19	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T38	1		T41	2		T16	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T26	1		T50	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T38	2		T26	1		T49	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T26	1		T197	1		T189	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T254	1		T255	1		T256	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	275	1			T13	1		T14	1		T38	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	324	1			T14	1		T38	4		T26	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T44	1		T16	1		T199	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T43	1		T19	1		T189	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T14	1		T41	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T158	1		T166	2		T19	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T14	2		T26	1		T101	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T14	1		T37	1		T101	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T101	1		T16	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	25	1			T38	2		T37	1		T101	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T3	4		T13	2		T14	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T14	1		T38	4		T37	3