Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4229	1			T38	91		T26	24		T184	12
values[1]	3722	1			T13	20		T38	33		T37	40
values[2]	3263	1			T14	20		T38	20		T37	20
values[3]	4555	1			T5	8		T13	20		T14	50
values[4]	4158	1			T3	22		T14	31		T38	70
values[5]	4232	1			T14	33		T38	83		T55	20
values[6]	3758	1			T3	20		T8	10		T14	28
values[7]	3940	1			T3	20		T12	4		T37	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3606	1			T3	42		T8	10		T14	33
values[1]	4432	1			T5	8		T12	4		T37	60
values[2]	3528	1			T14	59		T38	46		T37	20
values[3]	3584	1			T13	40		T55	20		T37	20
values[4]	4374	1			T14	50		T26	50		T224	2
values[5]	3690	1			T3	20		T14	20		T38	166
values[6]	3919	1			T38	98		T37	20		T26	73
values[7]	4724	1			T57	2		T91	20		T26	44

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30998

1

T3

58

T5

8

T8

10

auto[1]

859

1

T3

4

T14

7

T38

8

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	338	1			T38	20		T235	6		T22	20
auto[0]	values[0]	values[1]	723	1			T101	20		T43	19		T41	22
auto[0]	values[0]	values[2]	474	1			T38	25		T58	110		T41	17
auto[0]	values[0]	values[3]	604	1			T184	12		T48	58		T40	52
auto[0]	values[0]	values[4]	507	1			T161	18		T49	22		T149	21
auto[0]	values[0]	values[5]	416	1			T38	44		T41	24		T210	20
auto[0]	values[0]	values[6]	502	1			T18	19		T192	14		T242	18
auto[0]	values[0]	values[7]	523	1			T26	24		T197	20		T188	19
auto[0]	values[1]	values[0]	440	1			T210	23		T16	19		T157	20
auto[0]	values[1]	values[1]	514	1			T37	19		T50	21		T207	19
auto[0]	values[1]	values[2]	546	1			T16	29		T19	21		T50	20
auto[0]	values[1]	values[3]	301	1			T13	20		T43	30		T50	19
auto[0]	values[1]	values[4]	353	1			T43	20		T187	4		T88	19
auto[0]	values[1]	values[5]	455	1			T212	47		T73	59		T257	23
auto[0]	values[1]	values[6]	531	1			T38	31		T37	17		T82	20
auto[0]	values[1]	values[7]	477	1			T26	20		T188	19		T166	20
auto[0]	values[2]	values[0]	403	1			T26	35		T227	2		T44	60
auto[0]	values[2]	values[1]	508	1			T37	20		T44	18		T50	20
auto[0]	values[2]	values[2]	295	1			T92	2		T199	25		T189	20
auto[0]	values[2]	values[3]	274	1			T258	14		T189	16		T149	24
auto[0]	values[2]	values[4]	576	1			T14	20		T93	18		T16	19
auto[0]	values[2]	values[5]	379	1			T38	19		T41	20		T155	8
auto[0]	values[2]	values[6]	385	1			T197	18		T90	20		T257	23
auto[0]	values[2]	values[7]	346	1			T91	20		T157	39		T214	19
auto[0]	values[3]	values[0]	370	1			T157	20		T166	20		T71	20
auto[0]	values[3]	values[1]	751	1			T5	8		T41	20		T19	20
auto[0]	values[3]	values[2]	247	1			T82	20		T245	10		T22	23
auto[0]	values[3]	values[3]	365	1			T13	20		T26	20		T166	25
auto[0]	values[3]	values[4]	701	1			T14	30		T26	44		T41	20
auto[0]	values[3]	values[5]	484	1			T14	20		T38	58		T85	14
auto[0]	values[3]	values[6]	579	1			T41	43		T157	20		T166	18
auto[0]	values[3]	values[7]	944	1			T16	64		T158	43		T213	22
auto[0]	values[4]	values[0]	466	1			T3	18		T38	25		T83	6
auto[0]	values[4]	values[1]	383	1			T40	21		T43	34		T197	20
auto[0]	values[4]	values[2]	648	1			T14	29		T241	2		T249	2
auto[0]	values[4]	values[3]	312	1			T41	23		T221	49		T166	20
auto[0]	values[4]	values[4]	470	1			T157	20		T166	40		T50	22
auto[0]	values[4]	values[5]	774	1			T37	20		T252	6		T259	78
auto[0]	values[4]	values[6]	619	1			T38	45		T26	72		T16	20
auto[0]	values[4]	values[7]	383	1			T57	2		T40	19		T16	19
auto[0]	values[5]	values[0]	583	1			T14	29		T239	4		T260	10
auto[0]	values[5]	values[1]	549	1			T84	10		T210	109		T205	28
auto[0]	values[5]	values[2]	452	1			T38	20		T26	17		T50	20
auto[0]	values[5]	values[3]	927	1			T55	20		T37	16		T19	23
auto[0]	values[5]	values[4]	507	1			T102	4		T261	6		T88	20
auto[0]	values[5]	values[5]	310	1			T38	43		T49	18		T198	20
auto[0]	values[5]	values[6]	207	1			T38	19		T262	4		T189	20
auto[0]	values[5]	values[7]	596	1			T41	22		T49	20		T19	22
auto[0]	values[6]	values[0]	556	1			T8	10		T38	27		T43	50
auto[0]	values[6]	values[1]	551	1			T37	20		T228	8		T250	4
auto[0]	values[6]	values[2]	314	1			T14	27		T26	20		T19	20
auto[0]	values[6]	values[3]	237	1			T195	4		T44	24		T263	10
auto[0]	values[6]	values[4]	411	1			T224	2		T41	22		T158	20
auto[0]	values[6]	values[5]	548	1			T3	20		T26	53		T44	164
auto[0]	values[6]	values[6]	461	1			T41	23		T186	12		T230	2
auto[0]	values[6]	values[7]	585	1			T44	19		T16	40		T50	22
auto[0]	values[7]	values[0]	344	1			T3	20		T37	20		T215	8
auto[0]	values[7]	values[1]	319	1			T12	4		T49	21		T199	33
auto[0]	values[7]	values[2]	452	1			T37	19		T49	18		T50	19
auto[0]	values[7]	values[3]	457	1			T196	14		T158	43		T166	26
auto[0]	values[7]	values[4]	732	1			T44	39		T16	157		T199	36
auto[0]	values[7]	values[5]	248	1			T16	44		T19	24		T73	20
auto[0]	values[7]	values[6]	518	1			T237	2		T16	44		T19	23
auto[0]	values[7]	values[7]	768	1			T247	14		T86	4		T197	24
auto[1]	values[0]	values[0]	16	1			T22	1		T73	4		T246	1
auto[1]	values[0]	values[1]	29	1			T43	1		T41	2		T166	4
auto[1]	values[0]	values[2]	17	1			T38	1		T41	3		T88	2
auto[1]	values[0]	values[3]	19	1			T40	3		T158	1		T19	3
auto[1]	values[0]	values[4]	17	1			T49	1		T149	1		T220	2
auto[1]	values[0]	values[5]	9	1			T38	1		T165	2		T208	2
auto[1]	values[0]	values[6]	18	1			T18	1		T226	2		T264	4
auto[1]	values[0]	values[7]	17	1			T188	1		T166	2		T198	5
auto[1]	values[1]	values[0]	11	1			T210	2		T16	1		T22	1
auto[1]	values[1]	values[1]	30	1			T37	1		T50	4		T207	1
auto[1]	values[1]	values[2]	17	1			T16	1		T72	1		T30	2
auto[1]	values[1]	values[3]	6	1			T50	1		T256	1		T265	3
auto[1]	values[1]	values[4]	11	1			T88	1		T236	1		T266	2
auto[1]	values[1]	values[5]	9	1			T212	1		T73	1		T267	1
auto[1]	values[1]	values[6]	15	1			T38	2		T37	3		T82	2
auto[1]	values[1]	values[7]	6	1			T188	1		T198	1		T268	1
auto[1]	values[2]	values[0]	18	1			T26	1		T44	1		T269	2
auto[1]	values[2]	values[1]	12	1			T44	2		T72	1		T264	1
auto[1]	values[2]	values[2]	5	1			T198	1		T88	1		T270	1
auto[1]	values[2]	values[3]	11	1			T189	4		T201	1		T154	3
auto[1]	values[2]	values[4]	18	1			T16	1		T49	1		T30	1
auto[1]	values[2]	values[5]	7	1			T38	1		T271	1		T265	2
auto[1]	values[2]	values[6]	16	1			T197	4		T271	2		T272	3
auto[1]	values[2]	values[7]	10	1			T157	1		T214	1		T220	3
auto[1]	values[3]	values[0]	9	1			T226	1		T216	1		T254	2
auto[1]	values[3]	values[1]	18	1			T199	1		T273	1		T274	1
auto[1]	values[3]	values[2]	5	1			T149	1		T165	2		T226	1
auto[1]	values[3]	values[3]	15	1			T88	2		T207	1		T233	1
auto[1]	values[3]	values[4]	18	1			T26	6		T41	1		T158	2
auto[1]	values[3]	values[5]	11	1			T158	1		T189	1		T165	1
auto[1]	values[3]	values[6]	20	1			T166	2		T199	3		T198	1
auto[1]	values[3]	values[7]	18	1			T16	1		T158	1		T72	2
auto[1]	values[4]	values[0]	13	1			T3	4		T42	2		T264	1
auto[1]	values[4]	values[1]	10	1			T158	3		T205	1		T251	2
auto[1]	values[4]	values[2]	23	1			T14	2		T249	2		T198	2
auto[1]	values[4]	values[3]	14	1			T41	1		T221	1		T166	1
auto[1]	values[4]	values[4]	9	1			T268	1		T275	3		T276	2
auto[1]	values[4]	values[5]	12	1			T277	2		T254	1		T274	2
auto[1]	values[4]	values[6]	8	1			T26	1		T158	3		T251	1
auto[1]	values[4]	values[7]	14	1			T40	1		T16	1		T220	3
auto[1]	values[5]	values[0]	15	1			T14	4		T260	4		T226	2
auto[1]	values[5]	values[1]	10	1			T210	3		T205	2		T271	2
auto[1]	values[5]	values[2]	14	1			T26	3		T165	2		T277	1
auto[1]	values[5]	values[3]	23	1			T37	4		T226	2		T151	2
auto[1]	values[5]	values[4]	18	1			T236	2		T207	3		T165	4
auto[1]	values[5]	values[5]	9	1			T49	3		T254	1		T278	3
auto[1]	values[5]	values[6]	4	1			T38	1		T265	1		T279	1
auto[1]	values[5]	values[7]	8	1			T205	1		T207	3		T269	1
auto[1]	values[6]	values[0]	12	1			T38	2		T43	2		T49	1
auto[1]	values[6]	values[1]	16	1			T44	2		T210	2		T19	1
auto[1]	values[6]	values[2]	6	1			T14	1		T198	2		T150	1
auto[1]	values[6]	values[3]	1	1			T280	1		-	-		-	-
auto[1]	values[6]	values[4]	4	1			T281	4		-	-		-	-
auto[1]	values[6]	values[5]	17	1			T44	4		T189	2		T270	3
auto[1]	values[6]	values[6]	19	1			T41	3		T282	4		T205	3
auto[1]	values[6]	values[7]	20	1			T44	1		T50	1		T273	1
auto[1]	values[7]	values[0]	12	1			T88	1		T208	2		T264	3
auto[1]	values[7]	values[1]	9	1			T199	4		T226	1		T150	3
auto[1]	values[7]	values[2]	13	1			T37	1		T49	2		T50	1
auto[1]	values[7]	values[3]	18	1			T166	1		T220	2		T151	1
auto[1]	values[7]	values[4]	22	1			T44	1		T16	4		T32	3
auto[1]	values[7]	values[5]	2	1			T16	1		T283	1		-	-
auto[1]	values[7]	values[6]	17	1			T16	2		T220	1		T53	3
auto[1]	values[7]	values[7]	9	1			T49	3		T198	2		T264	1