Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	879	1			T3	10		T14	10		T16	10
all_values[1]	879	1			T3	10		T14	10		T16	10
all_values[2]	879	1			T3	10		T14	10		T16	10
all_values[3]	879	1			T3	10		T14	10		T16	10
all_values[4]	879	1			T3	10		T14	10		T16	10
all_values[5]	879	1			T3	10		T14	10		T16	10
all_values[6]	879	1			T3	10		T14	10		T16	10
all_values[7]	879	1			T3	10		T14	10		T16	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3753

1

T3

35

T14

53

T16

34

auto[1]

3279

1

T3

45

T14

27

T16

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2742

1

T3

33

T14

30

T16

36

auto[1]

4290

1

T3

47

T14

50

T16

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3986

1

T3

42

T14

46

T16

51

auto[1]

3046

1

T3

38

T14

34

T16

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	173	1			T3	5		T14	3		T17	2
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T16	2		T19	2		T21	1
all_values[0]	auto[0]	auto[1]	auto[0]	133	1			T3	2		T16	1		T17	2
all_values[0]	auto[0]	auto[1]	auto[1]	86	1			T14	1		T19	3		T20	2
all_values[0]	auto[1]	auto[0]	auto[1]	211	1			T3	1		T14	3		T16	1
all_values[0]	auto[1]	auto[1]	auto[1]	182	1			T3	2		T14	3		T16	6
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T3	2		T14	2		T16	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1			T14	1		T18	1		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T14	2		T16	3		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	106	1			T3	2		T16	2		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	201	1			T3	2		T14	4		T17	1
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T3	4		T14	1		T16	3
all_values[2]	auto[0]	auto[0]	auto[0]	181	1			T14	1		T17	3		T19	5
all_values[2]	auto[0]	auto[0]	auto[1]	74	1			T14	2		T16	3		T165	1
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T3	2		T16	3		T18	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T3	3		T14	2		T19	3
all_values[2]	auto[1]	auto[0]	auto[1]	220	1			T3	4		T14	4		T16	2
all_values[2]	auto[1]	auto[1]	auto[1]	166	1			T3	1		T14	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[0]	171	1			T3	3		T14	1		T17	2
all_values[3]	auto[0]	auto[0]	auto[1]	85	1			T14	2		T16	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	142	1			T3	2		T16	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[1]	110	1			T3	1		T14	2		T16	4
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T14	3		T16	2		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T3	4		T14	2		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T14	6		T16	2		T19	2
all_values[4]	auto[0]	auto[0]	auto[1]	93	1			T3	3		T21	1		T30	2
all_values[4]	auto[0]	auto[1]	auto[0]	144	1			T3	2		T14	1		T16	5
all_values[4]	auto[0]	auto[1]	auto[1]	97	1			T16	1		T18	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	206	1			T3	2		T14	1		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	164	1			T3	3		T14	2		T16	2
all_values[5]	auto[0]	auto[0]	auto[0]	249	1			T3	3		T14	6		T16	4
all_values[5]	auto[0]	auto[1]	auto[0]	245	1			T3	3		T14	2		T16	3
all_values[5]	auto[1]	auto[0]	auto[1]	209	1			T3	2		T14	1		T16	3
all_values[5]	auto[1]	auto[1]	auto[1]	176	1			T3	2		T14	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T3	3		T14	4		T16	5
all_values[6]	auto[0]	auto[0]	auto[1]	77	1			T14	3		T17	1		T18	1
all_values[6]	auto[0]	auto[1]	auto[0]	152	1			T3	2		T16	2		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T14	1		T17	1		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	223	1			T3	2		T14	1		T16	3
all_values[6]	auto[1]	auto[1]	auto[1]	177	1			T3	3		T14	1		T19	4
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T14	1		T16	3		T19	4
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T14	1		T17	2		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T3	4		T14	1		T16	2
all_values[7]	auto[0]	auto[1]	auto[1]	91	1			T14	1		T16	2		T18	2
all_values[7]	auto[1]	auto[0]	auto[1]	216	1			T3	3		T14	3		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	165	1			T3	3		T14	3		T16	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal