Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1860

1

T2

5

T3

12

T10

5

auto[1]

1960

1

T3

19

T10

4

T14

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2094

1

T2

3

T3

24

T14

17

auto[1]

1726

1

T2

2

T3

7

T10

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3020

1

T2

5

T3

21

T10

9

auto[1]

800

1

T3

10

T14

5

T23

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	724	1			T2	1		T3	5		T10	2
valid[1]	779	1			T2	2		T3	5		T10	1
valid[2]	765	1			T2	1		T3	9		T10	2
valid[3]	785	1			T3	6		T10	2		T14	5
valid[4]	767	1			T2	1		T3	6		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	114	1			T2	1		T3	2		T14	2
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T3	1		T10	2		T27	5
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T2	1		T14	2		T25	1
auto[0]	auto[0]	valid[1]	auto[1]	173	1			T2	1		T24	1		T27	5
auto[0]	auto[0]	valid[2]	auto[0]	149	1			T2	1		T3	3		T24	1
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T24	1		T27	2		T28	2
auto[0]	auto[0]	valid[3]	auto[0]	129	1			T3	1		T14	3		T23	1
auto[0]	auto[0]	valid[3]	auto[1]	178	1			T3	1		T10	1		T27	2
auto[0]	auto[0]	valid[4]	auto[0]	130	1			T3	1		T26	1		T47	1
auto[0]	auto[0]	valid[4]	auto[1]	160	1			T2	1		T10	2		T24	1
auto[0]	auto[1]	valid[0]	auto[0]	135	1			T3	1		T14	2		T23	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T24	1		T27	2		T28	3
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T3	2		T14	1		T301	1
auto[0]	auto[1]	valid[1]	auto[1]	196	1			T3	1		T10	1		T24	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T47	2		T41	1		T167	1
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T3	2		T10	2		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	133	1			T3	2		T14	2		T24	2
auto[0]	auto[1]	valid[3]	auto[1]	172	1			T10	1		T27	2		T28	7
auto[0]	auto[1]	valid[4]	auto[0]	144	1			T3	2		T24	1		T301	1
auto[0]	auto[1]	valid[4]	auto[1]	190	1			T3	2		T27	4		T28	5
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T26	1		T82	1		T301	1
auto[1]	auto[0]	valid[1]	auto[0]	84	1			T14	2		T47	1		T59	1
auto[1]	auto[0]	valid[2]	auto[0]	87	1			T3	1		T301	1		T306	1
auto[1]	auto[0]	valid[3]	auto[0]	90	1			T3	1		T24	1		T47	1
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T3	1		T24	1		T47	1
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T3	1		T47	2		T41	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T3	2		T24	2		T59	1
auto[1]	auto[1]	valid[2]	auto[0]	81	1			T3	3		T14	2		T24	2
auto[1]	auto[1]	valid[3]	auto[0]	83	1			T3	1		T24	1		T26	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T14	1		T23	1		T301	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal