Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52241

1

T2

207

T3

524

T14

358

auto[1]

16645

1

T2

34

T3

74

T10

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49908

1

T2

166

T3

408

T10

9

auto[1]

18978

1

T2

75

T3

190

T14

117

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35602	1			T2	132		T3	320		T10	9
others[1]	5834	1			T2	19		T3	52		T14	40
others[2]	5814	1			T2	15		T3	47		T14	33
others[3]	6503	1			T2	26		T3	51		T14	31
interest[1]	3783	1			T2	9		T3	42		T14	21
interest[4]	23343	1			T2	89		T3	206		T10	9
interest[64]	11350	1			T2	40		T3	86		T14	57

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17113	1			T2	79		T3	184		T14	113
auto[0]	auto[0]	others[1]	2850	1			T2	6		T3	25		T14	28
auto[0]	auto[0]	others[2]	2789	1			T2	7		T3	25		T14	25
auto[0]	auto[0]	others[3]	3144	1			T2	16		T3	31		T14	20
auto[0]	auto[0]	interest[1]	1834	1			T2	5		T3	23		T14	16
auto[0]	auto[0]	interest[4]	11040	1			T2	52		T3	119		T14	82
auto[0]	auto[0]	interest[64]	5533	1			T2	19		T3	46		T14	39
auto[0]	auto[1]	others[0]	8704	1			T2	13		T3	38		T10	9
auto[0]	auto[1]	others[1]	1383	1			T2	4		T3	9		T24	6
auto[0]	auto[1]	others[2]	1408	1			T2	2		T3	6		T24	7
auto[0]	auto[1]	others[3]	1584	1			T2	4		T3	4		T24	6
auto[0]	auto[1]	interest[1]	878	1			T2	3		T3	5		T24	1
auto[0]	auto[1]	interest[4]	5842	1			T2	10		T3	23		T10	9
auto[0]	auto[1]	interest[64]	2688	1			T2	8		T3	12		T24	12
auto[1]	auto[0]	others[0]	9785	1			T2	40		T3	98		T14	63
auto[1]	auto[0]	others[1]	1601	1			T2	9		T3	18		T14	12
auto[1]	auto[0]	others[2]	1617	1			T2	6		T3	16		T14	8
auto[1]	auto[0]	others[3]	1775	1			T2	6		T3	16		T14	11
auto[1]	auto[0]	interest[1]	1071	1			T2	1		T3	14		T14	5
auto[1]	auto[0]	interest[4]	6461	1			T2	27		T3	64		T14	34
auto[1]	auto[0]	interest[64]	3129	1			T2	13		T3	28		T14	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal