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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T116 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.927552566 Jul 22 06:36:48 PM PDT 24 Jul 22 06:37:25 PM PDT 24 536662648 ps
T117 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1418602270 Jul 22 06:37:12 PM PDT 24 Jul 22 06:37:51 PM PDT 24 10777008672 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1383965526 Jul 22 06:36:53 PM PDT 24 Jul 22 06:37:13 PM PDT 24 3537836118 ps
T114 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.907426752 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:55 PM PDT 24 136752036 ps
T100 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3956686908 Jul 22 06:36:50 PM PDT 24 Jul 22 06:37:02 PM PDT 24 368805727 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2622550291 Jul 22 06:36:59 PM PDT 24 Jul 22 06:37:01 PM PDT 24 182288488 ps
T118 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.266043758 Jul 22 06:36:54 PM PDT 24 Jul 22 06:36:59 PM PDT 24 151726937 ps
T1040 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1835860022 Jul 22 06:36:59 PM PDT 24 Jul 22 06:37:01 PM PDT 24 14028134 ps
T1041 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.259756819 Jul 22 06:36:59 PM PDT 24 Jul 22 06:37:01 PM PDT 24 11528065 ps
T134 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2603646203 Jul 22 06:36:49 PM PDT 24 Jul 22 06:36:56 PM PDT 24 198234207 ps
T119 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.617324091 Jul 22 06:37:14 PM PDT 24 Jul 22 06:37:39 PM PDT 24 1293514987 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2340694048 Jul 22 06:36:32 PM PDT 24 Jul 22 06:36:35 PM PDT 24 13188458 ps
T175 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1076458965 Jul 22 06:36:55 PM PDT 24 Jul 22 06:37:10 PM PDT 24 1948632145 ps
T106 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2716395618 Jul 22 06:36:52 PM PDT 24 Jul 22 06:36:59 PM PDT 24 53114684 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.947141344 Jul 22 06:36:31 PM PDT 24 Jul 22 06:36:34 PM PDT 24 46662371 ps
T1043 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1816072165 Jul 22 06:36:56 PM PDT 24 Jul 22 06:37:02 PM PDT 24 42159422 ps
T1044 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.930599204 Jul 22 06:36:46 PM PDT 24 Jul 22 06:37:11 PM PDT 24 324383048 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.503449819 Jul 22 06:37:14 PM PDT 24 Jul 22 06:37:16 PM PDT 24 31291792 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1493247887 Jul 22 06:37:02 PM PDT 24 Jul 22 06:37:06 PM PDT 24 156254638 ps
T105 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2288119481 Jul 22 06:36:44 PM PDT 24 Jul 22 06:36:47 PM PDT 24 349974689 ps
T1046 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3959142323 Jul 22 06:36:58 PM PDT 24 Jul 22 06:37:01 PM PDT 24 526406077 ps
T1047 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.109464293 Jul 22 06:37:00 PM PDT 24 Jul 22 06:37:01 PM PDT 24 31824721 ps
T1048 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2306758813 Jul 22 06:36:58 PM PDT 24 Jul 22 06:37:07 PM PDT 24 288948145 ps
T176 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1712452112 Jul 22 06:38:01 PM PDT 24 Jul 22 06:38:22 PM PDT 24 814295914 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.756858875 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:52 PM PDT 24 1069707374 ps
T1049 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1578607942 Jul 22 06:36:56 PM PDT 24 Jul 22 06:36:59 PM PDT 24 12458840 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.61053903 Jul 22 06:36:44 PM PDT 24 Jul 22 06:36:47 PM PDT 24 24167192 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4143483007 Jul 22 06:36:51 PM PDT 24 Jul 22 06:36:57 PM PDT 24 197383507 ps
T1052 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2972874612 Jul 22 06:37:00 PM PDT 24 Jul 22 06:37:02 PM PDT 24 17126922 ps
T1053 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3572021851 Jul 22 06:36:42 PM PDT 24 Jul 22 06:36:58 PM PDT 24 961923685 ps
T143 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.434163742 Jul 22 06:36:51 PM PDT 24 Jul 22 06:37:10 PM PDT 24 859044167 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2544924931 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 19608173 ps
T109 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1271662951 Jul 22 06:36:47 PM PDT 24 Jul 22 06:36:53 PM PDT 24 46137001 ps
T177 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.43194785 Jul 22 06:36:47 PM PDT 24 Jul 22 06:37:10 PM PDT 24 3366716398 ps
T1055 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3149254890 Jul 22 06:37:00 PM PDT 24 Jul 22 06:37:02 PM PDT 24 19452312 ps
T1056 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2370371971 Jul 22 06:37:01 PM PDT 24 Jul 22 06:37:03 PM PDT 24 14920608 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1387078872 Jul 22 06:36:46 PM PDT 24 Jul 22 06:37:03 PM PDT 24 224228672 ps
T1058 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3743284220 Jul 22 06:37:01 PM PDT 24 Jul 22 06:37:03 PM PDT 24 13913896 ps
T144 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2947157709 Jul 22 06:36:59 PM PDT 24 Jul 22 06:37:05 PM PDT 24 3126815126 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1595044030 Jul 22 06:36:32 PM PDT 24 Jul 22 06:36:40 PM PDT 24 433080761 ps
T1060 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2888060551 Jul 22 06:37:08 PM PDT 24 Jul 22 06:37:10 PM PDT 24 51483360 ps
T77 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4115018628 Jul 22 06:36:32 PM PDT 24 Jul 22 06:36:35 PM PDT 24 40562003 ps
T1061 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4079114229 Jul 22 06:36:50 PM PDT 24 Jul 22 06:36:55 PM PDT 24 46262170 ps
T1062 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1742851885 Jul 22 06:37:05 PM PDT 24 Jul 22 06:37:07 PM PDT 24 22478621 ps
T179 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3812810212 Jul 22 06:36:52 PM PDT 24 Jul 22 06:37:09 PM PDT 24 2162634170 ps
T1063 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3979536154 Jul 22 06:37:05 PM PDT 24 Jul 22 06:37:07 PM PDT 24 46415812 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3831287597 Jul 22 06:36:50 PM PDT 24 Jul 22 06:36:55 PM PDT 24 40713609 ps
T1064 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2688653348 Jul 22 06:37:05 PM PDT 24 Jul 22 06:37:07 PM PDT 24 14453582 ps
T1065 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4230558901 Jul 22 06:38:51 PM PDT 24 Jul 22 06:38:52 PM PDT 24 43946763 ps
T1066 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4041888408 Jul 22 06:36:52 PM PDT 24 Jul 22 06:36:56 PM PDT 24 19433977 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.480155971 Jul 22 06:36:51 PM PDT 24 Jul 22 06:36:56 PM PDT 24 15714504 ps
T145 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.257415855 Jul 22 06:36:49 PM PDT 24 Jul 22 06:36:55 PM PDT 24 291809195 ps
T122 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1910619669 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:51 PM PDT 24 98339758 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.586399949 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 13679637 ps
T1069 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3204676982 Jul 22 06:36:50 PM PDT 24 Jul 22 06:36:57 PM PDT 24 38476934 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3244449068 Jul 22 06:36:55 PM PDT 24 Jul 22 06:37:03 PM PDT 24 134235871 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2263619334 Jul 22 06:37:54 PM PDT 24 Jul 22 06:38:00 PM PDT 24 78355206 ps
T1070 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.111265766 Jul 22 06:37:08 PM PDT 24 Jul 22 06:37:10 PM PDT 24 27012228 ps
T178 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3536655553 Jul 22 06:37:43 PM PDT 24 Jul 22 06:38:01 PM PDT 24 560078030 ps
T1071 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2000876894 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:52 PM PDT 24 158216343 ps
T1072 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3338657832 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 15324208 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3977032567 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:45 PM PDT 24 22340531 ps
T1073 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.607994313 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:51 PM PDT 24 101501625 ps
T1074 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3798342843 Jul 22 06:37:02 PM PDT 24 Jul 22 06:37:04 PM PDT 24 23778669 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2786689006 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:58 PM PDT 24 19460556 ps
T1076 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3254108379 Jul 22 06:36:51 PM PDT 24 Jul 22 06:36:57 PM PDT 24 82257466 ps
T146 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2549847446 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:59 PM PDT 24 2592992703 ps
T147 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3558397952 Jul 22 06:36:52 PM PDT 24 Jul 22 06:37:00 PM PDT 24 647296391 ps
T163 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1779208206 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:58 PM PDT 24 432618795 ps
T1077 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2542786379 Jul 22 06:36:50 PM PDT 24 Jul 22 06:36:56 PM PDT 24 85148818 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4268133118 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:00 PM PDT 24 243599082 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1745219813 Jul 22 06:37:04 PM PDT 24 Jul 22 06:37:06 PM PDT 24 45656309 ps
T1080 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3322883546 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:00 PM PDT 24 39795851 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.221893347 Jul 22 06:36:45 PM PDT 24 Jul 22 06:36:49 PM PDT 24 277860952 ps
T79 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.844448070 Jul 22 06:36:51 PM PDT 24 Jul 22 06:36:56 PM PDT 24 21422179 ps
T1082 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1014049359 Jul 22 06:37:04 PM PDT 24 Jul 22 06:37:05 PM PDT 24 24047175 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1662998242 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:01 PM PDT 24 228730984 ps
T1084 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2466626077 Jul 22 06:36:50 PM PDT 24 Jul 22 06:37:15 PM PDT 24 2276779313 ps
T1085 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4244379830 Jul 22 06:37:01 PM PDT 24 Jul 22 06:37:03 PM PDT 24 23665834 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.874193177 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 94140431 ps
T1087 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2352364432 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:47 PM PDT 24 515116657 ps
T123 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.165488974 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:58 PM PDT 24 133613671 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.145133673 Jul 22 06:37:53 PM PDT 24 Jul 22 06:37:56 PM PDT 24 32717582 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4098957031 Jul 22 06:36:48 PM PDT 24 Jul 22 06:37:06 PM PDT 24 293173813 ps
T1089 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2258475916 Jul 22 06:37:01 PM PDT 24 Jul 22 06:37:03 PM PDT 24 13079206 ps
T125 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2940166204 Jul 22 06:36:52 PM PDT 24 Jul 22 06:36:58 PM PDT 24 141883549 ps
T1090 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2953724213 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:08 PM PDT 24 199172674 ps
T1091 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3844189283 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:54 PM PDT 24 665326613 ps
T1092 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1987633848 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:51 PM PDT 24 326591976 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1514822486 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:58 PM PDT 24 139693606 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3463207972 Jul 22 06:36:46 PM PDT 24 Jul 22 06:36:53 PM PDT 24 283146953 ps
T1095 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2801145122 Jul 22 06:36:41 PM PDT 24 Jul 22 06:37:05 PM PDT 24 8852616492 ps
T1096 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.450014190 Jul 22 06:36:31 PM PDT 24 Jul 22 06:36:34 PM PDT 24 29408630 ps
T174 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4089816000 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:59 PM PDT 24 33923521 ps
T1097 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3223261052 Jul 22 06:36:31 PM PDT 24 Jul 22 06:36:34 PM PDT 24 165403745 ps
T1098 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3066934150 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:01 PM PDT 24 55736207 ps
T1099 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1191061529 Jul 22 06:36:55 PM PDT 24 Jul 22 06:36:59 PM PDT 24 25627008 ps
T1100 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3340271427 Jul 22 06:36:45 PM PDT 24 Jul 22 06:37:11 PM PDT 24 3203545552 ps
T126 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1985804952 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:54 PM PDT 24 118149413 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2873486451 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 436817614 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2591318889 Jul 22 06:36:45 PM PDT 24 Jul 22 06:36:49 PM PDT 24 13260207 ps
T1103 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2474946165 Jul 22 06:37:06 PM PDT 24 Jul 22 06:37:07 PM PDT 24 18349062 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3784105539 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:56 PM PDT 24 247781185 ps
T1105 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2534836047 Jul 22 06:37:06 PM PDT 24 Jul 22 06:37:07 PM PDT 24 23185294 ps
T1106 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1389972934 Jul 22 06:36:52 PM PDT 24 Jul 22 06:36:59 PM PDT 24 219020937 ps
T1107 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.822103934 Jul 22 06:36:40 PM PDT 24 Jul 22 06:36:41 PM PDT 24 18032385 ps
T1108 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1922727150 Jul 22 06:37:12 PM PDT 24 Jul 22 06:37:14 PM PDT 24 18127399 ps
T1109 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.275045710 Jul 22 06:36:54 PM PDT 24 Jul 22 06:36:58 PM PDT 24 11575203 ps
T1110 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3318667779 Jul 22 06:36:56 PM PDT 24 Jul 22 06:37:18 PM PDT 24 1168230422 ps
T1111 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1459618145 Jul 22 06:36:58 PM PDT 24 Jul 22 06:37:01 PM PDT 24 122029553 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1437755203 Jul 22 06:36:48 PM PDT 24 Jul 22 06:37:07 PM PDT 24 3892205523 ps
T1113 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2227677300 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:57 PM PDT 24 32538670 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4223085821 Jul 22 06:36:47 PM PDT 24 Jul 22 06:36:58 PM PDT 24 273136276 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2138492037 Jul 22 06:36:32 PM PDT 24 Jul 22 06:36:35 PM PDT 24 160870901 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4023119414 Jul 22 06:36:58 PM PDT 24 Jul 22 06:37:02 PM PDT 24 109036556 ps
T1117 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1220897608 Jul 22 06:36:57 PM PDT 24 Jul 22 06:37:00 PM PDT 24 13440220 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4199884691 Jul 22 06:36:45 PM PDT 24 Jul 22 06:36:51 PM PDT 24 102786561 ps
T1119 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1565902984 Jul 22 06:37:03 PM PDT 24 Jul 22 06:37:04 PM PDT 24 46749339 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.374369203 Jul 22 06:36:45 PM PDT 24 Jul 22 06:37:11 PM PDT 24 750344619 ps
T1121 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1771721986 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:45 PM PDT 24 113405605 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.865932366 Jul 22 06:36:47 PM PDT 24 Jul 22 06:36:54 PM PDT 24 640150965 ps
T1123 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3452095687 Jul 22 06:36:49 PM PDT 24 Jul 22 06:36:55 PM PDT 24 165600328 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2440621442 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:53 PM PDT 24 189093238 ps
T1125 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1645888769 Jul 22 06:36:58 PM PDT 24 Jul 22 06:37:00 PM PDT 24 26781617 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2319385205 Jul 22 06:37:18 PM PDT 24 Jul 22 06:37:19 PM PDT 24 13279161 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3832868386 Jul 22 06:36:45 PM PDT 24 Jul 22 06:36:48 PM PDT 24 99713016 ps
T1128 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4290809326 Jul 22 06:36:54 PM PDT 24 Jul 22 06:37:00 PM PDT 24 44661598 ps
T1129 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1235426356 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:45 PM PDT 24 44760021 ps
T1130 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3683722264 Jul 22 06:37:06 PM PDT 24 Jul 22 06:37:08 PM PDT 24 956951187 ps
T1131 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.899024 Jul 22 06:36:55 PM PDT 24 Jul 22 06:37:05 PM PDT 24 112927859 ps
T180 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3518701171 Jul 22 06:36:43 PM PDT 24 Jul 22 06:36:53 PM PDT 24 447478440 ps
T1132 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2548574573 Jul 22 06:36:52 PM PDT 24 Jul 22 06:36:58 PM PDT 24 458675721 ps
T1133 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3254363651 Jul 22 06:38:08 PM PDT 24 Jul 22 06:38:11 PM PDT 24 627934638 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1660704348 Jul 22 06:36:45 PM PDT 24 Jul 22 06:36:49 PM PDT 24 589087879 ps
T1135 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.669709635 Jul 22 06:37:00 PM PDT 24 Jul 22 06:37:02 PM PDT 24 55252045 ps
T1136 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1543623951 Jul 22 06:36:49 PM PDT 24 Jul 22 06:36:55 PM PDT 24 62442841 ps
T1137 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2600057098 Jul 22 06:36:48 PM PDT 24 Jul 22 06:36:59 PM PDT 24 186240023 ps
T1138 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2588534433 Jul 22 06:36:50 PM PDT 24 Jul 22 06:36:58 PM PDT 24 147186865 ps
T1139 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.649258101 Jul 22 06:36:51 PM PDT 24 Jul 22 06:36:59 PM PDT 24 49759601 ps
T1140 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3240356764 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:58 PM PDT 24 169169322 ps
T1141 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.839480371 Jul 22 06:38:51 PM PDT 24 Jul 22 06:38:52 PM PDT 24 48134790 ps
T1142 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1842210507 Jul 22 06:36:54 PM PDT 24 Jul 22 06:36:58 PM PDT 24 15240305 ps
T1143 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1654670909 Jul 22 06:37:00 PM PDT 24 Jul 22 06:37:02 PM PDT 24 63625797 ps
T1144 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3789761274 Jul 22 06:36:44 PM PDT 24 Jul 22 06:37:00 PM PDT 24 1136597274 ps
T1145 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.242778910 Jul 22 06:36:53 PM PDT 24 Jul 22 06:36:57 PM PDT 24 27314117 ps
T1146 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2363912174 Jul 22 06:36:54 PM PDT 24 Jul 22 06:36:59 PM PDT 24 628571256 ps
T1147 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3968027703 Jul 22 06:38:51 PM PDT 24 Jul 22 06:38:52 PM PDT 24 14653327 ps
T1148 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2530508148 Jul 22 06:36:55 PM PDT 24 Jul 22 06:37:01 PM PDT 24 93125125 ps
T1149 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1347227625 Jul 22 06:37:01 PM PDT 24 Jul 22 06:37:04 PM PDT 24 334926769 ps
T1150 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1817512631 Jul 22 06:37:14 PM PDT 24 Jul 22 06:37:15 PM PDT 24 12111263 ps

Test location /workspace/coverage/default/33.spi_device_stress_all.2601237674
Short name T3
Test name
Test status
Simulation time 45945710030 ps
CPU time 424.06 seconds
Started Jul 22 05:00:26 PM PDT 24
Finished Jul 22 05:07:32 PM PDT 24
Peak memory 267468 kb
Host smart-a637f9e1-3b14-4eff-8e68-1eb100db1b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601237674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2601237674
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2162556407
Short name T8
Test name
Test status
Simulation time 1386682708 ps
CPU time 5.31 seconds
Started Jul 22 05:00:07 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 233532 kb
Host smart-b19a985d-c996-41aa-8430-c04bcba4219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162556407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2162556407
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4200826032
Short name T16
Test name
Test status
Simulation time 191344925358 ps
CPU time 180.56 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 05:02:19 PM PDT 24
Peak memory 270616 kb
Host smart-383a6825-6c83-4473-86d9-2bfdc5360d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200826032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4200826032
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1375601885
Short name T108
Test name
Test status
Simulation time 1557356986 ps
CPU time 3.08 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 217532 kb
Host smart-6acf6ab0-f4d5-4af2-807d-28ad4dbb9436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375601885 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1375601885
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3026036949
Short name T14
Test name
Test status
Simulation time 6424938481 ps
CPU time 118.27 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:02:55 PM PDT 24
Peak memory 261300 kb
Host smart-eb533022-93e6-421c-9ec5-1c71d55e36e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026036949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3026036949
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2692325919
Short name T62
Test name
Test status
Simulation time 16963572 ps
CPU time 0.71 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 216692 kb
Host smart-76a72fcf-b2e2-4d30-ac08-e35bbf9134a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692325919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2692325919
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2904065948
Short name T41
Test name
Test status
Simulation time 87254818893 ps
CPU time 459.31 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 05:05:03 PM PDT 24
Peak memory 267476 kb
Host smart-de3bb142-c463-4943-8c16-19c5ac1b8e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904065948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2904065948
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.596678399
Short name T198
Test name
Test status
Simulation time 42043466610 ps
CPU time 203.59 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 05:02:52 PM PDT 24
Peak memory 273828 kb
Host smart-93908aab-77c0-4b1a-95c6-dd63e3f261ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596678399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.596678399
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.182878242
Short name T226
Test name
Test status
Simulation time 341709007468 ps
CPU time 843.03 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 05:13:50 PM PDT 24
Peak memory 282944 kb
Host smart-2d9f15e9-309e-4c7b-9428-7edad07d5b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182878242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.182878242
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2681269344
Short name T49
Test name
Test status
Simulation time 146832229293 ps
CPU time 703.09 seconds
Started Jul 22 05:04:58 PM PDT 24
Finished Jul 22 05:16:41 PM PDT 24
Peak memory 274508 kb
Host smart-e99bc9cb-1e8a-4243-8e8c-59a5df3f4806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681269344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2681269344
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2234525512
Short name T96
Test name
Test status
Simulation time 3138005840 ps
CPU time 20.43 seconds
Started Jul 22 06:36:31 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216208 kb
Host smart-0e2e6c3b-ae02-4ee0-92c3-35743b4b48e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234525512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2234525512
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.402066013
Short name T158
Test name
Test status
Simulation time 86188067968 ps
CPU time 341.98 seconds
Started Jul 22 04:58:18 PM PDT 24
Finished Jul 22 05:04:01 PM PDT 24
Peak memory 265516 kb
Host smart-b5136bf5-414a-4781-adef-a8c901a1f4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402066013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.402066013
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4227534305
Short name T4
Test name
Test status
Simulation time 4310676141 ps
CPU time 18.96 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:48 PM PDT 24
Peak memory 236852 kb
Host smart-109f9c6a-5a54-446e-9a21-85cb1233bbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227534305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4227534305
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2831356372
Short name T320
Test name
Test status
Simulation time 25921063 ps
CPU time 0.74 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 206028 kb
Host smart-37ca646e-ed9c-48d3-845e-41f89a383247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831356372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2831356372
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1157162611
Short name T50
Test name
Test status
Simulation time 79383448041 ps
CPU time 796.07 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 05:11:37 PM PDT 24
Peak memory 253648 kb
Host smart-86e839d4-b1de-4d87-a445-e86ac48fe1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157162611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1157162611
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.534030294
Short name T264
Test name
Test status
Simulation time 35983213605 ps
CPU time 126.83 seconds
Started Jul 22 05:01:07 PM PDT 24
Finished Jul 22 05:03:14 PM PDT 24
Peak memory 273740 kb
Host smart-4bebe9ab-bdd9-42b2-9369-4dde212718d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534030294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.534030294
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.617324091
Short name T119
Test name
Test status
Simulation time 1293514987 ps
CPU time 24.53 seconds
Started Jul 22 06:37:14 PM PDT 24
Finished Jul 22 06:37:39 PM PDT 24
Peak memory 207792 kb
Host smart-2c053189-f3f1-4da4-9918-741f9ea3fb76
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617324091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.617324091
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2719846048
Short name T104
Test name
Test status
Simulation time 241525954 ps
CPU time 4.33 seconds
Started Jul 22 06:37:14 PM PDT 24
Finished Jul 22 06:37:19 PM PDT 24
Peak memory 215944 kb
Host smart-db0ac0d4-3fec-45a5-a1eb-17aef669607f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719846048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
719846048
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3192182041
Short name T34
Test name
Test status
Simulation time 377837815 ps
CPU time 1.03 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 218636 kb
Host smart-e294f9e9-872a-4ee8-be29-a4351378546e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192182041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3192182041
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.89522442
Short name T168
Test name
Test status
Simulation time 28465252837 ps
CPU time 101.52 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 05:00:31 PM PDT 24
Peak memory 233820 kb
Host smart-9941c4b7-5197-41f2-800c-450d9a9cb1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89522442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.89522442
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4085950562
Short name T271
Test name
Test status
Simulation time 21526669965 ps
CPU time 93.98 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:02:00 PM PDT 24
Peak memory 250408 kb
Host smart-ec75ef43-b0fe-4cfc-abea-601abe30a353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085950562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4085950562
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.4167759199
Short name T20
Test name
Test status
Simulation time 77469948058 ps
CPU time 361.18 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 05:05:12 PM PDT 24
Peak memory 266504 kb
Host smart-a58966c7-a143-4897-afcc-3363331a7480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167759199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.4167759199
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.236152791
Short name T825
Test name
Test status
Simulation time 4639698485 ps
CPU time 102.08 seconds
Started Jul 22 04:57:59 PM PDT 24
Finished Jul 22 04:59:42 PM PDT 24
Peak memory 268880 kb
Host smart-cca792da-c970-41d3-9384-4fc793c022a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236152791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
236152791
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3238308418
Short name T65
Test name
Test status
Simulation time 1548745782 ps
CPU time 1.17 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 237488 kb
Host smart-2552ac2e-dcde-4da2-8e4b-5d73a11a891f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238308418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3238308418
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3106763988
Short name T207
Test name
Test status
Simulation time 10344259595 ps
CPU time 59.28 seconds
Started Jul 22 05:01:15 PM PDT 24
Finished Jul 22 05:02:15 PM PDT 24
Peak memory 253244 kb
Host smart-5ab124db-86e3-4827-8219-a6f42816b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106763988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3106763988
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3483310657
Short name T38
Test name
Test status
Simulation time 1054836242498 ps
CPU time 374.02 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 05:05:23 PM PDT 24
Peak memory 265412 kb
Host smart-0e85e04a-a961-4012-adfc-19a37bd56708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483310657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3483310657
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2753062380
Short name T254
Test name
Test status
Simulation time 341449672152 ps
CPU time 595.59 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 05:08:02 PM PDT 24
Peak memory 267344 kb
Host smart-6dcd301a-85cb-4f54-b5fe-3e3bfbb16d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753062380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2753062380
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2398340712
Short name T24
Test name
Test status
Simulation time 3948181644 ps
CPU time 100.07 seconds
Started Jul 22 05:00:58 PM PDT 24
Finished Jul 22 05:02:39 PM PDT 24
Peak memory 258272 kb
Host smart-d3cf58d2-29eb-4ec4-b432-eb5e39753763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398340712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2398340712
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2318745956
Short name T19
Test name
Test status
Simulation time 71610639217 ps
CPU time 585.33 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:10:24 PM PDT 24
Peak memory 267820 kb
Host smart-741b8b70-2976-45e8-9d4c-aba9a5bebf34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318745956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2318745956
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3389380166
Short name T59
Test name
Test status
Simulation time 1941137541 ps
CPU time 21.5 seconds
Started Jul 22 05:04:25 PM PDT 24
Finished Jul 22 05:04:48 PM PDT 24
Peak memory 217068 kb
Host smart-a0e547c3-00d2-4396-b761-371696f232cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389380166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3389380166
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1712452112
Short name T176
Test name
Test status
Simulation time 814295914 ps
CPU time 21.71 seconds
Started Jul 22 06:38:01 PM PDT 24
Finished Jul 22 06:38:22 PM PDT 24
Peak memory 216756 kb
Host smart-98d5fcee-eccf-45bd-9c63-c823c39f0811
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712452112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1712452112
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.657458789
Short name T22
Test name
Test status
Simulation time 107657676852 ps
CPU time 478.97 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 05:07:20 PM PDT 24
Peak memory 255376 kb
Host smart-f59155cd-2785-4b39-be5c-64f5ba62e6ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657458789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.657458789
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4027354733
Short name T189
Test name
Test status
Simulation time 155417153457 ps
CPU time 298.63 seconds
Started Jul 22 04:59:56 PM PDT 24
Finished Jul 22 05:04:55 PM PDT 24
Peak memory 267044 kb
Host smart-b9be5331-dbe0-4a3f-9e89-ed5133feaf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027354733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4027354733
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.49432957
Short name T307
Test name
Test status
Simulation time 135017739939 ps
CPU time 87.06 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 249000 kb
Host smart-66cd8827-65e8-496a-9d75-083bf4b827d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49432957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress
_all.49432957
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.291322282
Short name T133
Test name
Test status
Simulation time 230522766 ps
CPU time 2.91 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 215992 kb
Host smart-8bbc7a69-1914-4c5a-a46e-894cb6a48d21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291322282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.291322282
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1606237618
Short name T95
Test name
Test status
Simulation time 60108130 ps
CPU time 2.01 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 216240 kb
Host smart-5a0528b2-16c2-4e95-97cb-daed7e6ba873
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606237618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1606237618
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1176029173
Short name T284
Test name
Test status
Simulation time 2081691962 ps
CPU time 13.27 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:16 PM PDT 24
Peak memory 234684 kb
Host smart-ef40080f-daf7-4592-9b25-16c92effe3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176029173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1176029173
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3129189174
Short name T265
Test name
Test status
Simulation time 68739962661 ps
CPU time 421.75 seconds
Started Jul 22 04:58:06 PM PDT 24
Finished Jul 22 05:05:09 PM PDT 24
Peak memory 271220 kb
Host smart-27212eeb-0d49-4c01-83c5-f6e2001bfca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129189174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3129189174
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2365384150
Short name T172
Test name
Test status
Simulation time 3484267926 ps
CPU time 76.34 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:04:34 PM PDT 24
Peak memory 254324 kb
Host smart-9be76756-0aad-4dfd-999c-7502a812cc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365384150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2365384150
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2083600411
Short name T848
Test name
Test status
Simulation time 66713824669 ps
CPU time 440.85 seconds
Started Jul 22 05:00:34 PM PDT 24
Finished Jul 22 05:07:56 PM PDT 24
Peak memory 266412 kb
Host smart-e6b88c8f-80cf-47a4-9729-e36432d82e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083600411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2083600411
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.46706388
Short name T290
Test name
Test status
Simulation time 816042554 ps
CPU time 6.46 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:30 PM PDT 24
Peak memory 225456 kb
Host smart-a683e6be-3843-4cdd-a9f0-79e1facf4a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46706388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.46706388
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2728115888
Short name T26
Test name
Test status
Simulation time 260593322304 ps
CPU time 249.51 seconds
Started Jul 22 05:00:52 PM PDT 24
Finished Jul 22 05:05:02 PM PDT 24
Peak memory 265856 kb
Host smart-8f86fedc-6fe5-4114-ac55-218d8b81f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728115888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2728115888
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3536655553
Short name T178
Test name
Test status
Simulation time 560078030 ps
CPU time 17.75 seconds
Started Jul 22 06:37:43 PM PDT 24
Finished Jul 22 06:38:01 PM PDT 24
Peak memory 216044 kb
Host smart-f74c1928-6125-458b-8379-154d6b8a09f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536655553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3536655553
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1942753517
Short name T507
Test name
Test status
Simulation time 24733039744 ps
CPU time 75.6 seconds
Started Jul 22 04:57:08 PM PDT 24
Finished Jul 22 04:58:24 PM PDT 24
Peak memory 255496 kb
Host smart-2e002154-13ef-47ad-af5d-29cc57ab9b21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942753517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1942753517
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2942956762
Short name T285
Test name
Test status
Simulation time 5097841287 ps
CPU time 68.75 seconds
Started Jul 22 04:58:10 PM PDT 24
Finished Jul 22 04:59:19 PM PDT 24
Peak memory 251632 kb
Host smart-ba6bcb92-6fa5-4854-9a83-1e27b5e2923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942956762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2942956762
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.327249007
Short name T280
Test name
Test status
Simulation time 8921862599 ps
CPU time 60.5 seconds
Started Jul 22 04:59:44 PM PDT 24
Finished Jul 22 05:00:45 PM PDT 24
Peak memory 250128 kb
Host smart-ed4f10e6-8489-4ed0-8a56-c244382846aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327249007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.327249007
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3187961513
Short name T281
Test name
Test status
Simulation time 4171756191 ps
CPU time 37.28 seconds
Started Jul 22 05:06:29 PM PDT 24
Finished Jul 22 05:07:07 PM PDT 24
Peak memory 251488 kb
Host smart-b188e4ab-eed7-41b0-ab7a-480c9f2fc2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187961513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3187961513
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2111117198
Short name T97
Test name
Test status
Simulation time 193780265 ps
CPU time 3.01 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 216284 kb
Host smart-8095e6cb-352f-4aeb-92be-c93377fe7d00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111117198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2111117198
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.979245089
Short name T245
Test name
Test status
Simulation time 4330980562 ps
CPU time 9.56 seconds
Started Jul 22 04:58:11 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 233616 kb
Host smart-4a1f7b62-7221-4a29-9c63-962f88678367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979245089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.979245089
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4115018628
Short name T77
Test name
Test status
Simulation time 40562003 ps
CPU time 1.45 seconds
Started Jul 22 06:36:32 PM PDT 24
Finished Jul 22 06:36:35 PM PDT 24
Peak memory 207868 kb
Host smart-c7b4fd80-b762-459f-a3af-8c3a5aabd955
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115018628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4115018628
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.148868374
Short name T32
Test name
Test status
Simulation time 20324118710 ps
CPU time 152.63 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:03:08 PM PDT 24
Peak memory 267260 kb
Host smart-5bb71b45-ee7f-497e-b8a8-996c1eac990d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148868374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.148868374
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1437755203
Short name T1112
Test name
Test status
Simulation time 3892205523 ps
CPU time 15.7 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 216144 kb
Host smart-35ae1d29-df67-481a-b38e-c082d7830451
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437755203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1437755203
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1595044030
Short name T1059
Test name
Test status
Simulation time 433080761 ps
CPU time 1.96 seconds
Started Jul 22 06:36:32 PM PDT 24
Finished Jul 22 06:36:40 PM PDT 24
Peak memory 217160 kb
Host smart-52c3cf3a-e209-43cf-94a1-84c99b3423d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595044030 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1595044030
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3223261052
Short name T1097
Test name
Test status
Simulation time 165403745 ps
CPU time 1.48 seconds
Started Jul 22 06:36:31 PM PDT 24
Finished Jul 22 06:36:34 PM PDT 24
Peak memory 207864 kb
Host smart-3131a1f4-6b28-4da6-a65b-1a6e670f4361
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223261052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
223261052
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2340694048
Short name T1042
Test name
Test status
Simulation time 13188458 ps
CPU time 0.72 seconds
Started Jul 22 06:36:32 PM PDT 24
Finished Jul 22 06:36:35 PM PDT 24
Peak memory 204504 kb
Host smart-07c4fe31-bd9c-4762-a6e7-98d0be26709e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340694048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
340694048
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.503449819
Short name T120
Test name
Test status
Simulation time 31291792 ps
CPU time 1.41 seconds
Started Jul 22 06:37:14 PM PDT 24
Finished Jul 22 06:37:16 PM PDT 24
Peak memory 215616 kb
Host smart-36be7319-c7b6-42a2-be85-f2667039b388
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503449819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.503449819
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1817512631
Short name T1150
Test name
Test status
Simulation time 12111263 ps
CPU time 0.69 seconds
Started Jul 22 06:37:14 PM PDT 24
Finished Jul 22 06:37:15 PM PDT 24
Peak memory 204016 kb
Host smart-5210d6e7-1fc1-4168-bd52-bf47302b1be9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817512631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1817512631
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3832868386
Short name T1127
Test name
Test status
Simulation time 99713016 ps
CPU time 1.73 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:36:48 PM PDT 24
Peak memory 216036 kb
Host smart-a813566c-3219-45e7-b89e-be51593ba2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832868386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3832868386
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2801145122
Short name T1095
Test name
Test status
Simulation time 8852616492 ps
CPU time 23.84 seconds
Started Jul 22 06:36:41 PM PDT 24
Finished Jul 22 06:37:05 PM PDT 24
Peak memory 216200 kb
Host smart-45841b30-0828-43ad-aeba-1185686f1caf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801145122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2801145122
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4098957031
Short name T124
Test name
Test status
Simulation time 293173813 ps
CPU time 14.46 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:37:06 PM PDT 24
Peak memory 216104 kb
Host smart-b5c52ded-4b8d-49ce-915f-441f7c28afe6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098957031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4098957031
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1418602270
Short name T117
Test name
Test status
Simulation time 10777008672 ps
CPU time 37.64 seconds
Started Jul 22 06:37:12 PM PDT 24
Finished Jul 22 06:37:51 PM PDT 24
Peak memory 216016 kb
Host smart-fba6b94b-792a-4d9f-b811-b2393f01c2ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418602270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1418602270
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3977032567
Short name T78
Test name
Test status
Simulation time 22340531 ps
CPU time 0.98 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:45 PM PDT 24
Peak memory 207580 kb
Host smart-dd252396-3d3f-40e1-88b8-d911ae7e1006
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977032567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3977032567
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3254108379
Short name T1076
Test name
Test status
Simulation time 82257466 ps
CPU time 2.62 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:57 PM PDT 24
Peak memory 217828 kb
Host smart-ab4527c7-f461-499c-9fca-6d717698cf4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254108379 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3254108379
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.947141344
Short name T142
Test name
Test status
Simulation time 46662371 ps
CPU time 1.4 seconds
Started Jul 22 06:36:31 PM PDT 24
Finished Jul 22 06:36:34 PM PDT 24
Peak memory 207880 kb
Host smart-6d257082-61b3-44b3-a087-3112f993647f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947141344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.947141344
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2319385205
Short name T1126
Test name
Test status
Simulation time 13279161 ps
CPU time 0.69 seconds
Started Jul 22 06:37:18 PM PDT 24
Finished Jul 22 06:37:19 PM PDT 24
Peak memory 204656 kb
Host smart-abda01ee-b17c-4c23-873d-eb4fb4b62d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319385205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
319385205
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2138492037
Short name T1115
Test name
Test status
Simulation time 160870901 ps
CPU time 1.33 seconds
Started Jul 22 06:36:32 PM PDT 24
Finished Jul 22 06:36:35 PM PDT 24
Peak memory 216080 kb
Host smart-b64da6f8-8d0c-4d0c-84eb-73aba92aa1c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138492037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2138492037
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.450014190
Short name T1096
Test name
Test status
Simulation time 29408630 ps
CPU time 0.66 seconds
Started Jul 22 06:36:31 PM PDT 24
Finished Jul 22 06:36:34 PM PDT 24
Peak memory 204372 kb
Host smart-36696494-80dc-45d1-b650-4003fb7cb347
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450014190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.450014190
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2973438468
Short name T103
Test name
Test status
Simulation time 123988149 ps
CPU time 3.63 seconds
Started Jul 22 06:37:17 PM PDT 24
Finished Jul 22 06:37:22 PM PDT 24
Peak memory 216104 kb
Host smart-02b152dd-f39e-4077-8d36-ee6ddec5bb06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973438468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
973438468
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1816072165
Short name T1043
Test name
Test status
Simulation time 42159422 ps
CPU time 2.63 seconds
Started Jul 22 06:36:56 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 218928 kb
Host smart-417ab670-72ae-45bd-80c0-fba0725b793e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816072165 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1816072165
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3240356764
Short name T1140
Test name
Test status
Simulation time 169169322 ps
CPU time 1.41 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 207780 kb
Host smart-e4aec185-24c1-482c-aa7d-9a08a8555e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240356764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3240356764
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1842210507
Short name T1142
Test name
Test status
Simulation time 15240305 ps
CPU time 0.86 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 204496 kb
Host smart-01344ccf-6247-4531-b447-b613392d400c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842210507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1842210507
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.329397819
Short name T132
Test name
Test status
Simulation time 158076227 ps
CPU time 4.2 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 215956 kb
Host smart-03237b16-17d2-4136-b2d0-44575639334a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329397819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.329397819
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.43194785
Short name T177
Test name
Test status
Simulation time 3366716398 ps
CPU time 19.95 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:37:10 PM PDT 24
Peak memory 216176 kb
Host smart-46a018ca-ac55-4917-bf51-c9b236dacc90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43194785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.43194785
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.257415855
Short name T145
Test name
Test status
Simulation time 291809195 ps
CPU time 2.01 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 217208 kb
Host smart-f9d87b81-516d-4c14-a170-d2f73508d898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257415855 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.257415855
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4001414053
Short name T131
Test name
Test status
Simulation time 118903854 ps
CPU time 1.31 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:51 PM PDT 24
Peak memory 207908 kb
Host smart-56b6958a-91a5-4dee-90be-a548cc7f8b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001414053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4001414053
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2227677300
Short name T1113
Test name
Test status
Simulation time 32538670 ps
CPU time 0.73 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:57 PM PDT 24
Peak memory 204512 kb
Host smart-751dadc1-6806-4c6a-a929-4b56a30835c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227677300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2227677300
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3330121910
Short name T130
Test name
Test status
Simulation time 1998604841 ps
CPU time 4.33 seconds
Started Jul 22 06:36:56 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 216064 kb
Host smart-d6fde374-9ffc-4d06-ae00-781078a5a2f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330121910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3330121910
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3463207972
Short name T1094
Test name
Test status
Simulation time 283146953 ps
CPU time 3.25 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216220 kb
Host smart-9987ab4a-8852-46e8-93bf-c5e5fb1a6fc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463207972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3463207972
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2603646203
Short name T134
Test name
Test status
Simulation time 198234207 ps
CPU time 2.3 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 215932 kb
Host smart-5593473a-eee9-43fc-ab02-ede75de709c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603646203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2603646203
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.480155971
Short name T1067
Test name
Test status
Simulation time 15714504 ps
CPU time 0.76 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 204772 kb
Host smart-c045fad8-ee17-48e2-802a-979a73a1520e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480155971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.480155971
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2947157709
Short name T144
Test name
Test status
Simulation time 3126815126 ps
CPU time 4.29 seconds
Started Jul 22 06:36:59 PM PDT 24
Finished Jul 22 06:37:05 PM PDT 24
Peak memory 216128 kb
Host smart-822d5a55-db38-4119-9b36-e81a82c1f398
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947157709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2947157709
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1389972934
Short name T1106
Test name
Test status
Simulation time 219020937 ps
CPU time 3.48 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216252 kb
Host smart-45cba2bb-1845-452b-b773-8283035dff9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389972934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1389972934
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3956686908
Short name T100
Test name
Test status
Simulation time 368805727 ps
CPU time 7.93 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 216020 kb
Host smart-8f5f48a8-c0f3-4abf-8fdf-7ab26bf74d76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956686908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3956686908
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.649258101
Short name T1139
Test name
Test status
Simulation time 49759601 ps
CPU time 3.34 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 218020 kb
Host smart-df84df7d-8361-40b9-8935-b4b6046cd74a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649258101 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.649258101
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3452095687
Short name T1123
Test name
Test status
Simulation time 165600328 ps
CPU time 2.15 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 216096 kb
Host smart-2fbea929-2acc-4a0f-a32c-da9f0953827d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452095687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3452095687
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3338657832
Short name T1072
Test name
Test status
Simulation time 15324208 ps
CPU time 0.77 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 204544 kb
Host smart-d769acc3-09b4-44f0-8c99-29572807213b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338657832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3338657832
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.865932366
Short name T1122
Test name
Test status
Simulation time 640150965 ps
CPU time 2.91 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:54 PM PDT 24
Peak memory 216008 kb
Host smart-a0cf98f0-dd5c-46bd-8935-aa14f0f8639c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865932366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.865932366
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3244449068
Short name T110
Test name
Test status
Simulation time 134235871 ps
CPU time 4.74 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 216296 kb
Host smart-d18322dd-9757-46cd-bf98-a614d6c3795b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244449068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3244449068
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3812810212
Short name T179
Test name
Test status
Simulation time 2162634170 ps
CPU time 13.79 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:37:09 PM PDT 24
Peak memory 216432 kb
Host smart-ad647bfc-ccf2-4e55-87e0-048ac0562058
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812810212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3812810212
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2476281828
Short name T113
Test name
Test status
Simulation time 184748874 ps
CPU time 1.6 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 216152 kb
Host smart-c32bd7a2-8d4c-41ca-953f-c4c17ec1050e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476281828 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2476281828
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1779208206
Short name T163
Test name
Test status
Simulation time 432618795 ps
CPU time 1.47 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 207772 kb
Host smart-f3b56cb8-96d9-4385-9aca-9520a1375bfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779208206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1779208206
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.586399949
Short name T1068
Test name
Test status
Simulation time 13679637 ps
CPU time 0.73 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 204528 kb
Host smart-7722ae56-8f47-492e-9771-4f39bf14a2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586399949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.586399949
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2000876894
Short name T1071
Test name
Test status
Simulation time 158216343 ps
CPU time 3.07 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:52 PM PDT 24
Peak memory 215924 kb
Host smart-27206f00-93e5-46bc-9b78-2457a3a68a61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000876894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2000876894
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4268133118
Short name T1078
Test name
Test status
Simulation time 243599082 ps
CPU time 3.27 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 216452 kb
Host smart-387b1038-c0fb-451f-9c37-3d852b9f5c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268133118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4268133118
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1076458965
Short name T175
Test name
Test status
Simulation time 1948632145 ps
CPU time 12.24 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:37:10 PM PDT 24
Peak memory 216284 kb
Host smart-0345004a-38c9-4a55-8e07-ef89dfd19825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076458965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1076458965
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3322883546
Short name T1080
Test name
Test status
Simulation time 39795851 ps
CPU time 2.86 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 217228 kb
Host smart-6bbf4fed-6860-4260-ac02-49322743dddb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322883546 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3322883546
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.266043758
Short name T118
Test name
Test status
Simulation time 151726937 ps
CPU time 2.28 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 207848 kb
Host smart-4888c9a6-4ea3-4429-baa6-aa39a5553894
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266043758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.266043758
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3800290306
Short name T1037
Test name
Test status
Simulation time 14663720 ps
CPU time 0.74 seconds
Started Jul 22 06:37:58 PM PDT 24
Finished Jul 22 06:37:59 PM PDT 24
Peak memory 204784 kb
Host smart-fc7a2294-58c6-446a-b034-b707f460183c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800290306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3800290306
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3683722264
Short name T1130
Test name
Test status
Simulation time 956951187 ps
CPU time 1.66 seconds
Started Jul 22 06:37:06 PM PDT 24
Finished Jul 22 06:37:08 PM PDT 24
Peak memory 215724 kb
Host smart-93b9a252-dfeb-4914-9ab1-7dc57c316839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683722264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3683722264
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3204676982
Short name T1069
Test name
Test status
Simulation time 38476934 ps
CPU time 2.66 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:36:57 PM PDT 24
Peak memory 217852 kb
Host smart-7a070c69-4270-4601-93d5-168d2a64afd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204676982 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3204676982
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.165488974
Short name T123
Test name
Test status
Simulation time 133613671 ps
CPU time 1.34 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 216112 kb
Host smart-c6db1a8e-a433-469c-bf32-1110c6d72c9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165488974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.165488974
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4041888408
Short name T1066
Test name
Test status
Simulation time 19433977 ps
CPU time 0.79 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 204820 kb
Host smart-7a8f48c1-66da-41b6-8156-42fcb1c885ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041888408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4041888408
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3558397952
Short name T147
Test name
Test status
Simulation time 647296391 ps
CPU time 4.4 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 215992 kb
Host smart-478bb9b9-7837-45c3-80d7-9bbdc44839ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558397952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3558397952
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4089816000
Short name T174
Test name
Test status
Simulation time 33923521 ps
CPU time 2.1 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216340 kb
Host smart-14048b91-2a9a-4264-a7ff-f1083e248fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089816000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4089816000
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2953724213
Short name T1090
Test name
Test status
Simulation time 199172674 ps
CPU time 10.85 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:08 PM PDT 24
Peak memory 216096 kb
Host smart-b2b52a04-7acc-4b70-9f90-d6a5101b589e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953724213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2953724213
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1662998242
Short name T1083
Test name
Test status
Simulation time 228730984 ps
CPU time 3.61 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 218684 kb
Host smart-c6d06a77-8d8f-4f28-b3d7-0147d2c17f8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662998242 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1662998242
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1514822486
Short name T1093
Test name
Test status
Simulation time 139693606 ps
CPU time 1.36 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 207936 kb
Host smart-b7e58fa6-1a21-4cf9-9121-e27d8f3d7350
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514822486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1514822486
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2622550291
Short name T1039
Test name
Test status
Simulation time 182288488 ps
CPU time 0.8 seconds
Started Jul 22 06:36:59 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 204464 kb
Host smart-6b85fae9-d728-416e-946a-8e3e84970787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622550291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2622550291
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4023119414
Short name T1116
Test name
Test status
Simulation time 109036556 ps
CPU time 2.84 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 216224 kb
Host smart-5eab37c6-bd43-4881-b085-09764e0da47d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023119414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4023119414
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3066934150
Short name T1098
Test name
Test status
Simulation time 55736207 ps
CPU time 3.75 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 216180 kb
Host smart-bb689685-b465-4f26-999e-943941c58c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066934150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3066934150
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.899024
Short name T1131
Test name
Test status
Simulation time 112927859 ps
CPU time 7.13 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:37:05 PM PDT 24
Peak memory 216048 kb
Host smart-b9ee8ab7-eace-4a46-9e6e-30f3569f2449
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl
_intg_err.899024
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3309929688
Short name T112
Test name
Test status
Simulation time 595872072 ps
CPU time 3.68 seconds
Started Jul 22 06:36:59 PM PDT 24
Finished Jul 22 06:37:04 PM PDT 24
Peak memory 217916 kb
Host smart-7ed0483d-5c48-41d8-bce4-aa499730bf61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309929688 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3309929688
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2530508148
Short name T1148
Test name
Test status
Simulation time 93125125 ps
CPU time 2.72 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 216056 kb
Host smart-f08fcee9-0fcc-40a0-aa9b-ea533d972a69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530508148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2530508148
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.275045710
Short name T1109
Test name
Test status
Simulation time 11575203 ps
CPU time 0.75 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 204476 kb
Host smart-ddddecf1-2e56-4726-92bd-d60cc9df8d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275045710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.275045710
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1745219813
Short name T1079
Test name
Test status
Simulation time 45656309 ps
CPU time 1.69 seconds
Started Jul 22 06:37:04 PM PDT 24
Finished Jul 22 06:37:06 PM PDT 24
Peak memory 207700 kb
Host smart-26a600b0-3715-459f-a238-95cb2f1d831b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745219813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1745219813
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2716395618
Short name T106
Test name
Test status
Simulation time 53114684 ps
CPU time 3.55 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216256 kb
Host smart-9620d734-3f0b-4ad3-9c4c-223c119dea6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716395618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2716395618
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.434163742
Short name T143
Test name
Test status
Simulation time 859044167 ps
CPU time 15.17 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:37:10 PM PDT 24
Peak memory 216064 kb
Host smart-a8b72dfa-1a7b-4a48-964b-c1aca9db4072
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434163742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.434163742
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3959142323
Short name T1046
Test name
Test status
Simulation time 526406077 ps
CPU time 1.59 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 216068 kb
Host smart-787b7d28-7869-4df2-8ea6-d2b11a45de2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959142323 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3959142323
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.145133673
Short name T1088
Test name
Test status
Simulation time 32717582 ps
CPU time 2.02 seconds
Started Jul 22 06:37:53 PM PDT 24
Finished Jul 22 06:37:56 PM PDT 24
Peak memory 216048 kb
Host smart-694638a6-0b2e-4cad-9e3c-e147d03ecaf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145133673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.145133673
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2210749890
Short name T1033
Test name
Test status
Simulation time 27446027 ps
CPU time 0.73 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 204472 kb
Host smart-42e1003e-77ad-4ffb-870b-9ebaef761bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210749890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2210749890
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1493247887
Short name T1045
Test name
Test status
Simulation time 156254638 ps
CPU time 2.77 seconds
Started Jul 22 06:37:02 PM PDT 24
Finished Jul 22 06:37:06 PM PDT 24
Peak memory 216036 kb
Host smart-45395831-1e1e-432d-9d00-af58a6deaa3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493247887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1493247887
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2221757934
Short name T98
Test name
Test status
Simulation time 421956972 ps
CPU time 2.82 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 216416 kb
Host smart-beae4f03-a165-45e2-b8c9-e855444f452f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221757934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2221757934
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2306758813
Short name T1048
Test name
Test status
Simulation time 288948145 ps
CPU time 7.44 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 216312 kb
Host smart-0733afa5-de34-44c2-b91a-afabc30749a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306758813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2306758813
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1387078872
Short name T1057
Test name
Test status
Simulation time 224228672 ps
CPU time 15.21 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 207808 kb
Host smart-8ce0626c-229e-4d2a-8d8b-8943563c8784
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387078872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1387078872
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.927552566
Short name T116
Test name
Test status
Simulation time 536662648 ps
CPU time 33.56 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:37:25 PM PDT 24
Peak memory 215992 kb
Host smart-0ab43b36-c243-4ab2-bcbb-943c47fb8e52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927552566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.927552566
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.839480371
Short name T1141
Test name
Test status
Simulation time 48134790 ps
CPU time 0.99 seconds
Started Jul 22 06:38:51 PM PDT 24
Finished Jul 22 06:38:52 PM PDT 24
Peak memory 207640 kb
Host smart-dd5990d1-64a2-4bb1-bf08-86c6acdc48ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839480371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.839480371
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.61053903
Short name T1050
Test name
Test status
Simulation time 24167192 ps
CPU time 1.73 seconds
Started Jul 22 06:36:44 PM PDT 24
Finished Jul 22 06:36:47 PM PDT 24
Peak memory 216056 kb
Host smart-0d1cdab6-0d15-40b0-93cc-dc704129b754
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61053903 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.61053903
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1985804952
Short name T126
Test name
Test status
Simulation time 118149413 ps
CPU time 2.32 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:54 PM PDT 24
Peak memory 216052 kb
Host smart-0770e013-c274-4e21-a4b1-e4a4e4470d62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985804952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
985804952
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2544924931
Short name T1054
Test name
Test status
Simulation time 19608173 ps
CPU time 0.79 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 204852 kb
Host smart-a367b884-784f-4b34-9e58-066a166b459e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544924931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
544924931
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.822103934
Short name T1107
Test name
Test status
Simulation time 18032385 ps
CPU time 1.2 seconds
Started Jul 22 06:36:40 PM PDT 24
Finished Jul 22 06:36:41 PM PDT 24
Peak memory 215980 kb
Host smart-85c1437f-9331-4d24-bc80-36941829dabe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822103934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.822103934
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3588553915
Short name T1030
Test name
Test status
Simulation time 11204863 ps
CPU time 0.67 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:52 PM PDT 24
Peak memory 204724 kb
Host smart-b2d18a12-ae03-47bc-b918-ac81b47d32df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588553915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3588553915
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1771721986
Short name T1121
Test name
Test status
Simulation time 113405605 ps
CPU time 1.75 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:45 PM PDT 24
Peak memory 216092 kb
Host smart-12558523-898e-46a8-87b9-68b33f143a1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771721986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1771721986
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4199884691
Short name T1118
Test name
Test status
Simulation time 102786561 ps
CPU time 3.08 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:36:51 PM PDT 24
Peak memory 216300 kb
Host smart-2eea9e3f-c975-4adb-8597-d78617fb34ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199884691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
199884691
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2549847446
Short name T146
Test name
Test status
Simulation time 2592992703 ps
CPU time 14.76 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216640 kb
Host smart-de681a84-45f3-493b-b196-2515c7292e64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549847446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2549847446
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.111265766
Short name T1070
Test name
Test status
Simulation time 27012228 ps
CPU time 0.83 seconds
Started Jul 22 06:37:08 PM PDT 24
Finished Jul 22 06:37:10 PM PDT 24
Peak memory 204480 kb
Host smart-62ad66b3-ea60-4e6c-8138-73105b7214e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111265766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.111265766
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4223430093
Short name T1031
Test name
Test status
Simulation time 12811264 ps
CPU time 0.74 seconds
Started Jul 22 06:37:53 PM PDT 24
Finished Jul 22 06:37:54 PM PDT 24
Peak memory 204484 kb
Host smart-116c789b-1eae-4be1-961a-6dab422eb068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223430093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4223430093
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3149254890
Short name T1055
Test name
Test status
Simulation time 19452312 ps
CPU time 0.74 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 204484 kb
Host smart-27a8ebc8-da6b-47f3-8b26-eff6a2e7be05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149254890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3149254890
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1742851885
Short name T1062
Test name
Test status
Simulation time 22478621 ps
CPU time 0.72 seconds
Started Jul 22 06:37:05 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 204436 kb
Host smart-3a0318ff-a2fe-4333-9e95-2f86409b0a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742851885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1742851885
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1835860022
Short name T1040
Test name
Test status
Simulation time 14028134 ps
CPU time 0.71 seconds
Started Jul 22 06:36:59 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 204504 kb
Host smart-dc9d050f-58cf-4378-bdf7-9befc678d615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835860022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1835860022
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1220897608
Short name T1117
Test name
Test status
Simulation time 13440220 ps
CPU time 0.75 seconds
Started Jul 22 06:36:57 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 204512 kb
Host smart-3f287697-93ad-4063-a308-4d95d44fd177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220897608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1220897608
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1014049359
Short name T1082
Test name
Test status
Simulation time 24047175 ps
CPU time 0.78 seconds
Started Jul 22 06:37:04 PM PDT 24
Finished Jul 22 06:37:05 PM PDT 24
Peak memory 204460 kb
Host smart-64bf804a-4db8-4cd7-8edb-d9a76c202357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014049359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1014049359
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2559877450
Short name T1032
Test name
Test status
Simulation time 43410136 ps
CPU time 0.78 seconds
Started Jul 22 06:37:02 PM PDT 24
Finished Jul 22 06:37:04 PM PDT 24
Peak memory 204520 kb
Host smart-c46bcad4-98cb-4408-9127-8daac3cabba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559877450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2559877450
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3743284220
Short name T1058
Test name
Test status
Simulation time 13913896 ps
CPU time 0.77 seconds
Started Jul 22 06:37:01 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 204480 kb
Host smart-cc6969de-2d08-4973-a6a9-ba735c4d580c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743284220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3743284220
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2972874612
Short name T1052
Test name
Test status
Simulation time 17126922 ps
CPU time 0.78 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 204856 kb
Host smart-cf09a64c-8c6c-4744-8d01-d187a2f6c35b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972874612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2972874612
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.930599204
Short name T1044
Test name
Test status
Simulation time 324383048 ps
CPU time 22.29 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:37:11 PM PDT 24
Peak memory 216076 kb
Host smart-6a61e3c1-df01-455e-b7b6-706b8e0b421c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930599204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.930599204
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3340271427
Short name T1100
Test name
Test status
Simulation time 3203545552 ps
CPU time 23.29 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:37:11 PM PDT 24
Peak memory 216128 kb
Host smart-5a887439-72ef-497e-813d-10af71cb0117
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340271427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3340271427
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.844448070
Short name T79
Test name
Test status
Simulation time 21422179 ps
CPU time 1.03 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 207648 kb
Host smart-98b017f0-c8d2-4cdb-9b80-d8bd4de15087
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844448070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.844448070
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.907426752
Short name T114
Test name
Test status
Simulation time 136752036 ps
CPU time 2.8 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 218636 kb
Host smart-b34afe7b-d080-4937-a69e-5b7b63c0468c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907426752 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.907426752
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1910619669
Short name T122
Test name
Test status
Simulation time 98339758 ps
CPU time 1.89 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:51 PM PDT 24
Peak memory 207912 kb
Host smart-9e8e159b-e9bf-4390-a8b3-cbd4425c15c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910619669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
910619669
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3968027703
Short name T1147
Test name
Test status
Simulation time 14653327 ps
CPU time 0.73 seconds
Started Jul 22 06:38:51 PM PDT 24
Finished Jul 22 06:38:52 PM PDT 24
Peak memory 204292 kb
Host smart-0223dab4-d0ab-4ef0-957d-a6fdb96efec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968027703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
968027703
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2440621442
Short name T1124
Test name
Test status
Simulation time 189093238 ps
CPU time 1.21 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216068 kb
Host smart-e5871c4e-1cf2-4db8-bc89-a2a6d672b1cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440621442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2440621442
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2591318889
Short name T1102
Test name
Test status
Simulation time 13260207 ps
CPU time 0.72 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:36:49 PM PDT 24
Peak memory 204364 kb
Host smart-1219c208-768d-4a41-a15a-77fec645556e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591318889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2591318889
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1660704348
Short name T1134
Test name
Test status
Simulation time 589087879 ps
CPU time 1.87 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:36:49 PM PDT 24
Peak memory 216092 kb
Host smart-70a77979-10b1-4674-a9cc-33dd109146d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660704348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1660704348
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.756858875
Short name T107
Test name
Test status
Simulation time 1069707374 ps
CPU time 3.37 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:52 PM PDT 24
Peak memory 216316 kb
Host smart-3acbe838-8bb1-4020-865e-2ba8b65ddf57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756858875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.756858875
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2660007339
Short name T99
Test name
Test status
Simulation time 357962125 ps
CPU time 18.03 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:37:08 PM PDT 24
Peak memory 216028 kb
Host smart-1894cefa-932d-4776-9288-90669a0bde5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660007339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2660007339
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4244379830
Short name T1085
Test name
Test status
Simulation time 23665834 ps
CPU time 0.73 seconds
Started Jul 22 06:37:01 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 204492 kb
Host smart-7e1d982f-c8a8-497e-8e1a-f07c91bc8010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244379830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4244379830
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1459618145
Short name T1111
Test name
Test status
Simulation time 122029553 ps
CPU time 0.82 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 204464 kb
Host smart-64c85065-9890-4a17-9f9a-9a6f08400113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459618145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1459618145
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2688653348
Short name T1064
Test name
Test status
Simulation time 14453582 ps
CPU time 0.69 seconds
Started Jul 22 06:37:05 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 204464 kb
Host smart-11889bb4-033e-4bd7-a017-e78ab2785504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688653348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2688653348
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3798342843
Short name T1074
Test name
Test status
Simulation time 23778669 ps
CPU time 0.71 seconds
Started Jul 22 06:37:02 PM PDT 24
Finished Jul 22 06:37:04 PM PDT 24
Peak memory 204828 kb
Host smart-f8c959c1-7c60-49bf-98cf-6656d6bdd054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798342843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3798342843
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1578607942
Short name T1049
Test name
Test status
Simulation time 12458840 ps
CPU time 0.82 seconds
Started Jul 22 06:36:56 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 204492 kb
Host smart-044bb5a1-c112-4014-a02a-3af80428a5e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578607942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1578607942
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1565902984
Short name T1119
Test name
Test status
Simulation time 46749339 ps
CPU time 0.77 seconds
Started Jul 22 06:37:03 PM PDT 24
Finished Jul 22 06:37:04 PM PDT 24
Peak memory 204788 kb
Host smart-82889c5b-8029-438c-9dee-cefb8231382d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565902984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1565902984
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.259756819
Short name T1041
Test name
Test status
Simulation time 11528065 ps
CPU time 0.75 seconds
Started Jul 22 06:36:59 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 204800 kb
Host smart-edaeeb84-25bf-4161-81a2-b265e70bf297
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259756819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.259756819
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2474946165
Short name T1103
Test name
Test status
Simulation time 18349062 ps
CPU time 0.78 seconds
Started Jul 22 06:37:06 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 204672 kb
Host smart-67823a85-a902-40e8-9432-4ebe31c2fe84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474946165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2474946165
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.669709635
Short name T1135
Test name
Test status
Simulation time 55252045 ps
CPU time 0.77 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 204484 kb
Host smart-92e43f02-5f30-45db-abed-bceccea0ae59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669709635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.669709635
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2534836047
Short name T1105
Test name
Test status
Simulation time 23185294 ps
CPU time 0.78 seconds
Started Jul 22 06:37:06 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 204120 kb
Host smart-64822832-e303-4149-889e-e76a2ee63d10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534836047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2534836047
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1383965526
Short name T1038
Test name
Test status
Simulation time 3537836118 ps
CPU time 15.89 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:37:13 PM PDT 24
Peak memory 208000 kb
Host smart-f4a09503-9c3e-45a5-86cb-e7828efaf36f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383965526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1383965526
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.374369203
Short name T1120
Test name
Test status
Simulation time 750344619 ps
CPU time 23.1 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:37:11 PM PDT 24
Peak memory 207736 kb
Host smart-0acedad8-81e8-4e9c-9592-c55c216c335d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374369203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.374369203
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2315605766
Short name T76
Test name
Test status
Simulation time 185677229 ps
CPU time 1.46 seconds
Started Jul 22 06:36:44 PM PDT 24
Finished Jul 22 06:36:47 PM PDT 24
Peak memory 216936 kb
Host smart-fb2ed4cd-140a-4630-86cb-96220960130b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315605766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2315605766
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3254363651
Short name T1133
Test name
Test status
Simulation time 627934638 ps
CPU time 2.68 seconds
Started Jul 22 06:38:08 PM PDT 24
Finished Jul 22 06:38:11 PM PDT 24
Peak memory 218512 kb
Host smart-e7779338-c256-4ba4-ba22-5654765eb261
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254363651 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3254363651
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2363912174
Short name T1146
Test name
Test status
Simulation time 628571256 ps
CPU time 2.28 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216048 kb
Host smart-83802f19-e260-4935-8073-931bf4b8317c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363912174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
363912174
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4230558901
Short name T1065
Test name
Test status
Simulation time 43946763 ps
CPU time 0.77 seconds
Started Jul 22 06:38:51 PM PDT 24
Finished Jul 22 06:38:52 PM PDT 24
Peak memory 204804 kb
Host smart-1f60eb82-932f-4671-b90a-31e5d465dbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230558901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
230558901
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3831287597
Short name T121
Test name
Test status
Simulation time 40713609 ps
CPU time 1.37 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 216072 kb
Host smart-880eb0cd-8787-42b2-9356-6834c30e33af
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831287597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3831287597
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.242778910
Short name T1145
Test name
Test status
Simulation time 27314117 ps
CPU time 0.69 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:57 PM PDT 24
Peak memory 204376 kb
Host smart-fd88ee29-298d-432f-beb6-70528948e617
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242778910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.242778910
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.221893347
Short name T1081
Test name
Test status
Simulation time 277860952 ps
CPU time 1.78 seconds
Started Jul 22 06:36:45 PM PDT 24
Finished Jul 22 06:36:49 PM PDT 24
Peak memory 216008 kb
Host smart-aee5bdc8-b4a8-4f57-99f7-1fed2a57d869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221893347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.221893347
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2263619334
Short name T111
Test name
Test status
Simulation time 78355206 ps
CPU time 4.83 seconds
Started Jul 22 06:37:54 PM PDT 24
Finished Jul 22 06:38:00 PM PDT 24
Peak memory 216296 kb
Host smart-8dd66255-4d58-4e93-97f1-e39b8e28ea5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263619334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
263619334
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3518701171
Short name T180
Test name
Test status
Simulation time 447478440 ps
CPU time 8.58 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216332 kb
Host smart-cace8738-598e-4bf7-a72e-973c893768f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518701171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3518701171
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1645888769
Short name T1125
Test name
Test status
Simulation time 26781617 ps
CPU time 0.72 seconds
Started Jul 22 06:36:58 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 204984 kb
Host smart-b73acd95-44a8-4b34-b6a4-aa7bc1ba9390
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645888769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1645888769
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3979536154
Short name T1063
Test name
Test status
Simulation time 46415812 ps
CPU time 0.71 seconds
Started Jul 22 06:37:05 PM PDT 24
Finished Jul 22 06:37:07 PM PDT 24
Peak memory 204336 kb
Host smart-48aa1ecd-a849-4ccd-9ca5-4a3a5f711dd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979536154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3979536154
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1191061529
Short name T1099
Test name
Test status
Simulation time 25627008 ps
CPU time 0.79 seconds
Started Jul 22 06:36:55 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 204520 kb
Host smart-8bf087ce-3e28-4f5a-8a87-c3e0050179b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191061529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1191061529
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2258475916
Short name T1089
Test name
Test status
Simulation time 13079206 ps
CPU time 0.72 seconds
Started Jul 22 06:37:01 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 204504 kb
Host smart-d174cfee-e95e-4e5a-be2a-433091565d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258475916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2258475916
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2888060551
Short name T1060
Test name
Test status
Simulation time 51483360 ps
CPU time 0.76 seconds
Started Jul 22 06:37:08 PM PDT 24
Finished Jul 22 06:37:10 PM PDT 24
Peak memory 204484 kb
Host smart-b087f1c0-b30a-4274-bdfa-4f840d5417cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888060551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2888060551
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1654670909
Short name T1143
Test name
Test status
Simulation time 63625797 ps
CPU time 0.7 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 204420 kb
Host smart-0e40a004-f8b4-4e87-aab6-e56c968fe174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654670909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1654670909
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2370371971
Short name T1056
Test name
Test status
Simulation time 14920608 ps
CPU time 0.71 seconds
Started Jul 22 06:37:01 PM PDT 24
Finished Jul 22 06:37:03 PM PDT 24
Peak memory 204788 kb
Host smart-d1348a32-103d-44b9-bdcc-c4c58267050f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370371971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2370371971
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.109464293
Short name T1047
Test name
Test status
Simulation time 31824721 ps
CPU time 0.76 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:01 PM PDT 24
Peak memory 204448 kb
Host smart-0284460d-97c0-4788-8b96-0619e505fbc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109464293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.109464293
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3862491567
Short name T1036
Test name
Test status
Simulation time 19865601 ps
CPU time 0.72 seconds
Started Jul 22 06:37:00 PM PDT 24
Finished Jul 22 06:37:02 PM PDT 24
Peak memory 204496 kb
Host smart-704bbca4-e59a-4256-9f22-2e5aba526676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862491567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3862491567
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1282880435
Short name T1035
Test name
Test status
Simulation time 20620224 ps
CPU time 0.82 seconds
Started Jul 22 06:36:57 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 204524 kb
Host smart-a6e09d2f-29fa-47c3-9fc5-9ea91b8f2f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282880435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1282880435
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1987633848
Short name T1092
Test name
Test status
Simulation time 326591976 ps
CPU time 1.8 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:51 PM PDT 24
Peak memory 217128 kb
Host smart-513a980d-457e-49c5-830a-09b6daf18104
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987633848 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1987633848
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1303772300
Short name T115
Test name
Test status
Simulation time 112982486 ps
CPU time 2.57 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 215984 kb
Host smart-593b11e4-782a-40e3-906c-a19ad464992a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303772300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
303772300
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1922727150
Short name T1108
Test name
Test status
Simulation time 18127399 ps
CPU time 0.73 seconds
Started Jul 22 06:37:12 PM PDT 24
Finished Jul 22 06:37:14 PM PDT 24
Peak memory 204656 kb
Host smart-6109ffb9-40ec-444c-b241-a0dbf687de9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922727150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
922727150
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.607994313
Short name T1073
Test name
Test status
Simulation time 101501625 ps
CPU time 1.94 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:51 PM PDT 24
Peak memory 216076 kb
Host smart-35bc38aa-c606-42f5-aca2-10f77445e03b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607994313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.607994313
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1271662951
Short name T109
Test name
Test status
Simulation time 46137001 ps
CPU time 2.71 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216300 kb
Host smart-16edf3ac-cb2e-4bde-a7b1-be4ea8d0261f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271662951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
271662951
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3572021851
Short name T1053
Test name
Test status
Simulation time 961923685 ps
CPU time 14.7 seconds
Started Jul 22 06:36:42 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 216584 kb
Host smart-2fbf0b2c-32ed-4dae-ab87-83b344488070
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572021851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3572021851
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2588534433
Short name T1138
Test name
Test status
Simulation time 147186865 ps
CPU time 3.74 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 217720 kb
Host smart-a1a67da6-bfe2-47a2-889e-0bff954a4deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588534433 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2588534433
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2873486451
Short name T1101
Test name
Test status
Simulation time 436817614 ps
CPU time 1.45 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 216060 kb
Host smart-3a08c245-bef0-461b-a4d3-d06b9ca62920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873486451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
873486451
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4079114229
Short name T1061
Test name
Test status
Simulation time 46262170 ps
CPU time 0.7 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 204508 kb
Host smart-0cd78d1f-f234-4da0-b921-398a386cdef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079114229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
079114229
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3784105539
Short name T1104
Test name
Test status
Simulation time 247781185 ps
CPU time 3.06 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 216084 kb
Host smart-827ccefc-ffd9-4241-8b92-c5456da1edbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784105539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3784105539
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2600057098
Short name T1137
Test name
Test status
Simulation time 186240023 ps
CPU time 6.2 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:59 PM PDT 24
Peak memory 216264 kb
Host smart-70afae33-30ef-45d8-bfce-292838c92629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600057098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
600057098
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2466626077
Short name T1084
Test name
Test status
Simulation time 2276779313 ps
CPU time 20.74 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:37:15 PM PDT 24
Peak memory 216248 kb
Host smart-4e0f98b8-2b64-4e87-98b1-5acb3690a881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466626077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2466626077
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3844189283
Short name T1091
Test name
Test status
Simulation time 665326613 ps
CPU time 3.94 seconds
Started Jul 22 06:36:46 PM PDT 24
Finished Jul 22 06:36:54 PM PDT 24
Peak memory 218400 kb
Host smart-821555c5-e1f4-40a0-8d2f-601bf86c8a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844189283 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3844189283
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2940166204
Short name T125
Test name
Test status
Simulation time 141883549 ps
CPU time 2.55 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 215988 kb
Host smart-6d95af16-4831-4031-b312-75088b019ca1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940166204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
940166204
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3890828723
Short name T1034
Test name
Test status
Simulation time 30939629 ps
CPU time 0.82 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 205048 kb
Host smart-408f2029-d8d1-4b12-89c9-8b434c87faab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890828723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
890828723
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4143483007
Short name T1051
Test name
Test status
Simulation time 197383507 ps
CPU time 1.67 seconds
Started Jul 22 06:36:51 PM PDT 24
Finished Jul 22 06:36:57 PM PDT 24
Peak memory 216060 kb
Host smart-39d7ba45-4525-42f1-b8b0-f6d6d2042e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143483007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4143483007
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2288119481
Short name T105
Test name
Test status
Simulation time 349974689 ps
CPU time 2.46 seconds
Started Jul 22 06:36:44 PM PDT 24
Finished Jul 22 06:36:47 PM PDT 24
Peak memory 217304 kb
Host smart-304ecf2c-79b2-41a9-bbcd-7341b0959912
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288119481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
288119481
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3789761274
Short name T1144
Test name
Test status
Simulation time 1136597274 ps
CPU time 15.03 seconds
Started Jul 22 06:36:44 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 216784 kb
Host smart-ddfb4680-7572-4d1c-bf07-8cb226934bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789761274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3789761274
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2432831717
Short name T94
Test name
Test status
Simulation time 156727086 ps
CPU time 2.85 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 217208 kb
Host smart-4d07f3e8-104d-44b1-9d2b-ddd40be564b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432831717 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2432831717
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.874193177
Short name T1086
Test name
Test status
Simulation time 94140431 ps
CPU time 2.03 seconds
Started Jul 22 06:36:48 PM PDT 24
Finished Jul 22 06:36:53 PM PDT 24
Peak memory 215976 kb
Host smart-f8e00516-8160-4cd7-a7e8-995bfa7ae1a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874193177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.874193177
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1235426356
Short name T1129
Test name
Test status
Simulation time 44760021 ps
CPU time 0.71 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:45 PM PDT 24
Peak memory 204488 kb
Host smart-0558fe8a-12e8-49ee-b035-dd363ab0e94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235426356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
235426356
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2352364432
Short name T1087
Test name
Test status
Simulation time 515116657 ps
CPU time 3.11 seconds
Started Jul 22 06:36:43 PM PDT 24
Finished Jul 22 06:36:47 PM PDT 24
Peak memory 216080 kb
Host smart-860cd349-edbe-46c8-84cb-582a1d17263c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352364432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2352364432
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2548574573
Short name T1132
Test name
Test status
Simulation time 458675721 ps
CPU time 2.8 seconds
Started Jul 22 06:36:52 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 217292 kb
Host smart-7d182fbf-58ab-450e-b295-678de10b1568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548574573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
548574573
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4223085821
Short name T1114
Test name
Test status
Simulation time 273136276 ps
CPU time 7.49 seconds
Started Jul 22 06:36:47 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 216056 kb
Host smart-f04238ed-018f-40bc-9ece-28a1869016c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223085821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4223085821
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2542786379
Short name T1077
Test name
Test status
Simulation time 85148818 ps
CPU time 1.5 seconds
Started Jul 22 06:36:50 PM PDT 24
Finished Jul 22 06:36:56 PM PDT 24
Peak memory 216056 kb
Host smart-88724014-0203-417c-a2c3-67eb0b9e0979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542786379 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2542786379
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1543623951
Short name T1136
Test name
Test status
Simulation time 62442841 ps
CPU time 1.77 seconds
Started Jul 22 06:36:49 PM PDT 24
Finished Jul 22 06:36:55 PM PDT 24
Peak memory 216124 kb
Host smart-9e8f288f-49c0-49f9-ae23-f0062f59cd28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543623951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
543623951
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2786689006
Short name T1075
Test name
Test status
Simulation time 19460556 ps
CPU time 0.82 seconds
Started Jul 22 06:36:53 PM PDT 24
Finished Jul 22 06:36:58 PM PDT 24
Peak memory 204844 kb
Host smart-a5c96216-db82-4ef4-9027-960766d03018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786689006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
786689006
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4290809326
Short name T1128
Test name
Test status
Simulation time 44661598 ps
CPU time 3.06 seconds
Started Jul 22 06:36:54 PM PDT 24
Finished Jul 22 06:37:00 PM PDT 24
Peak memory 215992 kb
Host smart-a778aaf8-e600-4581-95be-63b52248125f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290809326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4290809326
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1347227625
Short name T1149
Test name
Test status
Simulation time 334926769 ps
CPU time 1.95 seconds
Started Jul 22 06:37:01 PM PDT 24
Finished Jul 22 06:37:04 PM PDT 24
Peak memory 216180 kb
Host smart-705b2e79-994a-44ea-8980-2fd0eaefdf86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347227625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
347227625
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3318667779
Short name T1110
Test name
Test status
Simulation time 1168230422 ps
CPU time 19.27 seconds
Started Jul 22 06:36:56 PM PDT 24
Finished Jul 22 06:37:18 PM PDT 24
Peak memory 216448 kb
Host smart-50b999b9-ef0d-4d31-be46-070cdf54fe81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318667779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3318667779
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.313426266
Short name T724
Test name
Test status
Simulation time 19099372 ps
CPU time 0.78 seconds
Started Jul 22 04:57:08 PM PDT 24
Finished Jul 22 04:57:09 PM PDT 24
Peak memory 205940 kb
Host smart-14a5bf03-3980-4a92-9819-8869f4c233b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313426266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.313426266
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3066294462
Short name T446
Test name
Test status
Simulation time 359468048 ps
CPU time 2.35 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 225360 kb
Host smart-fc8d3c4d-9bb7-496f-baae-7c5190ff73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066294462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3066294462
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.656977585
Short name T606
Test name
Test status
Simulation time 72070697 ps
CPU time 0.78 seconds
Started Jul 22 04:57:07 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 207248 kb
Host smart-2a03c9dc-eebd-48cd-ae04-38acb0097e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656977585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.656977585
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3335886510
Short name T733
Test name
Test status
Simulation time 7323452743 ps
CPU time 71.58 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:58:22 PM PDT 24
Peak memory 253616 kb
Host smart-df6c05c2-9264-45f4-9a4f-593275354a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335886510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3335886510
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3749137544
Short name T857
Test name
Test status
Simulation time 10375876416 ps
CPU time 140.5 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:59:27 PM PDT 24
Peak memory 272104 kb
Host smart-36cb7aea-7f9b-47d2-b93b-05825261aa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749137544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3749137544
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1696617670
Short name T648
Test name
Test status
Simulation time 29421073496 ps
CPU time 175.62 seconds
Started Jul 22 04:57:03 PM PDT 24
Finished Jul 22 04:59:59 PM PDT 24
Peak memory 254292 kb
Host smart-7d9eeb8a-3433-4a33-b1d7-ca9d0a0464b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696617670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1696617670
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2863070225
Short name T902
Test name
Test status
Simulation time 29226689431 ps
CPU time 89.9 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:58:41 PM PDT 24
Peak memory 250072 kb
Host smart-08c5bbaf-974b-4ae1-a4c2-6bfa187a8673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863070225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2863070225
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3275418435
Short name T391
Test name
Test status
Simulation time 3748394814 ps
CPU time 10.33 seconds
Started Jul 22 04:57:01 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 225468 kb
Host smart-0e6a8b64-7ce3-44fa-9d60-318982013717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275418435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3275418435
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3811697288
Short name T684
Test name
Test status
Simulation time 5417923285 ps
CPU time 45.84 seconds
Started Jul 22 04:57:04 PM PDT 24
Finished Jul 22 04:57:50 PM PDT 24
Peak memory 240456 kb
Host smart-f5875cec-6140-41d2-9412-5a2879c0f39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811697288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3811697288
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1310814974
Short name T858
Test name
Test status
Simulation time 113952719 ps
CPU time 1.02 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 217236 kb
Host smart-9f68879f-261b-4e11-a76a-a15dddff7505
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310814974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1310814974
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.631731733
Short name T808
Test name
Test status
Simulation time 13258740752 ps
CPU time 25.08 seconds
Started Jul 22 04:57:03 PM PDT 24
Finished Jul 22 04:57:29 PM PDT 24
Peak memory 241832 kb
Host smart-ae739e9e-28c0-436f-bb3c-5fea09064cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631731733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
631731733
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.635417588
Short name T470
Test name
Test status
Simulation time 201691234 ps
CPU time 2.99 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 225392 kb
Host smart-ab2921c3-d976-4577-a277-4a7dbfcf9e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635417588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.635417588
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2122245485
Short name T597
Test name
Test status
Simulation time 264114250 ps
CPU time 4.67 seconds
Started Jul 22 04:57:01 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 223948 kb
Host smart-17fb998f-8fb7-4a00-8308-dbce3d4c8dd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2122245485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2122245485
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2565733652
Short name T421
Test name
Test status
Simulation time 45153549 ps
CPU time 0.72 seconds
Started Jul 22 04:57:07 PM PDT 24
Finished Jul 22 04:57:08 PM PDT 24
Peak memory 206356 kb
Host smart-b1bf4d34-1c05-4d6a-ab05-336da767cc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565733652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2565733652
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2972610568
Short name T938
Test name
Test status
Simulation time 1731380691 ps
CPU time 5.6 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:18 PM PDT 24
Peak memory 216936 kb
Host smart-45d2fe63-81f5-4976-b109-ecec67980785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972610568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2972610568
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1524371881
Short name T589
Test name
Test status
Simulation time 51376410 ps
CPU time 1.58 seconds
Started Jul 22 04:57:02 PM PDT 24
Finished Jul 22 04:57:04 PM PDT 24
Peak memory 217188 kb
Host smart-a3f89856-4429-4e79-bb55-c9ccb29d9a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524371881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1524371881
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.871906441
Short name T69
Test name
Test status
Simulation time 342739206 ps
CPU time 1.02 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 206900 kb
Host smart-8a5980f2-4f4f-4711-82d0-a58c84c54c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871906441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.871906441
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.727314436
Short name T161
Test name
Test status
Simulation time 13711787766 ps
CPU time 11.27 seconds
Started Jul 22 04:57:08 PM PDT 24
Finished Jul 22 04:57:20 PM PDT 24
Peak memory 233560 kb
Host smart-4327bb04-926c-4dc1-a84e-c8602e236bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727314436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.727314436
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.656551539
Short name T466
Test name
Test status
Simulation time 38153006 ps
CPU time 0.73 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:14 PM PDT 24
Peak memory 206388 kb
Host smart-3bf3173b-4ef1-4de7-9fb2-e1283f1af33c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656551539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.656551539
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3856447893
Short name T1004
Test name
Test status
Simulation time 35254706803 ps
CPU time 18.21 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:31 PM PDT 24
Peak memory 225424 kb
Host smart-c5692dae-8ed9-4209-8811-5f8324667547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856447893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3856447893
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1732828330
Short name T734
Test name
Test status
Simulation time 13489657 ps
CPU time 0.77 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:57:06 PM PDT 24
Peak memory 207232 kb
Host smart-2b3a35c8-66cf-4f86-9972-fd68d436be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732828330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1732828330
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2800304474
Short name T568
Test name
Test status
Simulation time 2695037759 ps
CPU time 42.6 seconds
Started Jul 22 04:57:13 PM PDT 24
Finished Jul 22 04:57:56 PM PDT 24
Peak memory 250064 kb
Host smart-b8aa1d8c-8f34-44ce-8d39-06b896cb4704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800304474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2800304474
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2597646865
Short name T452
Test name
Test status
Simulation time 67474554267 ps
CPU time 165.71 seconds
Started Jul 22 04:57:14 PM PDT 24
Finished Jul 22 05:00:00 PM PDT 24
Peak memory 250172 kb
Host smart-dd18cbc2-d2c9-4e67-9bf3-2b518c34d03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597646865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2597646865
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1293436212
Short name T52
Test name
Test status
Simulation time 40158059353 ps
CPU time 352.53 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:06:55 PM PDT 24
Peak memory 253064 kb
Host smart-c6a22813-dd7b-4ca7-bd7f-0c137a668076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293436212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1293436212
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3667101966
Short name T639
Test name
Test status
Simulation time 427740172 ps
CPU time 4.22 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 225308 kb
Host smart-23532a39-c74f-43c0-9b23-c770f22d8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667101966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3667101966
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.277862878
Short name T759
Test name
Test status
Simulation time 44984632773 ps
CPU time 92.21 seconds
Started Jul 22 04:57:09 PM PDT 24
Finished Jul 22 04:58:42 PM PDT 24
Peak memory 254976 kb
Host smart-0e5dd783-8a4a-407d-9e64-273136547dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277862878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
277862878
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1968551562
Short name T626
Test name
Test status
Simulation time 12591682785 ps
CPU time 16.77 seconds
Started Jul 22 04:57:14 PM PDT 24
Finished Jul 22 04:57:31 PM PDT 24
Peak memory 225476 kb
Host smart-5a7242ab-7b82-4dc1-a25c-06c0ff598757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968551562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1968551562
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.667148275
Short name T829
Test name
Test status
Simulation time 38165563 ps
CPU time 2.1 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:01:05 PM PDT 24
Peak memory 224956 kb
Host smart-c73918f8-7847-4eb0-bed6-ab9c1aea54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667148275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.667148275
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.188626583
Short name T500
Test name
Test status
Simulation time 170549111 ps
CPU time 1.03 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 217248 kb
Host smart-22b816aa-205d-4b5d-8ffd-0f8dfe4f518d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188626583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.188626583
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.15516510
Short name T751
Test name
Test status
Simulation time 2204649154 ps
CPU time 9.38 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:21 PM PDT 24
Peak memory 241820 kb
Host smart-2f8ce090-e030-4cc1-b839-a7d42583fe9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15516510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.15516510
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3129175887
Short name T879
Test name
Test status
Simulation time 2192664993 ps
CPU time 7.29 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:19 PM PDT 24
Peak memory 233620 kb
Host smart-e1c709f6-06ae-4697-bd36-5d2b69b839b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129175887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3129175887
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4188115060
Short name T140
Test name
Test status
Simulation time 88349388 ps
CPU time 3.48 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 221204 kb
Host smart-5d25e140-b005-4955-b194-2287e11fb336
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4188115060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4188115060
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1902725633
Short name T63
Test name
Test status
Simulation time 123391619 ps
CPU time 0.98 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 235892 kb
Host smart-26beba2b-d9c6-453a-af67-e4da43aeecab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902725633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1902725633
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2645803275
Short name T21
Test name
Test status
Simulation time 33547037041 ps
CPU time 161.17 seconds
Started Jul 22 04:57:15 PM PDT 24
Finished Jul 22 04:59:56 PM PDT 24
Peak memory 250132 kb
Host smart-e68a0e42-9d7d-4318-a34d-7b8b9bab7ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645803275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2645803275
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1828982080
Short name T581
Test name
Test status
Simulation time 16015012878 ps
CPU time 17.83 seconds
Started Jul 22 04:57:05 PM PDT 24
Finished Jul 22 04:57:23 PM PDT 24
Peak memory 217160 kb
Host smart-ffa990b1-d90c-4232-8e72-687a2eb32b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828982080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1828982080
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3534405396
Short name T748
Test name
Test status
Simulation time 13550229697 ps
CPU time 9.63 seconds
Started Jul 22 05:01:00 PM PDT 24
Finished Jul 22 05:01:10 PM PDT 24
Peak memory 217196 kb
Host smart-f88a8b48-66ee-4acf-891a-0ea0486ff62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534405396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3534405396
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1956993812
Short name T46
Test name
Test status
Simulation time 39601484 ps
CPU time 0.78 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:13 PM PDT 24
Peak memory 206768 kb
Host smart-59cfc118-aba3-4eb5-bbb7-1a88d00c8c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956993812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1956993812
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2211577782
Short name T416
Test name
Test status
Simulation time 407061072 ps
CPU time 1.04 seconds
Started Jul 22 04:57:09 PM PDT 24
Finished Jul 22 04:57:11 PM PDT 24
Peak memory 207776 kb
Host smart-c7320a64-f5eb-4f36-a111-d944427a61cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211577782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2211577782
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3366442507
Short name T966
Test name
Test status
Simulation time 6337830001 ps
CPU time 6.37 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:18 PM PDT 24
Peak memory 225484 kb
Host smart-e726e43c-26a0-4f18-aeac-d6699be60526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366442507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3366442507
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2603878992
Short name T981
Test name
Test status
Simulation time 693699984 ps
CPU time 7.19 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:17 PM PDT 24
Peak memory 233580 kb
Host smart-0aa3dfe6-3f2a-4e2f-830b-da067054d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603878992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2603878992
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3857794970
Short name T693
Test name
Test status
Simulation time 147364567 ps
CPU time 0.71 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:10 PM PDT 24
Peak memory 206220 kb
Host smart-999d1b1a-66ec-4ae9-aaed-9b0d9bc3836c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857794970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3857794970
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3528262066
Short name T272
Test name
Test status
Simulation time 4174741706 ps
CPU time 85.23 seconds
Started Jul 22 04:58:06 PM PDT 24
Finished Jul 22 04:59:32 PM PDT 24
Peak memory 266160 kb
Host smart-819c4b99-b5cb-435e-be91-2a4c020a51d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528262066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3528262066
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.347660013
Short name T677
Test name
Test status
Simulation time 3104799494 ps
CPU time 26.87 seconds
Started Jul 22 04:58:04 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 225556 kb
Host smart-1088c988-6cdb-49e1-b80e-74e1eb38a532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347660013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.347660013
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3541333691
Short name T907
Test name
Test status
Simulation time 218359774 ps
CPU time 3.97 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:13 PM PDT 24
Peak memory 233600 kb
Host smart-dbe6e6aa-f818-487b-93a9-58b91ba70d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541333691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3541333691
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2533663358
Short name T71
Test name
Test status
Simulation time 22815027745 ps
CPU time 161.95 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 05:00:51 PM PDT 24
Peak memory 241884 kb
Host smart-efba80d6-f808-4476-8fc0-eca566b0638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533663358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2533663358
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4145924815
Short name T861
Test name
Test status
Simulation time 7578420932 ps
CPU time 20.38 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 233700 kb
Host smart-27f614f3-919e-4802-a61a-402f092abadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145924815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4145924815
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2727746056
Short name T867
Test name
Test status
Simulation time 3750852148 ps
CPU time 24.3 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 233612 kb
Host smart-8bb4567e-43d2-47f9-a52d-2982a7d55b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727746056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2727746056
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1553462975
Short name T703
Test name
Test status
Simulation time 7312622863 ps
CPU time 16.62 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:26 PM PDT 24
Peak memory 225444 kb
Host smart-4fdfe659-90f6-47d5-9b51-e1e31e9eb803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553462975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1553462975
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.352421696
Short name T762
Test name
Test status
Simulation time 323243142 ps
CPU time 2.65 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:11 PM PDT 24
Peak memory 233644 kb
Host smart-1115ac43-2f70-499e-8eb1-7eb9e01561ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352421696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.352421696
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2253744320
Short name T958
Test name
Test status
Simulation time 7129349771 ps
CPU time 15.45 seconds
Started Jul 22 04:58:12 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 220352 kb
Host smart-8e0259d5-aa48-482f-b19a-a80794481c04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2253744320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2253744320
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1788222118
Short name T47
Test name
Test status
Simulation time 46184038172 ps
CPU time 39.05 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:47 PM PDT 24
Peak memory 217248 kb
Host smart-a3d52bdb-5d4e-45b8-b3f3-9747e3b31f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788222118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1788222118
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1043800160
Short name T783
Test name
Test status
Simulation time 823301042 ps
CPU time 2.58 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:35 PM PDT 24
Peak memory 208752 kb
Host smart-849b9f0d-03b7-4035-b761-464666dae49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043800160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1043800160
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2037314822
Short name T332
Test name
Test status
Simulation time 58782734 ps
CPU time 1.46 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:10 PM PDT 24
Peak memory 208932 kb
Host smart-d0f7f919-a58e-4bf1-9b3a-e5529d4839b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037314822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2037314822
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3620215179
Short name T1019
Test name
Test status
Simulation time 53779158 ps
CPU time 0.71 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 206760 kb
Host smart-5590e07a-0e58-429a-825d-1560c320ffaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620215179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3620215179
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1535089739
Short name T771
Test name
Test status
Simulation time 196175016 ps
CPU time 3.25 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:12 PM PDT 24
Peak memory 225420 kb
Host smart-001c8ee8-061a-40c0-b2f9-1b09a2541212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535089739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1535089739
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2976430037
Short name T335
Test name
Test status
Simulation time 49675390 ps
CPU time 0.71 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:18 PM PDT 24
Peak memory 205472 kb
Host smart-b26710a8-e845-4b80-b935-fe431af86793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976430037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2976430037
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1431259328
Short name T622
Test name
Test status
Simulation time 5196078799 ps
CPU time 10.38 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 225480 kb
Host smart-d5926972-b328-431d-8a9c-81c925e84c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431259328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1431259328
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1772638836
Short name T715
Test name
Test status
Simulation time 14615017 ps
CPU time 0.8 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 04:58:04 PM PDT 24
Peak memory 207248 kb
Host smart-253d445b-1640-4732-b970-27e89013fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772638836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1772638836
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2031445606
Short name T480
Test name
Test status
Simulation time 7220641519 ps
CPU time 70.57 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:59:26 PM PDT 24
Peak memory 233656 kb
Host smart-6f58f206-4df2-4b1b-be34-d8a00968f5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031445606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2031445606
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1309247942
Short name T775
Test name
Test status
Simulation time 104481658020 ps
CPU time 278.59 seconds
Started Jul 22 04:58:11 PM PDT 24
Finished Jul 22 05:02:50 PM PDT 24
Peak memory 258312 kb
Host smart-22746661-fc0b-4bbc-9551-ea0b1d4bee7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309247942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1309247942
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1086991781
Short name T90
Test name
Test status
Simulation time 18739068430 ps
CPU time 63.32 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 253464 kb
Host smart-d2f490ef-c03a-407c-874c-5a18c22e38b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086991781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1086991781
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4235694101
Short name T418
Test name
Test status
Simulation time 983245000 ps
CPU time 8.36 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:26 PM PDT 24
Peak memory 233536 kb
Host smart-447add63-3b83-48aa-805a-0a6a69186b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235694101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4235694101
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4016679585
Short name T884
Test name
Test status
Simulation time 1183363448 ps
CPU time 4.45 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:22 PM PDT 24
Peak memory 233576 kb
Host smart-06e560be-b3cc-4cb5-9122-3cb3e69e38ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016679585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4016679585
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.59058989
Short name T700
Test name
Test status
Simulation time 326990158 ps
CPU time 1.05 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 04:58:07 PM PDT 24
Peak memory 217400 kb
Host smart-236bb069-3d60-43f8-bdfd-21efdc1d16dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59058989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.59058989
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1192684730
Short name T609
Test name
Test status
Simulation time 539014540 ps
CPU time 7.06 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:17 PM PDT 24
Peak memory 233596 kb
Host smart-8b528d79-a5d1-4e5b-966c-973378cdb5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192684730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1192684730
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4181594132
Short name T555
Test name
Test status
Simulation time 1159486022 ps
CPU time 16.35 seconds
Started Jul 22 04:58:13 PM PDT 24
Finished Jul 22 04:58:30 PM PDT 24
Peak memory 220448 kb
Host smart-5b39a4a0-136f-47d8-bd69-9313107bb817
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181594132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4181594132
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.37815286
Short name T977
Test name
Test status
Simulation time 41052710162 ps
CPU time 334.21 seconds
Started Jul 22 05:01:45 PM PDT 24
Finished Jul 22 05:07:20 PM PDT 24
Peak memory 253372 kb
Host smart-fa23035b-9baf-4592-b625-e61dd03d41c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress
_all.37815286
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3841137179
Short name T986
Test name
Test status
Simulation time 20211080869 ps
CPU time 34.32 seconds
Started Jul 22 04:58:11 PM PDT 24
Finished Jul 22 04:58:46 PM PDT 24
Peak memory 217284 kb
Host smart-70f59598-a5c1-4384-98d3-136edd24f6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841137179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3841137179
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.156036264
Short name T27
Test name
Test status
Simulation time 2795350651 ps
CPU time 5.13 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 04:58:11 PM PDT 24
Peak memory 217108 kb
Host smart-53d1da8d-15ed-4820-938a-b2e00006ff7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156036264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.156036264
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1229452343
Short name T437
Test name
Test status
Simulation time 23390641 ps
CPU time 1.29 seconds
Started Jul 22 04:58:11 PM PDT 24
Finished Jul 22 04:58:13 PM PDT 24
Peak memory 217152 kb
Host smart-1b2c31ce-861c-41d9-ab82-732da9c3bd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229452343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1229452343
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4241637015
Short name T602
Test name
Test status
Simulation time 468612748 ps
CPU time 0.96 seconds
Started Jul 22 05:01:45 PM PDT 24
Finished Jul 22 05:01:47 PM PDT 24
Peak memory 206728 kb
Host smart-36ef6f8f-11f4-4f31-8513-3c987fd1c87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241637015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4241637015
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2228671000
Short name T184
Test name
Test status
Simulation time 528120888 ps
CPU time 2.55 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:23 PM PDT 24
Peak memory 225244 kb
Host smart-0efbd721-9b3b-4bae-b94f-cb5f9b7b1ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228671000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2228671000
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3325718550
Short name T818
Test name
Test status
Simulation time 21792936 ps
CPU time 0.68 seconds
Started Jul 22 04:59:47 PM PDT 24
Finished Jul 22 04:59:48 PM PDT 24
Peak memory 206064 kb
Host smart-f1577e84-076c-4bb4-85f7-371b08cc909c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325718550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3325718550
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1121100922
Short name T457
Test name
Test status
Simulation time 263898340 ps
CPU time 2.78 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:58:18 PM PDT 24
Peak memory 233496 kb
Host smart-b882b14f-83e2-4f4c-9c82-8aa3848772b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121100922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1121100922
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2033526647
Short name T651
Test name
Test status
Simulation time 46075182 ps
CPU time 0.76 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 207096 kb
Host smart-fdeb240b-6f20-4bdf-8af9-acffa914361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033526647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2033526647
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2557865442
Short name T917
Test name
Test status
Simulation time 4260423506 ps
CPU time 93.83 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:59:55 PM PDT 24
Peak memory 271280 kb
Host smart-19a7a708-0fbe-43cf-95c8-650c0ede67de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557865442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2557865442
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1819869963
Short name T913
Test name
Test status
Simulation time 20942742597 ps
CPU time 227.64 seconds
Started Jul 22 04:58:11 PM PDT 24
Finished Jul 22 05:01:59 PM PDT 24
Peak memory 270468 kb
Host smart-81c806f2-9b77-4146-9d17-2bf09b0fa567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819869963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1819869963
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3643987898
Short name T654
Test name
Test status
Simulation time 3929322594 ps
CPU time 25.51 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:43 PM PDT 24
Peak memory 250432 kb
Host smart-5a69b07f-4454-466c-a046-01a6d2e7435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643987898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3643987898
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1082703869
Short name T993
Test name
Test status
Simulation time 4830468346 ps
CPU time 33.45 seconds
Started Jul 22 05:01:58 PM PDT 24
Finished Jul 22 05:02:33 PM PDT 24
Peak memory 241888 kb
Host smart-5fb569ab-b77d-4ae8-9238-48a59a6b5197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082703869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1082703869
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.1706739182
Short name T774
Test name
Test status
Simulation time 14688960120 ps
CPU time 16.16 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 251612 kb
Host smart-bfa4928a-2276-48fd-b61d-6d803fed1178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706739182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.1706739182
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.118761289
Short name T1024
Test name
Test status
Simulation time 603656837 ps
CPU time 4.58 seconds
Started Jul 22 05:01:25 PM PDT 24
Finished Jul 22 05:01:30 PM PDT 24
Peak memory 233664 kb
Host smart-eda56db4-8ea4-48c7-b1bc-baed81cfeb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118761289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.118761289
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1292320402
Short name T101
Test name
Test status
Simulation time 7806650263 ps
CPU time 62.58 seconds
Started Jul 22 04:58:10 PM PDT 24
Finished Jul 22 04:59:13 PM PDT 24
Peak memory 233704 kb
Host smart-0e88663b-3f95-4ad2-8521-169d60e4f9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292320402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1292320402
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.457296517
Short name T387
Test name
Test status
Simulation time 30758334 ps
CPU time 1.04 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 218468 kb
Host smart-548e5b87-fdf9-4211-9e0e-6ec375d188fe
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457296517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.457296517
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.390186785
Short name T248
Test name
Test status
Simulation time 10984477165 ps
CPU time 10.35 seconds
Started Jul 22 04:58:12 PM PDT 24
Finished Jul 22 04:58:23 PM PDT 24
Peak memory 233684 kb
Host smart-cb808610-342c-4e92-bf84-df6a8f575de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390186785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.390186785
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.280618306
Short name T395
Test name
Test status
Simulation time 2421636696 ps
CPU time 8.71 seconds
Started Jul 22 04:58:39 PM PDT 24
Finished Jul 22 04:58:48 PM PDT 24
Peak memory 249248 kb
Host smart-07e74f74-dd39-48a6-b3f3-4d9aa89599b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280618306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.280618306
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1065686958
Short name T453
Test name
Test status
Simulation time 6584879628 ps
CPU time 10.27 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 220728 kb
Host smart-d6b3e340-d0ea-4ae8-9dc6-c96145df3a2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1065686958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1065686958
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3983731047
Short name T18
Test name
Test status
Simulation time 94147080807 ps
CPU time 190.47 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 05:01:28 PM PDT 24
Peak memory 266436 kb
Host smart-b34ce16c-5908-42b9-8fc4-c93e6f4326a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983731047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3983731047
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1609339251
Short name T297
Test name
Test status
Simulation time 13246331890 ps
CPU time 37.89 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:55 PM PDT 24
Peak memory 216876 kb
Host smart-f190e4f7-abfd-49c4-a67a-3212bdeb10d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609339251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1609339251
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2549090871
Short name T319
Test name
Test status
Simulation time 9868231597 ps
CPU time 10.29 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:58:27 PM PDT 24
Peak memory 217172 kb
Host smart-b6ab9162-3d80-44c7-b86d-d7f25738a24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549090871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2549090871
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2669080460
Short name T348
Test name
Test status
Simulation time 38676824 ps
CPU time 1.27 seconds
Started Jul 22 04:58:17 PM PDT 24
Finished Jul 22 04:58:19 PM PDT 24
Peak memory 208824 kb
Host smart-809b9648-129e-42ef-8d3d-6210c8eb39b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669080460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2669080460
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3451497842
Short name T711
Test name
Test status
Simulation time 97394103 ps
CPU time 0.84 seconds
Started Jul 22 04:58:39 PM PDT 24
Finished Jul 22 04:58:40 PM PDT 24
Peak memory 205936 kb
Host smart-05d85e9e-6730-445d-9abe-50551b01f32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451497842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3451497842
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3029225197
Short name T643
Test name
Test status
Simulation time 253473862 ps
CPU time 4.43 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:24 PM PDT 24
Peak memory 225272 kb
Host smart-fba2b1da-079c-4ead-92d9-601bc2e0d1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029225197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3029225197
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2386124568
Short name T611
Test name
Test status
Simulation time 38438194 ps
CPU time 0.7 seconds
Started Jul 22 04:58:25 PM PDT 24
Finished Jul 22 04:58:26 PM PDT 24
Peak memory 205396 kb
Host smart-029431c7-43f1-4ebd-8ba8-391b9013fa49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386124568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2386124568
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.65088478
Short name T566
Test name
Test status
Simulation time 272928957 ps
CPU time 4.5 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:26 PM PDT 24
Peak memory 233652 kb
Host smart-402897ad-4f44-43c9-bb82-587e9db5f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65088478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.65088478
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2891390230
Short name T630
Test name
Test status
Simulation time 52057458 ps
CPU time 0.74 seconds
Started Jul 22 05:01:24 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 206220 kb
Host smart-62360efd-b2ad-4102-8bee-dd7243826e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891390230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2891390230
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.543857706
Short name T484
Test name
Test status
Simulation time 22715347808 ps
CPU time 165.84 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:03:06 PM PDT 24
Peak memory 255964 kb
Host smart-b163ad53-7dd9-42a5-888a-cf0a31abda80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543857706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.543857706
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3661757092
Short name T205
Test name
Test status
Simulation time 6850668061 ps
CPU time 111.51 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 263368 kb
Host smart-41db8d0e-cd15-4545-841b-ebb4c068145d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661757092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3661757092
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1184050469
Short name T526
Test name
Test status
Simulation time 92834564 ps
CPU time 2.74 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:23 PM PDT 24
Peak memory 225336 kb
Host smart-735c7aed-94ee-4719-92c1-46fb63279b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184050469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1184050469
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3073390554
Short name T919
Test name
Test status
Simulation time 3285314330 ps
CPU time 13.12 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 219708 kb
Host smart-cb2a1626-d51c-4cb4-a859-10d5e3b00a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073390554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3073390554
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1416709379
Short name T155
Test name
Test status
Simulation time 4147527075 ps
CPU time 18 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 04:58:40 PM PDT 24
Peak memory 222660 kb
Host smart-9bc94bb9-093b-4c6c-81f7-10885fada554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416709379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1416709379
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.205034136
Short name T228
Test name
Test status
Simulation time 2209287401 ps
CPU time 16.4 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:37 PM PDT 24
Peak memory 245220 kb
Host smart-e8e506bf-f939-4208-bc82-b8807e0f5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205034136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.205034136
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3846813212
Short name T458
Test name
Test status
Simulation time 14551113 ps
CPU time 0.95 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:58:17 PM PDT 24
Peak memory 217280 kb
Host smart-16e5de35-733c-4ea1-a60c-52db34124e51
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846813212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3846813212
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.759788238
Short name T435
Test name
Test status
Simulation time 6166640401 ps
CPU time 8.3 seconds
Started Jul 22 05:01:45 PM PDT 24
Finished Jul 22 05:01:54 PM PDT 24
Peak memory 239800 kb
Host smart-308e9e1a-9284-498c-a815-2365df500a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759788238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.759788238
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3939846084
Short name T620
Test name
Test status
Simulation time 18117748180 ps
CPU time 8.69 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 233608 kb
Host smart-c4f93afc-22dd-47b5-9e42-d0157766be30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939846084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3939846084
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.318837076
Short name T790
Test name
Test status
Simulation time 3340846115 ps
CPU time 3.9 seconds
Started Jul 22 04:58:22 PM PDT 24
Finished Jul 22 04:58:27 PM PDT 24
Peak memory 225048 kb
Host smart-79f5d2e1-5d21-4f86-911d-21d915f0a7f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=318837076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.318837076
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.708674859
Short name T150
Test name
Test status
Simulation time 38270419917 ps
CPU time 112.14 seconds
Started Jul 22 04:58:26 PM PDT 24
Finished Jul 22 05:00:18 PM PDT 24
Peak memory 266460 kb
Host smart-efabbdfc-87e6-4368-ae0e-0949960f827c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708674859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.708674859
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.211968745
Short name T362
Test name
Test status
Simulation time 22164615 ps
CPU time 0.72 seconds
Started Jul 22 05:01:24 PM PDT 24
Finished Jul 22 05:01:26 PM PDT 24
Peak memory 206384 kb
Host smart-b15f1404-6a86-4430-ae4a-fcdb61d9422e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211968745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.211968745
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1787542710
Short name T935
Test name
Test status
Simulation time 1006153060 ps
CPU time 4.62 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:38 PM PDT 24
Peak memory 217228 kb
Host smart-b454c70e-a620-4d97-9020-b0513c9dfb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787542710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1787542710
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2198781690
Short name T1015
Test name
Test status
Simulation time 378655644 ps
CPU time 6.17 seconds
Started Jul 22 04:58:26 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 217092 kb
Host smart-1e31061d-ee12-4218-9dc0-6d37dcdf9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198781690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2198781690
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1467297051
Short name T494
Test name
Test status
Simulation time 18058014 ps
CPU time 0.74 seconds
Started Jul 22 04:58:15 PM PDT 24
Finished Jul 22 04:58:16 PM PDT 24
Peak memory 206668 kb
Host smart-efbfc783-f3c1-4a21-a058-b090e53dfcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467297051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1467297051
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2904142103
Short name T900
Test name
Test status
Simulation time 1453021732 ps
CPU time 6.23 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 225464 kb
Host smart-c84dfafe-2fc3-4e70-89b0-315bc8696303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904142103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2904142103
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.512501592
Short name T729
Test name
Test status
Simulation time 12865088 ps
CPU time 0.73 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 206116 kb
Host smart-2c292030-7b4b-43b3-99f8-5a429e055f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512501592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.512501592
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4048608775
Short name T797
Test name
Test status
Simulation time 167223026 ps
CPU time 2.74 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 04:58:25 PM PDT 24
Peak memory 233540 kb
Host smart-d9db01d7-30b0-4b34-9a02-b1b148ed530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048608775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4048608775
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.531303347
Short name T1026
Test name
Test status
Simulation time 43356095 ps
CPU time 0.77 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:20 PM PDT 24
Peak memory 207528 kb
Host smart-e439c773-c4b4-4e17-a655-73b9b7d960a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531303347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.531303347
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2135802865
Short name T448
Test name
Test status
Simulation time 63202154 ps
CPU time 0.8 seconds
Started Jul 22 04:58:30 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 216352 kb
Host smart-62910ce1-20ca-4a6e-b0dc-be5602e687ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135802865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2135802865
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2608693582
Short name T54
Test name
Test status
Simulation time 13371518277 ps
CPU time 162.02 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 05:01:11 PM PDT 24
Peak memory 250152 kb
Host smart-1084dc09-3e33-46c1-8525-98c0f2ba9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608693582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2608693582
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2338220321
Short name T880
Test name
Test status
Simulation time 67586762364 ps
CPU time 141.34 seconds
Started Jul 22 04:59:22 PM PDT 24
Finished Jul 22 05:01:43 PM PDT 24
Peak memory 250460 kb
Host smart-d442efa5-45ea-4d16-aeff-0feb63cb248a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338220321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2338220321
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3027706363
Short name T604
Test name
Test status
Simulation time 233988677 ps
CPU time 7.93 seconds
Started Jul 22 04:58:27 PM PDT 24
Finished Jul 22 04:58:36 PM PDT 24
Peak memory 241828 kb
Host smart-3410af5f-0ed1-43ea-9157-ea5c6b68bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027706363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3027706363
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2085192202
Short name T556
Test name
Test status
Simulation time 3102227840 ps
CPU time 57.2 seconds
Started Jul 22 04:58:33 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 255568 kb
Host smart-c066d4da-3f48-4eb1-ac5f-b7f22ba23f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085192202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2085192202
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1271766884
Short name T985
Test name
Test status
Simulation time 463155466 ps
CPU time 6.01 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:26 PM PDT 24
Peak memory 225392 kb
Host smart-1fa86ffd-845b-497c-a327-d7db7dd8d8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271766884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1271766884
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.701170263
Short name T343
Test name
Test status
Simulation time 996319681 ps
CPU time 11.58 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 240972 kb
Host smart-816b405a-ab39-4409-b599-c5968aa98c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701170263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.701170263
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.330135077
Short name T551
Test name
Test status
Simulation time 14565484 ps
CPU time 1.01 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:20 PM PDT 24
Peak memory 217292 kb
Host smart-7bc94c26-08cf-4d84-8831-474080fef09e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330135077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.330135077
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2495188864
Short name T213
Test name
Test status
Simulation time 5017579825 ps
CPU time 15.88 seconds
Started Jul 22 04:58:26 PM PDT 24
Finished Jul 22 04:58:42 PM PDT 24
Peak memory 233540 kb
Host smart-e46f7613-e1ba-40ca-a6bb-a63df579c290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495188864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2495188864
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1195091707
Short name T608
Test name
Test status
Simulation time 268972180 ps
CPU time 2.63 seconds
Started Jul 22 05:01:45 PM PDT 24
Finished Jul 22 05:01:48 PM PDT 24
Peak memory 225432 kb
Host smart-81d8eff9-c5a9-411b-b6fa-e208aabdcc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195091707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1195091707
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.189380903
Short name T414
Test name
Test status
Simulation time 288166321 ps
CPU time 4.69 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 223884 kb
Host smart-ee41cd37-6da0-4e2e-859a-fee63649ac8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=189380903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.189380903
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.85725789
Short name T813
Test name
Test status
Simulation time 4202234891 ps
CPU time 57.41 seconds
Started Jul 22 04:58:30 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 249996 kb
Host smart-7af9a254-9cce-4b6e-9d80-3e336212b310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85725789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress
_all.85725789
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.869260186
Short name T912
Test name
Test status
Simulation time 2108130042 ps
CPU time 17.4 seconds
Started Jul 22 05:01:45 PM PDT 24
Finished Jul 22 05:02:03 PM PDT 24
Peak memory 217400 kb
Host smart-c791e7ea-eb8f-40bb-97b8-176bdd57bc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869260186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.869260186
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.393104100
Short name T564
Test name
Test status
Simulation time 3332133230 ps
CPU time 11.66 seconds
Started Jul 22 04:58:21 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 217232 kb
Host smart-25d79825-6162-40fa-a067-4d97ad792d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393104100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.393104100
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.4060768397
Short name T25
Test name
Test status
Simulation time 88661037 ps
CPU time 1.06 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 208436 kb
Host smart-168eb19d-5300-4e6d-a6d6-0403bcc952df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060768397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.4060768397
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2695123973
Short name T588
Test name
Test status
Simulation time 75251312 ps
CPU time 0.84 seconds
Started Jul 22 04:58:19 PM PDT 24
Finished Jul 22 04:58:20 PM PDT 24
Peak memory 207716 kb
Host smart-c3360cbc-2fbb-4650-916d-fc426275cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695123973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2695123973
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3857171397
Short name T478
Test name
Test status
Simulation time 385056719 ps
CPU time 2.5 seconds
Started Jul 22 04:58:20 PM PDT 24
Finished Jul 22 04:58:23 PM PDT 24
Peak memory 225296 kb
Host smart-aa7189eb-3203-474b-853e-d7d7f1c8ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857171397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3857171397
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1184578476
Short name T664
Test name
Test status
Simulation time 23230826 ps
CPU time 0.71 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:08 PM PDT 24
Peak memory 206008 kb
Host smart-4411b32a-5b3a-4be5-9b69-85518f021135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184578476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1184578476
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.955373685
Short name T605
Test name
Test status
Simulation time 34849590 ps
CPU time 2.51 seconds
Started Jul 22 04:58:30 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 233552 kb
Host smart-da4a158e-287e-47b2-83de-4e0fb261d348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955373685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.955373685
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3899828029
Short name T338
Test name
Test status
Simulation time 22093812 ps
CPU time 0.72 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:58:30 PM PDT 24
Peak memory 206168 kb
Host smart-e88bb0e3-217e-4fe1-a63b-526e46475b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899828029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3899828029
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2268335677
Short name T269
Test name
Test status
Simulation time 85816027356 ps
CPU time 293.2 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 05:03:25 PM PDT 24
Peak memory 254328 kb
Host smart-e6970483-791a-4bbd-a3b9-0aebc3b82557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268335677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2268335677
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.210303223
Short name T129
Test name
Test status
Simulation time 4168402379 ps
CPU time 80.42 seconds
Started Jul 22 04:58:33 PM PDT 24
Finished Jul 22 04:59:54 PM PDT 24
Peak memory 254632 kb
Host smart-d4c1a157-66a8-44db-99d8-0eff7dc2ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210303223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.210303223
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3464677051
Short name T53
Test name
Test status
Simulation time 26804424462 ps
CPU time 35.52 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:59:04 PM PDT 24
Peak memory 225352 kb
Host smart-57206731-3a66-4b07-8c90-6c74033e33f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464677051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3464677051
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2462159973
Short name T649
Test name
Test status
Simulation time 1618370731 ps
CPU time 10.94 seconds
Started Jul 22 04:58:29 PM PDT 24
Finished Jul 22 04:58:41 PM PDT 24
Peak memory 225396 kb
Host smart-49edcfe1-d53f-4958-ade3-2d632641576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462159973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2462159973
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3873408126
Short name T736
Test name
Test status
Simulation time 11578425922 ps
CPU time 98.91 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 05:00:08 PM PDT 24
Peak memory 251684 kb
Host smart-178ea4a4-f1e4-4a1d-91b2-1f8ad377b385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873408126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3873408126
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1768688438
Short name T682
Test name
Test status
Simulation time 117061102 ps
CPU time 3.94 seconds
Started Jul 22 04:58:30 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 233552 kb
Host smart-17a2673d-2c5e-49a6-a8c3-302ad070db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768688438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1768688438
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1790250237
Short name T738
Test name
Test status
Simulation time 881807484 ps
CPU time 11.87 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:45 PM PDT 24
Peak memory 233648 kb
Host smart-7557fda9-e123-4ae5-a7e0-7bafaabcfed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790250237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1790250237
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.403027565
Short name T680
Test name
Test status
Simulation time 148227708 ps
CPU time 1.04 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 217292 kb
Host smart-2790bd92-0b45-4617-94e8-c065e10a06ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403027565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.403027565
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2962664041
Short name T545
Test name
Test status
Simulation time 147502060 ps
CPU time 2.19 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 225324 kb
Host smart-ba031f0f-ae6d-4591-9605-6fb50d7a8b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962664041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2962664041
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2511463271
Short name T91
Test name
Test status
Simulation time 7954215897 ps
CPU time 11.31 seconds
Started Jul 22 04:58:29 PM PDT 24
Finished Jul 22 04:58:41 PM PDT 24
Peak memory 233712 kb
Host smart-7f52b098-b37a-4f68-9a2a-52210832e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511463271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2511463271
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3526724776
Short name T461
Test name
Test status
Simulation time 123660578 ps
CPU time 2.97 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:58:32 PM PDT 24
Peak memory 223368 kb
Host smart-0fc4246b-876b-4cac-87be-f878550cee66
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526724776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3526724776
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4125827725
Short name T892
Test name
Test status
Simulation time 33326949121 ps
CPU time 106.82 seconds
Started Jul 22 04:58:27 PM PDT 24
Finished Jul 22 05:00:15 PM PDT 24
Peak memory 250488 kb
Host smart-ce43da56-1bc1-4be2-b053-a2d426cbbb11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125827725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4125827725
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2809070351
Short name T859
Test name
Test status
Simulation time 10099423198 ps
CPU time 42.06 seconds
Started Jul 22 04:58:27 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 217228 kb
Host smart-f3db8c79-9e39-4ffd-81d6-8aa319d430d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809070351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2809070351
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2809403522
Short name T827
Test name
Test status
Simulation time 691915583 ps
CPU time 2.02 seconds
Started Jul 22 04:58:31 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 217044 kb
Host smart-78d8e262-6e0f-4d20-8362-13798e991ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809403522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2809403522
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2020566065
Short name T304
Test name
Test status
Simulation time 41033374 ps
CPU time 0.89 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:34 PM PDT 24
Peak memory 207612 kb
Host smart-0c63da99-6389-4bb3-bc65-327b897afbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020566065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2020566065
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1687499965
Short name T325
Test name
Test status
Simulation time 370902945 ps
CPU time 0.86 seconds
Started Jul 22 04:58:35 PM PDT 24
Finished Jul 22 04:58:36 PM PDT 24
Peak memory 206616 kb
Host smart-1e311957-3e2d-48b3-8299-8a9f2c1481b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687499965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1687499965
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4040530043
Short name T242
Test name
Test status
Simulation time 41419246111 ps
CPU time 33.18 seconds
Started Jul 22 04:58:33 PM PDT 24
Finished Jul 22 04:59:07 PM PDT 24
Peak memory 236952 kb
Host smart-5e5c5e11-acd1-4156-bd4c-4a920ca91d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040530043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4040530043
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3541272478
Short name T546
Test name
Test status
Simulation time 22178751 ps
CPU time 0.73 seconds
Started Jul 22 04:58:36 PM PDT 24
Finished Jul 22 04:58:37 PM PDT 24
Peak memory 206332 kb
Host smart-dd322141-51f0-44c5-90ba-5f0f8221ebec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541272478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3541272478
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3320480038
Short name T488
Test name
Test status
Simulation time 2579375012 ps
CPU time 9.14 seconds
Started Jul 22 04:59:40 PM PDT 24
Finished Jul 22 04:59:50 PM PDT 24
Peak memory 225528 kb
Host smart-7af7a35d-2932-4da5-bddb-789f302aeb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320480038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3320480038
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1627340584
Short name T344
Test name
Test status
Simulation time 14385543 ps
CPU time 0.75 seconds
Started Jul 22 04:58:27 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 207572 kb
Host smart-eb30b6fb-f027-4eaf-8002-89c18747e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627340584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1627340584
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3479456907
Short name T402
Test name
Test status
Simulation time 3028205754 ps
CPU time 53.66 seconds
Started Jul 22 04:58:38 PM PDT 24
Finished Jul 22 04:59:32 PM PDT 24
Peak memory 252132 kb
Host smart-8df87d35-53c9-480c-b951-1e4433f379c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479456907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3479456907
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3587152277
Short name T659
Test name
Test status
Simulation time 39635681179 ps
CPU time 361.38 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:09:19 PM PDT 24
Peak memory 266148 kb
Host smart-5b9c88d2-af12-4e28-a093-b8b007e28e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587152277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3587152277
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3966740223
Short name T361
Test name
Test status
Simulation time 13325804916 ps
CPU time 133.39 seconds
Started Jul 22 04:58:36 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 250064 kb
Host smart-94c5dd8d-337a-41a9-b2cf-e4ad0409fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966740223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3966740223
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2934995571
Short name T975
Test name
Test status
Simulation time 366837609 ps
CPU time 11.49 seconds
Started Jul 22 04:58:36 PM PDT 24
Finished Jul 22 04:58:48 PM PDT 24
Peak memory 240152 kb
Host smart-3d0eb17e-8646-4c76-b592-a29d89c7cb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934995571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2934995571
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.4144114834
Short name T882
Test name
Test status
Simulation time 4817190515 ps
CPU time 23.52 seconds
Started Jul 22 04:58:41 PM PDT 24
Finished Jul 22 04:59:05 PM PDT 24
Peak memory 236132 kb
Host smart-1ef67a73-2c6b-430a-8d97-f57c74375268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144114834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.4144114834
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1062274061
Short name T878
Test name
Test status
Simulation time 574263861 ps
CPU time 7.84 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:28 PM PDT 24
Peak memory 225332 kb
Host smart-e5ef6e0f-f7f6-4587-8b25-0e81358f9e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062274061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1062274061
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3759601162
Short name T779
Test name
Test status
Simulation time 2161137597 ps
CPU time 11.11 seconds
Started Jul 22 04:58:36 PM PDT 24
Finished Jul 22 04:58:48 PM PDT 24
Peak memory 233748 kb
Host smart-408a19a1-4746-43c5-a606-ae7b47ccb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759601162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3759601162
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1792300723
Short name T36
Test name
Test status
Simulation time 35223606 ps
CPU time 1.06 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:58:30 PM PDT 24
Peak memory 217340 kb
Host smart-d281a275-ceba-4e9b-9c61-9cb21dd9b3fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792300723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1792300723
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4048211680
Short name T250
Test name
Test status
Simulation time 362373007 ps
CPU time 3.03 seconds
Started Jul 22 04:58:38 PM PDT 24
Finished Jul 22 04:58:41 PM PDT 24
Peak memory 233520 kb
Host smart-3b040dcd-f4a8-4d1b-88d1-9341ff6f7676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048211680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4048211680
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1242669017
Short name T756
Test name
Test status
Simulation time 52398290 ps
CPU time 2.34 seconds
Started Jul 22 04:58:39 PM PDT 24
Finished Jul 22 04:58:42 PM PDT 24
Peak memory 233468 kb
Host smart-abb4511d-d695-4bc4-8a6e-2ebe742124fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242669017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1242669017
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.301310950
Short name T469
Test name
Test status
Simulation time 3679663513 ps
CPU time 9.59 seconds
Started Jul 22 04:58:37 PM PDT 24
Finished Jul 22 04:58:47 PM PDT 24
Peak memory 223024 kb
Host smart-3d34180d-3aba-442e-a31b-ddafb3035151
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=301310950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.301310950
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3115582070
Short name T980
Test name
Test status
Simulation time 46857468929 ps
CPU time 413.81 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:10:13 PM PDT 24
Peak memory 273820 kb
Host smart-7c474d4f-dc9f-4497-a962-534ea4aa7a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115582070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3115582070
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1355921736
Short name T619
Test name
Test status
Simulation time 26926624810 ps
CPU time 30.82 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:59:04 PM PDT 24
Peak memory 217336 kb
Host smart-495d8ab2-f58e-41e4-a05a-19db4acfa805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355921736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1355921736
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2652104737
Short name T68
Test name
Test status
Simulation time 65130552 ps
CPU time 0.75 seconds
Started Jul 22 04:58:28 PM PDT 24
Finished Jul 22 04:58:30 PM PDT 24
Peak memory 206236 kb
Host smart-f29a1af7-aad0-4323-8542-7a62ade25e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652104737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2652104737
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1978922479
Short name T303
Test name
Test status
Simulation time 1907840277 ps
CPU time 2.01 seconds
Started Jul 22 04:58:36 PM PDT 24
Finished Jul 22 04:58:39 PM PDT 24
Peak memory 217204 kb
Host smart-d89f31b8-a179-4279-9cac-2762d4b98b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978922479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1978922479
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.545143902
Short name T331
Test name
Test status
Simulation time 75140796 ps
CPU time 0.95 seconds
Started Jul 22 04:58:30 PM PDT 24
Finished Jul 22 04:58:31 PM PDT 24
Peak memory 207684 kb
Host smart-19721e52-7b84-46b9-abf2-75ceec24d6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545143902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.545143902
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.770041266
Short name T492
Test name
Test status
Simulation time 9403668517 ps
CPU time 9.71 seconds
Started Jul 22 04:58:37 PM PDT 24
Finished Jul 22 04:58:47 PM PDT 24
Peak memory 233696 kb
Host smart-a292c624-5c38-4c15-a708-162ec61dd8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770041266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.770041266
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3777280486
Short name T1008
Test name
Test status
Simulation time 18832352 ps
CPU time 0.72 seconds
Started Jul 22 04:58:46 PM PDT 24
Finished Jul 22 04:58:47 PM PDT 24
Peak memory 205476 kb
Host smart-5fe38d4a-7dbd-4852-8879-309ce3d204db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777280486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3777280486
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2417831153
Short name T921
Test name
Test status
Simulation time 4964251946 ps
CPU time 13.22 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 225348 kb
Host smart-9171004c-0867-48bd-a8a5-6d4552063e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417831153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2417831153
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2199201011
Short name T573
Test name
Test status
Simulation time 13786163 ps
CPU time 0.78 seconds
Started Jul 22 04:58:40 PM PDT 24
Finished Jul 22 04:58:41 PM PDT 24
Peak memory 207236 kb
Host smart-7c6a601f-d8f4-4403-af16-13c09b230443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199201011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2199201011
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1352719307
Short name T989
Test name
Test status
Simulation time 1776494279 ps
CPU time 36.96 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:59:24 PM PDT 24
Peak memory 253708 kb
Host smart-9c44bbe0-6b30-4d4d-a0e4-5318f3820bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352719307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1352719307
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3193258443
Short name T822
Test name
Test status
Simulation time 86389333212 ps
CPU time 154.01 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 05:01:22 PM PDT 24
Peak memory 250084 kb
Host smart-f3e3596b-4055-4c05-ad58-d43a16534c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193258443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3193258443
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1529086339
Short name T728
Test name
Test status
Simulation time 446289674 ps
CPU time 4.31 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:58:53 PM PDT 24
Peak memory 233628 kb
Host smart-d1295bc3-d3ec-418e-94eb-6efa611cd0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529086339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1529086339
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.615911071
Short name T481
Test name
Test status
Simulation time 2339754302 ps
CPU time 56.86 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 04:59:46 PM PDT 24
Peak memory 258252 kb
Host smart-82beb825-1654-41d4-a747-24b1a7e514f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615911071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.615911071
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.252486849
Short name T950
Test name
Test status
Simulation time 7441859545 ps
CPU time 8.84 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:58:57 PM PDT 24
Peak memory 233624 kb
Host smart-09f4d05e-201f-474f-acc1-dfadacb9b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252486849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.252486849
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3119584845
Short name T903
Test name
Test status
Simulation time 210790138 ps
CPU time 6.91 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 241568 kb
Host smart-1edb1b43-052c-43dd-aac1-60728bff84f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119584845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3119584845
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3653877424
Short name T35
Test name
Test status
Simulation time 152130153 ps
CPU time 1.09 seconds
Started Jul 22 04:58:46 PM PDT 24
Finished Jul 22 04:58:48 PM PDT 24
Peak memory 217284 kb
Host smart-23481fc2-1c4f-48c7-a223-e5b5e0715b69
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653877424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3653877424
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.184633385
Short name T186
Test name
Test status
Simulation time 3067638960 ps
CPU time 7.79 seconds
Started Jul 22 04:58:46 PM PDT 24
Finished Jul 22 04:58:55 PM PDT 24
Peak memory 234612 kb
Host smart-2b44d330-d3e7-45d9-9255-3f26c57d225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184633385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.184633385
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3429332979
Short name T409
Test name
Test status
Simulation time 3890320091 ps
CPU time 15.15 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:59:04 PM PDT 24
Peak memory 225504 kb
Host smart-d266183d-a5bb-4a71-bc3e-be474c4bea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429332979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3429332979
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1998102060
Short name T502
Test name
Test status
Simulation time 1052069349 ps
CPU time 9.82 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:58:57 PM PDT 24
Peak memory 223668 kb
Host smart-d6ad4123-004d-4e69-a8bc-a062834595ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1998102060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1998102060
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3322002223
Short name T274
Test name
Test status
Simulation time 51774347927 ps
CPU time 483.89 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 05:06:51 PM PDT 24
Peak memory 273344 kb
Host smart-39422fa3-7969-47a8-a428-e757e33905f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322002223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3322002223
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3691536579
Short name T826
Test name
Test status
Simulation time 8879588837 ps
CPU time 35.53 seconds
Started Jul 22 04:58:45 PM PDT 24
Finished Jul 22 04:59:21 PM PDT 24
Peak memory 217240 kb
Host smart-c96dc1d8-664a-4c66-9fdc-ff356cfcfafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691536579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3691536579
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1265614131
Short name T530
Test name
Test status
Simulation time 8223819897 ps
CPU time 7.7 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 04:58:57 PM PDT 24
Peak memory 217476 kb
Host smart-eac2d298-5219-4dc3-8fa5-f597f8ac7c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265614131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1265614131
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2890525805
Short name T363
Test name
Test status
Simulation time 98804916 ps
CPU time 1.02 seconds
Started Jul 22 05:01:51 PM PDT 24
Finished Jul 22 05:01:53 PM PDT 24
Peak memory 208228 kb
Host smart-ac32b397-a375-4692-828d-a50de0af3170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890525805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2890525805
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1131684324
Short name T323
Test name
Test status
Simulation time 76137972 ps
CPU time 0.93 seconds
Started Jul 22 04:58:50 PM PDT 24
Finished Jul 22 04:58:52 PM PDT 24
Peak memory 206716 kb
Host smart-52660933-475a-4012-815d-8bc6407d3cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131684324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1131684324
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.209659860
Short name T229
Test name
Test status
Simulation time 120773839 ps
CPU time 2.4 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:01:00 PM PDT 24
Peak memory 225420 kb
Host smart-4f789998-8a38-4cd5-8fa7-c5bf8e5144b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209659860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.209659860
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4075930743
Short name T830
Test name
Test status
Simulation time 32108843 ps
CPU time 0.73 seconds
Started Jul 22 04:58:56 PM PDT 24
Finished Jul 22 04:58:57 PM PDT 24
Peak memory 206388 kb
Host smart-0f98c90d-eab8-456a-88fa-701bbe0e3f53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075930743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4075930743
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1315821880
Short name T795
Test name
Test status
Simulation time 471826331 ps
CPU time 5.14 seconds
Started Jul 22 04:58:46 PM PDT 24
Finished Jul 22 04:58:52 PM PDT 24
Peak memory 225352 kb
Host smart-4f38089b-7f5d-433f-b64a-1d059a5d19eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315821880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1315821880
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.414278510
Short name T310
Test name
Test status
Simulation time 21457664 ps
CPU time 0.83 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 04:58:50 PM PDT 24
Peak memory 207256 kb
Host smart-85a42c4d-8433-4887-ae0e-3d8d310ac4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414278510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.414278510
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.53903427
Short name T525
Test name
Test status
Simulation time 11829616412 ps
CPU time 97.58 seconds
Started Jul 22 04:58:49 PM PDT 24
Finished Jul 22 05:00:28 PM PDT 24
Peak memory 251692 kb
Host smart-36f83fbd-d2a9-44f8-9320-70c60ba84ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53903427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.53903427
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2586505590
Short name T169
Test name
Test status
Simulation time 4969152260 ps
CPU time 17.45 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:17 PM PDT 24
Peak memory 241948 kb
Host smart-0c558bc8-c4d5-4f4b-844e-74d1bba43ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586505590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2586505590
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.4179569438
Short name T236
Test name
Test status
Simulation time 89038161271 ps
CPU time 239.86 seconds
Started Jul 22 05:00:15 PM PDT 24
Finished Jul 22 05:04:16 PM PDT 24
Peak memory 257812 kb
Host smart-ffc74498-978c-4372-b2e4-cf10cf9ab1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179569438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.4179569438
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3214506085
Short name T291
Test name
Test status
Simulation time 1418609581 ps
CPU time 15.92 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:59:05 PM PDT 24
Peak memory 234400 kb
Host smart-63d58106-d332-49d1-b22d-aeed690f8128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214506085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3214506085
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.510240258
Short name T214
Test name
Test status
Simulation time 2218069908 ps
CPU time 22.54 seconds
Started Jul 22 04:58:45 PM PDT 24
Finished Jul 22 04:59:08 PM PDT 24
Peak memory 233648 kb
Host smart-65bb7967-2a16-40ba-874a-27a1c816733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510240258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.510240258
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2323387753
Short name T831
Test name
Test status
Simulation time 716108029 ps
CPU time 3.52 seconds
Started Jul 22 05:01:50 PM PDT 24
Finished Jul 22 05:01:55 PM PDT 24
Peak memory 225336 kb
Host smart-1632196a-b599-46b1-b321-bd917179609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323387753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2323387753
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2333687069
Short name T187
Test name
Test status
Simulation time 15090110619 ps
CPU time 70.48 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 05:00:00 PM PDT 24
Peak memory 241800 kb
Host smart-bdecbf56-6026-4e4c-a30d-14b7d5ea7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333687069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2333687069
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2242454546
Short name T352
Test name
Test status
Simulation time 14318107 ps
CPU time 1.07 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 04:58:50 PM PDT 24
Peak memory 217584 kb
Host smart-05bb077e-d969-4a57-8266-e18d7c07f456
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242454546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2242454546
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4153853469
Short name T625
Test name
Test status
Simulation time 49766307956 ps
CPU time 37.06 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:59:26 PM PDT 24
Peak memory 234660 kb
Host smart-ca0a532c-8ec7-417d-b4e9-63cc270b403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153853469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4153853469
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.298005192
Short name T241
Test name
Test status
Simulation time 46218424 ps
CPU time 2.34 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 233576 kb
Host smart-17c994c2-8ac1-4ead-9d14-cf0fa6d50463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298005192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.298005192
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3894321892
Short name T918
Test name
Test status
Simulation time 69015929 ps
CPU time 3.52 seconds
Started Jul 22 04:58:46 PM PDT 24
Finished Jul 22 04:58:51 PM PDT 24
Peak memory 223832 kb
Host smart-d9249716-532c-4414-9203-93ea1998dc57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3894321892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3894321892
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.862465738
Short name T148
Test name
Test status
Simulation time 2157387407 ps
CPU time 34.66 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:33 PM PDT 24
Peak memory 225564 kb
Host smart-1dacc68c-002d-4468-946e-060fbe7f5155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862465738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.862465738
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1022953722
Short name T371
Test name
Test status
Simulation time 42075684 ps
CPU time 0.72 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:58:49 PM PDT 24
Peak memory 206268 kb
Host smart-4f495315-6fad-4f3f-91a1-3eccb7f7f9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022953722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1022953722
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2740089508
Short name T599
Test name
Test status
Simulation time 19555685 ps
CPU time 0.71 seconds
Started Jul 22 04:58:47 PM PDT 24
Finished Jul 22 04:58:49 PM PDT 24
Peak memory 206288 kb
Host smart-42cc180b-e071-46e5-aa07-6cdfbb8a7bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740089508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2740089508
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2943181307
Short name T355
Test name
Test status
Simulation time 473622707 ps
CPU time 7.37 seconds
Started Jul 22 04:58:49 PM PDT 24
Finished Jul 22 04:58:57 PM PDT 24
Peak memory 217200 kb
Host smart-652d3b2d-f9c4-4c82-87e2-74b3a8b9731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943181307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2943181307
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.100423820
Short name T156
Test name
Test status
Simulation time 43832812 ps
CPU time 0.9 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 207800 kb
Host smart-a1ee55ab-c763-4def-827d-30315e44bfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100423820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.100423820
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.528061375
Short name T725
Test name
Test status
Simulation time 1901465836 ps
CPU time 11.82 seconds
Started Jul 22 04:58:48 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 240056 kb
Host smart-37405155-6958-4a6d-86be-80b6772f37cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528061375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.528061375
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2786177760
Short name T511
Test name
Test status
Simulation time 51804228 ps
CPU time 0.72 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:00 PM PDT 24
Peak memory 205496 kb
Host smart-ae76b2a0-3128-4ebe-8b18-5b8ea59bacd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786177760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2786177760
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2853062453
Short name T57
Test name
Test status
Simulation time 449515044 ps
CPU time 6.76 seconds
Started Jul 22 04:58:59 PM PDT 24
Finished Jul 22 04:59:06 PM PDT 24
Peak memory 233552 kb
Host smart-68c5e631-7cb4-4196-b7b5-06a9f9713e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853062453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2853062453
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1364992944
Short name T6
Test name
Test status
Simulation time 17130029 ps
CPU time 0.78 seconds
Started Jul 22 05:00:15 PM PDT 24
Finished Jul 22 05:00:17 PM PDT 24
Peak memory 206564 kb
Host smart-282534ee-d17b-4269-be93-193deb0c0ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364992944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1364992944
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.738680502
Short name T40
Test name
Test status
Simulation time 7967817445 ps
CPU time 60.39 seconds
Started Jul 22 04:59:01 PM PDT 24
Finished Jul 22 05:00:02 PM PDT 24
Peak memory 233692 kb
Host smart-19e7ae02-69be-45ec-8a17-72cda0b4338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738680502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.738680502
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1772209829
Short name T166
Test name
Test status
Simulation time 54362756062 ps
CPU time 180.47 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 05:01:59 PM PDT 24
Peak memory 258028 kb
Host smart-dc4a8ddd-24d2-4df8-b0b8-2f1d108bd065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772209829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1772209829
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3629559207
Short name T302
Test name
Test status
Simulation time 16152633189 ps
CPU time 34.66 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 225448 kb
Host smart-93453f11-ecce-420e-a9d9-3cf9635f6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629559207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3629559207
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1928850783
Short name T289
Test name
Test status
Simulation time 1993954429 ps
CPU time 8.99 seconds
Started Jul 22 04:59:01 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 234672 kb
Host smart-a09c27bd-587b-4532-8be1-73139d7a36b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928850783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1928850783
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1522088667
Short name T89
Test name
Test status
Simulation time 12997330679 ps
CPU time 74.75 seconds
Started Jul 22 04:58:57 PM PDT 24
Finished Jul 22 05:00:12 PM PDT 24
Peak memory 251384 kb
Host smart-3db11886-3fb6-40bf-b007-a8d079ba8019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522088667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1522088667
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3910188953
Short name T747
Test name
Test status
Simulation time 347783118 ps
CPU time 3.11 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:02 PM PDT 24
Peak memory 228800 kb
Host smart-fcfaf367-7edf-4dbd-8687-f849ab841c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910188953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3910188953
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1662939420
Short name T239
Test name
Test status
Simulation time 491243237 ps
CPU time 2.79 seconds
Started Jul 22 04:58:57 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 225464 kb
Host smart-2ac5e738-7f3e-422d-a569-2cbe45999af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662939420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1662939420
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3860708229
Short name T998
Test name
Test status
Simulation time 24409315 ps
CPU time 1.06 seconds
Started Jul 22 04:59:01 PM PDT 24
Finished Jul 22 04:59:02 PM PDT 24
Peak memory 217280 kb
Host smart-050e58a9-dcc3-4736-b5e1-643710b94ad1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860708229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3860708229
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1116438535
Short name T42
Test name
Test status
Simulation time 226127712 ps
CPU time 4.84 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:06 PM PDT 24
Peak memory 236208 kb
Host smart-95ec68d4-a9c0-4f53-b833-273137e5a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116438535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1116438535
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1697078258
Short name T595
Test name
Test status
Simulation time 12707617593 ps
CPU time 10.08 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:09 PM PDT 24
Peak memory 225416 kb
Host smart-552450aa-c5d3-4332-a0d6-58f079199815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697078258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1697078258
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2989365321
Short name T1011
Test name
Test status
Simulation time 825887534 ps
CPU time 6.44 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:05 PM PDT 24
Peak memory 223776 kb
Host smart-c56939be-a64d-494d-8ef0-5fd027802651
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989365321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2989365321
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2821360876
Short name T535
Test name
Test status
Simulation time 362438943 ps
CPU time 0.96 seconds
Started Jul 22 04:58:59 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 208448 kb
Host smart-446386f5-d224-4639-abec-2b6eabcfd0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821360876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2821360876
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1253072952
Short name T773
Test name
Test status
Simulation time 1678924057 ps
CPU time 20.04 seconds
Started Jul 22 04:58:59 PM PDT 24
Finished Jul 22 04:59:20 PM PDT 24
Peak memory 217132 kb
Host smart-fd263326-22fc-4959-927e-7aca831156d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253072952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1253072952
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.350038592
Short name T498
Test name
Test status
Simulation time 2110378098 ps
CPU time 7.68 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:08 PM PDT 24
Peak memory 217072 kb
Host smart-1917c186-62b9-4fe3-a15e-e9828170830f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350038592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.350038592
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1554340028
Short name T894
Test name
Test status
Simulation time 19308521 ps
CPU time 1.15 seconds
Started Jul 22 04:58:57 PM PDT 24
Finished Jul 22 04:58:59 PM PDT 24
Peak memory 208868 kb
Host smart-31b50376-8514-43fa-89bc-0326522f21a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554340028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1554340028
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4071941048
Short name T548
Test name
Test status
Simulation time 58539527 ps
CPU time 0.87 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 206700 kb
Host smart-5452c9ed-06ad-481a-ae6f-ddab515dc107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071941048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4071941048
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1502982932
Short name T841
Test name
Test status
Simulation time 4447468090 ps
CPU time 21.48 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:20 PM PDT 24
Peak memory 241104 kb
Host smart-b3c72d85-7490-4660-bf1d-ba876d723056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502982932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1502982932
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3311302149
Short name T334
Test name
Test status
Simulation time 16885734 ps
CPU time 0.67 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:24 PM PDT 24
Peak memory 205444 kb
Host smart-a6a57d5b-8d12-4341-868c-fb8dab8af5a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311302149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
311302149
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1338286747
Short name T487
Test name
Test status
Simulation time 285825478 ps
CPU time 5.55 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:18 PM PDT 24
Peak memory 233624 kb
Host smart-0db325bb-edd4-454b-8ce4-c6940afe4fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338286747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1338286747
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1321595539
Short name T447
Test name
Test status
Simulation time 139926832 ps
CPU time 0.77 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 207164 kb
Host smart-ad5fe57a-8b09-42dc-ae96-87e591977811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321595539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1321595539
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1216974648
Short name T1023
Test name
Test status
Simulation time 44778033770 ps
CPU time 119.14 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 249992 kb
Host smart-b82a8c5d-f970-4c98-9e65-94fe8bbb7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216974648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1216974648
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2620905643
Short name T190
Test name
Test status
Simulation time 134835699033 ps
CPU time 263.83 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 05:01:47 PM PDT 24
Peak memory 250152 kb
Host smart-870ae877-c0e1-4f1b-bfa8-584d0ce13c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620905643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2620905643
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3717692599
Short name T288
Test name
Test status
Simulation time 12611810535 ps
CPU time 48.13 seconds
Started Jul 22 04:57:13 PM PDT 24
Finished Jul 22 04:58:02 PM PDT 24
Peak memory 245228 kb
Host smart-8e99f12a-fa7c-430c-b2ab-838f5a3fcac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717692599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3717692599
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1571095906
Short name T800
Test name
Test status
Simulation time 87735666708 ps
CPU time 283.75 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:05:46 PM PDT 24
Peak memory 265128 kb
Host smart-029cba65-b514-42c1-a4c9-79149baec471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571095906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1571095906
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3889436650
Short name T799
Test name
Test status
Simulation time 105600479 ps
CPU time 2.39 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 233128 kb
Host smart-9cf1256f-42e2-4d3c-902e-8a270a99bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889436650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3889436650
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1226041903
Short name T203
Test name
Test status
Simulation time 784786986 ps
CPU time 5.98 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:18 PM PDT 24
Peak memory 225344 kb
Host smart-4acd6257-7d90-4194-9f17-b6681bcbf2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226041903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1226041903
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1017205658
Short name T839
Test name
Test status
Simulation time 18454214 ps
CPU time 1.06 seconds
Started Jul 22 04:57:11 PM PDT 24
Finished Jul 22 04:57:14 PM PDT 24
Peak memory 217388 kb
Host smart-6a59c06e-c3e2-44ee-9ee9-1a25b1854238
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017205658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1017205658
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1044225803
Short name T933
Test name
Test status
Simulation time 537726822 ps
CPU time 8.07 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:21 PM PDT 24
Peak memory 233484 kb
Host smart-635c9480-8cba-495d-bd6c-a6db46c20e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044225803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1044225803
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.106362827
Short name T12
Test name
Test status
Simulation time 56572567 ps
CPU time 2.63 seconds
Started Jul 22 04:57:13 PM PDT 24
Finished Jul 22 04:57:16 PM PDT 24
Peak memory 233612 kb
Host smart-04b65fcd-197b-4cfe-95fc-d6f72b549f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106362827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.106362827
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4272111500
Short name T483
Test name
Test status
Simulation time 566014385 ps
CPU time 5.9 seconds
Started Jul 22 04:57:10 PM PDT 24
Finished Jul 22 04:57:17 PM PDT 24
Peak memory 222936 kb
Host smart-3e64338d-c65f-4e90-a8a2-30ac5090ace2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4272111500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4272111500
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.767574279
Short name T66
Test name
Test status
Simulation time 166653738 ps
CPU time 0.96 seconds
Started Jul 22 04:57:25 PM PDT 24
Finished Jul 22 04:57:27 PM PDT 24
Peak memory 235912 kb
Host smart-8d98de10-9036-4176-83de-338a9d6dc7cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767574279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.767574279
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3980414302
Short name T17
Test name
Test status
Simulation time 57607202 ps
CPU time 1.03 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 04:57:25 PM PDT 24
Peak memory 208260 kb
Host smart-c976c0bb-f60f-43d6-9bab-8dddaef86046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980414302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3980414302
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2618322492
Short name T298
Test name
Test status
Simulation time 16330130397 ps
CPU time 42.37 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:01:45 PM PDT 24
Peak memory 217172 kb
Host smart-d16ad6ba-ab04-47ec-bc9b-f4939dcb19ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618322492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2618322492
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1817574584
Short name T689
Test name
Test status
Simulation time 173593324 ps
CPU time 1.73 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:15 PM PDT 24
Peak memory 208928 kb
Host smart-031bd6e3-fbaf-4736-9a3f-bf3b4439ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817574584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1817574584
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1586371457
Short name T1013
Test name
Test status
Simulation time 30327399 ps
CPU time 1.92 seconds
Started Jul 22 04:57:13 PM PDT 24
Finished Jul 22 04:57:16 PM PDT 24
Peak memory 217348 kb
Host smart-7366487f-db81-438f-98c1-d10386c466aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586371457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1586371457
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3683582175
Short name T840
Test name
Test status
Simulation time 56210955 ps
CPU time 0.82 seconds
Started Jul 22 04:57:12 PM PDT 24
Finished Jul 22 04:57:14 PM PDT 24
Peak memory 206700 kb
Host smart-e0bcc38d-7b3e-4a84-8eb0-d69801284b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683582175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3683582175
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1091996136
Short name T563
Test name
Test status
Simulation time 633873259 ps
CPU time 2.87 seconds
Started Jul 22 04:57:09 PM PDT 24
Finished Jul 22 04:57:12 PM PDT 24
Peak memory 233528 kb
Host smart-51bda517-3f27-414a-bd7a-f36348537c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091996136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1091996136
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1549514942
Short name T710
Test name
Test status
Simulation time 83236758 ps
CPU time 0.7 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 205960 kb
Host smart-069452b1-d6f3-4f93-a0f0-19bfbbd6e891
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549514942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1549514942
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2714693582
Short name T411
Test name
Test status
Simulation time 110895498 ps
CPU time 2.5 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 04:59:11 PM PDT 24
Peak memory 225304 kb
Host smart-f00a2151-df2f-4221-94e9-f028d54e59d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714693582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2714693582
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1594580259
Short name T358
Test name
Test status
Simulation time 36728973 ps
CPU time 0.85 seconds
Started Jul 22 04:58:58 PM PDT 24
Finished Jul 22 04:59:00 PM PDT 24
Peak memory 207508 kb
Host smart-8dde1096-3fdb-46c3-8ff3-f5ece455df75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594580259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1594580259
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2979766791
Short name T379
Test name
Test status
Simulation time 2619409310 ps
CPU time 13.82 seconds
Started Jul 22 04:59:10 PM PDT 24
Finished Jul 22 04:59:24 PM PDT 24
Peak memory 241872 kb
Host smart-382e0290-741a-4130-ad02-f164d6b30542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979766791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2979766791
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3149586420
Short name T170
Test name
Test status
Simulation time 1717359755 ps
CPU time 40.55 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 04:59:52 PM PDT 24
Peak memory 250424 kb
Host smart-f9a2c993-f8ea-49fa-b096-13535a89b675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149586420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3149586420
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3433966573
Short name T984
Test name
Test status
Simulation time 3481703546 ps
CPU time 38.15 seconds
Started Jul 22 04:59:12 PM PDT 24
Finished Jul 22 04:59:51 PM PDT 24
Peak memory 240008 kb
Host smart-fa5ed8e6-ad2e-46c9-993f-959b6bc55bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433966573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3433966573
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2162061037
Short name T292
Test name
Test status
Simulation time 908575996 ps
CPU time 18.7 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:27 PM PDT 24
Peak memory 226120 kb
Host smart-db52c5c9-6fde-4d1b-bf35-dcf91f692236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162061037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2162061037
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.778761848
Short name T454
Test name
Test status
Simulation time 1670711645 ps
CPU time 6.91 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:15 PM PDT 24
Peak memory 233624 kb
Host smart-b8ef830d-6202-4fde-bebf-29c158b614ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778761848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.778761848
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2955412136
Short name T443
Test name
Test status
Simulation time 2841430902 ps
CPU time 12.88 seconds
Started Jul 22 04:58:57 PM PDT 24
Finished Jul 22 04:59:11 PM PDT 24
Peak memory 225364 kb
Host smart-5539acca-f0c7-4220-96da-d66ba809b316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955412136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2955412136
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1942048563
Short name T412
Test name
Test status
Simulation time 32510479442 ps
CPU time 17.3 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:17 PM PDT 24
Peak memory 225448 kb
Host smart-d709963a-450c-4875-8c80-387477ea48dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942048563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1942048563
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.666375773
Short name T403
Test name
Test status
Simulation time 1777227503 ps
CPU time 7.26 seconds
Started Jul 22 04:59:01 PM PDT 24
Finished Jul 22 04:59:09 PM PDT 24
Peak memory 225408 kb
Host smart-bdd57b56-3d07-4750-8850-9df396c55cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666375773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.666375773
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.23082619
Short name T501
Test name
Test status
Simulation time 2029616558 ps
CPU time 5.17 seconds
Started Jul 22 04:59:00 PM PDT 24
Finished Jul 22 04:59:05 PM PDT 24
Peak memory 225356 kb
Host smart-1583c9f7-b7f2-40bf-9eac-702e6b0c3865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23082619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.23082619
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2891787971
Short name T538
Test name
Test status
Simulation time 547872399 ps
CPU time 4.81 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 220260 kb
Host smart-b9039295-8c11-414b-a643-0c32dca65f16
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2891787971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2891787971
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1173620673
Short name T586
Test name
Test status
Simulation time 36082502373 ps
CPU time 48.75 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 225464 kb
Host smart-32eae570-d002-477e-9e77-3181dc42a9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173620673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1173620673
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2489425730
Short name T970
Test name
Test status
Simulation time 1050147557 ps
CPU time 14.3 seconds
Started Jul 22 05:01:02 PM PDT 24
Finished Jul 22 05:01:18 PM PDT 24
Peak memory 217120 kb
Host smart-4de3a5ba-8fd6-4ec7-a592-6fa14362e373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489425730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2489425730
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1562519843
Short name T162
Test name
Test status
Simulation time 7578333142 ps
CPU time 20.47 seconds
Started Jul 22 04:58:59 PM PDT 24
Finished Jul 22 04:59:20 PM PDT 24
Peak memory 217188 kb
Host smart-3cb901f9-02d9-44d8-875c-b9a9482d4ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562519843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1562519843
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1640999573
Short name T305
Test name
Test status
Simulation time 308522267 ps
CPU time 2.1 seconds
Started Jul 22 04:58:59 PM PDT 24
Finished Jul 22 04:59:01 PM PDT 24
Peak memory 217128 kb
Host smart-eaee56ab-dca2-415e-9de7-2754ea0a9a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640999573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1640999573
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3892683489
Short name T1005
Test name
Test status
Simulation time 251407150 ps
CPU time 0.82 seconds
Started Jul 22 05:01:01 PM PDT 24
Finished Jul 22 05:01:03 PM PDT 24
Peak memory 206732 kb
Host smart-6f46df8a-dc8e-43d6-a1ae-64d4ae62e435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892683489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3892683489
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.208620332
Short name T467
Test name
Test status
Simulation time 706137344 ps
CPU time 8.53 seconds
Started Jul 22 04:59:10 PM PDT 24
Finished Jul 22 04:59:19 PM PDT 24
Peak memory 236640 kb
Host smart-c9c6cc26-5c74-4196-8785-e72bb7b7f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208620332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.208620332
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3174945429
Short name T603
Test name
Test status
Simulation time 34377677 ps
CPU time 0.71 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 205360 kb
Host smart-dcc19e28-fd5a-4af0-8f3e-0beb3828c650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174945429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3174945429
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1859648413
Short name T183
Test name
Test status
Simulation time 226536444 ps
CPU time 2.63 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 233608 kb
Host smart-d8a5055b-b3e8-4577-a2f0-f35d0766dbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859648413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1859648413
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1107189268
Short name T1012
Test name
Test status
Simulation time 17493723 ps
CPU time 0.76 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 206508 kb
Host smart-c47f1536-a2a2-4f77-92ed-d330755bfaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107189268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1107189268
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1797453614
Short name T251
Test name
Test status
Simulation time 73266801616 ps
CPU time 198.23 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 05:02:27 PM PDT 24
Peak memory 265660 kb
Host smart-c593af22-89d4-4cac-a23c-99ce284c38bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797453614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1797453614
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2408232247
Short name T565
Test name
Test status
Simulation time 2316721461 ps
CPU time 15.55 seconds
Started Jul 22 04:59:10 PM PDT 24
Finished Jul 22 04:59:26 PM PDT 24
Peak memory 241236 kb
Host smart-d3774d6a-a995-434b-a562-8072a990eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408232247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2408232247
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3725555516
Short name T836
Test name
Test status
Simulation time 39679420858 ps
CPU time 61.95 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 05:00:11 PM PDT 24
Peak memory 250052 kb
Host smart-50bca92b-acbc-42b3-81cb-8537c4b73477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725555516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3725555516
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3943364190
Short name T865
Test name
Test status
Simulation time 1793356805 ps
CPU time 21.37 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 04:59:30 PM PDT 24
Peak memory 225300 kb
Host smart-ca3babc7-d186-4986-940b-23641b6788df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943364190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3943364190
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.4061118980
Short name T434
Test name
Test status
Simulation time 48239689350 ps
CPU time 50.97 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:04:09 PM PDT 24
Peak memory 239968 kb
Host smart-2dc6e6de-9e8b-4963-abd7-19d1fba64ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061118980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.4061118980
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1527413500
Short name T613
Test name
Test status
Simulation time 3306850646 ps
CPU time 4.96 seconds
Started Jul 22 04:59:14 PM PDT 24
Finished Jul 22 04:59:19 PM PDT 24
Peak memory 233208 kb
Host smart-86545fae-fec8-4fcd-b38f-d15ab6004b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527413500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1527413500
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3511006129
Short name T937
Test name
Test status
Simulation time 11616546546 ps
CPU time 8.89 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 04:59:21 PM PDT 24
Peak memory 225496 kb
Host smart-88c4e3cb-1ff3-44cd-b508-fc20dbd0299d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511006129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3511006129
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2045852856
Short name T687
Test name
Test status
Simulation time 269200907 ps
CPU time 3.8 seconds
Started Jul 22 04:59:08 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 220244 kb
Host smart-9c7b2b9a-2a59-4c08-b2fa-8dd1c300b254
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2045852856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2045852856
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2386332382
Short name T451
Test name
Test status
Simulation time 4007836109 ps
CPU time 20.43 seconds
Started Jul 22 04:59:14 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 220728 kb
Host smart-241f9a9a-5140-49a8-9dd2-14df57479436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386332382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2386332382
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.156529934
Short name T377
Test name
Test status
Simulation time 10932360 ps
CPU time 0.73 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:10 PM PDT 24
Peak memory 206432 kb
Host smart-b762b593-c4e3-443a-a720-28bc32bcc12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156529934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.156529934
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1990273600
Short name T368
Test name
Test status
Simulation time 786931305 ps
CPU time 5.62 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:23 PM PDT 24
Peak memory 216972 kb
Host smart-a30ae66b-a68d-40e0-953d-9da5fdbeffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990273600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1990273600
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1840988269
Short name T781
Test name
Test status
Simulation time 60018618 ps
CPU time 0.86 seconds
Started Jul 22 04:59:14 PM PDT 24
Finished Jul 22 04:59:15 PM PDT 24
Peak memory 206648 kb
Host smart-29a6757a-2795-45f6-8d27-66be598118bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840988269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1840988269
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4123170772
Short name T679
Test name
Test status
Simulation time 2188893213 ps
CPU time 5.33 seconds
Started Jul 22 04:59:12 PM PDT 24
Finished Jul 22 04:59:18 PM PDT 24
Peak memory 233624 kb
Host smart-002a588f-516a-4d7b-892f-ec8a2804cf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123170772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4123170772
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4080562531
Short name T474
Test name
Test status
Simulation time 14304970 ps
CPU time 0.72 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:20 PM PDT 24
Peak memory 205496 kb
Host smart-1b242cbf-3f91-4818-a314-1f2ae16be86b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080562531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4080562531
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.597293560
Short name T870
Test name
Test status
Simulation time 664184402 ps
CPU time 4.28 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 04:59:23 PM PDT 24
Peak memory 233624 kb
Host smart-a3f94d54-ae19-4a3f-9454-ad38957c8f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597293560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.597293560
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1391422768
Short name T321
Test name
Test status
Simulation time 53347965 ps
CPU time 0.75 seconds
Started Jul 22 04:59:14 PM PDT 24
Finished Jul 22 04:59:15 PM PDT 24
Peak memory 207300 kb
Host smart-43e7243d-d372-4d62-b7f5-a27b3492d4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391422768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1391422768
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1713806315
Short name T15
Test name
Test status
Simulation time 20286977680 ps
CPU time 52.22 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 05:00:14 PM PDT 24
Peak memory 253248 kb
Host smart-1db29fb0-187e-422c-ba41-43b27463e841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713806315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1713806315
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1919529719
Short name T188
Test name
Test status
Simulation time 8089340087 ps
CPU time 51.22 seconds
Started Jul 22 04:59:21 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 250040 kb
Host smart-bdfff796-7f02-404c-8dac-4369caeff673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919529719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1919529719
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3343399494
Short name T216
Test name
Test status
Simulation time 1566005880 ps
CPU time 37.26 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:55 PM PDT 24
Peak memory 241856 kb
Host smart-ca4b6e7d-fe86-4989-86fc-26538bc76ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343399494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3343399494
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1757674392
Short name T286
Test name
Test status
Simulation time 540101945 ps
CPU time 14.93 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 240124 kb
Host smart-5e908bd1-2d14-4cc4-bfca-383b7fbba044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757674392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1757674392
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.504091758
Short name T544
Test name
Test status
Simulation time 16901574494 ps
CPU time 30.82 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 250032 kb
Host smart-fadac8ce-419a-4369-b820-d8cfa79ec147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504091758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.504091758
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1103125382
Short name T423
Test name
Test status
Simulation time 13752925023 ps
CPU time 30.16 seconds
Started Jul 22 05:01:35 PM PDT 24
Finished Jul 22 05:02:06 PM PDT 24
Peak memory 233644 kb
Host smart-c93ae4df-56c4-41f7-b129-6b1be1fb312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103125382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1103125382
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3130034946
Short name T743
Test name
Test status
Simulation time 101813299 ps
CPU time 3.47 seconds
Started Jul 22 05:03:26 PM PDT 24
Finished Jul 22 05:03:30 PM PDT 24
Peak memory 233632 kb
Host smart-02d20615-5c3b-47ce-a548-c213210823bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130034946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3130034946
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4071812403
Short name T194
Test name
Test status
Simulation time 22010471990 ps
CPU time 33.96 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:43 PM PDT 24
Peak memory 242376 kb
Host smart-47280166-1fdc-4b1b-9908-eb0713a25369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071812403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4071812403
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.771018732
Short name T873
Test name
Test status
Simulation time 10987666059 ps
CPU time 10.01 seconds
Started Jul 22 04:59:12 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 233568 kb
Host smart-495cd973-1e1f-4e9c-aa7c-b09b1e0c5e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771018732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.771018732
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4285115210
Short name T374
Test name
Test status
Simulation time 3891680945 ps
CPU time 25.77 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:43 PM PDT 24
Peak memory 219832 kb
Host smart-074baf2b-2c53-4962-84fe-faf9cb5c96b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4285115210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4285115210
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1103605600
Short name T427
Test name
Test status
Simulation time 5649311926 ps
CPU time 9.13 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 04:59:21 PM PDT 24
Peak memory 217120 kb
Host smart-451f111e-8858-40cc-a811-e475772f56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103605600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1103605600
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1341475662
Short name T983
Test name
Test status
Simulation time 20734966538 ps
CPU time 14.99 seconds
Started Jul 22 04:59:09 PM PDT 24
Finished Jul 22 04:59:25 PM PDT 24
Peak memory 218424 kb
Host smart-f2c94092-62ec-4fb3-9e96-45fed7e88363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341475662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1341475662
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3394185061
Short name T585
Test name
Test status
Simulation time 105973677 ps
CPU time 1.37 seconds
Started Jul 22 04:59:11 PM PDT 24
Finished Jul 22 04:59:12 PM PDT 24
Peak memory 217108 kb
Host smart-b8f3ae6f-d331-450e-8677-831e8fadf3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394185061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3394185061
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3908025229
Short name T339
Test name
Test status
Simulation time 88058332 ps
CPU time 0.99 seconds
Started Jul 22 04:59:12 PM PDT 24
Finished Jul 22 04:59:13 PM PDT 24
Peak memory 207724 kb
Host smart-255998e3-789d-4e2f-96c8-11486b65182b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908025229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3908025229
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.481247786
Short name T58
Test name
Test status
Simulation time 193285039 ps
CPU time 4.03 seconds
Started Jul 22 04:59:12 PM PDT 24
Finished Jul 22 04:59:16 PM PDT 24
Peak memory 225320 kb
Host smart-2b3414b6-02e6-4e66-8d56-5b1c65ccaf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481247786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.481247786
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.876172875
Short name T990
Test name
Test status
Simulation time 16022560 ps
CPU time 0.73 seconds
Started Jul 22 04:59:21 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 205500 kb
Host smart-9da55a32-a79b-4601-84fc-227b33c2cd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876172875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.876172875
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2770392490
Short name T1002
Test name
Test status
Simulation time 483730268 ps
CPU time 6.7 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 233328 kb
Host smart-ef033e63-eb4f-4ee7-b0a3-12748d846808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770392490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2770392490
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.720494229
Short name T505
Test name
Test status
Simulation time 15828539 ps
CPU time 0.75 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 206464 kb
Host smart-4dd123a4-60f8-4792-8e56-b574d5347a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720494229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.720494229
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2437230415
Short name T685
Test name
Test status
Simulation time 1812171999 ps
CPU time 23.03 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:41 PM PDT 24
Peak memory 225424 kb
Host smart-e3e96c54-ea4c-439d-a132-0cbf19aa5b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437230415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2437230415
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.754872742
Short name T618
Test name
Test status
Simulation time 77535575874 ps
CPU time 259.8 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 05:03:40 PM PDT 24
Peak memory 263920 kb
Host smart-6b68ee10-b215-49f7-8657-710efe64cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754872742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.754872742
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3577110624
Short name T655
Test name
Test status
Simulation time 104440371929 ps
CPU time 134.24 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 05:01:34 PM PDT 24
Peak memory 253940 kb
Host smart-376ae6b7-8a82-41b0-b2e7-496c55dfb02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577110624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3577110624
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2704178929
Short name T791
Test name
Test status
Simulation time 549520751 ps
CPU time 9.46 seconds
Started Jul 22 05:00:34 PM PDT 24
Finished Jul 22 05:00:44 PM PDT 24
Peak memory 237300 kb
Host smart-b975bcef-ced5-4953-bbd8-cd4d1cf1d639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704178929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2704178929
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2325903492
Short name T277
Test name
Test status
Simulation time 20172706095 ps
CPU time 125.79 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 05:01:27 PM PDT 24
Peak memory 255344 kb
Host smart-bb2c46ac-140c-4b70-bd59-9671138afb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325903492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2325903492
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.856770992
Short name T673
Test name
Test status
Simulation time 1287119142 ps
CPU time 4.04 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 233532 kb
Host smart-2bf5bf14-babd-4fc3-b8f0-96599c5a0786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856770992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.856770992
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1494304345
Short name T211
Test name
Test status
Simulation time 23386643536 ps
CPU time 33.58 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 04:59:54 PM PDT 24
Peak memory 240184 kb
Host smart-d0f79cd5-af83-4bce-b3cc-52334ed3b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494304345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1494304345
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.606691314
Short name T249
Test name
Test status
Simulation time 431616676 ps
CPU time 3.49 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 225360 kb
Host smart-275f5ffa-f5e4-4c3e-9b05-6a8aa5e404fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606691314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.606691314
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.499544475
Short name T232
Test name
Test status
Simulation time 13609090528 ps
CPU time 13.22 seconds
Started Jul 22 04:59:21 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 225168 kb
Host smart-04d44d28-5a6c-43dc-812a-cc5b47f414af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499544475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.499544475
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2463799872
Short name T560
Test name
Test status
Simulation time 806932038 ps
CPU time 11.17 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:29 PM PDT 24
Peak memory 223412 kb
Host smart-7c82b989-a9a3-486d-9dda-70998e781d46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2463799872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2463799872
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.127125799
Short name T796
Test name
Test status
Simulation time 2853060704 ps
CPU time 8.91 seconds
Started Jul 22 04:59:21 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 217312 kb
Host smart-bb26d3f9-7a83-41e4-ba23-e0e57eb474ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127125799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.127125799
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1658929445
Short name T28
Test name
Test status
Simulation time 3967284555 ps
CPU time 5.95 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 04:59:25 PM PDT 24
Peak memory 217192 kb
Host smart-4c44663e-c8c7-4d65-99bc-5cbcac069144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658929445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1658929445
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3761233548
Short name T676
Test name
Test status
Simulation time 317570011 ps
CPU time 2.95 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 217128 kb
Host smart-94e3648e-ee28-4087-8d4b-67744d9a1163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761233548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3761233548
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1964610784
Short name T634
Test name
Test status
Simulation time 146301545 ps
CPU time 0.84 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 04:59:19 PM PDT 24
Peak memory 207200 kb
Host smart-9127b3a1-1b3f-46b0-a806-0a31c2b1c61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964610784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1964610784
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1498783823
Short name T616
Test name
Test status
Simulation time 495405142 ps
CPU time 4.32 seconds
Started Jul 22 04:59:16 PM PDT 24
Finished Jul 22 04:59:21 PM PDT 24
Peak memory 225404 kb
Host smart-31e50333-bd39-4185-a3c7-ea95fca72b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498783823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1498783823
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1327181711
Short name T1021
Test name
Test status
Simulation time 37403199 ps
CPU time 0.73 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:27 PM PDT 24
Peak memory 205392 kb
Host smart-a7c738ec-fbea-4596-be49-eb74f2650ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327181711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1327181711
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2212467348
Short name T460
Test name
Test status
Simulation time 73498199 ps
CPU time 3.11 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:23 PM PDT 24
Peak memory 233640 kb
Host smart-753383c6-c84b-4de5-b6cd-3a4078d1ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212467348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2212467348
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1990870733
Short name T316
Test name
Test status
Simulation time 25071739 ps
CPU time 0.8 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:21 PM PDT 24
Peak memory 207532 kb
Host smart-99a72ba1-3c1e-43ad-a800-2cca6eedf1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990870733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1990870733
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2243027548
Short name T716
Test name
Test status
Simulation time 83214832539 ps
CPU time 156.01 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 05:01:56 PM PDT 24
Peak memory 254076 kb
Host smart-aa092056-da0a-4973-9f8f-183b2ff4c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243027548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2243027548
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1901770137
Short name T349
Test name
Test status
Simulation time 37680228815 ps
CPU time 325.7 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 05:04:53 PM PDT 24
Peak memory 266548 kb
Host smart-de3b085b-fa6a-45e6-b960-460509252d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901770137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1901770137
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1720605224
Short name T911
Test name
Test status
Simulation time 96304300 ps
CPU time 4.05 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:24 PM PDT 24
Peak memory 235724 kb
Host smart-a809e339-37f6-4b35-9d50-835af0227582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720605224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1720605224
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3515783766
Short name T171
Test name
Test status
Simulation time 69203621184 ps
CPU time 116.49 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 05:01:16 PM PDT 24
Peak memory 250112 kb
Host smart-5f5de7e9-cba3-4853-92ef-4561043989a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515783766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3515783766
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1935202327
Short name T400
Test name
Test status
Simulation time 716627063 ps
CPU time 3.81 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 04:59:23 PM PDT 24
Peak memory 233568 kb
Host smart-beb2c668-228b-487a-998f-4ad62a7eef82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935202327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1935202327
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.805659697
Short name T582
Test name
Test status
Simulation time 4667587145 ps
CPU time 24.63 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:44 PM PDT 24
Peak memory 241004 kb
Host smart-880693b5-30a0-481e-90b4-0ded708d327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805659697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.805659697
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.84332029
Short name T624
Test name
Test status
Simulation time 17223545915 ps
CPU time 13.08 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 233620 kb
Host smart-5acc5824-fa11-4cd3-ba64-2af428ea43c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84332029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.84332029
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.732851628
Short name T594
Test name
Test status
Simulation time 100360610 ps
CPU time 3.24 seconds
Started Jul 22 04:59:21 PM PDT 24
Finished Jul 22 04:59:25 PM PDT 24
Peak memory 233632 kb
Host smart-76b11f71-3e01-42af-adc3-fcd23b585c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732851628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.732851628
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1536818540
Short name T388
Test name
Test status
Simulation time 369433794 ps
CPU time 3.55 seconds
Started Jul 22 04:59:19 PM PDT 24
Finished Jul 22 04:59:24 PM PDT 24
Peak memory 219600 kb
Host smart-b295b195-ec59-4257-a867-6ed4600c6350
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1536818540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1536818540
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1506946796
Short name T30
Test name
Test status
Simulation time 36157335753 ps
CPU time 91.73 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 256148 kb
Host smart-343afe99-7abe-4c88-a6f7-1a9109937e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506946796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1506946796
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2581043667
Short name T730
Test name
Test status
Simulation time 43008494154 ps
CPU time 44.79 seconds
Started Jul 22 04:59:18 PM PDT 24
Finished Jul 22 05:00:03 PM PDT 24
Peak memory 217200 kb
Host smart-7d9601fb-e17f-420c-806a-0c9fbc908ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581043667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2581043667
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.620474354
Short name T512
Test name
Test status
Simulation time 1910243013 ps
CPU time 4.64 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 217124 kb
Host smart-f8532f6f-cbde-4c6b-ad57-555cc47d80e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620474354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.620474354
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4222757872
Short name T820
Test name
Test status
Simulation time 485098858 ps
CPU time 3.2 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 04:59:24 PM PDT 24
Peak memory 217116 kb
Host smart-0da60c3d-8a36-4fe1-8072-65cbb06a7b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222757872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4222757872
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2420960257
Short name T612
Test name
Test status
Simulation time 34928441 ps
CPU time 0.8 seconds
Started Jul 22 04:59:17 PM PDT 24
Finished Jul 22 04:59:19 PM PDT 24
Peak memory 206768 kb
Host smart-93271a3c-384e-49ab-abe0-a3adedea53dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420960257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2420960257
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2264298232
Short name T222
Test name
Test status
Simulation time 1947895515 ps
CPU time 10.85 seconds
Started Jul 22 04:59:20 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 225452 kb
Host smart-bd082e3d-fac5-4749-b7d0-0d40f4aa5fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264298232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2264298232
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3515561231
Short name T160
Test name
Test status
Simulation time 17048613 ps
CPU time 0.74 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 206348 kb
Host smart-a30f6782-8a6e-44fc-afdf-2f28b0198bf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515561231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3515561231
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.520571512
Short name T5
Test name
Test status
Simulation time 4387361029 ps
CPU time 10.57 seconds
Started Jul 22 04:59:25 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 225448 kb
Host smart-7ae1aaa2-5289-4f5d-85f2-bf05689b3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520571512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.520571512
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1019788515
Short name T591
Test name
Test status
Simulation time 18219281 ps
CPU time 0.77 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:19 PM PDT 24
Peak memory 206228 kb
Host smart-784c85d3-9773-4952-be09-4baedeff03a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019788515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1019788515
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3443889335
Short name T221
Test name
Test status
Simulation time 2517652764 ps
CPU time 17.18 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:44 PM PDT 24
Peak memory 233712 kb
Host smart-d86bbacc-0010-4aae-abcb-ccf9c3236a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443889335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3443889335
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1085613234
Short name T67
Test name
Test status
Simulation time 1847833946 ps
CPU time 45.85 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 05:00:14 PM PDT 24
Peak memory 250216 kb
Host smart-511e8d86-7789-4abf-a6a7-1be93086a604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085613234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1085613234
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3135049155
Short name T199
Test name
Test status
Simulation time 7427459068 ps
CPU time 111.61 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 05:01:20 PM PDT 24
Peak memory 266012 kb
Host smart-d06814d2-4f2b-422d-9309-3e51cac9a208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135049155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3135049155
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.359653711
Short name T897
Test name
Test status
Simulation time 602043996 ps
CPU time 0.96 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 04:59:29 PM PDT 24
Peak memory 216896 kb
Host smart-c07bc788-11ff-4ffb-8f67-17ce3340f384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359653711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.359653711
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3424601300
Short name T1007
Test name
Test status
Simulation time 1468985422 ps
CPU time 6.77 seconds
Started Jul 22 05:03:02 PM PDT 24
Finished Jul 22 05:03:09 PM PDT 24
Peak memory 225368 kb
Host smart-9ffa54dd-2e69-4a29-998c-bf3faa503ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424601300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3424601300
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.70747484
Short name T904
Test name
Test status
Simulation time 488504654 ps
CPU time 6.34 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:33 PM PDT 24
Peak memory 225420 kb
Host smart-a4fe0e1a-84b6-4295-865d-5741ec89033b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70747484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.70747484
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3495836171
Short name T590
Test name
Test status
Simulation time 471826535 ps
CPU time 5.23 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:34 PM PDT 24
Peak memory 225392 kb
Host smart-a90a964d-612e-44a3-ad18-0293087e98f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495836171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3495836171
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1807020706
Short name T217
Test name
Test status
Simulation time 195488196 ps
CPU time 5.59 seconds
Started Jul 22 04:59:25 PM PDT 24
Finished Jul 22 04:59:31 PM PDT 24
Peak memory 233528 kb
Host smart-0751ca7d-a578-4170-8801-d40e3e6ab1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807020706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1807020706
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1894802893
Short name T384
Test name
Test status
Simulation time 98059133 ps
CPU time 3.57 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:33 PM PDT 24
Peak memory 224028 kb
Host smart-feab4e97-6d1d-4271-b6cd-b8ef43000ef3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1894802893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1894802893
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3671190562
Short name T149
Test name
Test status
Simulation time 89279336307 ps
CPU time 124.81 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 05:01:33 PM PDT 24
Peak memory 254060 kb
Host smart-2c25be81-88ee-4d40-bbcb-dc1107d9cccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671190562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3671190562
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1591156582
Short name T690
Test name
Test status
Simulation time 8076532201 ps
CPU time 42.16 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 05:00:11 PM PDT 24
Peak memory 217216 kb
Host smart-bd895c95-606b-489b-ab76-9bf102b4a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591156582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1591156582
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.901840197
Short name T635
Test name
Test status
Simulation time 28029996958 ps
CPU time 13.83 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:41 PM PDT 24
Peak memory 218536 kb
Host smart-d3c5a54f-0a8b-4b5b-9fcb-bd548aef05fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901840197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.901840197
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3561388056
Short name T455
Test name
Test status
Simulation time 59442238 ps
CPU time 1.02 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 207752 kb
Host smart-e554ae67-18e9-4225-9595-2961d521a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561388056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3561388056
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4204812826
Short name T811
Test name
Test status
Simulation time 62731429 ps
CPU time 0.73 seconds
Started Jul 22 04:59:27 PM PDT 24
Finished Jul 22 04:59:29 PM PDT 24
Peak memory 206668 kb
Host smart-2c4771d5-a9a8-4b1a-8aec-7c8f88ea1c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204812826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4204812826
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4171975002
Short name T259
Test name
Test status
Simulation time 6652939146 ps
CPU time 8.93 seconds
Started Jul 22 05:03:02 PM PDT 24
Finished Jul 22 05:03:12 PM PDT 24
Peak memory 233624 kb
Host smart-d1df9f72-4c69-4cb6-a892-478eda1653f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171975002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4171975002
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2689241325
Short name T792
Test name
Test status
Simulation time 14328902 ps
CPU time 0.73 seconds
Started Jul 22 04:59:38 PM PDT 24
Finished Jul 22 04:59:39 PM PDT 24
Peak memory 206384 kb
Host smart-a33182bb-4f9e-4e08-9c7d-2f61fc2c6306
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689241325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2689241325
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2357267576
Short name T86
Test name
Test status
Simulation time 84845049 ps
CPU time 3.18 seconds
Started Jul 22 04:59:39 PM PDT 24
Finished Jul 22 04:59:43 PM PDT 24
Peak memory 225348 kb
Host smart-86176f21-509e-4a25-ab9c-d51512e86975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357267576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2357267576
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1072170964
Short name T961
Test name
Test status
Simulation time 33998962 ps
CPU time 0.76 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:30 PM PDT 24
Peak memory 206228 kb
Host smart-dd0b4836-6365-48f7-93e2-44e71ae76992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072170964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1072170964
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.370979497
Short name T360
Test name
Test status
Simulation time 2130359533 ps
CPU time 27.67 seconds
Started Jul 22 04:59:39 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 238816 kb
Host smart-11a0e7cf-e243-4a02-a15d-bcbdfe5efc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370979497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.370979497
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2763001917
Short name T889
Test name
Test status
Simulation time 47703674265 ps
CPU time 226.45 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 05:03:22 PM PDT 24
Peak memory 267908 kb
Host smart-353e3c47-d839-4b2c-8007-5f3e55acec3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763001917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2763001917
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3640453679
Short name T278
Test name
Test status
Simulation time 187519300164 ps
CPU time 431.79 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 05:06:47 PM PDT 24
Peak memory 256860 kb
Host smart-093e56b8-f3d1-4198-9472-e0d40070ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640453679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3640453679
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3343740500
Short name T550
Test name
Test status
Simulation time 306576032 ps
CPU time 2.56 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:37 PM PDT 24
Peak memory 225424 kb
Host smart-1a9a29d0-4d65-422e-97c3-8ba36307375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343740500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3343740500
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.380072313
Short name T997
Test name
Test status
Simulation time 34833909039 ps
CPU time 103.65 seconds
Started Jul 22 04:59:33 PM PDT 24
Finished Jul 22 05:01:17 PM PDT 24
Peak memory 251240 kb
Host smart-2b846352-7e37-4675-a36b-556a4c3fc1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380072313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.380072313
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.9301500
Short name T633
Test name
Test status
Simulation time 1981241708 ps
CPU time 5.71 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:23 PM PDT 24
Peak memory 233500 kb
Host smart-a7b58a47-1324-4775-a297-5e75cbd6af9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9301500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.9301500
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2603386668
Short name T521
Test name
Test status
Simulation time 3994614101 ps
CPU time 6.75 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 233728 kb
Host smart-8be33743-22d0-4887-b39c-1e0500e0adb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603386668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2603386668
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.333660381
Short name T672
Test name
Test status
Simulation time 333908955 ps
CPU time 3.1 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:21 PM PDT 24
Peak memory 233628 kb
Host smart-9bf71ac6-141c-4c42-9719-173c44bdba17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333660381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.333660381
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2061707417
Short name T75
Test name
Test status
Simulation time 5621937188 ps
CPU time 10.89 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:40 PM PDT 24
Peak memory 225504 kb
Host smart-8ecebbf1-fe6b-4c6b-907c-3adda122437c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061707417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2061707417
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1894797124
Short name T430
Test name
Test status
Simulation time 12757581225 ps
CPU time 9.98 seconds
Started Jul 22 04:59:39 PM PDT 24
Finished Jul 22 04:59:50 PM PDT 24
Peak memory 221268 kb
Host smart-36f78c27-a540-4bc8-840a-c84d4d8dbb79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1894797124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1894797124
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.662597376
Short name T760
Test name
Test status
Simulation time 3999460517 ps
CPU time 73.7 seconds
Started Jul 22 04:59:39 PM PDT 24
Finished Jul 22 05:00:53 PM PDT 24
Peak memory 256580 kb
Host smart-013a837a-6b63-4e8f-a100-92229533154b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662597376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.662597376
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.569500281
Short name T967
Test name
Test status
Simulation time 459969646 ps
CPU time 6.25 seconds
Started Jul 22 04:59:25 PM PDT 24
Finished Jul 22 04:59:32 PM PDT 24
Peak memory 217248 kb
Host smart-20fcb800-b6e3-4306-aeec-fdfc294abf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569500281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.569500281
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.545714400
Short name T936
Test name
Test status
Simulation time 1584289380 ps
CPU time 3.1 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:29 PM PDT 24
Peak memory 217160 kb
Host smart-0c11aacc-9702-4ef5-a0ed-de7400ba11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545714400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.545714400
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3273420101
Short name T45
Test name
Test status
Simulation time 226899705 ps
CPU time 4.56 seconds
Started Jul 22 04:59:28 PM PDT 24
Finished Jul 22 04:59:33 PM PDT 24
Peak memory 217096 kb
Host smart-57a833b9-18b2-47f8-9fd0-dc1233e00696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273420101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3273420101
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1677794123
Short name T1
Test name
Test status
Simulation time 12046321 ps
CPU time 0.68 seconds
Started Jul 22 04:59:26 PM PDT 24
Finished Jul 22 04:59:28 PM PDT 24
Peak memory 206216 kb
Host smart-d14fc8cf-8e83-4224-b1b0-94b459c4fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677794123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1677794123
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1973907037
Short name T739
Test name
Test status
Simulation time 76161597 ps
CPU time 2.4 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 04:59:38 PM PDT 24
Peak memory 225028 kb
Host smart-7a4a718b-854e-4d88-8b96-ef1fbec5d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973907037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1973907037
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4020125244
Short name T785
Test name
Test status
Simulation time 15153512 ps
CPU time 0.73 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 206056 kb
Host smart-f753ed6f-0f7c-4fcd-b9b8-cde051f254ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020125244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4020125244
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1812243273
Short name T915
Test name
Test status
Simulation time 1381791211 ps
CPU time 5.74 seconds
Started Jul 22 05:02:45 PM PDT 24
Finished Jul 22 05:02:51 PM PDT 24
Peak memory 225400 kb
Host smart-e9f61491-3a81-4708-8318-cb60659f69c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812243273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1812243273
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2319866570
Short name T569
Test name
Test status
Simulation time 31446263 ps
CPU time 0.71 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 206172 kb
Host smart-6e3e36c7-3a24-4319-bd74-ab85c566754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319866570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2319866570
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1156085884
Short name T510
Test name
Test status
Simulation time 94054330148 ps
CPU time 284.29 seconds
Started Jul 22 04:59:37 PM PDT 24
Finished Jul 22 05:04:22 PM PDT 24
Peak memory 266828 kb
Host smart-bda13b86-0abd-404d-a44e-e829e9921f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156085884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1156085884
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4167010969
Short name T73
Test name
Test status
Simulation time 75279783099 ps
CPU time 250.24 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 05:03:57 PM PDT 24
Peak memory 258228 kb
Host smart-684cac68-685b-46a2-a114-0909c0e91df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167010969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4167010969
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3744581272
Short name T875
Test name
Test status
Simulation time 194768395 ps
CPU time 4.23 seconds
Started Jul 22 04:59:36 PM PDT 24
Finished Jul 22 04:59:41 PM PDT 24
Peak memory 225660 kb
Host smart-bd825895-5066-4c73-90ba-3b6aa024f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744581272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3744581272
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3831432802
Short name T955
Test name
Test status
Simulation time 10607838177 ps
CPU time 57.54 seconds
Started Jul 22 04:59:38 PM PDT 24
Finished Jul 22 05:00:36 PM PDT 24
Peak memory 251124 kb
Host smart-68feb803-aaea-4489-a6cc-95956aa96442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831432802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3831432802
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1729891592
Short name T637
Test name
Test status
Simulation time 540723677 ps
CPU time 6.26 seconds
Started Jul 22 04:59:40 PM PDT 24
Finished Jul 22 04:59:46 PM PDT 24
Peak memory 225348 kb
Host smart-4bac5dae-9e3a-42e9-ab27-d2d5e940a9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729891592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1729891592
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.4135259663
Short name T92
Test name
Test status
Simulation time 11472618621 ps
CPU time 49.99 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 05:00:24 PM PDT 24
Peak memory 233680 kb
Host smart-a7ead212-91fb-43bd-9b71-0b3f54e77572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135259663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.4135259663
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1330064953
Short name T308
Test name
Test status
Simulation time 107112800 ps
CPU time 2.25 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:37 PM PDT 24
Peak memory 224600 kb
Host smart-ce4d03cc-637a-4120-a96a-554c549e9eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330064953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1330064953
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3210677440
Short name T240
Test name
Test status
Simulation time 1537212591 ps
CPU time 6.25 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:24 PM PDT 24
Peak memory 233612 kb
Host smart-074039b5-828e-45fe-8d4e-0388973be506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210677440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3210677440
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3010622714
Short name T136
Test name
Test status
Simulation time 2701699627 ps
CPU time 13.93 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 04:59:50 PM PDT 24
Peak memory 223884 kb
Host smart-cd2e4c3e-26bc-4507-bd8d-87e968a47063
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3010622714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3010622714
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.560917569
Short name T154
Test name
Test status
Simulation time 104665731151 ps
CPU time 956.01 seconds
Started Jul 22 05:01:00 PM PDT 24
Finished Jul 22 05:16:57 PM PDT 24
Peak memory 273788 kb
Host smart-9e59bcdb-a14e-4de8-bb70-7165472ea690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560917569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.560917569
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3174363483
Short name T780
Test name
Test status
Simulation time 1117319740 ps
CPU time 5.03 seconds
Started Jul 22 04:59:33 PM PDT 24
Finished Jul 22 04:59:39 PM PDT 24
Peak memory 217092 kb
Host smart-a9b775a6-8cad-47be-9724-e76ff4a51c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174363483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3174363483
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1387676544
Short name T405
Test name
Test status
Simulation time 698059937 ps
CPU time 8.3 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 04:59:44 PM PDT 24
Peak memory 217084 kb
Host smart-849293fa-8d91-4f95-be01-283bb5281530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387676544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1387676544
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3772284087
Short name T860
Test name
Test status
Simulation time 110730315 ps
CPU time 0.87 seconds
Started Jul 22 04:59:42 PM PDT 24
Finished Jul 22 04:59:43 PM PDT 24
Peak memory 206688 kb
Host smart-72cc732b-c06d-4369-918a-e201305e2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772284087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3772284087
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2510805962
Short name T809
Test name
Test status
Simulation time 2709512229 ps
CPU time 10.8 seconds
Started Jul 22 04:59:38 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 233712 kb
Host smart-7a00300b-40ac-42eb-9e67-5bca95f2839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510805962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2510805962
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.263547030
Short name T838
Test name
Test status
Simulation time 42989719 ps
CPU time 0.79 seconds
Started Jul 22 04:59:44 PM PDT 24
Finished Jul 22 04:59:45 PM PDT 24
Peak memory 205452 kb
Host smart-de93ad37-d4ad-46ed-b50a-20ab1e5971bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263547030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.263547030
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1123903839
Short name T868
Test name
Test status
Simulation time 218362033 ps
CPU time 2.69 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 225404 kb
Host smart-7811455a-ea73-48f0-87eb-28da60dac96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123903839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1123903839
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2467963812
Short name T337
Test name
Test status
Simulation time 56958604 ps
CPU time 0.72 seconds
Started Jul 22 04:59:44 PM PDT 24
Finished Jul 22 04:59:45 PM PDT 24
Peak memory 206220 kb
Host smart-e71727f4-fd95-4511-b178-d61a49046522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467963812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2467963812
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2175755286
Short name T944
Test name
Test status
Simulation time 3092168731 ps
CPU time 52.74 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 251796 kb
Host smart-b2e73115-9062-4890-b772-c7757b5f7edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175755286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2175755286
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3433840367
Short name T279
Test name
Test status
Simulation time 16711433059 ps
CPU time 186.69 seconds
Started Jul 22 04:59:47 PM PDT 24
Finished Jul 22 05:02:54 PM PDT 24
Peak memory 257016 kb
Host smart-4e1011dd-68fa-4577-8dd4-56d3864fc239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433840367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3433840367
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2915240778
Short name T642
Test name
Test status
Simulation time 6027788315 ps
CPU time 24.65 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 05:00:11 PM PDT 24
Peak memory 225516 kb
Host smart-9a852362-a7f4-4296-88f7-265797871052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915240778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2915240778
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1092718115
Short name T948
Test name
Test status
Simulation time 133754789406 ps
CPU time 217.02 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 05:03:22 PM PDT 24
Peak memory 258188 kb
Host smart-97d2c552-5be9-4ed4-ad8b-ab036c793e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092718115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1092718115
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2957522038
Short name T206
Test name
Test status
Simulation time 1803611360 ps
CPU time 5.35 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 04:59:52 PM PDT 24
Peak memory 225424 kb
Host smart-95359358-db9a-4e73-91c7-f55db65c01cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957522038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2957522038
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2816380163
Short name T253
Test name
Test status
Simulation time 2724173772 ps
CPU time 23.43 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 05:00:09 PM PDT 24
Peak memory 225484 kb
Host smart-48b58983-1d3d-45b0-b7a0-40f458825bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816380163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2816380163
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4235325463
Short name T359
Test name
Test status
Simulation time 759385048 ps
CPU time 4.35 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 04:59:51 PM PDT 24
Peak memory 233504 kb
Host smart-fe38d5d3-4a86-4488-8f4d-9b863cb8fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235325463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4235325463
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2861025338
Short name T243
Test name
Test status
Simulation time 3503540710 ps
CPU time 8.97 seconds
Started Jul 22 04:59:44 PM PDT 24
Finished Jul 22 04:59:54 PM PDT 24
Peak memory 233572 kb
Host smart-069c708a-abdc-4752-8ef8-08a0f39e7212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861025338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2861025338
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.42797364
Short name T39
Test name
Test status
Simulation time 208130225 ps
CPU time 4.33 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 04:59:51 PM PDT 24
Peak memory 223908 kb
Host smart-944ee1fb-531d-41f0-976d-dbd8d6026c23
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42797364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.42797364
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.736434425
Short name T517
Test name
Test status
Simulation time 5006040595 ps
CPU time 26.83 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 217212 kb
Host smart-dd0f17da-f148-4817-90d1-d7924218c82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736434425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.736434425
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1844144318
Short name T906
Test name
Test status
Simulation time 2086371175 ps
CPU time 6.06 seconds
Started Jul 22 04:59:46 PM PDT 24
Finished Jul 22 04:59:53 PM PDT 24
Peak memory 217044 kb
Host smart-249f6a9a-f47f-435d-a6ec-f34c6fb1582f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844144318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1844144318
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1551594388
Short name T766
Test name
Test status
Simulation time 202822667 ps
CPU time 2.64 seconds
Started Jul 22 04:59:45 PM PDT 24
Finished Jul 22 04:59:48 PM PDT 24
Peak memory 217132 kb
Host smart-a1d5618c-d877-4148-a88c-38572b7a73bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551594388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1551594388
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1311784597
Short name T317
Test name
Test status
Simulation time 71986635 ps
CPU time 0.82 seconds
Started Jul 22 05:02:44 PM PDT 24
Finished Jul 22 05:02:46 PM PDT 24
Peak memory 206764 kb
Host smart-f53dd8bb-2ffa-4c5f-bc6e-b43864b7b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311784597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1311784597
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2051594782
Short name T1022
Test name
Test status
Simulation time 393258460 ps
CPU time 2.35 seconds
Started Jul 22 04:59:47 PM PDT 24
Finished Jul 22 04:59:50 PM PDT 24
Peak memory 224912 kb
Host smart-b3d00957-4353-41e6-9302-675b1376b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051594782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2051594782
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2800063340
Short name T847
Test name
Test status
Simulation time 16144377 ps
CPU time 0.73 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 04:59:56 PM PDT 24
Peak memory 206036 kb
Host smart-25c8a9cc-1dee-4775-b292-9cc2c815b2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800063340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2800063340
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1825368989
Short name T996
Test name
Test status
Simulation time 500103457 ps
CPU time 7.06 seconds
Started Jul 22 04:59:53 PM PDT 24
Finished Jul 22 05:00:01 PM PDT 24
Peak memory 233476 kb
Host smart-f219564f-b64f-4e2d-ac55-780d06b8dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825368989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1825368989
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2431809602
Short name T499
Test name
Test status
Simulation time 49230811 ps
CPU time 0.76 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 207256 kb
Host smart-82d79a55-bfc3-47e4-80d0-78285fa7e9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431809602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2431809602
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1478002255
Short name T540
Test name
Test status
Simulation time 1051612880 ps
CPU time 12.65 seconds
Started Jul 22 05:03:04 PM PDT 24
Finished Jul 22 05:03:17 PM PDT 24
Peak memory 233936 kb
Host smart-380d1f32-505e-4f0b-8e65-112570e4ce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478002255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1478002255
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2322382293
Short name T193
Test name
Test status
Simulation time 11755512564 ps
CPU time 74.05 seconds
Started Jul 22 05:03:04 PM PDT 24
Finished Jul 22 05:04:19 PM PDT 24
Peak memory 225452 kb
Host smart-c49f5afb-6155-4348-ae18-a69f89b79490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322382293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2322382293
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2844223992
Short name T464
Test name
Test status
Simulation time 29844684114 ps
CPU time 170.27 seconds
Started Jul 22 04:59:56 PM PDT 24
Finished Jul 22 05:02:47 PM PDT 24
Peak memory 250552 kb
Host smart-df7cb77f-7d5e-4a76-af55-d7bfbb1c9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844223992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2844223992
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1715602853
Short name T141
Test name
Test status
Simulation time 14008350180 ps
CPU time 56.14 seconds
Started Jul 22 04:59:53 PM PDT 24
Finished Jul 22 05:00:49 PM PDT 24
Peak memory 233656 kb
Host smart-51ef8bbb-d1a9-4903-89a7-d13e9a41ba1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715602853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1715602853
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2956044889
Short name T181
Test name
Test status
Simulation time 8183368928 ps
CPU time 45.79 seconds
Started Jul 22 04:59:53 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 254940 kb
Host smart-3026aa4e-e76f-4399-b86d-485e25c9c944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956044889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2956044889
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.433088685
Short name T617
Test name
Test status
Simulation time 120655146 ps
CPU time 3.42 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 04:59:58 PM PDT 24
Peak memory 233548 kb
Host smart-41b12965-788b-493e-b150-805b3eb1b9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433088685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.433088685
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2320309415
Short name T497
Test name
Test status
Simulation time 29953090092 ps
CPU time 138.28 seconds
Started Jul 22 05:03:02 PM PDT 24
Finished Jul 22 05:05:21 PM PDT 24
Peak memory 236092 kb
Host smart-967f95af-9fba-4061-9323-4dde3819f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320309415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2320309415
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3017343088
Short name T389
Test name
Test status
Simulation time 30471455360 ps
CPU time 15.28 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:11 PM PDT 24
Peak memory 233652 kb
Host smart-b7f25395-1611-4839-b5bb-4cd516743608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017343088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3017343088
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.477936892
Short name T740
Test name
Test status
Simulation time 12847530156 ps
CPU time 22 seconds
Started Jul 22 05:02:42 PM PDT 24
Finished Jul 22 05:03:05 PM PDT 24
Peak memory 241256 kb
Host smart-dc853c9a-3007-4bf1-8015-fbeae591ce21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477936892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.477936892
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2536361130
Short name T592
Test name
Test status
Simulation time 8104243783 ps
CPU time 17.42 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 219684 kb
Host smart-4c7c9f9f-0007-49bc-ad3e-b83105b2be77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536361130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2536361130
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.653983404
Short name T979
Test name
Test status
Simulation time 226424134419 ps
CPU time 271.73 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 05:04:27 PM PDT 24
Peak memory 252392 kb
Host smart-d964821e-631b-43e6-83af-756ab6c78112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653983404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.653983404
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3246861037
Short name T357
Test name
Test status
Simulation time 4039326015 ps
CPU time 14.09 seconds
Started Jul 22 04:59:43 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 217580 kb
Host smart-66c9f4a7-09a3-484f-8356-5f9b38786cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246861037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3246861037
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2158776921
Short name T580
Test name
Test status
Simulation time 5333205742 ps
CPU time 7.44 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:03 PM PDT 24
Peak memory 217124 kb
Host smart-c7cd6b71-2d32-4006-84ab-6ddda358125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158776921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2158776921
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.201471598
Short name T696
Test name
Test status
Simulation time 47992445 ps
CPU time 1.06 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 207968 kb
Host smart-07969da1-0fbe-4cf1-b0db-c8551d404a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201471598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.201471598
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1358520575
Short name T364
Test name
Test status
Simulation time 310509488 ps
CPU time 0.93 seconds
Started Jul 22 04:59:58 PM PDT 24
Finished Jul 22 04:59:59 PM PDT 24
Peak memory 207116 kb
Host smart-d284e0e7-ebb7-44df-9a8d-b60a69aecce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358520575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1358520575
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2682840553
Short name T495
Test name
Test status
Simulation time 1065651698 ps
CPU time 8.4 seconds
Started Jul 22 04:59:57 PM PDT 24
Finished Jul 22 05:00:06 PM PDT 24
Peak memory 225456 kb
Host smart-79dd6858-b3b0-4288-a550-3ba9a274780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682840553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2682840553
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2537800958
Short name T314
Test name
Test status
Simulation time 16505406 ps
CPU time 0.74 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:34 PM PDT 24
Peak memory 205488 kb
Host smart-3cccc848-87be-4b36-b144-9542a5be3fb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537800958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
537800958
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1856993676
Short name T506
Test name
Test status
Simulation time 32565959 ps
CPU time 2.48 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:25 PM PDT 24
Peak memory 233240 kb
Host smart-11529ac7-7b1b-4ded-bb26-2702d642a87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856993676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1856993676
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4155744334
Short name T552
Test name
Test status
Simulation time 21076910 ps
CPU time 0.83 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 04:57:25 PM PDT 24
Peak memory 207240 kb
Host smart-b5a9b674-85fe-434c-9ff0-fd51c5322ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155744334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4155744334
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1784757372
Short name T757
Test name
Test status
Simulation time 1723852846 ps
CPU time 23.58 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:46 PM PDT 24
Peak memory 250000 kb
Host smart-b0f6c2ca-fe27-4f83-b14f-46f3562dae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784757372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1784757372
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1611487617
Short name T954
Test name
Test status
Simulation time 33301325964 ps
CPU time 48.3 seconds
Started Jul 22 04:57:32 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 241656 kb
Host smart-27d76722-42aa-42ef-8bde-2e7184ec3f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611487617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1611487617
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1590230218
Short name T543
Test name
Test status
Simulation time 7732585113 ps
CPU time 67.07 seconds
Started Jul 22 04:57:37 PM PDT 24
Finished Jul 22 04:58:44 PM PDT 24
Peak memory 239680 kb
Host smart-260b9e8b-6dd5-475c-a61d-525d3ebe23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590230218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1590230218
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.555953344
Short name T440
Test name
Test status
Simulation time 54434602941 ps
CPU time 102.44 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:59:04 PM PDT 24
Peak memory 250328 kb
Host smart-0f3a4655-ffc9-4918-84ca-6584f278e623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555953344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
555953344
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2936533840
Short name T462
Test name
Test status
Simulation time 1540009873 ps
CPU time 13.24 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 04:57:37 PM PDT 24
Peak memory 233508 kb
Host smart-b697e0e5-29dc-46c2-97ae-c9c6171dc1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936533840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2936533840
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1395642125
Short name T683
Test name
Test status
Simulation time 2485418193 ps
CPU time 19.51 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 04:57:43 PM PDT 24
Peak memory 225452 kb
Host smart-488542d6-e275-4cf2-83c2-90ea35fe3156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395642125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1395642125
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.821072910
Short name T668
Test name
Test status
Simulation time 31876795 ps
CPU time 1.07 seconds
Started Jul 22 04:57:29 PM PDT 24
Finished Jul 22 04:57:30 PM PDT 24
Peak memory 217400 kb
Host smart-5afb8df6-d9eb-413f-a0ac-00cb82e17fab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821072910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.821072910
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3476658371
Short name T577
Test name
Test status
Simulation time 2434295165 ps
CPU time 6.24 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:29 PM PDT 24
Peak memory 241704 kb
Host smart-9d14c952-a00a-4de0-88e1-266caa5a5af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476658371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3476658371
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1668325219
Short name T709
Test name
Test status
Simulation time 834638105 ps
CPU time 2.95 seconds
Started Jul 22 04:57:25 PM PDT 24
Finished Jul 22 04:57:29 PM PDT 24
Peak memory 225392 kb
Host smart-22dba451-1654-470a-9b04-84898b9fa3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668325219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1668325219
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3862845087
Short name T652
Test name
Test status
Simulation time 2035194991 ps
CPU time 26.8 seconds
Started Jul 22 04:57:25 PM PDT 24
Finished Jul 22 04:57:53 PM PDT 24
Peak memory 221084 kb
Host smart-094624c7-9bae-4718-994c-1379fb7137c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3862845087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3862845087
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3459680113
Short name T64
Test name
Test status
Simulation time 65690752 ps
CPU time 1.1 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:37 PM PDT 24
Peak memory 236336 kb
Host smart-df36f589-c9a0-469b-a567-c769d40f6678
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459680113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3459680113
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3900673695
Short name T257
Test name
Test status
Simulation time 35833790582 ps
CPU time 322.3 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:08:41 PM PDT 24
Peak memory 250044 kb
Host smart-822fa280-19fc-4175-8502-fbd5a76aab86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900673695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3900673695
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.271125692
Short name T541
Test name
Test status
Simulation time 8278407771 ps
CPU time 19.71 seconds
Started Jul 22 04:57:22 PM PDT 24
Finished Jul 22 04:57:42 PM PDT 24
Peak memory 217120 kb
Host smart-2fbfc775-2b6d-40bd-8d7a-f9c20464c3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271125692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.271125692
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1061517530
Short name T570
Test name
Test status
Simulation time 1677932028 ps
CPU time 9.29 seconds
Started Jul 22 04:59:35 PM PDT 24
Finished Jul 22 04:59:45 PM PDT 24
Peak memory 217104 kb
Host smart-ead2d5b2-8110-47c8-93d8-097bfa587108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061517530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1061517530
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2047371567
Short name T413
Test name
Test status
Simulation time 147912294 ps
CPU time 1.08 seconds
Started Jul 22 04:57:24 PM PDT 24
Finished Jul 22 04:57:25 PM PDT 24
Peak memory 208636 kb
Host smart-8d4d057b-5805-4f42-98ff-ce8d2ab5dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047371567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2047371567
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1331254513
Short name T959
Test name
Test status
Simulation time 282324444 ps
CPU time 0.86 seconds
Started Jul 22 04:57:21 PM PDT 24
Finished Jul 22 04:57:22 PM PDT 24
Peak memory 206716 kb
Host smart-d69d6e0a-c971-49b5-843a-196b0a2a898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331254513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1331254513
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3750981600
Short name T539
Test name
Test status
Simulation time 18819002776 ps
CPU time 16.12 seconds
Started Jul 22 04:57:23 PM PDT 24
Finished Jul 22 04:57:40 PM PDT 24
Peak memory 233692 kb
Host smart-a8d9ec3a-bf8a-4ea6-b772-71acf090185e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750981600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3750981600
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4244239753
Short name T1009
Test name
Test status
Simulation time 15346131 ps
CPU time 0.72 seconds
Started Jul 22 05:00:03 PM PDT 24
Finished Jul 22 05:00:04 PM PDT 24
Peak memory 205916 kb
Host smart-a252f297-f9b8-4a94-abae-d4892dae3971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244239753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4244239753
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2634643814
Short name T85
Test name
Test status
Simulation time 688231989 ps
CPU time 2.99 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 04:59:58 PM PDT 24
Peak memory 233648 kb
Host smart-d23f65a6-6be2-465d-a49a-6712d8e432bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634643814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2634643814
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3325525645
Short name T576
Test name
Test status
Simulation time 16503488 ps
CPU time 0.79 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 207240 kb
Host smart-e22fbf7e-28f1-426e-8ed7-6b0ff0899226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325525645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3325525645
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.4051825113
Short name T862
Test name
Test status
Simulation time 6265544505 ps
CPU time 59.58 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 05:00:54 PM PDT 24
Peak memory 256568 kb
Host smart-e8f09103-9a39-46db-8c72-7be7c68126d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051825113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.4051825113
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3629896523
Short name T157
Test name
Test status
Simulation time 3668328905 ps
CPU time 69.95 seconds
Started Jul 22 04:59:53 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 250060 kb
Host smart-60b9c179-9a9b-42de-b990-b0664ef6711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629896523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3629896523
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.4091220905
Short name T210
Test name
Test status
Simulation time 2103298577 ps
CPU time 36.88 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:33 PM PDT 24
Peak memory 254520 kb
Host smart-8fc392db-3889-43ca-b8da-ea6b2c6c80ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091220905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.4091220905
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3393841144
Short name T965
Test name
Test status
Simulation time 2122764001 ps
CPU time 30.3 seconds
Started Jul 22 05:02:45 PM PDT 24
Finished Jul 22 05:03:16 PM PDT 24
Peak memory 225420 kb
Host smart-9eafe2bb-4538-411b-a6cc-c41d74915841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393841144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3393841144
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3355133005
Short name T215
Test name
Test status
Simulation time 835957892 ps
CPU time 7.46 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:03 PM PDT 24
Peak memory 225368 kb
Host smart-13906912-74d8-4dd1-b0d4-cab23bb9275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355133005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3355133005
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1971372611
Short name T596
Test name
Test status
Simulation time 842726239 ps
CPU time 6.43 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:03 PM PDT 24
Peak memory 241512 kb
Host smart-0d6d5a62-e026-4220-9588-b0d49c3ba882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971372611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1971372611
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.939810877
Short name T974
Test name
Test status
Simulation time 1532187813 ps
CPU time 4.71 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 05:00:00 PM PDT 24
Peak memory 225452 kb
Host smart-ef4956a9-8a11-4458-a510-2a0fafe74b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939810877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.939810877
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3733726586
Short name T419
Test name
Test status
Simulation time 1726263597 ps
CPU time 9.07 seconds
Started Jul 22 04:59:57 PM PDT 24
Finished Jul 22 05:00:06 PM PDT 24
Peak memory 241444 kb
Host smart-f84acef5-7244-4792-895a-9e3dc5739aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733726586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3733726586
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2104956467
Short name T11
Test name
Test status
Simulation time 6546716066 ps
CPU time 15.07 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 05:00:11 PM PDT 24
Peak memory 220120 kb
Host smart-9c75d06a-a765-42d1-9c0d-43bb9914f313
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2104956467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2104956467
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3964040281
Short name T165
Test name
Test status
Simulation time 10203782711 ps
CPU time 158.24 seconds
Started Jul 22 04:59:57 PM PDT 24
Finished Jul 22 05:02:35 PM PDT 24
Peak memory 266868 kb
Host smart-fb24a235-3fd1-46ca-819a-9e2de1a34a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964040281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3964040281
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3130302327
Short name T787
Test name
Test status
Simulation time 11153405402 ps
CPU time 23.93 seconds
Started Jul 22 04:59:57 PM PDT 24
Finished Jul 22 05:00:22 PM PDT 24
Peak memory 217260 kb
Host smart-b7ce252a-7a36-42d1-808c-e64a2996425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130302327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3130302327
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1198199295
Short name T806
Test name
Test status
Simulation time 37882610 ps
CPU time 0.73 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 04:59:56 PM PDT 24
Peak memory 206268 kb
Host smart-1ef93366-6497-494f-b104-edeb5a427b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198199295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1198199295
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2662669656
Short name T793
Test name
Test status
Simulation time 587832289 ps
CPU time 2.47 seconds
Started Jul 22 04:59:54 PM PDT 24
Finished Jul 22 04:59:58 PM PDT 24
Peak memory 217072 kb
Host smart-8ea25a78-959c-473a-889d-d33521c22f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662669656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2662669656
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4024840118
Short name T341
Test name
Test status
Simulation time 61624971 ps
CPU time 0.81 seconds
Started Jul 22 04:59:55 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 206656 kb
Host smart-f40fb72d-e420-40e2-bbde-3cb21af6d56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024840118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4024840118
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.955170862
Short name T763
Test name
Test status
Simulation time 37852818513 ps
CPU time 31.16 seconds
Started Jul 22 05:02:42 PM PDT 24
Finished Jul 22 05:03:14 PM PDT 24
Peak memory 233680 kb
Host smart-cf1a3f0a-c076-4be6-9a50-afb9584219fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955170862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.955170862
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1086262596
Short name T778
Test name
Test status
Simulation time 15511058 ps
CPU time 0.74 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 205476 kb
Host smart-6dd92394-6b5d-4227-ad41-0d092f34575d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086262596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1086262596
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4194400887
Short name T182
Test name
Test status
Simulation time 211512708 ps
CPU time 4.25 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:10 PM PDT 24
Peak memory 225424 kb
Host smart-3c4b2bc5-e52d-40c3-9875-569e10a2c886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194400887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4194400887
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.134058310
Short name T330
Test name
Test status
Simulation time 22096865 ps
CPU time 0.83 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:06 PM PDT 24
Peak memory 207172 kb
Host smart-3c2fab17-d53d-4d86-80b8-68742fda11b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134058310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.134058310
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.475734898
Short name T515
Test name
Test status
Simulation time 104448838558 ps
CPU time 111.87 seconds
Started Jul 22 05:00:08 PM PDT 24
Finished Jul 22 05:02:00 PM PDT 24
Peak memory 252048 kb
Host smart-c7ffcb63-8e9a-44bf-a4d0-224cbe68737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475734898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.475734898
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.325014931
Short name T629
Test name
Test status
Simulation time 1541087390 ps
CPU time 43.12 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 233688 kb
Host smart-5a642440-a577-4b51-b8c6-6b2ae38a6fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325014931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.325014931
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3191592406
Short name T628
Test name
Test status
Simulation time 11686889615 ps
CPU time 90.2 seconds
Started Jul 22 05:00:07 PM PDT 24
Finished Jul 22 05:01:38 PM PDT 24
Peak memory 256972 kb
Host smart-17742abb-eb08-4f83-9a34-f4c07593ff94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191592406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3191592406
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1495139385
Short name T396
Test name
Test status
Simulation time 105608457 ps
CPU time 2.98 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:08 PM PDT 24
Peak memory 225304 kb
Host smart-40f84ca7-c590-4938-af69-f16620bf4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495139385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1495139385
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.949299714
Short name T842
Test name
Test status
Simulation time 36318971400 ps
CPU time 48.62 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 250012 kb
Host smart-8cf3085a-9b67-4d05-8a46-91595c096c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949299714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.949299714
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.288873892
Short name T964
Test name
Test status
Simulation time 201912935 ps
CPU time 4.95 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:12 PM PDT 24
Peak memory 225424 kb
Host smart-e984b671-7878-4594-84e5-a5dbc1de6073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288873892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.288873892
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.275982011
Short name T260
Test name
Test status
Simulation time 5295449439 ps
CPU time 15.51 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:21 PM PDT 24
Peak memory 225468 kb
Host smart-f11cb1f8-c62c-4ba4-8e29-9cbd83759569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275982011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.275982011
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3233298188
Short name T653
Test name
Test status
Simulation time 5588156997 ps
CPU time 15.98 seconds
Started Jul 22 05:00:07 PM PDT 24
Finished Jul 22 05:00:23 PM PDT 24
Peak memory 236656 kb
Host smart-236f4cc7-7c9c-447e-b58f-dd72a2418a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233298188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3233298188
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1634845227
Short name T854
Test name
Test status
Simulation time 1397315135 ps
CPU time 9.97 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:17 PM PDT 24
Peak memory 223008 kb
Host smart-a1e6512e-3b75-4f7f-9501-76d979cc9334
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1634845227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1634845227
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3161154334
Short name T151
Test name
Test status
Simulation time 89052177465 ps
CPU time 153.23 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:02:38 PM PDT 24
Peak memory 251448 kb
Host smart-8db9ffc8-c9d8-4ef3-af62-9a52320489cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161154334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3161154334
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3889465397
Short name T638
Test name
Test status
Simulation time 1615309788 ps
CPU time 9.12 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:16 PM PDT 24
Peak memory 217156 kb
Host smart-798234c5-bd7a-4219-aa9f-17ab37fd8799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889465397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3889465397
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1430427028
Short name T749
Test name
Test status
Simulation time 107913928 ps
CPU time 1.03 seconds
Started Jul 22 05:04:25 PM PDT 24
Finished Jul 22 05:04:27 PM PDT 24
Peak memory 208360 kb
Host smart-2307745b-0fee-4fcc-be0b-d59f8bd1395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430427028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1430427028
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1887742451
Short name T869
Test name
Test status
Simulation time 247136447 ps
CPU time 1.4 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 217160 kb
Host smart-3fba279a-f5a0-4001-8c63-dd91a9dd79ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887742451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1887742451
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2075652034
Short name T567
Test name
Test status
Simulation time 74617964 ps
CPU time 0.75 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:05 PM PDT 24
Peak memory 206724 kb
Host smart-daa9b5eb-d236-4416-bd62-c43630bb7a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075652034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2075652034
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3773041770
Short name T925
Test name
Test status
Simulation time 628205790 ps
CPU time 7.43 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:14 PM PDT 24
Peak memory 233616 kb
Host smart-81c27a5a-1d5d-43e2-8d85-6ae827990ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773041770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3773041770
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4233885884
Short name T398
Test name
Test status
Simulation time 13810896 ps
CPU time 0.71 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 205956 kb
Host smart-d1ce1a87-9bad-4525-ba18-e29331ce384d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233885884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4233885884
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2124263303
Short name T382
Test name
Test status
Simulation time 125024430 ps
CPU time 2.62 seconds
Started Jul 22 05:03:02 PM PDT 24
Finished Jul 22 05:03:05 PM PDT 24
Peak memory 225376 kb
Host smart-cb4a41af-068e-4f6b-8911-9cc90f4ff519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124263303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2124263303
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3478836649
Short name T324
Test name
Test status
Simulation time 33937798 ps
CPU time 0.79 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:08 PM PDT 24
Peak memory 207224 kb
Host smart-b35290fd-6991-4eff-a328-fcc4ecce0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478836649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3478836649
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1344395710
Short name T43
Test name
Test status
Simulation time 21218234364 ps
CPU time 52.3 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:57 PM PDT 24
Peak memory 251976 kb
Host smart-a6c16776-b2bc-4cc0-8bab-e190da395dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344395710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1344395710
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2687935731
Short name T536
Test name
Test status
Simulation time 7023721118 ps
CPU time 51.16 seconds
Started Jul 22 05:03:04 PM PDT 24
Finished Jul 22 05:03:56 PM PDT 24
Peak memory 256620 kb
Host smart-6d1b6682-649d-4749-af49-448ee71e1257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687935731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2687935731
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2190468368
Short name T926
Test name
Test status
Simulation time 24996108425 ps
CPU time 223.35 seconds
Started Jul 22 05:00:03 PM PDT 24
Finished Jul 22 05:03:47 PM PDT 24
Peak memory 250100 kb
Host smart-873ed634-0f0f-4272-b59f-b831f335e798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190468368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2190468368
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2196618296
Short name T893
Test name
Test status
Simulation time 1989383240 ps
CPU time 6.96 seconds
Started Jul 22 05:00:06 PM PDT 24
Finished Jul 22 05:00:14 PM PDT 24
Peak memory 236532 kb
Host smart-7194b3de-9363-45a9-9a07-b1c531be73e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196618296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2196618296
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.284170558
Short name T13
Test name
Test status
Simulation time 21809594362 ps
CPU time 43.77 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 238956 kb
Host smart-c7cd923a-039a-4728-adf3-7eafa34d6714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284170558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.284170558
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.883557191
Short name T262
Test name
Test status
Simulation time 290759149 ps
CPU time 4.54 seconds
Started Jul 22 05:04:25 PM PDT 24
Finished Jul 22 05:04:32 PM PDT 24
Peak memory 225292 kb
Host smart-02b1fe14-3921-4bc3-ad25-ff8415bc3fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883557191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.883557191
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2056333646
Short name T1029
Test name
Test status
Simulation time 21740105282 ps
CPU time 50.36 seconds
Started Jul 22 05:05:45 PM PDT 24
Finished Jul 22 05:06:36 PM PDT 24
Peak memory 233692 kb
Host smart-39788763-1655-4d9b-af31-5711797a73f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056333646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2056333646
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3517518723
Short name T282
Test name
Test status
Simulation time 3964491466 ps
CPU time 13.07 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:19 PM PDT 24
Peak memory 233636 kb
Host smart-7dbba48f-337f-4709-9869-415bd6a3cc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517518723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3517518723
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1984039323
Short name T803
Test name
Test status
Simulation time 10163269118 ps
CPU time 12.91 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:19 PM PDT 24
Peak memory 225376 kb
Host smart-fd59dffb-d2e2-42bd-871a-d9c4326f3dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984039323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1984039323
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2356814553
Short name T490
Test name
Test status
Simulation time 6952136362 ps
CPU time 11.72 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:18 PM PDT 24
Peak memory 220000 kb
Host smart-28fe9894-7ec3-413b-a841-d7361872a5bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2356814553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2356814553
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.4213443862
Short name T153
Test name
Test status
Simulation time 13331867508 ps
CPU time 124.21 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:02:10 PM PDT 24
Peak memory 266832 kb
Host smart-5f2eb62e-4cf2-4c5b-9d83-15a3744daeed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213443862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.4213443862
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.421213590
Short name T874
Test name
Test status
Simulation time 3121876070 ps
CPU time 12.06 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:17 PM PDT 24
Peak memory 217216 kb
Host smart-b64290bf-ec06-41d8-9f17-baf18980a02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421213590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.421213590
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3075319486
Short name T351
Test name
Test status
Simulation time 36453156 ps
CPU time 0.7 seconds
Started Jul 22 05:00:04 PM PDT 24
Finished Jul 22 05:00:06 PM PDT 24
Peak memory 206300 kb
Host smart-0c48a653-5f11-4546-957b-e9586667808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075319486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3075319486
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4051254459
Short name T463
Test name
Test status
Simulation time 29473162 ps
CPU time 0.78 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 206740 kb
Host smart-cb2a00ff-7f67-4f7a-93aa-655651377d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051254459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4051254459
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1549504568
Short name T890
Test name
Test status
Simulation time 45677802 ps
CPU time 0.75 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:07 PM PDT 24
Peak memory 206788 kb
Host smart-a5a37a95-aa18-4067-b948-a563c87ec0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549504568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1549504568
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1667688057
Short name T244
Test name
Test status
Simulation time 7320069579 ps
CPU time 7.29 seconds
Started Jul 22 05:00:05 PM PDT 24
Finished Jul 22 05:00:13 PM PDT 24
Peak memory 233752 kb
Host smart-3d80be40-5049-4b78-8ac9-71293d29ec3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667688057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1667688057
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.411202513
Short name T366
Test name
Test status
Simulation time 12317585 ps
CPU time 0.74 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:18 PM PDT 24
Peak memory 206376 kb
Host smart-ba5790bc-be68-4769-ae86-cd87d9969f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411202513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.411202513
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2680855982
Short name T263
Test name
Test status
Simulation time 260727386 ps
CPU time 4.99 seconds
Started Jul 22 05:00:33 PM PDT 24
Finished Jul 22 05:00:38 PM PDT 24
Peak memory 225436 kb
Host smart-7659f855-91b8-42a0-82de-d4d9aed1454d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680855982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2680855982
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3190978381
Short name T520
Test name
Test status
Simulation time 16871978 ps
CPU time 0.79 seconds
Started Jul 22 05:03:02 PM PDT 24
Finished Jul 22 05:03:03 PM PDT 24
Peak memory 207244 kb
Host smart-ec9afb9b-a20c-40ae-8af6-84de55102167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190978381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3190978381
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2816066442
Short name T1001
Test name
Test status
Simulation time 3098061388 ps
CPU time 21.27 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 236396 kb
Host smart-2e2238cf-fbf6-4911-a3a1-467f717df817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816066442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2816066442
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3075700901
Short name T855
Test name
Test status
Simulation time 39193477991 ps
CPU time 106.43 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:02:04 PM PDT 24
Peak memory 250532 kb
Host smart-5ae22663-93e7-4e9e-8400-5c3cb65f957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075700901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3075700901
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1403092473
Short name T449
Test name
Test status
Simulation time 18388660600 ps
CPU time 44.39 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:01:10 PM PDT 24
Peak memory 251196 kb
Host smart-d676fdf1-13b1-4561-8fcf-0e789c551b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403092473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1403092473
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3367412214
Short name T542
Test name
Test status
Simulation time 4512910347 ps
CPU time 34.21 seconds
Started Jul 22 05:00:14 PM PDT 24
Finished Jul 22 05:00:49 PM PDT 24
Peak memory 251300 kb
Host smart-f9bfe00d-3b96-48ea-b410-c7d91c3a1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367412214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3367412214
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3179186420
Short name T708
Test name
Test status
Simulation time 3051753558 ps
CPU time 9.09 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:26 PM PDT 24
Peak memory 233688 kb
Host smart-62aaa47d-c84b-489b-8311-b016c4d8a006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179186420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3179186420
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.138364832
Short name T713
Test name
Test status
Simulation time 1328141062 ps
CPU time 13.47 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:30 PM PDT 24
Peak memory 233564 kb
Host smart-2ccebc70-8d4f-4c5b-8d2a-443f3852c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138364832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.138364832
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3497936843
Short name T381
Test name
Test status
Simulation time 618951586 ps
CPU time 2.84 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:19 PM PDT 24
Peak memory 225304 kb
Host smart-98e918b2-ed81-4ba9-bf67-469b79acb0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497936843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3497936843
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2581080417
Short name T947
Test name
Test status
Simulation time 955878487 ps
CPU time 5.76 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:22 PM PDT 24
Peak memory 233564 kb
Host smart-35b75ea8-2935-4b53-badf-b84a2a42e2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581080417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2581080417
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2421476871
Short name T138
Test name
Test status
Simulation time 2182519433 ps
CPU time 13.51 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 220184 kb
Host smart-2870af36-ce91-46f9-a127-81855f948f3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2421476871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2421476871
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2030761968
Short name T850
Test name
Test status
Simulation time 32456093 ps
CPU time 0.72 seconds
Started Jul 22 05:04:18 PM PDT 24
Finished Jul 22 05:04:20 PM PDT 24
Peak memory 206376 kb
Host smart-a6f788b3-31e3-4596-9414-e86cc47daa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030761968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2030761968
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1546905445
Short name T312
Test name
Test status
Simulation time 1481887849 ps
CPU time 4.38 seconds
Started Jul 22 05:00:19 PM PDT 24
Finished Jul 22 05:00:25 PM PDT 24
Peak memory 217156 kb
Host smart-b11dc4d9-e634-4826-a8cf-edb9617d4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546905445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1546905445
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1124350788
Short name T531
Test name
Test status
Simulation time 27797472 ps
CPU time 1.56 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:20 PM PDT 24
Peak memory 217128 kb
Host smart-a8260337-5680-4fcb-b95e-665cbc9745d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124350788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1124350788
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.506925489
Short name T369
Test name
Test status
Simulation time 170772256 ps
CPU time 0.99 seconds
Started Jul 22 05:00:15 PM PDT 24
Finished Jul 22 05:00:17 PM PDT 24
Peak memory 206664 kb
Host smart-0bbb4dc4-5956-44a5-a731-b34bc25c4dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506925489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.506925489
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3302889495
Short name T746
Test name
Test status
Simulation time 554346986 ps
CPU time 6.83 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:24 PM PDT 24
Peak memory 225328 kb
Host smart-b6cdc5ee-08ce-4d6e-9842-266c292a9fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302889495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3302889495
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.988312668
Short name T972
Test name
Test status
Simulation time 14593112 ps
CPU time 0.69 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:28 PM PDT 24
Peak memory 206064 kb
Host smart-0a040521-91e5-4cb8-89c3-0cf8036dfc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988312668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.988312668
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1552020280
Short name T185
Test name
Test status
Simulation time 3816945311 ps
CPU time 6.8 seconds
Started Jul 22 05:04:25 PM PDT 24
Finished Jul 22 05:04:33 PM PDT 24
Peak memory 225248 kb
Host smart-bb7d4ec7-72aa-467d-a5eb-6c567e96a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552020280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1552020280
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.973113720
Short name T365
Test name
Test status
Simulation time 74673789 ps
CPU time 0.79 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:19 PM PDT 24
Peak memory 207548 kb
Host smart-8f3cc85a-ed66-4fc5-9959-707bfb80c063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973113720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.973113720
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.863962631
Short name T598
Test name
Test status
Simulation time 64044347659 ps
CPU time 146.84 seconds
Started Jul 22 05:00:19 PM PDT 24
Finished Jul 22 05:02:48 PM PDT 24
Peak memory 264136 kb
Host smart-cc6f79aa-d7fd-48ac-94e1-83e05a94c7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863962631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.863962631
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.4129570341
Short name T438
Test name
Test status
Simulation time 7472730618 ps
CPU time 30.34 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 218460 kb
Host smart-4e48b805-c38b-4c8e-8345-584f6ad98841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129570341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.4129570341
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2858319398
Short name T197
Test name
Test status
Simulation time 14816489735 ps
CPU time 138.33 seconds
Started Jul 22 05:00:23 PM PDT 24
Finished Jul 22 05:02:42 PM PDT 24
Peak memory 249684 kb
Host smart-3f6950ba-9aba-4a12-a5a5-1a5391802073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858319398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2858319398
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2323064885
Short name T527
Test name
Test status
Simulation time 1544613058 ps
CPU time 5.41 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:23 PM PDT 24
Peak memory 225432 kb
Host smart-2e979a1e-a67e-4e8b-b1f7-2afbd42e7b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323064885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2323064885
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.70260207
Short name T37
Test name
Test status
Simulation time 2145718973 ps
CPU time 43.83 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:01:01 PM PDT 24
Peak memory 251096 kb
Host smart-bce48ba4-9c9d-4678-8486-4784af9cb74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70260207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.70260207
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2604958938
Short name T807
Test name
Test status
Simulation time 154141657 ps
CPU time 4.93 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:23 PM PDT 24
Peak memory 233544 kb
Host smart-23109b28-2909-42d2-8347-8c6957d25034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604958938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2604958938
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2023282470
Short name T529
Test name
Test status
Simulation time 1170486563 ps
CPU time 5.6 seconds
Started Jul 22 05:00:16 PM PDT 24
Finished Jul 22 05:00:22 PM PDT 24
Peak memory 238708 kb
Host smart-ed9f4abd-45f1-4626-9ec6-6c334a45cbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023282470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2023282470
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1652459315
Short name T646
Test name
Test status
Simulation time 3852443895 ps
CPU time 8.69 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:29 PM PDT 24
Peak memory 225472 kb
Host smart-9918a8f8-59d4-472d-886e-4cf9b292302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652459315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1652459315
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2099916382
Short name T523
Test name
Test status
Simulation time 5901312164 ps
CPU time 22.12 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 233712 kb
Host smart-ff895d46-fdc8-49b2-b2c9-ca5c3e32d21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099916382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2099916382
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1009503161
Short name T353
Test name
Test status
Simulation time 4608776606 ps
CPU time 11.83 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:38 PM PDT 24
Peak memory 220216 kb
Host smart-e3b945b0-8f73-493b-89c2-82aec8c00a42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1009503161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1009503161
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1983100058
Short name T152
Test name
Test status
Simulation time 155157699 ps
CPU time 0.9 seconds
Started Jul 22 05:00:19 PM PDT 24
Finished Jul 22 05:00:21 PM PDT 24
Peak memory 207624 kb
Host smart-ab4d0725-4df9-4a0b-a512-ad129324a774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983100058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1983100058
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2165044895
Short name T2
Test name
Test status
Simulation time 14930650615 ps
CPU time 19.99 seconds
Started Jul 22 05:00:26 PM PDT 24
Finished Jul 22 05:00:47 PM PDT 24
Peak memory 217184 kb
Host smart-cc97e7aa-1c3b-4ab5-bf82-f70b81433971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165044895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2165044895
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3539462822
Short name T764
Test name
Test status
Simulation time 3424684396 ps
CPU time 12.19 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:31 PM PDT 24
Peak memory 217252 kb
Host smart-d11ed965-aaa4-4279-9820-0218a41588b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539462822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3539462822
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1039794874
Short name T372
Test name
Test status
Simulation time 41245480 ps
CPU time 1.41 seconds
Started Jul 22 05:00:15 PM PDT 24
Finished Jul 22 05:00:17 PM PDT 24
Peak memory 217176 kb
Host smart-7acf9d2b-ce83-45a3-9e8e-e661dfef5344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039794874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1039794874
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2523209571
Short name T910
Test name
Test status
Simulation time 341752337 ps
CPU time 0.96 seconds
Started Jul 22 05:00:15 PM PDT 24
Finished Jul 22 05:00:16 PM PDT 24
Peak memory 206776 kb
Host smart-7977ec34-fd43-4958-8b83-92fcc3b531b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523209571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2523209571
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3766743392
Short name T887
Test name
Test status
Simulation time 334583523 ps
CPU time 2.17 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:22 PM PDT 24
Peak memory 225440 kb
Host smart-c6e45502-acb5-4e60-bb51-38538c00bd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766743392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3766743392
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3167417572
Short name T930
Test name
Test status
Simulation time 25635262 ps
CPU time 0.71 seconds
Started Jul 22 05:00:26 PM PDT 24
Finished Jul 22 05:00:28 PM PDT 24
Peak memory 206100 kb
Host smart-c7934363-7745-4ecb-b80f-8974a03737ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167417572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3167417572
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2729757052
Short name T258
Test name
Test status
Simulation time 2255975329 ps
CPU time 7.21 seconds
Started Jul 22 05:00:32 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 225508 kb
Host smart-4bcade6d-a1e3-45dc-8931-9b135cbda249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729757052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2729757052
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2636252010
Short name T1010
Test name
Test status
Simulation time 43902363 ps
CPU time 0.76 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:21 PM PDT 24
Peak memory 207132 kb
Host smart-5604821d-5a42-454f-9d58-db4556db127d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636252010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2636252010
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.994118698
Short name T44
Test name
Test status
Simulation time 9744250213 ps
CPU time 119.82 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:02:27 PM PDT 24
Peak memory 259228 kb
Host smart-aa00b4b2-437b-496d-804e-95b5f322a274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994118698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.994118698
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2830935580
Short name T296
Test name
Test status
Simulation time 21629178029 ps
CPU time 92.81 seconds
Started Jul 22 05:00:28 PM PDT 24
Finished Jul 22 05:02:02 PM PDT 24
Peak memory 250152 kb
Host smart-12e06056-c4db-43e1-bd6f-721826692b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830935580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2830935580
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1890262320
Short name T695
Test name
Test status
Simulation time 20200750961 ps
CPU time 226.42 seconds
Started Jul 22 05:00:24 PM PDT 24
Finished Jul 22 05:04:11 PM PDT 24
Peak memory 255092 kb
Host smart-5c1c1eb3-81b0-477a-b47e-f50d168b2c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890262320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1890262320
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1203480714
Short name T816
Test name
Test status
Simulation time 785765118 ps
CPU time 5.78 seconds
Started Jul 22 05:00:30 PM PDT 24
Finished Jul 22 05:00:36 PM PDT 24
Peak memory 235220 kb
Host smart-61fc8513-6385-45fb-869c-1212974565e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203480714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1203480714
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3140893585
Short name T688
Test name
Test status
Simulation time 19202699135 ps
CPU time 59.58 seconds
Started Jul 22 05:00:32 PM PDT 24
Finished Jul 22 05:01:33 PM PDT 24
Peak memory 249080 kb
Host smart-3c6c083b-d6c5-4278-9f1e-451e5d5476e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140893585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3140893585
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2722592551
Short name T87
Test name
Test status
Simulation time 3425967889 ps
CPU time 19.89 seconds
Started Jul 22 05:00:32 PM PDT 24
Finished Jul 22 05:00:53 PM PDT 24
Peak memory 225512 kb
Host smart-482b215e-78e4-43fd-8d67-02a84750cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722592551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2722592551
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3117314479
Short name T370
Test name
Test status
Simulation time 13084548676 ps
CPU time 41.29 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 235264 kb
Host smart-599dabc4-ddc4-439c-abbd-ff41eb24f2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117314479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3117314479
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3550329877
Short name T777
Test name
Test status
Simulation time 36407980301 ps
CPU time 10.15 seconds
Started Jul 22 05:00:18 PM PDT 24
Finished Jul 22 05:00:29 PM PDT 24
Peak memory 225452 kb
Host smart-7cf07981-ee94-4fdb-9e91-afeb622461e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550329877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3550329877
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1146018668
Short name T234
Test name
Test status
Simulation time 32227488 ps
CPU time 2.3 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:20 PM PDT 24
Peak memory 233548 kb
Host smart-37dbd55b-1dbc-4d77-a746-f760d7159518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146018668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1146018668
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2313721879
Short name T135
Test name
Test status
Simulation time 396093204 ps
CPU time 3.76 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 222616 kb
Host smart-269d6c99-dde9-4339-a237-94486be68484
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2313721879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2313721879
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1898844309
Short name T678
Test name
Test status
Simulation time 158617924 ps
CPU time 1.02 seconds
Started Jul 22 05:00:50 PM PDT 24
Finished Jul 22 05:00:51 PM PDT 24
Peak memory 208280 kb
Host smart-38ca1042-763d-40be-ab5b-b29d437b47ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898844309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1898844309
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3071819676
Short name T422
Test name
Test status
Simulation time 22885597147 ps
CPU time 35.5 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:53 PM PDT 24
Peak memory 217224 kb
Host smart-b3713197-056b-4226-aed2-21fa9af5d12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071819676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3071819676
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.843911096
Short name T486
Test name
Test status
Simulation time 1914079333 ps
CPU time 5.23 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:32 PM PDT 24
Peak memory 217112 kb
Host smart-a6171ffd-34e7-47e8-b4bd-674e0f16066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843911096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.843911096
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4241457623
Short name T306
Test name
Test status
Simulation time 38240688 ps
CPU time 1.19 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:19 PM PDT 24
Peak memory 217352 kb
Host smart-6a91d990-4550-44d3-9a07-254829322757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241457623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4241457623
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2407237743
Short name T988
Test name
Test status
Simulation time 277096588 ps
CPU time 0.86 seconds
Started Jul 22 05:00:17 PM PDT 24
Finished Jul 22 05:00:18 PM PDT 24
Peak memory 206732 kb
Host smart-ff482d28-d3f1-4ed3-8e9a-ae4b96bd9eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407237743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2407237743
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1415807025
Short name T772
Test name
Test status
Simulation time 4111715015 ps
CPU time 18.15 seconds
Started Jul 22 05:00:24 PM PDT 24
Finished Jul 22 05:00:42 PM PDT 24
Peak memory 233688 kb
Host smart-12644332-759e-41ae-b001-351605605a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415807025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1415807025
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.345104620
Short name T393
Test name
Test status
Simulation time 25094495 ps
CPU time 0.74 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:00:29 PM PDT 24
Peak memory 206000 kb
Host smart-3d998011-c587-4692-a49a-2cb65918c661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345104620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.345104620
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1978788466
Short name T881
Test name
Test status
Simulation time 1281930522 ps
CPU time 13.39 seconds
Started Jul 22 05:00:24 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 225456 kb
Host smart-9b50cabf-9b54-462a-afa1-701c63d24810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978788466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1978788466
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1522496148
Short name T496
Test name
Test status
Simulation time 69445759 ps
CPU time 0.77 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:27 PM PDT 24
Peak memory 207224 kb
Host smart-680ad567-f607-481c-b595-d611d0ab444e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522496148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1522496148
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.271025886
Short name T225
Test name
Test status
Simulation time 1073408917 ps
CPU time 10.25 seconds
Started Jul 22 05:00:31 PM PDT 24
Finished Jul 22 05:00:42 PM PDT 24
Peak memory 237416 kb
Host smart-a50808bf-2076-4c01-ba79-b60d404f8092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271025886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.271025886
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.545229470
Short name T863
Test name
Test status
Simulation time 23378926988 ps
CPU time 222.56 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:04:09 PM PDT 24
Peak memory 256652 kb
Host smart-3d5bde36-2ab0-49d7-b656-0b2da00a5d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545229470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.545229470
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.641505853
Short name T767
Test name
Test status
Simulation time 2204382320 ps
CPU time 51.42 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:01:19 PM PDT 24
Peak memory 250088 kb
Host smart-666ec20d-099c-4d63-88bb-73875854ccdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641505853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.641505853
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2341599114
Short name T968
Test name
Test status
Simulation time 6758576813 ps
CPU time 24.73 seconds
Started Jul 22 05:00:32 PM PDT 24
Finished Jul 22 05:00:58 PM PDT 24
Peak memory 233688 kb
Host smart-b78c6972-5871-4d2e-943d-50d7894035f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341599114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2341599114
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1523202293
Short name T627
Test name
Test status
Simulation time 39772894252 ps
CPU time 40.75 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:01:07 PM PDT 24
Peak memory 251596 kb
Host smart-f97ca833-e15c-4cbf-80a7-6eb35bc4678e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523202293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1523202293
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3347148890
Short name T102
Test name
Test status
Simulation time 414078763 ps
CPU time 3.83 seconds
Started Jul 22 05:00:26 PM PDT 24
Finished Jul 22 05:00:31 PM PDT 24
Peak memory 225344 kb
Host smart-96174e63-c194-4a16-9998-d5cc278088d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347148890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3347148890
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4097967790
Short name T385
Test name
Test status
Simulation time 837985203 ps
CPU time 4.56 seconds
Started Jul 22 05:00:26 PM PDT 24
Finished Jul 22 05:00:32 PM PDT 24
Peak memory 225432 kb
Host smart-1fe5a22e-409d-47c7-a3c4-78cc14f7e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097967790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4097967790
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3480839020
Short name T908
Test name
Test status
Simulation time 1157944946 ps
CPU time 6.22 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:00:34 PM PDT 24
Peak memory 225308 kb
Host smart-69128b81-3284-40f2-a1d0-76d18e4bd5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480839020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3480839020
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3098486620
Short name T528
Test name
Test status
Simulation time 1126129098 ps
CPU time 8.54 seconds
Started Jul 22 05:00:31 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 233648 kb
Host smart-7f317cf4-0a9c-4479-9014-b650a0dc935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098486620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3098486620
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3437161601
Short name T707
Test name
Test status
Simulation time 1141327178 ps
CPU time 12.53 seconds
Started Jul 22 05:00:28 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 221376 kb
Host smart-ea8adac6-7578-455b-8add-fc5260d7bbad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3437161601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3437161601
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.468941201
Short name T932
Test name
Test status
Simulation time 2619201176 ps
CPU time 13.41 seconds
Started Jul 22 05:00:25 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 217272 kb
Host smart-0864b944-ed77-4a98-a505-73aa98498867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468941201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.468941201
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.808491109
Short name T81
Test name
Test status
Simulation time 8956495690 ps
CPU time 12.19 seconds
Started Jul 22 05:00:28 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 217116 kb
Host smart-1f6d0c88-5bff-4a4d-8c06-e7e74c99bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808491109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.808491109
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3166647963
Short name T714
Test name
Test status
Simulation time 11398086 ps
CPU time 0.72 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:00:29 PM PDT 24
Peak memory 206260 kb
Host smart-7f19d059-f0c4-46e8-a4a5-e61aa8a207bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166647963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3166647963
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1101209913
Short name T503
Test name
Test status
Simulation time 97931965 ps
CPU time 0.8 seconds
Started Jul 22 05:00:30 PM PDT 24
Finished Jul 22 05:00:31 PM PDT 24
Peak memory 206616 kb
Host smart-59743fda-1e6e-4868-b8d6-cb859ad7df8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101209913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1101209913
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.120261118
Short name T810
Test name
Test status
Simulation time 1049008074 ps
CPU time 5.54 seconds
Started Jul 22 05:00:51 PM PDT 24
Finished Jul 22 05:00:57 PM PDT 24
Peak memory 225368 kb
Host smart-2b9b5f0a-cba4-445e-92fa-44a08baa5f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120261118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.120261118
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.219298595
Short name T60
Test name
Test status
Simulation time 118753185 ps
CPU time 0.73 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:00:38 PM PDT 24
Peak memory 205976 kb
Host smart-ef3ae12e-9192-42c6-972c-4589a2008004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219298595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.219298595
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2551139892
Short name T995
Test name
Test status
Simulation time 2488547069 ps
CPU time 4.74 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 233612 kb
Host smart-0194d386-cd66-4824-b172-f2d4209e9c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551139892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2551139892
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3929448196
Short name T518
Test name
Test status
Simulation time 113125833 ps
CPU time 0.76 seconds
Started Jul 22 05:03:05 PM PDT 24
Finished Jul 22 05:03:06 PM PDT 24
Peak memory 206140 kb
Host smart-ad4ad371-82f7-4301-ad06-6cb4f6abab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929448196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3929448196
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1866830858
Short name T819
Test name
Test status
Simulation time 23595764505 ps
CPU time 44.77 seconds
Started Jul 22 05:00:30 PM PDT 24
Finished Jul 22 05:01:15 PM PDT 24
Peak memory 250488 kb
Host smart-b7acc8d2-b918-47d5-98cb-a27f349a484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866830858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1866830858
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3524837898
Short name T82
Test name
Test status
Simulation time 140412171521 ps
CPU time 85.74 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:02:03 PM PDT 24
Peak memory 241896 kb
Host smart-0ea55d86-322d-4aa6-97d8-28ce2f7fb0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524837898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3524837898
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1139046266
Short name T786
Test name
Test status
Simulation time 1268976678 ps
CPU time 20.71 seconds
Started Jul 22 05:03:04 PM PDT 24
Finished Jul 22 05:03:25 PM PDT 24
Peak memory 233596 kb
Host smart-cf3cad84-051d-4dc7-bdc9-409070532625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139046266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1139046266
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3550670315
Short name T999
Test name
Test status
Simulation time 39813183606 ps
CPU time 279.18 seconds
Started Jul 22 05:03:04 PM PDT 24
Finished Jul 22 05:07:44 PM PDT 24
Peak memory 251012 kb
Host smart-01da98d4-7740-410f-abc9-e69a17e067bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550670315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3550670315
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3383548525
Short name T661
Test name
Test status
Simulation time 169487868 ps
CPU time 2.03 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:00:30 PM PDT 24
Peak memory 219468 kb
Host smart-168cf8ed-f64c-403b-8457-ff2cc5744ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383548525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3383548525
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2209896104
Short name T238
Test name
Test status
Simulation time 383602001 ps
CPU time 4.23 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 225352 kb
Host smart-e8a4663a-fcd0-45ef-8859-22a00092afde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209896104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2209896104
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2742414201
Short name T784
Test name
Test status
Simulation time 8957380674 ps
CPU time 8.32 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:00:46 PM PDT 24
Peak memory 233612 kb
Host smart-93ee8fc7-2d25-4c1d-97ae-eb8c28422e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742414201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2742414201
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2743476246
Short name T722
Test name
Test status
Simulation time 10877454941 ps
CPU time 9.71 seconds
Started Jul 22 05:00:32 PM PDT 24
Finished Jul 22 05:00:43 PM PDT 24
Peak memory 233664 kb
Host smart-3bffd5d4-7fb1-4ea4-a95f-7000f4dbc352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743476246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2743476246
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3152282455
Short name T441
Test name
Test status
Simulation time 927418301 ps
CPU time 5.95 seconds
Started Jul 22 05:03:05 PM PDT 24
Finished Jul 22 05:03:12 PM PDT 24
Peak memory 221400 kb
Host smart-2e9bbd70-4e22-42a0-96ec-882ce4dc20d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3152282455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3152282455
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1723065840
Short name T956
Test name
Test status
Simulation time 65875857190 ps
CPU time 287.05 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:05:24 PM PDT 24
Peak memory 250004 kb
Host smart-fa76ecea-5bf1-4118-9cd3-443f8c60ab03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723065840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1723065840
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1917303690
Short name T23
Test name
Test status
Simulation time 210811565 ps
CPU time 3.35 seconds
Started Jul 22 05:00:30 PM PDT 24
Finished Jul 22 05:00:34 PM PDT 24
Peak memory 217068 kb
Host smart-f114dd4d-d373-469e-adee-eaecf2adf62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917303690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1917303690
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2945191160
Short name T80
Test name
Test status
Simulation time 4063893389 ps
CPU time 6.54 seconds
Started Jul 22 05:00:28 PM PDT 24
Finished Jul 22 05:00:36 PM PDT 24
Peak memory 217208 kb
Host smart-4b93f0ce-d45e-4ff5-a20c-1066e2719e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945191160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2945191160
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3563493903
Short name T834
Test name
Test status
Simulation time 426180078 ps
CPU time 2.19 seconds
Started Jul 22 05:00:27 PM PDT 24
Finished Jul 22 05:00:31 PM PDT 24
Peak memory 218568 kb
Host smart-30e10c4f-a89d-4634-94b2-6860de1c5d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563493903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3563493903
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2996987012
Short name T801
Test name
Test status
Simulation time 191216304 ps
CPU time 0.95 seconds
Started Jul 22 05:00:31 PM PDT 24
Finished Jul 22 05:00:33 PM PDT 24
Peak memory 207048 kb
Host smart-1c9bacf7-633d-4fa8-939d-badde49cf703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996987012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2996987012
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3837266807
Short name T726
Test name
Test status
Simulation time 266272712 ps
CPU time 3.43 seconds
Started Jul 22 05:00:28 PM PDT 24
Finished Jul 22 05:00:32 PM PDT 24
Peak memory 237376 kb
Host smart-c6093462-3301-4bce-af21-1e4adf25c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837266807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3837266807
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2391008975
Short name T732
Test name
Test status
Simulation time 14277734 ps
CPU time 0.75 seconds
Started Jul 22 05:00:40 PM PDT 24
Finished Jul 22 05:00:42 PM PDT 24
Peak memory 205920 kb
Host smart-1f6c5959-9f71-4776-a0f5-dd6691ddf066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391008975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2391008975
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1662363930
Short name T942
Test name
Test status
Simulation time 2508554820 ps
CPU time 22.59 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 225404 kb
Host smart-7a524ea7-3ed8-462d-afef-9d67e5f53551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662363930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1662363930
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.285572181
Short name T631
Test name
Test status
Simulation time 15895068 ps
CPU time 0.83 seconds
Started Jul 22 05:04:19 PM PDT 24
Finished Jul 22 05:04:20 PM PDT 24
Peak memory 207556 kb
Host smart-9c500f6c-96b1-484b-bd7f-09ab62904023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285572181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.285572181
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.906468801
Short name T394
Test name
Test status
Simulation time 22029873475 ps
CPU time 72.41 seconds
Started Jul 22 05:04:21 PM PDT 24
Finished Jul 22 05:05:34 PM PDT 24
Peak memory 253436 kb
Host smart-f2ad2493-66fc-4bcd-b051-8e9710f1cfa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906468801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.906468801
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2412960005
Short name T645
Test name
Test status
Simulation time 28934114295 ps
CPU time 189.79 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:03:46 PM PDT 24
Peak memory 251748 kb
Host smart-4434eee7-c2a0-45e3-90dc-f333f467097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412960005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2412960005
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2930719881
Short name T294
Test name
Test status
Simulation time 2417734608 ps
CPU time 12.21 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:00:49 PM PDT 24
Peak memory 218688 kb
Host smart-8a0e520c-258b-4a8d-b838-98b779e45c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930719881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2930719881
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.841190186
Short name T287
Test name
Test status
Simulation time 6758583858 ps
CPU time 40.22 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:01:17 PM PDT 24
Peak memory 234652 kb
Host smart-d398c9f5-75a3-4843-b8ba-ae7fbd94ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841190186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.841190186
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3917594216
Short name T923
Test name
Test status
Simulation time 833235394 ps
CPU time 16.74 seconds
Started Jul 22 05:00:38 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 238996 kb
Host smart-b811a39f-c41d-4f2e-96ec-e0e96f3e3712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917594216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3917594216
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1172865310
Short name T350
Test name
Test status
Simulation time 167399237 ps
CPU time 2.78 seconds
Started Jul 22 05:00:34 PM PDT 24
Finished Jul 22 05:00:37 PM PDT 24
Peak memory 233492 kb
Host smart-3fd8103d-ac68-4aec-bb87-b0d18481d0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172865310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1172865310
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4146598201
Short name T702
Test name
Test status
Simulation time 835266894 ps
CPU time 10.91 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 225416 kb
Host smart-fda278d9-27e5-4276-80e7-7acc0f627095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146598201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4146598201
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1619347580
Short name T390
Test name
Test status
Simulation time 61100355 ps
CPU time 2.47 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 233180 kb
Host smart-45fe6620-422d-4a73-ab86-133a3a98b0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619347580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1619347580
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.922013332
Short name T727
Test name
Test status
Simulation time 462509340 ps
CPU time 3.11 seconds
Started Jul 22 05:00:34 PM PDT 24
Finished Jul 22 05:00:37 PM PDT 24
Peak memory 233608 kb
Host smart-715d8dcc-f119-404b-ab08-8eb338be151b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922013332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.922013332
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1289638019
Short name T508
Test name
Test status
Simulation time 597967602 ps
CPU time 7.26 seconds
Started Jul 22 05:00:38 PM PDT 24
Finished Jul 22 05:00:46 PM PDT 24
Peak memory 220232 kb
Host smart-56481926-330f-4878-9aa8-4a168bc57602
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289638019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1289638019
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2392214709
Short name T896
Test name
Test status
Simulation time 28763015769 ps
CPU time 273.8 seconds
Started Jul 22 05:00:38 PM PDT 24
Finished Jul 22 05:05:12 PM PDT 24
Peak memory 255120 kb
Host smart-88ffdbc9-5aba-488e-b86c-4becd6f43b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392214709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2392214709
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4096605515
Short name T424
Test name
Test status
Simulation time 1090129439 ps
CPU time 3.86 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:00:41 PM PDT 24
Peak memory 217476 kb
Host smart-cdbaa8e1-91ab-437f-b2e4-1f9970d7e0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096605515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4096605515
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.368009465
Short name T845
Test name
Test status
Simulation time 2142375770 ps
CPU time 3.71 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 217064 kb
Host smart-8e83c55b-5416-40d7-be10-83e79c9cf2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368009465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.368009465
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2137460724
Short name T758
Test name
Test status
Simulation time 478699980 ps
CPU time 1.9 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:00:39 PM PDT 24
Peak memory 217052 kb
Host smart-9faacaba-68f4-45c7-b322-038a3368eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137460724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2137460724
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2942851285
Short name T533
Test name
Test status
Simulation time 44702576 ps
CPU time 0.88 seconds
Started Jul 22 05:00:33 PM PDT 24
Finished Jul 22 05:00:35 PM PDT 24
Peak memory 206700 kb
Host smart-af67887e-ee06-429b-a84e-237e6dd541f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942851285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2942851285
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.148548056
Short name T386
Test name
Test status
Simulation time 12278757282 ps
CPU time 24.67 seconds
Started Jul 22 05:00:36 PM PDT 24
Finished Jul 22 05:01:02 PM PDT 24
Peak memory 225488 kb
Host smart-6064b00d-fceb-4b4e-b087-a5db0b69cb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148548056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.148548056
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2651582312
Short name T333
Test name
Test status
Simulation time 10987655 ps
CPU time 0.73 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 205920 kb
Host smart-e3e92afb-5af9-40da-b7de-ec9c337591b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651582312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2651582312
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.251096822
Short name T407
Test name
Test status
Simulation time 198274389 ps
CPU time 3.92 seconds
Started Jul 22 05:00:44 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 233660 kb
Host smart-2556cab4-e218-4f28-969e-bec4e7426055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251096822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.251096822
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1708050932
Short name T459
Test name
Test status
Simulation time 14608056 ps
CPU time 0.81 seconds
Started Jul 22 05:00:42 PM PDT 24
Finished Jul 22 05:00:43 PM PDT 24
Peak memory 206096 kb
Host smart-9e8d8c50-8489-4249-9eb9-307c4d3db0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708050932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1708050932
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2199461018
Short name T705
Test name
Test status
Simulation time 43620695296 ps
CPU time 285.88 seconds
Started Jul 22 05:02:18 PM PDT 24
Finished Jul 22 05:07:05 PM PDT 24
Peak memory 269260 kb
Host smart-30b2a4d8-6366-489e-affe-66eea024ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199461018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2199461018
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3691404003
Short name T794
Test name
Test status
Simulation time 19265753380 ps
CPU time 84.4 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:02:12 PM PDT 24
Peak memory 257360 kb
Host smart-16137c83-6704-4665-9e28-3164ac8175a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691404003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3691404003
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2087812987
Short name T804
Test name
Test status
Simulation time 824296759 ps
CPU time 14.13 seconds
Started Jul 22 05:00:45 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 233592 kb
Host smart-53933798-3bb8-466d-9638-9abd30c81e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087812987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2087812987
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2842060940
Short name T283
Test name
Test status
Simulation time 9051335689 ps
CPU time 79.29 seconds
Started Jul 22 05:00:43 PM PDT 24
Finished Jul 22 05:02:03 PM PDT 24
Peak memory 249148 kb
Host smart-e52d4834-5ad0-4d4a-ba04-c8a3457d8475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842060940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2842060940
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3026639591
Short name T593
Test name
Test status
Simulation time 1452612610 ps
CPU time 15.18 seconds
Started Jul 22 05:00:39 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 233576 kb
Host smart-8d360f42-b36f-4f59-aa83-221096ab4030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026639591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3026639591
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.938445894
Short name T623
Test name
Test status
Simulation time 578713295 ps
CPU time 8.97 seconds
Started Jul 22 05:00:45 PM PDT 24
Finished Jul 22 05:00:55 PM PDT 24
Peak memory 233572 kb
Host smart-af43414f-a99e-4e15-8878-acd1519af30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938445894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.938445894
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2921324432
Short name T247
Test name
Test status
Simulation time 20262452980 ps
CPU time 20.11 seconds
Started Jul 22 05:00:38 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 233616 kb
Host smart-d94af5fc-e2b0-41ce-9ae0-0976bdff084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921324432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2921324432
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1150831163
Short name T367
Test name
Test status
Simulation time 32060891 ps
CPU time 2.5 seconds
Started Jul 22 05:00:39 PM PDT 24
Finished Jul 22 05:00:42 PM PDT 24
Peak memory 233184 kb
Host smart-d01b7823-5421-46bb-a504-d80b746fdb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150831163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1150831163
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.530880351
Short name T973
Test name
Test status
Simulation time 346851715 ps
CPU time 3.9 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:51 PM PDT 24
Peak memory 223668 kb
Host smart-2539844d-f440-4323-a55e-edba7ad78157
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530880351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.530880351
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3494239916
Short name T837
Test name
Test status
Simulation time 50243039600 ps
CPU time 253.21 seconds
Started Jul 22 05:00:45 PM PDT 24
Finished Jul 22 05:04:59 PM PDT 24
Peak memory 259244 kb
Host smart-34d8dd34-a9ba-441d-b759-ccf62e999c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494239916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3494239916
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1572220087
Short name T761
Test name
Test status
Simulation time 7086584697 ps
CPU time 28.36 seconds
Started Jul 22 05:00:37 PM PDT 24
Finished Jul 22 05:01:07 PM PDT 24
Peak memory 217232 kb
Host smart-7394e9e3-4e10-40cb-90e6-a23b23a73aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572220087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1572220087
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.163746365
Short name T313
Test name
Test status
Simulation time 9950532375 ps
CPU time 13.71 seconds
Started Jul 22 05:00:38 PM PDT 24
Finished Jul 22 05:00:52 PM PDT 24
Peak memory 217152 kb
Host smart-cad11758-f369-454c-ad0c-7b2ce438e557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163746365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.163746365
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2135185058
Short name T877
Test name
Test status
Simulation time 190902971 ps
CPU time 2.54 seconds
Started Jul 22 05:04:21 PM PDT 24
Finished Jul 22 05:04:24 PM PDT 24
Peak memory 217180 kb
Host smart-88dc885c-a95b-45bb-84a8-2a16f427e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135185058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2135185058
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1998121279
Short name T489
Test name
Test status
Simulation time 811432645 ps
CPU time 0.93 seconds
Started Jul 22 05:00:35 PM PDT 24
Finished Jul 22 05:00:36 PM PDT 24
Peak memory 206748 kb
Host smart-a60ce6ce-0c03-4ae8-a143-2abfb7157784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998121279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1998121279
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.393082354
Short name T916
Test name
Test status
Simulation time 76062776 ps
CPU time 2.48 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 233176 kb
Host smart-36731b20-ffd7-4d19-b6ae-78b1710f8b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393082354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.393082354
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1051424032
Short name T554
Test name
Test status
Simulation time 13890825 ps
CPU time 0.7 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 206288 kb
Host smart-6aaad851-5e28-461d-97ae-4223397095c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051424032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
051424032
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2152324228
Short name T853
Test name
Test status
Simulation time 379322303 ps
CPU time 4.79 seconds
Started Jul 22 04:57:39 PM PDT 24
Finished Jul 22 04:57:44 PM PDT 24
Peak memory 233556 kb
Host smart-fa3dfb5f-dc94-4863-952c-3b7a5f79ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152324228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2152324228
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.354225559
Short name T844
Test name
Test status
Simulation time 49477307 ps
CPU time 0.71 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:34 PM PDT 24
Peak memory 206100 kb
Host smart-d44732cc-652c-4eaa-bf2d-18568f4b97ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354225559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.354225559
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3889317076
Short name T201
Test name
Test status
Simulation time 3533484232 ps
CPU time 77.18 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:58:53 PM PDT 24
Peak memory 266460 kb
Host smart-c71ba53f-3e72-4419-80a1-bbacaddfe9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889317076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3889317076
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1991544086
Short name T941
Test name
Test status
Simulation time 21834778202 ps
CPU time 205.33 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:06:43 PM PDT 24
Peak memory 266428 kb
Host smart-a63ae68d-0423-4438-ab6d-c22b9a0fca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991544086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1991544086
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2780173592
Short name T901
Test name
Test status
Simulation time 32292570083 ps
CPU time 309.16 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 05:02:44 PM PDT 24
Peak memory 267468 kb
Host smart-f3d82188-4c95-452d-bf8d-6c6eb15696b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780173592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2780173592
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1132278893
Short name T524
Test name
Test status
Simulation time 334220755 ps
CPU time 9.15 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:44 PM PDT 24
Peak memory 233624 kb
Host smart-08d9e45b-09db-4ada-8085-930b7115ed52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132278893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1132278893
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2974941704
Short name T268
Test name
Test status
Simulation time 196258425432 ps
CPU time 179.43 seconds
Started Jul 22 04:57:36 PM PDT 24
Finished Jul 22 05:00:37 PM PDT 24
Peak memory 256440 kb
Host smart-4df949c5-f619-45f2-9c3e-5ca70eeeac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974941704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2974941704
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3363439377
Short name T719
Test name
Test status
Simulation time 14854348760 ps
CPU time 13.18 seconds
Started Jul 22 04:59:24 PM PDT 24
Finished Jul 22 04:59:38 PM PDT 24
Peak memory 231220 kb
Host smart-8d4d3a77-d6a3-46ff-98c7-8229bda5af45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363439377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3363439377
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3151059313
Short name T342
Test name
Test status
Simulation time 374303541 ps
CPU time 11.7 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:45 PM PDT 24
Peak memory 241448 kb
Host smart-f5c42128-2af3-4220-8abd-460292fdbc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151059313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3151059313
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.2886508371
Short name T345
Test name
Test status
Simulation time 51012111 ps
CPU time 1.08 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:37 PM PDT 24
Peak memory 217340 kb
Host smart-99ed582f-dc66-44a5-bcbd-8dacf4bc80bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886508371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.2886508371
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.791181293
Short name T951
Test name
Test status
Simulation time 2717942579 ps
CPU time 4.36 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:37 PM PDT 24
Peak memory 233668 kb
Host smart-863703c2-e783-45aa-9520-865b89f0114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791181293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
791181293
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.683529604
Short name T994
Test name
Test status
Simulation time 1954500155 ps
CPU time 7.05 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:41 PM PDT 24
Peak memory 233560 kb
Host smart-d6fa167a-e081-48e2-9199-934a43f09476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683529604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.683529604
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3658468720
Short name T768
Test name
Test status
Simulation time 460435224 ps
CPU time 4.27 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:22 PM PDT 24
Peak memory 222736 kb
Host smart-b7941454-6584-42b7-960b-8e31b36994ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3658468720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3658468720
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1314036415
Short name T29
Test name
Test status
Simulation time 185149415 ps
CPU time 1.15 seconds
Started Jul 22 04:57:37 PM PDT 24
Finished Jul 22 04:57:38 PM PDT 24
Peak memory 235896 kb
Host smart-e1df0b9d-29da-4eae-ab2c-de02a4a5e07a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314036415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1314036415
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2721647397
Short name T208
Test name
Test status
Simulation time 22387382745 ps
CPU time 113.62 seconds
Started Jul 22 04:57:40 PM PDT 24
Finished Jul 22 04:59:35 PM PDT 24
Peak memory 272912 kb
Host smart-9bef10b1-9e4f-4c8c-b03f-d59b8027e81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721647397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2721647397
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3809782466
Short name T1020
Test name
Test status
Simulation time 2153062159 ps
CPU time 21.6 seconds
Started Jul 22 04:57:38 PM PDT 24
Finished Jul 22 04:58:00 PM PDT 24
Peak memory 216680 kb
Host smart-6accc385-fab7-43cf-9e76-f1ec3d7fdc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809782466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3809782466
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3458821412
Short name T574
Test name
Test status
Simulation time 17917913080 ps
CPU time 13.78 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:48 PM PDT 24
Peak memory 217188 kb
Host smart-15b2ea6f-fea0-4f17-8924-52354eb626e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458821412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3458821412
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2894086086
Short name T641
Test name
Test status
Simulation time 64310179 ps
CPU time 1.61 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:36 PM PDT 24
Peak memory 217056 kb
Host smart-f636bff3-109a-47a0-8f85-516dae38a511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894086086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2894086086
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1167716305
Short name T329
Test name
Test status
Simulation time 342343817 ps
CPU time 0.93 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:08 PM PDT 24
Peak memory 207076 kb
Host smart-86104bf6-1c2b-43c4-b2be-b91021d45c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167716305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1167716305
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4021465262
Short name T731
Test name
Test status
Simulation time 726907527 ps
CPU time 7.3 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:42 PM PDT 24
Peak memory 233600 kb
Host smart-c84a7082-989d-4ae4-b41b-f097e8d3d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021465262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4021465262
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1985989359
Short name T817
Test name
Test status
Simulation time 11902706 ps
CPU time 0.73 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 205432 kb
Host smart-228753f5-8e8b-4f51-8ac7-03a7399e7303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985989359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1985989359
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.170832915
Short name T769
Test name
Test status
Simulation time 79875986 ps
CPU time 2.25 seconds
Started Jul 22 05:00:51 PM PDT 24
Finished Jul 22 05:00:54 PM PDT 24
Peak memory 225300 kb
Host smart-c1e5b944-16af-4fde-987d-8413fcdf9ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170832915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.170832915
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.814983036
Short name T776
Test name
Test status
Simulation time 49780497 ps
CPU time 0.79 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 207248 kb
Host smart-e62c1a6f-8029-400f-aac0-232cc9b0ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814983036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.814983036
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.188225154
Short name T883
Test name
Test status
Simulation time 9821396789 ps
CPU time 35.77 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:01:23 PM PDT 24
Peak memory 252420 kb
Host smart-ee58edb4-aebb-4afb-b836-8fbbed0c86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188225154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.188225154
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1052930661
Short name T615
Test name
Test status
Simulation time 6707633416 ps
CPU time 107.65 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:02:35 PM PDT 24
Peak memory 254188 kb
Host smart-f3a16326-76df-465e-b885-2c043eb35cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052930661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1052930661
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2893176020
Short name T295
Test name
Test status
Simulation time 9331910840 ps
CPU time 98.23 seconds
Started Jul 22 05:00:45 PM PDT 24
Finished Jul 22 05:02:24 PM PDT 24
Peak memory 254416 kb
Host smart-81aa37da-65ea-492d-9e87-f068ec89b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893176020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2893176020
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3932791750
Short name T737
Test name
Test status
Simulation time 151980364 ps
CPU time 7.72 seconds
Started Jul 22 05:00:50 PM PDT 24
Finished Jul 22 05:00:58 PM PDT 24
Peak memory 250340 kb
Host smart-b52001ab-4c1b-43dd-9959-0515def298d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932791750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3932791750
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3791963495
Short name T922
Test name
Test status
Simulation time 4423843129 ps
CPU time 84.76 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:02:18 PM PDT 24
Peak memory 272528 kb
Host smart-238ee727-b543-4934-95ee-747700766098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791963495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3791963495
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1942841082
Short name T789
Test name
Test status
Simulation time 144236205 ps
CPU time 3.49 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:50 PM PDT 24
Peak memory 233544 kb
Host smart-f83da6c3-ddc9-4caa-abd9-fd9cdf211e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942841082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1942841082
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.664210168
Short name T408
Test name
Test status
Simulation time 21082652938 ps
CPU time 29.72 seconds
Started Jul 22 05:00:48 PM PDT 24
Finished Jul 22 05:01:18 PM PDT 24
Peak memory 233600 kb
Host smart-92f9ce64-9dbe-4544-b14b-16eddd394bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664210168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.664210168
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1397280497
Short name T741
Test name
Test status
Simulation time 215855082 ps
CPU time 3.07 seconds
Started Jul 22 05:00:47 PM PDT 24
Finished Jul 22 05:00:51 PM PDT 24
Peak memory 233556 kb
Host smart-5bb4ac18-37cc-413b-9390-eb97564a876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397280497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1397280497
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.232352104
Short name T571
Test name
Test status
Simulation time 22549118647 ps
CPU time 16.95 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 233692 kb
Host smart-4288dcba-51af-4d27-bb2a-18101c80dd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232352104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.232352104
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4002340255
Short name T354
Test name
Test status
Simulation time 8212922009 ps
CPU time 13.06 seconds
Started Jul 22 05:04:53 PM PDT 24
Finished Jul 22 05:05:07 PM PDT 24
Peak memory 220840 kb
Host smart-fdf53a9f-d58c-4057-9f5f-1b9bbed10756
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4002340255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4002340255
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1150581512
Short name T276
Test name
Test status
Simulation time 84106711618 ps
CPU time 825.91 seconds
Started Jul 22 05:00:49 PM PDT 24
Finished Jul 22 05:14:35 PM PDT 24
Peak memory 274752 kb
Host smart-e49089e8-24d7-402d-9de5-4598e8375c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150581512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1150581512
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2761863934
Short name T572
Test name
Test status
Simulation time 18260398 ps
CPU time 0.71 seconds
Started Jul 22 05:00:44 PM PDT 24
Finished Jul 22 05:00:45 PM PDT 24
Peak memory 206348 kb
Host smart-984ade9b-10af-4468-befb-0b56f1ddbc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761863934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2761863934
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3634306516
Short name T328
Test name
Test status
Simulation time 36467989 ps
CPU time 0.73 seconds
Started Jul 22 05:00:45 PM PDT 24
Finished Jul 22 05:00:47 PM PDT 24
Peak memory 206384 kb
Host smart-342d91c2-b29a-46bf-94d0-a022ed2c4e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634306516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3634306516
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3516960991
Short name T472
Test name
Test status
Simulation time 23609854 ps
CPU time 0.71 seconds
Started Jul 22 05:00:44 PM PDT 24
Finished Jul 22 05:00:45 PM PDT 24
Peak memory 206768 kb
Host smart-5212a611-c576-48b8-a852-9b15a469857d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516960991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3516960991
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3422638481
Short name T347
Test name
Test status
Simulation time 93722219 ps
CPU time 0.79 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:48 PM PDT 24
Peak memory 206664 kb
Host smart-7e91a0d0-0641-49d2-a66f-2db2aec8b763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422638481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3422638481
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1158300000
Short name T404
Test name
Test status
Simulation time 4041351675 ps
CPU time 9.3 seconds
Started Jul 22 05:00:46 PM PDT 24
Finished Jul 22 05:00:56 PM PDT 24
Peak memory 234684 kb
Host smart-86595a3a-8870-4e09-a249-a31b0094b8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158300000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1158300000
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1699404305
Short name T410
Test name
Test status
Simulation time 121350434 ps
CPU time 0.69 seconds
Started Jul 22 05:00:58 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 205948 kb
Host smart-e6507688-7c2b-440b-9535-9a297249805b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699404305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1699404305
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.463623984
Short name T1003
Test name
Test status
Simulation time 519510455 ps
CPU time 5.91 seconds
Started Jul 22 05:04:58 PM PDT 24
Finished Jul 22 05:05:04 PM PDT 24
Peak memory 233556 kb
Host smart-ff759ded-3502-4830-9789-76a1f6134a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463623984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.463623984
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1418583803
Short name T439
Test name
Test status
Simulation time 26000814 ps
CPU time 0.74 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:00:54 PM PDT 24
Peak memory 207508 kb
Host smart-a46e7478-f506-4f6b-8723-d267856f5527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418583803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1418583803
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1952506407
Short name T223
Test name
Test status
Simulation time 38917002151 ps
CPU time 274.98 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:05:33 PM PDT 24
Peak memory 257184 kb
Host smart-02b95197-5312-43fd-bcb3-76cf6540bca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952506407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1952506407
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.914671307
Short name T1016
Test name
Test status
Simulation time 20295115651 ps
CPU time 110.4 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:02:44 PM PDT 24
Peak memory 258360 kb
Host smart-e305673c-e8ba-4c25-834b-c15533c41cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914671307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.914671307
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1278137235
Short name T485
Test name
Test status
Simulation time 3487343691 ps
CPU time 10.06 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:06 PM PDT 24
Peak memory 233728 kb
Host smart-8818af27-6e8d-47e6-b02f-5e944cf7e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278137235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1278137235
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.648604170
Short name T782
Test name
Test status
Simulation time 327359097 ps
CPU time 0.88 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:00:58 PM PDT 24
Peak memory 216900 kb
Host smart-405622f7-5113-4eb4-8e22-48e78b806872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648604170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.648604170
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.175869752
Short name T699
Test name
Test status
Simulation time 240201526 ps
CPU time 3.88 seconds
Started Jul 22 05:04:58 PM PDT 24
Finished Jul 22 05:05:02 PM PDT 24
Peak memory 225384 kb
Host smart-0f96d252-e89a-4e70-a8c7-df99c79cbf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175869752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.175869752
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3566408423
Short name T770
Test name
Test status
Simulation time 606379333 ps
CPU time 8.36 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:01:02 PM PDT 24
Peak memory 225424 kb
Host smart-1e1b64f3-53bf-45d3-b4de-f4003137636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566408423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3566408423
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3657949076
Short name T694
Test name
Test status
Simulation time 10799814995 ps
CPU time 8.92 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:05 PM PDT 24
Peak memory 225472 kb
Host smart-5c9620e3-f3c6-4355-abf1-e529fc48319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657949076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3657949076
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1102041412
Short name T456
Test name
Test status
Simulation time 31503729 ps
CPU time 2.37 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:00:57 PM PDT 24
Peak memory 233172 kb
Host smart-36d5fa5d-651f-4edd-978c-c72a116b697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102041412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1102041412
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.310988212
Short name T376
Test name
Test status
Simulation time 4368517814 ps
CPU time 13.76 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:09 PM PDT 24
Peak memory 219588 kb
Host smart-8dc45143-16c4-41d2-a559-d6fe1693292b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=310988212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.310988212
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2018623191
Short name T299
Test name
Test status
Simulation time 4312348250 ps
CPU time 29.41 seconds
Started Jul 22 05:04:53 PM PDT 24
Finished Jul 22 05:05:23 PM PDT 24
Peak memory 217144 kb
Host smart-7b91894c-5e39-4399-b73c-9efdcdbb9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018623191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2018623191
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.24186935
Short name T74
Test name
Test status
Simulation time 8070589148 ps
CPU time 20.74 seconds
Started Jul 22 05:00:53 PM PDT 24
Finished Jul 22 05:01:14 PM PDT 24
Peak memory 217100 kb
Host smart-00f273ed-90d5-4aaf-978f-cf3508682a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24186935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.24186935
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3518970866
Short name T905
Test name
Test status
Simulation time 47224514 ps
CPU time 0.67 seconds
Started Jul 22 05:00:52 PM PDT 24
Finished Jul 22 05:00:53 PM PDT 24
Peak memory 206204 kb
Host smart-d9026d22-308c-4e4a-8d69-a310d6cd390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518970866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3518970866
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.148354615
Short name T380
Test name
Test status
Simulation time 365821868 ps
CPU time 0.98 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:00:56 PM PDT 24
Peak memory 206684 kb
Host smart-b3daf1f5-7d75-4878-a1b1-5dd696d5697a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148354615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.148354615
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.583277626
Short name T55
Test name
Test status
Simulation time 1662327871 ps
CPU time 6.34 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:01:01 PM PDT 24
Peak memory 233688 kb
Host smart-148414d2-3f83-4a47-bbce-7227d34a5cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583277626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.583277626
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3634549293
Short name T587
Test name
Test status
Simulation time 70712482 ps
CPU time 0.71 seconds
Started Jul 22 05:01:07 PM PDT 24
Finished Jul 22 05:01:09 PM PDT 24
Peak memory 205472 kb
Host smart-ba6c1497-5707-41ce-b2d5-bd808d28c67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634549293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3634549293
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.726441825
Short name T832
Test name
Test status
Simulation time 1235749138 ps
CPU time 9.5 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:05 PM PDT 24
Peak memory 233576 kb
Host smart-cb1ea6c1-627a-4358-90e2-1e879be1a9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726441825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.726441825
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3535803032
Short name T442
Test name
Test status
Simulation time 45070795 ps
CPU time 0.72 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:00:58 PM PDT 24
Peak memory 206552 kb
Host smart-aff688e9-67eb-4933-8ecf-a9bec74bfd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535803032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3535803032
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.985826426
Short name T191
Test name
Test status
Simulation time 11263148347 ps
CPU time 64.75 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:02:01 PM PDT 24
Peak memory 250072 kb
Host smart-c11d7b09-ec73-421c-8484-118dc6245a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985826426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.985826426
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3048140245
Short name T273
Test name
Test status
Simulation time 7562582948 ps
CPU time 43.39 seconds
Started Jul 22 05:00:59 PM PDT 24
Finished Jul 22 05:01:43 PM PDT 24
Peak memory 252852 kb
Host smart-0cd661bd-e237-4735-8fc7-c4d1d82af191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048140245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3048140245
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1434360623
Short name T426
Test name
Test status
Simulation time 524750660 ps
CPU time 3.36 seconds
Started Jul 22 05:00:59 PM PDT 24
Finished Jul 22 05:01:03 PM PDT 24
Peak memory 225416 kb
Host smart-5ab9366d-4ae5-4275-aa2a-d63f030cbe33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434360623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1434360623
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.626364338
Short name T949
Test name
Test status
Simulation time 5268371408 ps
CPU time 68.24 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:02:05 PM PDT 24
Peak memory 250120 kb
Host smart-1012af3b-f78e-410c-ad36-a1de972ee1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626364338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.626364338
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1919446041
Short name T1025
Test name
Test status
Simulation time 177368733 ps
CPU time 2.88 seconds
Started Jul 22 05:00:56 PM PDT 24
Finished Jul 22 05:00:59 PM PDT 24
Peak memory 233572 kb
Host smart-f58c0d14-71b0-4ebf-bb4a-acb02aefafdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919446041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1919446041
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4126077088
Short name T9
Test name
Test status
Simulation time 100206926 ps
CPU time 3.77 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:01:02 PM PDT 24
Peak memory 233500 kb
Host smart-ddbad0bb-975e-40af-a0d6-ca0310eb8701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126077088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4126077088
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2647723070
Short name T717
Test name
Test status
Simulation time 5142849014 ps
CPU time 14.83 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:01:09 PM PDT 24
Peak memory 240480 kb
Host smart-1699e142-07c1-4045-a624-c616f2a9bf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647723070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2647723070
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2171744939
Short name T383
Test name
Test status
Simulation time 7632086817 ps
CPU time 11.72 seconds
Started Jul 22 05:00:52 PM PDT 24
Finished Jul 22 05:01:05 PM PDT 24
Peak memory 249860 kb
Host smart-cf0bfa64-e58b-48d4-b3db-83d0ed04ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171744939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2171744939
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1914353057
Short name T139
Test name
Test status
Simulation time 3615659783 ps
CPU time 7.98 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 222800 kb
Host smart-62c7bf8c-20d7-4fe0-9522-a270c4b35d85
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1914353057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1914353057
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.381238313
Short name T428
Test name
Test status
Simulation time 67615620 ps
CPU time 1.16 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:06 PM PDT 24
Peak memory 207480 kb
Host smart-932bf682-20e3-4e52-9df6-568ec43b364e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381238313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.381238313
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1283774533
Short name T373
Test name
Test status
Simulation time 2930567467 ps
CPU time 17.59 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:01:13 PM PDT 24
Peak memory 217156 kb
Host smart-dd4d11ca-3c76-43b2-8330-7e45f739ffe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283774533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1283774533
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3006522187
Short name T721
Test name
Test status
Simulation time 3842362961 ps
CPU time 13.08 seconds
Started Jul 22 05:00:54 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 217320 kb
Host smart-608eaf71-e4fd-43f8-8794-90c20e65241b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006522187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3006522187
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3628091409
Short name T929
Test name
Test status
Simulation time 18171963 ps
CPU time 0.83 seconds
Started Jul 22 05:00:55 PM PDT 24
Finished Jul 22 05:00:56 PM PDT 24
Peak memory 207256 kb
Host smart-a66440d3-134c-4a95-ab6d-226eb6ba851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628091409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3628091409
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.260953600
Short name T662
Test name
Test status
Simulation time 43520243 ps
CPU time 0.67 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:00:58 PM PDT 24
Peak memory 206620 kb
Host smart-499cab11-e8a1-4bb9-970e-27300efc4273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260953600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.260953600
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.752929777
Short name T753
Test name
Test status
Simulation time 27828683241 ps
CPU time 21.38 seconds
Started Jul 22 05:00:57 PM PDT 24
Finished Jul 22 05:01:20 PM PDT 24
Peak memory 249828 kb
Host smart-1bc8f3f7-22a2-443a-92fa-aa7616a1cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752929777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.752929777
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1910729912
Short name T475
Test name
Test status
Simulation time 185958007 ps
CPU time 0.73 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:06 PM PDT 24
Peak memory 205724 kb
Host smart-99f79e80-ff79-4581-99b8-b0329ecff1ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910729912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1910729912
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.802084541
Short name T754
Test name
Test status
Simulation time 1088468093 ps
CPU time 10.94 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:18 PM PDT 24
Peak memory 233548 kb
Host smart-1ca0f3e4-40b9-4825-95f8-3a0f314600f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802084541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.802084541
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3274225213
Short name T579
Test name
Test status
Simulation time 40623693 ps
CPU time 0.8 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:05 PM PDT 24
Peak memory 207184 kb
Host smart-facb16d6-6a5b-494c-949f-47847be46ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274225213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3274225213
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1366126458
Short name T493
Test name
Test status
Simulation time 282567194215 ps
CPU time 226.3 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:04:53 PM PDT 24
Peak memory 259672 kb
Host smart-afccc38b-d7db-42eb-88f4-7ba9f9ace317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366126458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1366126458
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4067537214
Short name T246
Test name
Test status
Simulation time 46512741980 ps
CPU time 103.38 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:02:49 PM PDT 24
Peak memory 254672 kb
Host smart-f77f210d-6635-4843-b0f8-f87921f6e06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067537214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4067537214
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4002891117
Short name T300
Test name
Test status
Simulation time 11736133622 ps
CPU time 16.08 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:21 PM PDT 24
Peak memory 218548 kb
Host smart-10351d0e-5065-4821-9d08-180ac1554cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002891117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4002891117
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.326780670
Short name T137
Test name
Test status
Simulation time 3113139621 ps
CPU time 16.11 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:23 PM PDT 24
Peak memory 251508 kb
Host smart-82d6765e-a391-4484-9d08-cb2852a5a636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326780670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.326780670
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.925212291
Short name T196
Test name
Test status
Simulation time 202537246 ps
CPU time 5.7 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:10 PM PDT 24
Peak memory 225408 kb
Host smart-849290b6-2886-4aeb-80a6-ad3c21f6a4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925212291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.925212291
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.171815185
Short name T195
Test name
Test status
Simulation time 243192737 ps
CPU time 3.8 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:10 PM PDT 24
Peak memory 225404 kb
Host smart-5a90eef3-ca49-4166-b71d-1a83ee4309f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171815185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.171815185
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2859567136
Short name T723
Test name
Test status
Simulation time 16100056001 ps
CPU time 15.28 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:22 PM PDT 24
Peak memory 233580 kb
Host smart-ffed1b2b-aaeb-4152-8aec-fb2b13d09500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859567136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2859567136
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2460846309
Short name T663
Test name
Test status
Simulation time 31621229406 ps
CPU time 12.81 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:20 PM PDT 24
Peak memory 241164 kb
Host smart-42ae2bad-9ca3-40af-80b1-d9d69a23b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460846309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2460846309
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1301452050
Short name T674
Test name
Test status
Simulation time 86286301 ps
CPU time 3.47 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 222832 kb
Host smart-8a404cee-d0ac-4e36-a6fb-f73519233a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1301452050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1301452050
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3016370900
Short name T692
Test name
Test status
Simulation time 108993749 ps
CPU time 1 seconds
Started Jul 22 05:01:07 PM PDT 24
Finished Jul 22 05:01:09 PM PDT 24
Peak memory 207348 kb
Host smart-7757cbdb-0783-423a-81b0-f3ebf0dd37a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016370900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3016370900
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3152103094
Short name T750
Test name
Test status
Simulation time 3565357436 ps
CPU time 19.09 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 217340 kb
Host smart-c8fb5ae4-b2cf-4182-a2b2-8be50a3840f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152103094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3152103094
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3482219425
Short name T798
Test name
Test status
Simulation time 1277857228 ps
CPU time 2.6 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 217132 kb
Host smart-7aa94246-3677-4360-92d2-de9701a99b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482219425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3482219425
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3200706087
Short name T666
Test name
Test status
Simulation time 58303651 ps
CPU time 1.18 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 216876 kb
Host smart-e60b3f26-f6f0-40d0-b356-3282df922e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200706087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3200706087
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3906263160
Short name T931
Test name
Test status
Simulation time 19640011 ps
CPU time 0.73 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:06 PM PDT 24
Peak memory 206756 kb
Host smart-a38408e7-20bb-4157-9fdf-86e22a4eb796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906263160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3906263160
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.17357395
Short name T640
Test name
Test status
Simulation time 6325706356 ps
CPU time 18.73 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 233676 kb
Host smart-ad5392a1-39b5-4e3d-800d-682fd1de217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17357395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.17357395
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.972010131
Short name T953
Test name
Test status
Simulation time 25446650 ps
CPU time 0.74 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:01:22 PM PDT 24
Peak memory 206116 kb
Host smart-838df80d-0f53-49f9-9380-fe22f43297bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972010131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.972010131
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1738119401
Short name T227
Test name
Test status
Simulation time 253602931 ps
CPU time 4.11 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:23 PM PDT 24
Peak memory 225356 kb
Host smart-aad534bc-228d-4558-b3fc-58d1a5d21d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738119401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1738119401
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.660502181
Short name T671
Test name
Test status
Simulation time 20545966 ps
CPU time 0.79 seconds
Started Jul 22 05:01:06 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 207132 kb
Host smart-934e5042-fffe-4421-9832-bab410493ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660502181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.660502181
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4097255215
Short name T513
Test name
Test status
Simulation time 27384729312 ps
CPU time 181.4 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:04:20 PM PDT 24
Peak memory 256236 kb
Host smart-8d242e15-0328-496b-91bb-026e9d28f126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097255215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4097255215
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3095764834
Short name T909
Test name
Test status
Simulation time 31298285612 ps
CPU time 259.59 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:05:38 PM PDT 24
Peak memory 250164 kb
Host smart-2b6112cc-f5e5-40e7-8da2-c4423f4662cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095764834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3095764834
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.86231949
Short name T824
Test name
Test status
Simulation time 19987518689 ps
CPU time 136.91 seconds
Started Jul 22 05:03:32 PM PDT 24
Finished Jul 22 05:05:49 PM PDT 24
Peak memory 253820 kb
Host smart-2cf8878e-3b98-405e-a736-390ac950fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86231949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.86231949
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3838059306
Short name T704
Test name
Test status
Simulation time 214220834 ps
CPU time 4.27 seconds
Started Jul 22 05:01:16 PM PDT 24
Finished Jul 22 05:01:21 PM PDT 24
Peak memory 233636 kb
Host smart-204b4de6-9486-4faf-ace1-9e5ecf82db04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838059306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3838059306
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3006237663
Short name T401
Test name
Test status
Simulation time 1202241305 ps
CPU time 12.93 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:17 PM PDT 24
Peak memory 233524 kb
Host smart-264a0e63-cde2-415d-9b86-2d9537a87fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006237663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3006237663
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1559180673
Short name T583
Test name
Test status
Simulation time 94438870384 ps
CPU time 49.26 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:55 PM PDT 24
Peak memory 233688 kb
Host smart-b30ca2a1-c695-41b7-a6b0-84b021ba2742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559180673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1559180673
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1665238411
Short name T952
Test name
Test status
Simulation time 49778550954 ps
CPU time 17.43 seconds
Started Jul 22 05:01:07 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 239276 kb
Host smart-50451dec-309c-4151-8bff-07318178e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665238411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1665238411
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3578459490
Short name T939
Test name
Test status
Simulation time 7035526876 ps
CPU time 9.64 seconds
Started Jul 22 05:01:04 PM PDT 24
Finished Jul 22 05:01:14 PM PDT 24
Peak memory 233700 kb
Host smart-d6a63dd9-578c-4b3f-b870-de5d83241de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578459490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3578459490
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3661684033
Short name T399
Test name
Test status
Simulation time 863798909 ps
CPU time 4.06 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:22 PM PDT 24
Peak memory 220448 kb
Host smart-dea1d7ef-8528-46e6-9138-83da740d9f3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3661684033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3661684033
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3957602793
Short name T706
Test name
Test status
Simulation time 58840070531 ps
CPU time 181.18 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:04:22 PM PDT 24
Peak memory 272172 kb
Host smart-7c25a80f-3890-4200-acd9-824e599d5989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957602793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3957602793
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2121930181
Short name T924
Test name
Test status
Simulation time 22544128 ps
CPU time 0.67 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:06 PM PDT 24
Peak memory 206288 kb
Host smart-d6a42d73-19aa-490b-93c2-23d94720834c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121930181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2121930181
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.967277870
Short name T697
Test name
Test status
Simulation time 9876405053 ps
CPU time 8.88 seconds
Started Jul 22 05:01:05 PM PDT 24
Finished Jul 22 05:01:15 PM PDT 24
Peak memory 217244 kb
Host smart-8f279300-1450-4ce1-a6b0-b153f947f0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967277870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.967277870
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.285162942
Short name T326
Test name
Test status
Simulation time 40050147 ps
CPU time 0.7 seconds
Started Jul 22 05:01:03 PM PDT 24
Finished Jul 22 05:01:04 PM PDT 24
Peak memory 206180 kb
Host smart-de4681a2-687e-4296-881f-6e9a5acee0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285162942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.285162942
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4078996636
Short name T318
Test name
Test status
Simulation time 52586273 ps
CPU time 0.82 seconds
Started Jul 22 05:01:07 PM PDT 24
Finished Jul 22 05:01:08 PM PDT 24
Peak memory 206616 kb
Host smart-fde943e8-463c-4380-88c5-ff5331d5b760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078996636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4078996636
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4240265
Short name T436
Test name
Test status
Simulation time 515148702 ps
CPU time 3.27 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 225372 kb
Host smart-68534aac-5553-4541-95bc-c1c842cf198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4240265
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3825037709
Short name T686
Test name
Test status
Simulation time 30550229 ps
CPU time 0.74 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:19 PM PDT 24
Peak memory 205392 kb
Host smart-5087987b-b95d-428e-844f-143b9f38b450
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825037709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3825037709
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3219562860
Short name T742
Test name
Test status
Simulation time 11202477331 ps
CPU time 21.47 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:40 PM PDT 24
Peak memory 225504 kb
Host smart-6dad4364-e965-4f86-bd32-d5774fd06589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219562860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3219562860
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1393083912
Short name T562
Test name
Test status
Simulation time 19552858 ps
CPU time 0.82 seconds
Started Jul 22 05:04:13 PM PDT 24
Finished Jul 22 05:04:15 PM PDT 24
Peak memory 207460 kb
Host smart-f5ec9db1-52fd-42ee-8681-dc3530981124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393083912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1393083912
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.365110629
Short name T656
Test name
Test status
Simulation time 2610543779 ps
CPU time 53.71 seconds
Started Jul 22 05:01:16 PM PDT 24
Finished Jul 22 05:02:10 PM PDT 24
Peak memory 255672 kb
Host smart-1dc38312-6f82-4403-b176-66bfc53b688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365110629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.365110629
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1365479776
Short name T802
Test name
Test status
Simulation time 68501879287 ps
CPU time 664.91 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:12:23 PM PDT 24
Peak memory 263780 kb
Host smart-524019ec-c488-430a-a890-ec413f3d3445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365479776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1365479776
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.397813637
Short name T415
Test name
Test status
Simulation time 12358665884 ps
CPU time 132.71 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:03:34 PM PDT 24
Peak memory 250068 kb
Host smart-f8467f32-56a5-45ec-a925-e6b845fe4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397813637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.397813637
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4259280360
Short name T1017
Test name
Test status
Simulation time 721157784 ps
CPU time 4.92 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:23 PM PDT 24
Peak memory 225684 kb
Host smart-71e66a81-1d82-4bfb-8c26-fe9d8ec67752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259280360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4259280360
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1557544455
Short name T450
Test name
Test status
Simulation time 88973822 ps
CPU time 2.31 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:21 PM PDT 24
Peak memory 225392 kb
Host smart-02e31657-d446-43da-87ef-c98cec5168ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557544455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1557544455
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1471013508
Short name T828
Test name
Test status
Simulation time 523320371 ps
CPU time 9.3 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:01:31 PM PDT 24
Peak memory 233524 kb
Host smart-deafc981-bdf2-4b3d-9ec9-6f29a5a3ab64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471013508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1471013508
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.650533603
Short name T392
Test name
Test status
Simulation time 506238779 ps
CPU time 5.98 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:25 PM PDT 24
Peak memory 233652 kb
Host smart-4629abe2-df32-402c-b53a-6a689d0d27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650533603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.650533603
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3367517993
Short name T872
Test name
Test status
Simulation time 5793104315 ps
CPU time 8.2 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:27 PM PDT 24
Peak memory 225428 kb
Host smart-1df4f21f-ddcd-4701-885a-294e3b5ffbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367517993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3367517993
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.144154506
Short name T675
Test name
Test status
Simulation time 947843397 ps
CPU time 6.48 seconds
Started Jul 22 05:03:32 PM PDT 24
Finished Jul 22 05:03:39 PM PDT 24
Peak memory 223092 kb
Host smart-5aeefe38-c21e-4e24-87b4-1a06bb5fe5ac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=144154506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.144154506
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1941004891
Short name T891
Test name
Test status
Simulation time 40205904840 ps
CPU time 110.84 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:03:09 PM PDT 24
Peak memory 240592 kb
Host smart-54db91f1-71c9-4a94-b882-e0dfc9c82f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941004891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1941004891
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.690721594
Short name T934
Test name
Test status
Simulation time 8630419829 ps
CPU time 17.92 seconds
Started Jul 22 05:03:41 PM PDT 24
Finished Jul 22 05:04:01 PM PDT 24
Peak memory 217276 kb
Host smart-b86cd88d-11f1-4917-9277-23ae8bc1e875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690721594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.690721594
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2275834110
Short name T946
Test name
Test status
Simulation time 906410718 ps
CPU time 3.69 seconds
Started Jul 22 05:01:18 PM PDT 24
Finished Jul 22 05:01:22 PM PDT 24
Peak memory 217212 kb
Host smart-f52b1b35-5487-4eac-ac87-b2a2b24a537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275834110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2275834110
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1163227075
Short name T943
Test name
Test status
Simulation time 79983904 ps
CPU time 1.55 seconds
Started Jul 22 05:01:16 PM PDT 24
Finished Jul 22 05:01:18 PM PDT 24
Peak memory 217116 kb
Host smart-39d3af56-3719-4e00-ae27-6fd686ff9579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163227075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1163227075
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.70454217
Short name T718
Test name
Test status
Simulation time 14243313 ps
CPU time 0.74 seconds
Started Jul 22 05:01:21 PM PDT 24
Finished Jul 22 05:01:23 PM PDT 24
Peak memory 206808 kb
Host smart-cd11c256-3971-4e12-9238-f355670ea6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70454217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.70454217
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3656024636
Short name T856
Test name
Test status
Simulation time 166438484 ps
CPU time 2.27 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:20 PM PDT 24
Peak memory 225364 kb
Host smart-afa7a268-3b33-4601-8928-4cad22d02810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656024636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3656024636
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3569045451
Short name T444
Test name
Test status
Simulation time 31318934 ps
CPU time 0.78 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 206072 kb
Host smart-4a7c6321-5dc3-4eb5-8b05-8912010441c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569045451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3569045451
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1354126829
Short name T504
Test name
Test status
Simulation time 117825281 ps
CPU time 3.3 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 225592 kb
Host smart-a7e7fa1a-6c7a-49c7-a09d-d258f76ae757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354126829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1354126829
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1178189167
Short name T650
Test name
Test status
Simulation time 52271766 ps
CPU time 0.8 seconds
Started Jul 22 05:04:13 PM PDT 24
Finished Jul 22 05:04:15 PM PDT 24
Peak memory 207440 kb
Host smart-81fb6d97-3cf9-4748-afa4-39dbfaa05833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178189167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1178189167
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1674828396
Short name T220
Test name
Test status
Simulation time 20246312804 ps
CPU time 216.05 seconds
Started Jul 22 05:01:29 PM PDT 24
Finished Jul 22 05:05:06 PM PDT 24
Peak memory 263468 kb
Host smart-69ce9437-64df-43c9-8677-6a4356f723be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674828396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1674828396
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3588324943
Short name T698
Test name
Test status
Simulation time 2344908069 ps
CPU time 16.33 seconds
Started Jul 22 05:01:27 PM PDT 24
Finished Jul 22 05:01:44 PM PDT 24
Peak memory 240692 kb
Host smart-1e1902db-6979-491b-b7dc-60d4c407e751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588324943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3588324943
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3303895015
Short name T200
Test name
Test status
Simulation time 95696523714 ps
CPU time 265.87 seconds
Started Jul 22 05:01:33 PM PDT 24
Finished Jul 22 05:06:00 PM PDT 24
Peak memory 255020 kb
Host smart-0256c3e1-e5a8-4131-9d5a-86dd45d68d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303895015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3303895015
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.676141832
Short name T821
Test name
Test status
Simulation time 211328593 ps
CPU time 7.25 seconds
Started Jul 22 05:01:58 PM PDT 24
Finished Jul 22 05:02:07 PM PDT 24
Peak memory 233564 kb
Host smart-cd345333-5115-44da-a5e6-3ab71cd0f327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676141832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.676141832
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1928139025
Short name T233
Test name
Test status
Simulation time 288466999124 ps
CPU time 465.56 seconds
Started Jul 22 05:01:33 PM PDT 24
Finished Jul 22 05:09:20 PM PDT 24
Peak memory 265672 kb
Host smart-012ab6e2-62c9-4af0-b744-2438b3a25526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928139025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1928139025
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2301130049
Short name T607
Test name
Test status
Simulation time 936850511 ps
CPU time 8.37 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:01:42 PM PDT 24
Peak memory 225340 kb
Host smart-ae04e70a-6535-4c6e-b634-3a5257fc99ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301130049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2301130049
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2830979188
Short name T252
Test name
Test status
Simulation time 844243842 ps
CPU time 14.06 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:46 PM PDT 24
Peak memory 233640 kb
Host smart-8f4b5ba9-a072-4466-9ae5-7f64e68337cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830979188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2830979188
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2230128970
Short name T885
Test name
Test status
Simulation time 23575395151 ps
CPU time 19.42 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:01:52 PM PDT 24
Peak memory 233600 kb
Host smart-f8e0ee46-64c4-4036-b8be-46754141c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230128970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2230128970
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2027112103
Short name T971
Test name
Test status
Simulation time 1960778230 ps
CPU time 4.23 seconds
Started Jul 22 05:01:28 PM PDT 24
Finished Jul 22 05:01:33 PM PDT 24
Peak memory 225340 kb
Host smart-a5c7a572-e3fd-4daf-9353-f183b91a5093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027112103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2027112103
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3181416453
Short name T945
Test name
Test status
Simulation time 988421493 ps
CPU time 5.58 seconds
Started Jul 22 05:06:30 PM PDT 24
Finished Jul 22 05:06:37 PM PDT 24
Peak memory 223792 kb
Host smart-6024ee24-f0eb-4ccd-a0b1-105a921a1331
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3181416453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3181416453
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.929880267
Short name T866
Test name
Test status
Simulation time 177311620 ps
CPU time 1.12 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:31 PM PDT 24
Peak memory 207828 kb
Host smart-e901efce-efb6-4a57-9797-251e8b071317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929880267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.929880267
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4055584827
Short name T301
Test name
Test status
Simulation time 27167580971 ps
CPU time 39.76 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:57 PM PDT 24
Peak memory 217112 kb
Host smart-ff49be96-dfbc-4c3f-83cf-8c35f472b082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055584827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4055584827
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1879827599
Short name T667
Test name
Test status
Simulation time 2635169919 ps
CPU time 3.49 seconds
Started Jul 22 05:01:17 PM PDT 24
Finished Jul 22 05:01:21 PM PDT 24
Peak memory 217212 kb
Host smart-b071233d-0474-4954-a681-0fe5087bbea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879827599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1879827599
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3706745841
Short name T432
Test name
Test status
Simulation time 96134715 ps
CPU time 1.42 seconds
Started Jul 22 05:01:35 PM PDT 24
Finished Jul 22 05:01:37 PM PDT 24
Peak memory 217140 kb
Host smart-bc602c83-be0e-4b55-bafd-4bc028696c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706745841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3706745841
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1414279017
Short name T960
Test name
Test status
Simulation time 61345949 ps
CPU time 0.94 seconds
Started Jul 22 05:01:20 PM PDT 24
Finished Jul 22 05:01:21 PM PDT 24
Peak memory 207756 kb
Host smart-1c1637b7-bb05-4faa-a854-581bb3cb4d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414279017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1414279017
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2267862336
Short name T957
Test name
Test status
Simulation time 351799374 ps
CPU time 2.76 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:34 PM PDT 24
Peak memory 233144 kb
Host smart-708ad25a-d6e3-4491-94dc-8975f1904eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267862336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2267862336
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3498103512
Short name T557
Test name
Test status
Simulation time 18636083 ps
CPU time 0.72 seconds
Started Jul 22 05:01:28 PM PDT 24
Finished Jul 22 05:01:29 PM PDT 24
Peak memory 205476 kb
Host smart-5c6c9e41-e120-44c8-8256-e61981cd182b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498103512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3498103512
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3665166837
Short name T982
Test name
Test status
Simulation time 2816918844 ps
CPU time 4.14 seconds
Started Jul 22 05:06:29 PM PDT 24
Finished Jul 22 05:06:36 PM PDT 24
Peak memory 233676 kb
Host smart-38a585bb-6a72-4fd5-bebe-0517d828a48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665166837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3665166837
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2961930335
Short name T340
Test name
Test status
Simulation time 41605547 ps
CPU time 0.74 seconds
Started Jul 22 05:01:29 PM PDT 24
Finished Jul 22 05:01:30 PM PDT 24
Peak memory 207244 kb
Host smart-168c1978-463e-4414-90b5-a820a8447453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961930335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2961930335
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1899320770
Short name T275
Test name
Test status
Simulation time 152238524101 ps
CPU time 252.47 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:05:43 PM PDT 24
Peak memory 258136 kb
Host smart-1f9d0040-4550-40a3-b5c4-ddb1d7be263d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899320770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1899320770
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3558983926
Short name T173
Test name
Test status
Simulation time 2394274750 ps
CPU time 46.19 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:02:19 PM PDT 24
Peak memory 238000 kb
Host smart-f0478444-de80-459a-8a01-ff251bc16690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558983926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3558983926
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2368202251
Short name T270
Test name
Test status
Simulation time 2549310215 ps
CPU time 65.39 seconds
Started Jul 22 05:01:28 PM PDT 24
Finished Jul 22 05:02:34 PM PDT 24
Peak memory 272344 kb
Host smart-bee21960-6862-4599-bf2a-c7db6d74a7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368202251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2368202251
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.909989049
Short name T647
Test name
Test status
Simulation time 238385033 ps
CPU time 6.66 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:37 PM PDT 24
Peak memory 233504 kb
Host smart-ba107510-ccc7-4291-a8c4-30492c2cfaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909989049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.909989049
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3166544622
Short name T406
Test name
Test status
Simulation time 9071410640 ps
CPU time 77.6 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:02:49 PM PDT 24
Peak memory 251828 kb
Host smart-1f0c2ce5-f96e-4794-a360-58d0f9b1a118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166544622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3166544622
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3753964374
Short name T479
Test name
Test status
Simulation time 245196506 ps
CPU time 4.62 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:37 PM PDT 24
Peak memory 233560 kb
Host smart-7fcbe8a3-f881-44f0-b619-a0dabbdf1f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753964374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3753964374
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3037966223
Short name T745
Test name
Test status
Simulation time 1150779849 ps
CPU time 16.45 seconds
Started Jul 22 05:01:33 PM PDT 24
Finished Jul 22 05:01:50 PM PDT 24
Peak memory 233624 kb
Host smart-3a11173e-59e0-4752-ab93-322f69473be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037966223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3037966223
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2463374117
Short name T420
Test name
Test status
Simulation time 23503216578 ps
CPU time 6.23 seconds
Started Jul 22 05:06:30 PM PDT 24
Finished Jul 22 05:06:37 PM PDT 24
Peak memory 225408 kb
Host smart-901eaf75-e425-4f4b-8e4f-552ccef8d8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463374117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2463374117
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.346124572
Short name T237
Test name
Test status
Simulation time 335833308 ps
CPU time 2.31 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:34 PM PDT 24
Peak memory 225412 kb
Host smart-59a06648-043c-4f71-bad1-2a249cd22f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346124572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.346124572
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3471974771
Short name T445
Test name
Test status
Simulation time 1494007622 ps
CPU time 16.77 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:01:50 PM PDT 24
Peak memory 223112 kb
Host smart-cb17053c-f46e-4ece-8973-613dee325864
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3471974771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3471974771
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.377557004
Short name T51
Test name
Test status
Simulation time 5664160441 ps
CPU time 67.18 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:02:39 PM PDT 24
Peak memory 252944 kb
Host smart-831cb22c-26af-4a9c-afc8-6531cfe65993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377557004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.377557004
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.902352120
Short name T669
Test name
Test status
Simulation time 25612027 ps
CPU time 0.72 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:32 PM PDT 24
Peak memory 206276 kb
Host smart-8e460e40-a88c-44ea-8ae5-1fc59ec5a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902352120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.902352120
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2665416644
Short name T482
Test name
Test status
Simulation time 17349795335 ps
CPU time 14.67 seconds
Started Jul 22 05:01:34 PM PDT 24
Finished Jul 22 05:01:50 PM PDT 24
Peak memory 217152 kb
Host smart-4de4ca1b-c342-4464-971b-ad91a85e004c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665416644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2665416644
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2571288940
Short name T537
Test name
Test status
Simulation time 243109559 ps
CPU time 3.62 seconds
Started Jul 22 05:01:34 PM PDT 24
Finished Jul 22 05:01:39 PM PDT 24
Peak memory 217116 kb
Host smart-21a2f532-473d-461d-95e8-37459cfe2223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571288940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2571288940
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1855615930
Short name T895
Test name
Test status
Simulation time 87004467 ps
CPU time 0.78 seconds
Started Jul 22 05:01:58 PM PDT 24
Finished Jul 22 05:02:01 PM PDT 24
Peak memory 206620 kb
Host smart-b50f96e4-e2a5-4a46-9952-9f1637122b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855615930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1855615930
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.168101763
Short name T992
Test name
Test status
Simulation time 2315641583 ps
CPU time 5.09 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:37 PM PDT 24
Peak memory 233632 kb
Host smart-aa911156-b8bd-41b2-afa0-ebeb521ad482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168101763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.168101763
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2762744314
Short name T56
Test name
Test status
Simulation time 17384603 ps
CPU time 0.75 seconds
Started Jul 22 05:06:30 PM PDT 24
Finished Jul 22 05:06:32 PM PDT 24
Peak memory 206392 kb
Host smart-3586657a-d380-43e5-aae4-3ab1ffcd746a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762744314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2762744314
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3227314336
Short name T549
Test name
Test status
Simulation time 2406116779 ps
CPU time 18.92 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:52 PM PDT 24
Peak memory 225444 kb
Host smart-83a9526d-73ea-4bda-81f1-6a5b887f700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227314336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3227314336
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.612140852
Short name T823
Test name
Test status
Simulation time 37342395 ps
CPU time 0.73 seconds
Started Jul 22 05:01:28 PM PDT 24
Finished Jul 22 05:01:29 PM PDT 24
Peak memory 206124 kb
Host smart-838546a6-9369-4696-ad3b-cb570942bf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612140852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.612140852
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3543960616
Short name T425
Test name
Test status
Simulation time 158168559 ps
CPU time 5.25 seconds
Started Jul 22 05:01:35 PM PDT 24
Finished Jul 22 05:01:42 PM PDT 24
Peak memory 225488 kb
Host smart-26bcbba8-dc8f-49a2-8882-af4929f60436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543960616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3543960616
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.920875778
Short name T744
Test name
Test status
Simulation time 12987255778 ps
CPU time 25.1 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:57 PM PDT 24
Peak memory 218572 kb
Host smart-d36dc582-2bfa-4fe3-919f-10785bdd3df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920875778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.920875778
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.809421922
Short name T267
Test name
Test status
Simulation time 19150991399 ps
CPU time 67.02 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:02:39 PM PDT 24
Peak memory 250084 kb
Host smart-9dba156c-a327-4cc9-b53f-70fadaf88eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809421922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.809421922
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.607979893
Short name T164
Test name
Test status
Simulation time 9055523088 ps
CPU time 28.16 seconds
Started Jul 22 05:01:33 PM PDT 24
Finished Jul 22 05:02:02 PM PDT 24
Peak memory 233516 kb
Host smart-739e442b-f1d2-4fe9-bd83-bfdb347a7bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607979893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.607979893
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4118670946
Short name T843
Test name
Test status
Simulation time 86670497882 ps
CPU time 93.82 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:03:04 PM PDT 24
Peak memory 237936 kb
Host smart-f5da7330-2307-4626-8ecc-a814788ef623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118670946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4118670946
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3445660569
Short name T84
Test name
Test status
Simulation time 1877681832 ps
CPU time 6.22 seconds
Started Jul 22 05:06:29 PM PDT 24
Finished Jul 22 05:06:36 PM PDT 24
Peak memory 225412 kb
Host smart-f9cecb54-e0c6-4960-a519-6b07d5eab0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445660569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3445660569
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.774296551
Short name T468
Test name
Test status
Simulation time 3891167411 ps
CPU time 36.21 seconds
Started Jul 22 05:01:29 PM PDT 24
Finished Jul 22 05:02:06 PM PDT 24
Peak memory 233664 kb
Host smart-c259383f-c26f-4874-80b7-fc59be1f1822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774296551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.774296551
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1918424535
Short name T433
Test name
Test status
Simulation time 3535985446 ps
CPU time 5.92 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:38 PM PDT 24
Peak memory 225348 kb
Host smart-1b9617d0-c310-441c-a563-db0e277271dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918424535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1918424535
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2909189210
Short name T963
Test name
Test status
Simulation time 284911370 ps
CPU time 2.23 seconds
Started Jul 22 05:01:35 PM PDT 24
Finished Jul 22 05:01:38 PM PDT 24
Peak memory 225360 kb
Host smart-10168efd-b5fd-4c45-b6d6-ba87a60cfd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909189210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2909189210
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2918705145
Short name T614
Test name
Test status
Simulation time 309786047 ps
CPU time 4.87 seconds
Started Jul 22 05:01:36 PM PDT 24
Finished Jul 22 05:01:42 PM PDT 24
Peak memory 221064 kb
Host smart-2776f667-350c-406e-abc5-40e7aa717ac1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2918705145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2918705145
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1500933018
Short name T128
Test name
Test status
Simulation time 241082254036 ps
CPU time 288.14 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:06:20 PM PDT 24
Peak memory 274724 kb
Host smart-01dccb6f-7dfa-4329-8681-006439226906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500933018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1500933018
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.871745446
Short name T397
Test name
Test status
Simulation time 1077637959 ps
CPU time 15.94 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:47 PM PDT 24
Peak memory 217136 kb
Host smart-e1987d3d-d825-485f-a2bb-a617108d420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871745446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.871745446
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1572743111
Short name T516
Test name
Test status
Simulation time 1660564608 ps
CPU time 6.73 seconds
Started Jul 22 05:03:41 PM PDT 24
Finished Jul 22 05:03:49 PM PDT 24
Peak memory 217060 kb
Host smart-20940c71-a68e-44ab-9bfc-b3cc8ea5946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572743111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1572743111
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3510285359
Short name T534
Test name
Test status
Simulation time 330485196 ps
CPU time 2.73 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 217172 kb
Host smart-872985ee-512b-4d7d-b59f-61b9029dcaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510285359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3510285359
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1148500521
Short name T356
Test name
Test status
Simulation time 76674579 ps
CPU time 0.95 seconds
Started Jul 22 05:01:30 PM PDT 24
Finished Jul 22 05:01:32 PM PDT 24
Peak memory 206972 kb
Host smart-e3530aa3-788f-40d0-8c7d-e1227f263039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148500521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1148500521
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2276192910
Short name T720
Test name
Test status
Simulation time 1008263771 ps
CPU time 4.86 seconds
Started Jul 22 05:03:52 PM PDT 24
Finished Jul 22 05:03:58 PM PDT 24
Peak memory 239908 kb
Host smart-8f98f5a1-df79-46d2-9514-4d7dbbdb0b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276192910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2276192910
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.273264134
Short name T561
Test name
Test status
Simulation time 44434036 ps
CPU time 0.73 seconds
Started Jul 22 05:03:52 PM PDT 24
Finished Jul 22 05:03:53 PM PDT 24
Peak memory 205932 kb
Host smart-af01fa80-3d36-454b-b5f2-315511a8d595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273264134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.273264134
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.184042588
Short name T962
Test name
Test status
Simulation time 23687768926 ps
CPU time 17.76 seconds
Started Jul 22 05:01:40 PM PDT 24
Finished Jul 22 05:01:59 PM PDT 24
Peak memory 225376 kb
Host smart-b9a33466-9df7-4ba3-8356-16910b40892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184042588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.184042588
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.675015848
Short name T473
Test name
Test status
Simulation time 35964275 ps
CPU time 0.73 seconds
Started Jul 22 05:01:33 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 206228 kb
Host smart-3f1a9195-024a-457e-85cf-e319510b3172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675015848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.675015848
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3225200043
Short name T72
Test name
Test status
Simulation time 76552860202 ps
CPU time 119.37 seconds
Started Jul 22 05:01:43 PM PDT 24
Finished Jul 22 05:03:43 PM PDT 24
Peak memory 250136 kb
Host smart-e062d269-28cd-460c-bfee-1b989ffd75a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225200043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3225200043
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3079976205
Short name T805
Test name
Test status
Simulation time 35380121025 ps
CPU time 303.64 seconds
Started Jul 22 05:01:43 PM PDT 24
Finished Jul 22 05:06:47 PM PDT 24
Peak memory 256288 kb
Host smart-78e374a7-6f65-4dea-9c93-336f0e028f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079976205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3079976205
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3322644170
Short name T712
Test name
Test status
Simulation time 3645679954 ps
CPU time 11.8 seconds
Started Jul 22 05:01:41 PM PDT 24
Finished Jul 22 05:01:54 PM PDT 24
Peak memory 233636 kb
Host smart-5772fc7f-51c4-4f86-ac08-875aa3835552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322644170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3322644170
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1243153318
Short name T88
Test name
Test status
Simulation time 298220118493 ps
CPU time 507.69 seconds
Started Jul 22 05:01:38 PM PDT 24
Finished Jul 22 05:10:07 PM PDT 24
Peak memory 264832 kb
Host smart-276039dc-6e39-4c10-8b47-a8b2e3de3192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243153318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1243153318
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.934815348
Short name T219
Test name
Test status
Simulation time 3498030066 ps
CPU time 12.07 seconds
Started Jul 22 05:01:42 PM PDT 24
Finished Jul 22 05:01:55 PM PDT 24
Peak memory 233672 kb
Host smart-6dc38633-0e92-4e19-bf0f-6ce09d1bf85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934815348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.934815348
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2308101098
Short name T202
Test name
Test status
Simulation time 5226247519 ps
CPU time 17.41 seconds
Started Jul 22 05:01:48 PM PDT 24
Finished Jul 22 05:02:06 PM PDT 24
Peak memory 239364 kb
Host smart-0eea4279-6cba-4028-a5cd-8e3720a95d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308101098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2308101098
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1865332069
Short name T311
Test name
Test status
Simulation time 197611528 ps
CPU time 2.67 seconds
Started Jul 22 05:01:40 PM PDT 24
Finished Jul 22 05:01:43 PM PDT 24
Peak memory 233272 kb
Host smart-b952d65f-bdb1-4e49-a0a7-cce1da6aa70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865332069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1865332069
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1973234219
Short name T230
Test name
Test status
Simulation time 223174896 ps
CPU time 2.87 seconds
Started Jul 22 05:01:35 PM PDT 24
Finished Jul 22 05:01:39 PM PDT 24
Peak memory 233668 kb
Host smart-15bc2cbd-89ba-4ead-8cf3-00f901b53716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973234219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1973234219
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2953247789
Short name T558
Test name
Test status
Simulation time 1466241689 ps
CPU time 6.08 seconds
Started Jul 22 05:01:40 PM PDT 24
Finished Jul 22 05:01:47 PM PDT 24
Peak memory 220656 kb
Host smart-f8985bab-7362-434f-b776-536b2e6d2647
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953247789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2953247789
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3477166353
Short name T851
Test name
Test status
Simulation time 158857741 ps
CPU time 1.03 seconds
Started Jul 22 05:01:39 PM PDT 24
Finished Jul 22 05:01:41 PM PDT 24
Peak memory 207860 kb
Host smart-c9accbaf-0604-4820-8312-b607dbe71143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477166353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3477166353
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1252108095
Short name T159
Test name
Test status
Simulation time 51072278621 ps
CPU time 34.56 seconds
Started Jul 22 05:01:36 PM PDT 24
Finished Jul 22 05:02:11 PM PDT 24
Peak memory 221324 kb
Host smart-79749e25-b3c6-4e05-bf55-40ddf47ceff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252108095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1252108095
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3604320183
Short name T584
Test name
Test status
Simulation time 4385375995 ps
CPU time 13.35 seconds
Started Jul 22 05:01:36 PM PDT 24
Finished Jul 22 05:01:50 PM PDT 24
Peak memory 217244 kb
Host smart-ed531230-5aee-4e66-a46d-68e829e12ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604320183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3604320183
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.382476779
Short name T670
Test name
Test status
Simulation time 17404913 ps
CPU time 0.68 seconds
Started Jul 22 05:01:31 PM PDT 24
Finished Jul 22 05:01:33 PM PDT 24
Peak memory 206288 kb
Host smart-3519c5d4-dcd5-4394-b4af-24fb5257693f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382476779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.382476779
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3102191698
Short name T578
Test name
Test status
Simulation time 49425548 ps
CPU time 0.84 seconds
Started Jul 22 05:01:32 PM PDT 24
Finished Jul 22 05:01:35 PM PDT 24
Peak memory 206740 kb
Host smart-993f6b5a-bac0-4a1d-aea7-b7302d9f133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102191698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3102191698
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2650319535
Short name T928
Test name
Test status
Simulation time 8717220658 ps
CPU time 8.82 seconds
Started Jul 22 05:01:38 PM PDT 24
Finished Jul 22 05:01:48 PM PDT 24
Peak memory 233668 kb
Host smart-2e8f0a47-be70-4a0f-abe1-4fadb5e3061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650319535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2650319535
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3060477604
Short name T547
Test name
Test status
Simulation time 32490495 ps
CPU time 0.73 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:46 PM PDT 24
Peak memory 206008 kb
Host smart-8c214a52-f784-459b-bbb0-b06676eb5366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060477604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
060477604
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.942082796
Short name T431
Test name
Test status
Simulation time 3504519205 ps
CPU time 11.51 seconds
Started Jul 22 05:03:17 PM PDT 24
Finished Jul 22 05:03:29 PM PDT 24
Peak memory 225360 kb
Host smart-815adda5-c794-412d-9f35-6d08c9d46258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942082796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.942082796
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1417890858
Short name T322
Test name
Test status
Simulation time 43926141 ps
CPU time 0.73 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:36 PM PDT 24
Peak memory 207176 kb
Host smart-b7e747f4-22b3-4163-831c-8fa0fce0cba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417890858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1417890858
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3321600776
Short name T256
Test name
Test status
Simulation time 3428442191 ps
CPU time 77.29 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:59:04 PM PDT 24
Peak memory 273840 kb
Host smart-e6f4e3f4-a2a0-44d5-a58f-c77b21d2cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321600776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3321600776
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4184726511
Short name T601
Test name
Test status
Simulation time 21021924466 ps
CPU time 47.88 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 04:58:35 PM PDT 24
Peak memory 250032 kb
Host smart-cbfbdb01-a3e8-4bbd-bf4c-76af5d24c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184726511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4184726511
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4112035849
Short name T378
Test name
Test status
Simulation time 17691657713 ps
CPU time 48.72 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:58:35 PM PDT 24
Peak memory 225300 kb
Host smart-919f1429-a2cc-464e-ad11-647856068456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112035849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4112035849
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.592716542
Short name T293
Test name
Test status
Simulation time 428785940 ps
CPU time 10.7 seconds
Started Jul 22 04:57:35 PM PDT 24
Finished Jul 22 04:57:47 PM PDT 24
Peak memory 241824 kb
Host smart-7f17b072-5a38-4b97-8950-a6d4b327fb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592716542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.592716542
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2502848837
Short name T969
Test name
Test status
Simulation time 9341951105 ps
CPU time 75.07 seconds
Started Jul 22 04:59:24 PM PDT 24
Finished Jul 22 05:00:40 PM PDT 24
Peak memory 253660 kb
Host smart-a1acc14e-2e00-4323-aed0-974a887b0e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502848837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2502848837
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3939692865
Short name T70
Test name
Test status
Simulation time 620965410 ps
CPU time 4.99 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:40 PM PDT 24
Peak memory 225432 kb
Host smart-f19790e1-6425-4ad0-b739-dfdeb6c8dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939692865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3939692865
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4257425020
Short name T192
Test name
Test status
Simulation time 2320392850 ps
CPU time 28.61 seconds
Started Jul 22 04:57:36 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 219848 kb
Host smart-721b1077-ed14-403a-abd0-09d25bc38108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257425020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4257425020
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1831588974
Short name T788
Test name
Test status
Simulation time 95961247 ps
CPU time 1.01 seconds
Started Jul 22 04:57:39 PM PDT 24
Finished Jul 22 04:57:42 PM PDT 24
Peak memory 217240 kb
Host smart-390605ee-dbe6-45b2-990b-10e1ce12f70a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831588974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1831588974
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3723092058
Short name T1006
Test name
Test status
Simulation time 552148855 ps
CPU time 6.96 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:14 PM PDT 24
Peak memory 241320 kb
Host smart-0981a476-a038-42f6-828a-1dd055c6cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723092058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3723092058
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1680626134
Short name T532
Test name
Test status
Simulation time 60819947716 ps
CPU time 9.42 seconds
Started Jul 22 04:59:07 PM PDT 24
Finished Jul 22 04:59:16 PM PDT 24
Peak memory 233668 kb
Host smart-abd8b2b9-2404-4660-9482-8b5f8f45fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680626134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1680626134
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1248918205
Short name T575
Test name
Test status
Simulation time 3307033794 ps
CPU time 5.76 seconds
Started Jul 22 04:57:32 PM PDT 24
Finished Jul 22 04:57:39 PM PDT 24
Peak memory 223400 kb
Host smart-5d177a07-4f3a-4533-a2e1-1046d5159942
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1248918205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1248918205
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1449669678
Short name T255
Test name
Test status
Simulation time 84583071038 ps
CPU time 313.43 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 05:03:00 PM PDT 24
Peak memory 268808 kb
Host smart-664ddd5f-dc60-468f-a6f5-d0d60b4257bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449669678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1449669678
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2687685679
Short name T991
Test name
Test status
Simulation time 1757316655 ps
CPU time 14.75 seconds
Started Jul 22 04:57:35 PM PDT 24
Finished Jul 22 04:57:50 PM PDT 24
Peak memory 217104 kb
Host smart-a5314671-400c-4205-b95d-6675f7aff6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687685679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2687685679
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3264031877
Short name T920
Test name
Test status
Simulation time 1313999169 ps
CPU time 3.6 seconds
Started Jul 22 04:57:34 PM PDT 24
Finished Jul 22 04:57:38 PM PDT 24
Peak memory 217080 kb
Host smart-b6f12fa5-ca9d-40f5-9588-f71df33e2e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264031877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3264031877
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1197857674
Short name T429
Test name
Test status
Simulation time 24258467 ps
CPU time 0.9 seconds
Started Jul 22 04:57:33 PM PDT 24
Finished Jul 22 04:57:35 PM PDT 24
Peak memory 207732 kb
Host smart-a82e741a-62ff-4279-8510-dfe6a60d50f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197857674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1197857674
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3938288585
Short name T315
Test name
Test status
Simulation time 72872233 ps
CPU time 0.94 seconds
Started Jul 22 04:57:38 PM PDT 24
Finished Jul 22 04:57:39 PM PDT 24
Peak memory 206052 kb
Host smart-bac4d697-009b-49f7-bbef-2cdd9d370e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938288585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3938288585
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2442853940
Short name T1028
Test name
Test status
Simulation time 423329359 ps
CPU time 5.25 seconds
Started Jul 22 04:57:39 PM PDT 24
Finished Jul 22 04:57:46 PM PDT 24
Peak memory 225248 kb
Host smart-6d78ef73-4c76-4d31-8a44-fc63375870d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442853940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2442853940
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.270518383
Short name T309
Test name
Test status
Simulation time 17245758 ps
CPU time 0.72 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 04:57:48 PM PDT 24
Peak memory 205528 kb
Host smart-b72a08fa-6903-467d-9f37-f00b6a8b86bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270518383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.270518383
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.978160904
Short name T235
Test name
Test status
Simulation time 221646453 ps
CPU time 3.17 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 04:57:51 PM PDT 24
Peak memory 233844 kb
Host smart-cd643d8f-109e-4922-8513-5031034405fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978160904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.978160904
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.591697216
Short name T927
Test name
Test status
Simulation time 19851666 ps
CPU time 0.8 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:36 PM PDT 24
Peak memory 207492 kb
Host smart-6dc212fa-4d4b-4ca4-80c8-0e39718bedbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591697216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.591697216
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.928987546
Short name T898
Test name
Test status
Simulation time 59348091330 ps
CPU time 104.5 seconds
Started Jul 22 04:57:49 PM PDT 24
Finished Jul 22 04:59:34 PM PDT 24
Peak memory 250096 kb
Host smart-5ed9fd12-c0e6-45ec-8d31-640a8f29af53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928987546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.928987546
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2639294874
Short name T31
Test name
Test status
Simulation time 15894402668 ps
CPU time 28.01 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:58:13 PM PDT 24
Peak memory 234812 kb
Host smart-a450afbe-f19b-42da-93bf-8091ca34ec92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639294874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2639294874
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.180086952
Short name T600
Test name
Test status
Simulation time 6025825682 ps
CPU time 21.07 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:58:08 PM PDT 24
Peak memory 218368 kb
Host smart-c24843db-19e3-4c3e-bd32-977a7066fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180086952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
180086952
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3829481517
Short name T886
Test name
Test status
Simulation time 5386043467 ps
CPU time 21.49 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:58:07 PM PDT 24
Peak memory 225476 kb
Host smart-29b06356-dac3-45f5-a924-b3a3a6051b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829481517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3829481517
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2809453727
Short name T864
Test name
Test status
Simulation time 6963559417 ps
CPU time 96.58 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:59:23 PM PDT 24
Peak memory 258116 kb
Host smart-2b09f120-abc1-47d2-aebd-a96328cefb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809453727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2809453727
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.106280983
Short name T681
Test name
Test status
Simulation time 243885276 ps
CPU time 5.26 seconds
Started Jul 22 04:58:13 PM PDT 24
Finished Jul 22 04:58:19 PM PDT 24
Peak memory 233644 kb
Host smart-9e5adb1f-f410-4222-bfe7-0620652edcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106280983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.106280983
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.365426065
Short name T261
Test name
Test status
Simulation time 12537372113 ps
CPU time 42.57 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:58:28 PM PDT 24
Peak memory 225428 kb
Host smart-2a42745b-b00b-4566-bfb2-2784bc66263e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365426065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.365426065
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.821930511
Short name T815
Test name
Test status
Simulation time 62356666 ps
CPU time 1.08 seconds
Started Jul 22 05:00:03 PM PDT 24
Finished Jul 22 05:00:05 PM PDT 24
Peak memory 217360 kb
Host smart-d6e1b347-407c-4d21-ad7a-f8e98709391d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821930511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.821930511
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.73102533
Short name T519
Test name
Test status
Simulation time 20721006745 ps
CPU time 13.09 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:58 PM PDT 24
Peak memory 233572 kb
Host smart-6f6a77a9-910d-4949-98e5-c0198d08e0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73102533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.73102533
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.616666473
Short name T940
Test name
Test status
Simulation time 2413467041 ps
CPU time 5.04 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:57:52 PM PDT 24
Peak memory 233616 kb
Host smart-64a8006c-8cf3-42fd-9d67-fc55fe6b74d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616666473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.616666473
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2841829513
Short name T491
Test name
Test status
Simulation time 5312769389 ps
CPU time 17.52 seconds
Started Jul 22 04:57:44 PM PDT 24
Finished Jul 22 04:58:02 PM PDT 24
Peak memory 223344 kb
Host smart-c77f4ae1-1b93-46ed-bb1e-886f5c7529c8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2841829513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2841829513
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3633153294
Short name T849
Test name
Test status
Simulation time 329867241562 ps
CPU time 288.81 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 05:02:36 PM PDT 24
Peak memory 268560 kb
Host smart-4ce4d4fb-ce4a-4223-ad6b-178acf720da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633153294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3633153294
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1629529306
Short name T1018
Test name
Test status
Simulation time 1009445376 ps
CPU time 10.9 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:57:58 PM PDT 24
Peak memory 217100 kb
Host smart-15b3b2ab-5fb8-4ee6-9bad-f2d0377f8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629529306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1629529306
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3152554524
Short name T1014
Test name
Test status
Simulation time 15523524419 ps
CPU time 7.28 seconds
Started Jul 22 04:57:44 PM PDT 24
Finished Jul 22 04:57:52 PM PDT 24
Peak memory 217092 kb
Host smart-92f72b7b-8be1-4fd8-8b86-01b5b3064f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152554524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3152554524
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3629111468
Short name T833
Test name
Test status
Simulation time 139283430 ps
CPU time 1.67 seconds
Started Jul 22 04:57:44 PM PDT 24
Finished Jul 22 04:57:46 PM PDT 24
Peak memory 217216 kb
Host smart-2b63b72a-0301-453c-8153-ba4414d80bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629111468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3629111468
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2339100171
Short name T636
Test name
Test status
Simulation time 213336525 ps
CPU time 0.92 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 04:57:48 PM PDT 24
Peak memory 206684 kb
Host smart-871601ec-8eba-43fd-b845-562df3d4f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339100171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2339100171
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1220309333
Short name T48
Test name
Test status
Simulation time 8991807916 ps
CPU time 13.86 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:58:00 PM PDT 24
Peak memory 233724 kb
Host smart-862a4039-c18f-4346-8093-4e64ca6ffc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220309333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1220309333
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1737075908
Short name T327
Test name
Test status
Simulation time 44098384 ps
CPU time 0.72 seconds
Started Jul 22 04:57:59 PM PDT 24
Finished Jul 22 04:58:00 PM PDT 24
Peak memory 205460 kb
Host smart-209fcddb-3af7-42cf-967a-58418dd3d1d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737075908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
737075908
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3501831590
Short name T876
Test name
Test status
Simulation time 109980151 ps
CPU time 2.41 seconds
Started Jul 22 04:57:47 PM PDT 24
Finished Jul 22 04:57:50 PM PDT 24
Peak memory 233224 kb
Host smart-5fedd712-7b65-4c4f-9722-e4c13e877b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501831590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3501831590
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1045034011
Short name T691
Test name
Test status
Simulation time 33114179 ps
CPU time 0.76 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:47 PM PDT 24
Peak memory 207172 kb
Host smart-f5ac4afe-d0de-492b-a033-db4c858992f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045034011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1045034011
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2484301788
Short name T914
Test name
Test status
Simulation time 4956365717 ps
CPU time 21.78 seconds
Started Jul 22 04:57:58 PM PDT 24
Finished Jul 22 04:58:20 PM PDT 24
Peak memory 250068 kb
Host smart-0ba24b9f-4cbe-44f1-be64-5d91fd73bbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484301788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2484301788
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2925915994
Short name T266
Test name
Test status
Simulation time 17700459968 ps
CPU time 50.68 seconds
Started Jul 22 04:57:59 PM PDT 24
Finished Jul 22 04:58:51 PM PDT 24
Peak memory 258216 kb
Host smart-42efd3fc-2143-429d-895c-0743dfefd82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925915994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2925915994
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3305934911
Short name T846
Test name
Test status
Simulation time 3169520251 ps
CPU time 70.05 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:59:11 PM PDT 24
Peak memory 250072 kb
Host smart-5a8861dc-0227-4990-b0f9-0c30f7b84423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305934911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3305934911
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3979017658
Short name T477
Test name
Test status
Simulation time 1283440541 ps
CPU time 6.09 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:07 PM PDT 24
Peak memory 241768 kb
Host smart-c77e489c-878f-4463-b176-8547aa298417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979017658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3979017658
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1838252463
Short name T987
Test name
Test status
Simulation time 325087491 ps
CPU time 3.63 seconds
Started Jul 22 04:57:49 PM PDT 24
Finished Jul 22 04:57:53 PM PDT 24
Peak memory 233616 kb
Host smart-302e62f4-4fb8-40ef-abd2-78be0cbfe7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838252463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1838252463
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.239131871
Short name T522
Test name
Test status
Simulation time 2029815160 ps
CPU time 16.62 seconds
Started Jul 22 04:59:32 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 233616 kb
Host smart-b114261c-aad8-4660-a9c7-8688d788826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239131871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.239131871
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.297777878
Short name T765
Test name
Test status
Simulation time 88397520 ps
CPU time 1.06 seconds
Started Jul 22 04:57:48 PM PDT 24
Finished Jul 22 04:57:49 PM PDT 24
Peak memory 217396 kb
Host smart-5bbdcb8f-aaf0-4d92-86f7-e1bceb493801
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297777878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.297777878
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.599925516
Short name T755
Test name
Test status
Simulation time 5768314792 ps
CPU time 16.87 seconds
Started Jul 22 04:59:31 PM PDT 24
Finished Jul 22 04:59:49 PM PDT 24
Peak memory 233632 kb
Host smart-4eb9e19e-9002-4ad2-837d-17896612cd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599925516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
599925516
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2150810747
Short name T899
Test name
Test status
Simulation time 4550819676 ps
CPU time 6.28 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:52 PM PDT 24
Peak memory 225480 kb
Host smart-5e1d1b3c-2cc9-4161-8246-4813ce32b41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150810747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2150810747
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.529782428
Short name T127
Test name
Test status
Simulation time 3355853316 ps
CPU time 4.71 seconds
Started Jul 22 05:00:03 PM PDT 24
Finished Jul 22 05:00:09 PM PDT 24
Peak memory 223828 kb
Host smart-d35cbdd2-4d6d-48ff-8e2a-6137223de976
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=529782428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.529782428
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.550667927
Short name T1027
Test name
Test status
Simulation time 504840075972 ps
CPU time 385.42 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 05:04:29 PM PDT 24
Peak memory 282948 kb
Host smart-378341d0-dcb3-48f9-bfb7-39c4503b2185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550667927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.550667927
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2529464368
Short name T509
Test name
Test status
Simulation time 10493086778 ps
CPU time 18.13 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 218548 kb
Host smart-88207fbd-4c2a-486b-8c76-f99684b14fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529464368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2529464368
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3264259997
Short name T465
Test name
Test status
Simulation time 11137075972 ps
CPU time 7.21 seconds
Started Jul 22 04:57:49 PM PDT 24
Finished Jul 22 04:57:56 PM PDT 24
Peak memory 217228 kb
Host smart-82e5d627-d61c-4e7f-a274-0d5193bbd0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264259997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3264259997
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1100009180
Short name T852
Test name
Test status
Simulation time 1558263698 ps
CPU time 3.47 seconds
Started Jul 22 04:57:46 PM PDT 24
Finished Jul 22 04:57:50 PM PDT 24
Peak memory 218044 kb
Host smart-8b7b0c1d-dfb5-4c17-8d7f-d7bb7c5ce650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100009180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1100009180
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1784910574
Short name T346
Test name
Test status
Simulation time 783395060 ps
CPU time 0.82 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:47 PM PDT 24
Peak memory 206692 kb
Host smart-79ff8531-08a7-4285-9261-b9e6074ef23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784910574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1784910574
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1601846635
Short name T224
Test name
Test status
Simulation time 232539118 ps
CPU time 2.35 seconds
Started Jul 22 04:57:45 PM PDT 24
Finished Jul 22 04:57:48 PM PDT 24
Peak memory 225336 kb
Host smart-9757c147-c164-43b2-a318-a16b8c1b0ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601846635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1601846635
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1471239040
Short name T735
Test name
Test status
Simulation time 41946363 ps
CPU time 0.75 seconds
Started Jul 22 04:58:04 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 205420 kb
Host smart-002d1972-2bf6-4fef-9b67-4aac418ad7e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471239040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
471239040
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.734754163
Short name T514
Test name
Test status
Simulation time 113701580 ps
CPU time 3.05 seconds
Started Jul 22 04:57:59 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 233580 kb
Host smart-9df68f05-43da-43fd-9abb-dc92bf168e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734754163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.734754163
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.569496005
Short name T7
Test name
Test status
Simulation time 22520096 ps
CPU time 0.8 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 04:58:04 PM PDT 24
Peak memory 207576 kb
Host smart-b93e2fcc-800e-40fd-93d7-875e95e01486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569496005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.569496005
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3078567276
Short name T553
Test name
Test status
Simulation time 175055755195 ps
CPU time 228.26 seconds
Started Jul 22 04:58:04 PM PDT 24
Finished Jul 22 05:01:53 PM PDT 24
Peak memory 255576 kb
Host smart-2ea5b413-99c2-4562-ad8d-7a3128850c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078567276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3078567276
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3071520549
Short name T871
Test name
Test status
Simulation time 164535873140 ps
CPU time 123.47 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 05:00:10 PM PDT 24
Peak memory 257528 kb
Host smart-d0396902-cec1-48ec-b223-d61f331cbcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071520549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3071520549
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2685126059
Short name T33
Test name
Test status
Simulation time 40438266199 ps
CPU time 223.73 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 05:01:48 PM PDT 24
Peak memory 252208 kb
Host smart-ab6e5a09-ca5b-4b0b-a46f-d0b9a926bdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685126059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2685126059
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1701938039
Short name T621
Test name
Test status
Simulation time 239289022 ps
CPU time 8.3 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 240520 kb
Host smart-7b40706f-547c-4a08-9d7f-8e7c82f6f283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701938039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1701938039
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.273935789
Short name T231
Test name
Test status
Simulation time 6362715859 ps
CPU time 44.57 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 04:58:54 PM PDT 24
Peak memory 235784 kb
Host smart-47b4904a-372e-4b70-94ef-ebea44640427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273935789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
273935789
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3728897039
Short name T812
Test name
Test status
Simulation time 90952826 ps
CPU time 2.57 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 233596 kb
Host smart-32e16ab5-a416-4ea1-8415-77a16aea7e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728897039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3728897039
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3404999698
Short name T204
Test name
Test status
Simulation time 3252474525 ps
CPU time 13.08 seconds
Started Jul 22 04:58:02 PM PDT 24
Finished Jul 22 04:58:16 PM PDT 24
Peak memory 233660 kb
Host smart-e33b6e32-82cf-4d2c-96b9-c2cca4f771cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404999698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3404999698
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3009739978
Short name T417
Test name
Test status
Simulation time 55609439 ps
CPU time 1.01 seconds
Started Jul 22 04:59:37 PM PDT 24
Finished Jul 22 04:59:38 PM PDT 24
Peak memory 217384 kb
Host smart-8cbd54b8-da38-47af-bb90-8bcb681390b3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009739978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3009739978
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1670871144
Short name T218
Test name
Test status
Simulation time 35402182 ps
CPU time 2.43 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:10 PM PDT 24
Peak memory 233652 kb
Host smart-5fabe7b9-9eaa-49ab-ba5d-3d8e09d3958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670871144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1670871144
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.671625521
Short name T610
Test name
Test status
Simulation time 5863959206 ps
CPU time 6.74 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 04:58:13 PM PDT 24
Peak memory 233644 kb
Host smart-8fb0f9c6-d058-4410-8a83-135b02145091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671625521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.671625521
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2357788649
Short name T835
Test name
Test status
Simulation time 4521240716 ps
CPU time 12.96 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:14 PM PDT 24
Peak memory 220752 kb
Host smart-17625cd9-51b6-4506-84b8-3208a50f2c1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2357788649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2357788649
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.999677329
Short name T209
Test name
Test status
Simulation time 74574818035 ps
CPU time 742.08 seconds
Started Jul 22 04:57:59 PM PDT 24
Finished Jul 22 05:10:22 PM PDT 24
Peak memory 283808 kb
Host smart-8f4da9ab-51a7-4503-b9bf-17e0cd409e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999677329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.999677329
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3937821291
Short name T701
Test name
Test status
Simulation time 10509688288 ps
CPU time 22.31 seconds
Started Jul 22 04:59:34 PM PDT 24
Finished Jul 22 04:59:57 PM PDT 24
Peak memory 221364 kb
Host smart-128bab6f-a2d1-4ca4-92b0-2fe3c4bfc6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937821291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3937821291
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3146270629
Short name T375
Test name
Test status
Simulation time 35047559340 ps
CPU time 11.2 seconds
Started Jul 22 04:57:58 PM PDT 24
Finished Jul 22 04:58:10 PM PDT 24
Peak memory 217160 kb
Host smart-09ec433e-2244-421c-a639-73509b24c01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146270629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3146270629
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2139195667
Short name T665
Test name
Test status
Simulation time 93701860 ps
CPU time 1.68 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 217184 kb
Host smart-2c01dd3d-eb9e-44f9-8465-56f3baa81409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139195667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2139195667
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.515994493
Short name T10
Test name
Test status
Simulation time 221059716 ps
CPU time 0.91 seconds
Started Jul 22 04:57:58 PM PDT 24
Finished Jul 22 04:58:00 PM PDT 24
Peak memory 206768 kb
Host smart-3d2b1a6c-b146-4f3e-9823-ce1f97da9a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515994493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.515994493
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3718973344
Short name T814
Test name
Test status
Simulation time 1023351121 ps
CPU time 5.91 seconds
Started Jul 22 04:58:00 PM PDT 24
Finished Jul 22 04:58:07 PM PDT 24
Peak memory 233512 kb
Host smart-0f47c09a-ddd8-4238-b637-ea4c5c0e1a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718973344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3718973344
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.608410678
Short name T61
Test name
Test status
Simulation time 11968662 ps
CPU time 0.72 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 206632 kb
Host smart-a8937516-cf2d-4fba-8927-aaf57d9dcab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608410678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.608410678
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3341009231
Short name T83
Test name
Test status
Simulation time 1700257469 ps
CPU time 9.66 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:17 PM PDT 24
Peak memory 225260 kb
Host smart-28405d90-6fd6-4be8-95c4-743e63e0616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341009231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3341009231
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2660935622
Short name T976
Test name
Test status
Simulation time 48227045 ps
CPU time 0.76 seconds
Started Jul 22 04:58:01 PM PDT 24
Finished Jul 22 04:58:02 PM PDT 24
Peak memory 206504 kb
Host smart-f00f750e-2d80-45b4-b9df-e50c0077b7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660935622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2660935622
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.964916529
Short name T212
Test name
Test status
Simulation time 35142627766 ps
CPU time 226.03 seconds
Started Jul 22 04:58:08 PM PDT 24
Finished Jul 22 05:01:55 PM PDT 24
Peak memory 238260 kb
Host smart-0bd20e45-e68e-4a49-9d3d-39c18168eede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964916529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.964916529
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.887862118
Short name T559
Test name
Test status
Simulation time 2204700730 ps
CPU time 12.58 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:21 PM PDT 24
Peak memory 218436 kb
Host smart-effd1e4f-e59e-4099-b483-56471d5b55df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887862118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.887862118
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2025505442
Short name T167
Test name
Test status
Simulation time 136122692245 ps
CPU time 312.66 seconds
Started Jul 22 04:58:06 PM PDT 24
Finished Jul 22 05:03:20 PM PDT 24
Peak memory 250084 kb
Host smart-6d286567-073f-4e08-a265-58bcdaafed37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025505442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2025505442
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.628470687
Short name T752
Test name
Test status
Simulation time 16738692416 ps
CPU time 74.48 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:59:22 PM PDT 24
Peak memory 241884 kb
Host smart-17440bdd-0c1b-4c22-b3c8-c3e9ea8ce920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628470687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.628470687
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1455366508
Short name T978
Test name
Test status
Simulation time 140164531 ps
CPU time 3.84 seconds
Started Jul 22 04:58:03 PM PDT 24
Finished Jul 22 04:58:08 PM PDT 24
Peak memory 233680 kb
Host smart-0404f292-51d9-415c-9f46-54d6d4f2b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455366508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1455366508
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.904749906
Short name T93
Test name
Test status
Simulation time 29292724217 ps
CPU time 67.76 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 04:59:14 PM PDT 24
Peak memory 233576 kb
Host smart-b0d940b0-61e7-481a-a770-8d128e89d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904749906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.904749906
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2696187802
Short name T644
Test name
Test status
Simulation time 196363313 ps
CPU time 1 seconds
Started Jul 22 04:58:01 PM PDT 24
Finished Jul 22 04:58:03 PM PDT 24
Peak memory 217352 kb
Host smart-d0290c51-2db2-42fd-aa40-60da65ef404f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696187802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2696187802
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1433503149
Short name T657
Test name
Test status
Simulation time 70421956 ps
CPU time 2.52 seconds
Started Jul 22 04:58:02 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 233488 kb
Host smart-f5343ae4-074c-4423-a379-e1f8ad6ecb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433503149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1433503149
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1566660150
Short name T660
Test name
Test status
Simulation time 115466532 ps
CPU time 2.4 seconds
Started Jul 22 04:58:05 PM PDT 24
Finished Jul 22 04:58:09 PM PDT 24
Peak memory 225284 kb
Host smart-afb6e1cd-7558-44d9-96a8-0674e177cf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566660150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1566660150
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.662367738
Short name T476
Test name
Test status
Simulation time 1269586809 ps
CPU time 12.23 seconds
Started Jul 22 04:58:32 PM PDT 24
Finished Jul 22 04:58:45 PM PDT 24
Peak memory 219732 kb
Host smart-237caa37-49a2-421c-976e-fe2186b82cf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=662367738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.662367738
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3107468171
Short name T888
Test name
Test status
Simulation time 237776113661 ps
CPU time 151.98 seconds
Started Jul 22 04:58:06 PM PDT 24
Finished Jul 22 05:00:38 PM PDT 24
Peak memory 255228 kb
Host smart-10763914-ef72-416e-b21e-33abdca3e8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107468171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3107468171
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2412455231
Short name T658
Test name
Test status
Simulation time 12667787985 ps
CPU time 16.68 seconds
Started Jul 22 04:58:01 PM PDT 24
Finished Jul 22 04:58:18 PM PDT 24
Peak memory 217116 kb
Host smart-be624ad9-af1a-496c-ba14-449c547a81af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412455231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2412455231
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2752726875
Short name T336
Test name
Test status
Simulation time 9487393400 ps
CPU time 13.38 seconds
Started Jul 22 04:58:02 PM PDT 24
Finished Jul 22 04:58:16 PM PDT 24
Peak memory 217192 kb
Host smart-5f781b0b-e342-4226-bd6a-96d04453d782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752726875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2752726875
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1592385005
Short name T471
Test name
Test status
Simulation time 13771014 ps
CPU time 0.73 seconds
Started Jul 22 04:58:04 PM PDT 24
Finished Jul 22 04:58:05 PM PDT 24
Peak memory 206220 kb
Host smart-8c3780ee-a0f2-41db-8157-7bf06863cb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592385005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1592385005
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1753187568
Short name T1000
Test name
Test status
Simulation time 169523146 ps
CPU time 0.98 seconds
Started Jul 22 04:58:04 PM PDT 24
Finished Jul 22 04:58:06 PM PDT 24
Peak memory 207812 kb
Host smart-d8013a94-70b4-4fbc-baf4-7d975cfecc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753187568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1753187568
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4104824872
Short name T632
Test name
Test status
Simulation time 8058598750 ps
CPU time 25.19 seconds
Started Jul 22 04:58:07 PM PDT 24
Finished Jul 22 04:58:33 PM PDT 24
Peak memory 233548 kb
Host smart-7ccfa7df-a2c4-432f-9a79-2597c2a8f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104824872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4104824872
Directory /workspace/9.spi_device_upload/latest
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