Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2633908	1			T1	1		T2	1		T3	32
all_values[1]	2633908	1			T1	1		T2	1		T3	32
all_values[2]	2633908	1			T1	1		T2	1		T3	32
all_values[3]	2633908	1			T1	1		T2	1		T3	32
all_values[4]	2633908	1			T1	1		T2	1		T3	32
all_values[5]	2633908	1			T1	1		T2	1		T3	32
all_values[6]	2633908	1			T1	1		T2	1		T3	32
all_values[7]	2633908	1			T1	1		T2	1		T3	32

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20852081

1

T1

8

T2

8

T3

140

auto[1]

219183

1

T3

116

T7

100

T13

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21044664

1

T1

8

T2

8

T3

161

auto[1]

26600

1

T3

95

T6

459

T7

155

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2586873	1			T1	1		T2	1		T3	6
all_values[0]	auto[0]	auto[1]	12147	1			T3	9		T6	228		T7	47
all_values[0]	auto[1]	auto[0]	34437	1			T3	6		T7	7		T13	3
all_values[0]	auto[1]	auto[1]	451	1			T3	11		T7	6		T13	5
all_values[1]	auto[0]	auto[0]	2585832	1			T1	1		T2	1		T3	14
all_values[1]	auto[0]	auto[1]	8134	1			T3	8		T6	185		T7	45
all_values[1]	auto[1]	auto[0]	39498	1			T3	5		T7	3		T13	3
all_values[1]	auto[1]	auto[1]	444	1			T3	5		T7	6		T13	5
all_values[2]	auto[0]	auto[0]	2593686	1			T1	1		T2	1		T3	12
all_values[2]	auto[0]	auto[1]	3157	1			T3	6		T6	46		T7	2
all_values[2]	auto[1]	auto[0]	36776	1			T3	11		T7	9		T13	3
all_values[2]	auto[1]	auto[1]	289	1			T3	3		T7	8		T13	3
all_values[3]	auto[0]	auto[0]	2624186	1			T1	1		T2	1		T3	15
all_values[3]	auto[0]	auto[1]	217	1			T3	6		T7	1		T13	2
all_values[3]	auto[1]	auto[0]	9328	1			T3	9		T7	6		T13	2
all_values[3]	auto[1]	auto[1]	177	1			T3	2		T7	5		T13	2
all_values[4]	auto[0]	auto[0]	2607768	1			T1	1		T2	1		T3	14
all_values[4]	auto[0]	auto[1]	182	1			T3	4		T7	1		T13	4
all_values[4]	auto[1]	auto[0]	25773	1			T3	9		T7	8		T13	1
all_values[4]	auto[1]	auto[1]	185	1			T3	5		T7	4		T13	3
all_values[5]	auto[0]	auto[0]	2612342	1			T1	1		T2	1		T3	4
all_values[5]	auto[0]	auto[1]	194	1			T3	9		T7	7		T13	4
all_values[5]	auto[1]	auto[0]	21172	1			T3	13		T7	7		T13	1
all_values[5]	auto[1]	auto[1]	200	1			T3	6		T7	3		T13	3
all_values[6]	auto[0]	auto[0]	2609095	1			T1	1		T2	1		T3	18
all_values[6]	auto[0]	auto[1]	214	1			T3	3		T7	3		T13	5
all_values[6]	auto[1]	auto[0]	24373	1			T3	6		T7	7		T13	2
all_values[6]	auto[1]	auto[1]	226	1			T3	5		T7	7		T13	3
all_values[7]	auto[0]	auto[0]	2607851	1			T1	1		T2	1		T3	5
all_values[7]	auto[0]	auto[1]	203	1			T3	7		T7	5		T13	2
all_values[7]	auto[1]	auto[0]	25674	1			T3	14		T7	9		T13	6
all_values[7]	auto[1]	auto[1]	180	1			T3	6		T7	5		T17	3