Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34322	1			T2	2		T4	10		T5	527
auto[SpiFlashAddrCfg]	7263	1			T5	44		T6	43		T7	16
auto[SpiFlashAddr3b]	9110	1			T1	2		T2	4		T5	72
auto[SpiFlashAddr4b]	7440	1			T2	12		T5	48		T6	52

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33051

1

T1

2

T4

10

T5

468

auto[1]

25084

1

T2

18

T5

223

T6

143

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30755

1

T1

2

T2

8

T4

10

auto[1]

27380

1

T2

10

T5

288

T6

121

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38935	1			T1	2		T2	8		T4	10
values[1]	1048	1			T5	10		T6	5		T7	3
values[2]	1362	1			T5	5		T6	9		T7	2
values[3]	1461	1			T5	14		T6	13		T7	1
values[4]	1360	1			T5	10		T6	3		T7	1
values[5]	1458	1			T2	2		T5	9		T6	9
values[6]	1471	1			T2	4		T5	11		T6	10
values[7]	1384	1			T5	4		T6	15		T7	6
values[8]	9656	1			T2	4		T5	66		T6	60

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27458

1

T1

2

T2

18

T4

10

auto[1]

30677

1

T5

691

T6

294

T12

120

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54951

1

T2

18

T4

10

T5

670

write

3184

1

T1

2

T5

21

T6

27

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18796

1

T2

16

T4

10

T5

119

valids[0x1]

39339

1

T1

2

T2

2

T5

572

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1593	1			T5	13		T6	6		T7	3
internal_process_ops[0x5a]	1537	1			T5	15		T6	9		T7	3
internal_process_ops[0x05]	20598	1			T5	415		T6	42		T7	33
internal_process_ops[0x35]	1613	1			T5	19		T6	12		T7	5
internal_process_ops[0x15]	1569	1			T5	16		T6	12		T7	3
internal_process_ops[0x03]	1057	1			T5	4		T6	2		T7	3
internal_process_ops[0x0b]	991	1			T2	2		T5	8		T6	8
internal_process_ops[0x3b]	1032	1			T5	4		T6	4		T7	4
internal_process_ops[0x6b]	1015	1			T5	4		T6	1		T7	2
internal_process_ops[0xbb]	1008	1			T5	6		T6	5		T7	4
internal_process_ops[0xeb]	1052	1			T5	7		T6	2		T7	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56579

1

T1

2

T2

18

T4

10

auto[1]

1556

1

T5

9

T6

11

T7

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55839

1

T1

2

T2

18

T4

10

auto[1]

2296

1

T5

19

T6

21

T7

5

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9237

1

T4

10

T7

53

T11

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5317

1

T2

2

T7

8

T13

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1943

1

T7

12

T11

6

T13

1

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1592

1

T7

3

T13

4

T33

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2424

1

T7

10

T11

2

T13

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2023

1

T2

4

T7

18

T13

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1831

1

T7

3

T14

23

T39

5

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1699

1

T2

12

T7

15

T13

7

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

95

1

T13

1

T16

4

T152

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T7

1

T14

6

T16

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

88

1

T16

1

T153

3

T154

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T33

2

T14

1

T16

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

100

1

T14

4

T39

3

T32

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

64

1

T40

1

T153

1

T155

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

85

1

T16

2

T41

2

T156

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

86

1

T7

1

T13

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

111

1

T1

2

T7

3

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

77

1

T16

5

T40

1

T156

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

72

1

T14

1

T16

2

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T14

4

T32

1

T41

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

90

1

T7

2

T14

1

T16

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

78

1

T16

2

T32

1

T153

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T7

1

T14

1

T16

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T7

1

T14

2

T16

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10956

1

T5

387

T6

81

T12

31

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7997

1

T5

136

T6

42

T12

25

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1509

1

T5

16

T6

13

T12

10

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1487

1

T5

20

T6

25

T12

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1928

1

T5

32

T6

25

T12

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1869

1

T5

32

T6

32

T12

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1617

1

T5

19

T6

20

T12

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1522

1

T5

28

T6

29

T12

5

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T6

4

T12

1

T157

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

130

1

T5

4

T6

3

T85

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

110

1

T6

2

T12

2

T85

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

115

1

T6

3

T12

1

T85

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T5

2

T6

1

T85

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T5

1

T6

1

T12

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T5

4

T6

3

T85

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T5

1

T90

2

T158

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

133

1

T5

3

T6

1

T12

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

130

1

T5

3

T12

1

T31

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

138

1

T5

2

T6

3

T12

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T6

3

T31

2

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T5

1

T6

2

T157

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T31

2

T85

2

T48

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

107

1

T85

2

T86

1

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T6

1

T31

1

T85

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3490	1			T2	6		T4	10		T7	19
auto[0]	values[0]	valids[0x1]	13649	1			T1	2		T2	2		T7	64
auto[0]	values[1]	valids[0x1]	489	1			T7	3		T13	1		T14	3
auto[0]	values[2]	valids[0x0]	457	1			T14	6		T16	11		T40	1
auto[0]	values[2]	valids[0x1]	266	1			T7	2		T13	1		T14	5
auto[0]	values[3]	valids[0x0]	509	1			T7	1		T14	7		T16	8
auto[0]	values[3]	valids[0x1]	287	1			T33	2		T14	1		T16	10
auto[0]	values[4]	valids[0x0]	499	1			T13	3		T14	8		T16	10
auto[0]	values[4]	valids[0x1]	258	1			T7	1		T14	4		T16	6
auto[0]	values[5]	valids[0x0]	533	1			T2	2		T7	2		T13	1
auto[0]	values[5]	valids[0x1]	283	1			T13	2		T14	5		T39	1
auto[0]	values[6]	valids[0x0]	547	1			T2	4		T7	2		T13	1
auto[0]	values[6]	valids[0x1]	244	1			T44	2		T14	9		T16	10
auto[0]	values[7]	valids[0x0]	483	1			T7	5		T13	1		T14	11
auto[0]	values[7]	valids[0x1]	257	1			T7	1		T33	2		T14	2
auto[0]	values[8]	valids[0x0]	3299	1			T2	4		T7	25		T11	6
auto[0]	values[8]	valids[0x1]	1908	1			T7	6		T13	2		T33	4
auto[1]	values[0]	valids[0x0]	4059	1			T5	53		T6	48		T12	18
auto[1]	values[0]	valids[0x1]	17737	1			T5	509		T6	122		T12	54
auto[1]	values[1]	valids[0x1]	559	1			T5	10		T6	5		T31	1
auto[1]	values[2]	valids[0x0]	397	1			T5	2		T6	6		T85	2
auto[1]	values[2]	valids[0x1]	242	1			T5	3		T6	3		T12	1
auto[1]	values[3]	valids[0x0]	385	1			T5	11		T6	8		T12	1
auto[1]	values[3]	valids[0x1]	280	1			T5	3		T6	5		T85	3
auto[1]	values[4]	valids[0x0]	352	1			T35	1		T85	3		T157	1
auto[1]	values[4]	valids[0x1]	251	1			T5	10		T6	3		T12	1
auto[1]	values[5]	valids[0x0]	392	1			T5	4		T6	3		T12	4
auto[1]	values[5]	valids[0x1]	250	1			T5	5		T6	6		T12	2
auto[1]	values[6]	valids[0x0]	375	1			T5	2		T6	5		T12	5
auto[1]	values[6]	valids[0x1]	305	1			T5	9		T6	5		T12	3
auto[1]	values[7]	valids[0x0]	382	1			T5	3		T6	8		T12	3
auto[1]	values[7]	valids[0x1]	262	1			T5	1		T6	7		T31	2
auto[1]	values[8]	valids[0x0]	2637	1			T5	44		T6	37		T12	16
auto[1]	values[8]	valids[0x1]	1812	1			T5	22		T6	23		T12	12