Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270007

1

T1

1

T2

1

T4

898

auto[1]

28905

1

T5

411

T6

34

T7

31

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018164

1

T1

1

T2

1

T4

898

auto[1]

2280748

1

T5

17994

T6

18012

T7

9079

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	594298	1			T1	1		T2	1		T4	185
auto[524288:1048575]	382134	1			T4	106		T5	2692		T6	1365
auto[1048576:1572863]	390530	1			T4	164		T5	420		T6	2941
auto[1572864:2097151]	363795	1			T4	114		T5	3807		T6	8303
auto[2097152:2621439]	386985	1			T4	108		T5	3453		T6	2454
auto[2621440:3145727]	387933	1			T4	167		T5	5678		T6	1035
auto[3145728:3670015]	401178	1			T5	285		T6	18		T7	2362
auto[3670016:4194303]	392059	1			T4	54		T5	1378		T6	135

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2315028

1

T1

1

T2

1

T4

58

auto[1]

983884

1

T4

840

T5

12

T6

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2861810

1

T1

1

T2

1

T4

898

auto[1]

437102

1

T5

881

T6

1169

T7

513

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	228835	1			T1	1		T2	1		T4	185
auto[0]	auto[0]	auto[0:524287]	auto[1]	296671	1			T5	303		T6	1839		T7	3253
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	112028	1			T4	106		T5	6		T6	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	224944	1			T5	2636		T6	1091		T7	2922
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	116993	1			T4	164		T5	2		T6	8
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	220024	1			T5	264		T6	2913		T7	7
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	102448	1			T4	114		T5	8		T6	13
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	211472	1			T5	3785		T6	7400		T12	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	110616	1			T4	108		T5	7		T6	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	208813	1			T5	2658		T6	2448		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	87486	1			T4	167		T5	11		T6	6
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	242648	1			T5	5595		T6	1026		T14	3840
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	122340	1			T5	11		T6	7		T7	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	217276	1			T5	262		T6	7		T7	2357
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	116216	1			T4	54		T5	7		T6	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	220269	1			T5	1321		T6	129		T12	200
auto[0]	auto[1]	auto[0:524287]	auto[0]	1724	1			T6	2		T7	1		T13	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	62744	1			T6	1		T7	512		T16	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2053	1			T5	1		T6	1		T12	9
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39143	1			T5	1		T6	258		T12	1027
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	650	1			T5	7		T6	4		T85	19
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	48233	1			T5	130		T6	4		T31	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3637	1			T5	1		T6	3		T85	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	42369	1			T6	882		T41	2100		T156	129
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	4392	1			T5	10		T16	7		T41	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59192	1			T5	642		T16	532		T156	2307
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1294	1			T5	4		T14	2		T230	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53487	1			T14	5		T16	256		T157	661
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	946	1			T5	1		T14	2		T16	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	58495	1			T14	3		T40	1		T157	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2561	1			T5	1		T6	2		T12	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	50008	1			T5	5		T6	1		T14	1295
auto[1]	auto[0]	auto[0:524287]	auto[0]	492	1			T5	1		T6	1		T7	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3309	1			T5	73		T7	8		T14	56
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	382	1			T5	1		T6	3		T12	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1986	1			T5	43		T6	2		T12	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	380	1			T6	4		T7	1		T13	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3426	1			T6	4		T7	16		T13	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	514	1			T5	1		T6	1		T12	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2719	1			T5	12		T12	3		T14	14
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	360	1			T5	3		T6	1		T7	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2876	1			T5	90		T7	2		T31	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	328	1			T5	3		T6	2		T14	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1940	1			T5	65		T6	1		T14	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	322	1			T5	2		T6	3		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1298	1			T5	9		T6	1		T14	12
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	392	1			T5	2		T12	1		T14	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2007	1			T5	28		T12	1		T14	16
auto[1]	auto[1]	auto[0:524287]	auto[0]	87	1			T6	1		T156	2		T210	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	436	1			T6	1		T156	48		T210	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	122	1			T5	1		T12	3		T16	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1476	1			T5	3		T12	4		T16	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	109	1			T5	2		T6	2		T48	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	715	1			T5	15		T6	2		T77	18
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	95	1			T6	2		T156	1		T155	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	541	1			T6	2		T155	48		T77	23
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	87	1			T5	2		T16	1		T154	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	649	1			T5	41		T16	1		T154	35
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	83	1			T90	14		T155	1		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	667	1			T90	10		T155	3		T171	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	100	1			T40	1		T157	1		T48	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	401	1			T40	1		T157	10		T48	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	92	1			T5	1		T6	1		T16	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	514	1			T5	13		T16	1		T156	2

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1868449	1			T1	1		T2	1		T4	58
auto[0]	auto[0]	auto[1]	970630	1			T4	840		T5	9		T14	2
auto[0]	auto[1]	auto[0]	418319	1			T5	800		T6	1158		T7	513
auto[0]	auto[1]	auto[1]	12609	1			T5	3		T230	2		T231	118
auto[1]	auto[0]	auto[0]	22215	1			T5	333		T6	22		T7	31
auto[1]	auto[0]	auto[1]	516	1			T6	1		T12	1		T14	2
auto[1]	auto[1]	auto[0]	6045	1			T5	78		T6	9		T12	7
auto[1]	auto[1]	auto[1]	129	1			T6	2		T157	2		T90	6