Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2633908	1			T1	1		T2	1		T3	32
all_pins[1]	2633908	1			T1	1		T2	1		T3	32
all_pins[2]	2633908	1			T1	1		T2	1		T3	32
all_pins[3]	2633908	1			T1	1		T2	1		T3	32
all_pins[4]	2633908	1			T1	1		T2	1		T3	32
all_pins[5]	2633908	1			T1	1		T2	1		T3	32
all_pins[6]	2633908	1			T1	1		T2	1		T3	32
all_pins[7]	2633908	1			T1	1		T2	1		T3	32

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21049321	1			T1	8		T2	8		T3	213
values[0x1]	21943	1			T3	43		T7	44		T13	24
transitions[0x0=>0x1]	20416	1			T3	34		T7	30		T13	18
transitions[0x1=>0x0]	20431	1			T3	34		T7	30		T13	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2633402	1			T1	1		T2	1		T3	21
all_pins[0]	values[0x1]	506	1			T3	11		T7	6		T13	5
all_pins[0]	transitions[0x0=>0x1]	177	1			T3	8		T7	6		T13	2
all_pins[0]	transitions[0x1=>0x0]	162	1			T3	2		T7	6		T13	2
all_pins[1]	values[0x0]	2633417	1			T1	1		T2	1		T3	27
all_pins[1]	values[0x1]	491	1			T3	5		T7	6		T13	5
all_pins[1]	transitions[0x0=>0x1]	405	1			T3	5		T7	2		T13	3
all_pins[1]	transitions[0x1=>0x0]	218	1			T3	3		T7	4		T13	1
all_pins[2]	values[0x0]	2633604	1			T1	1		T2	1		T3	29
all_pins[2]	values[0x1]	304	1			T3	3		T7	8		T13	3
all_pins[2]	transitions[0x0=>0x1]	249	1			T3	3		T7	5		T13	3
all_pins[2]	transitions[0x1=>0x0]	122	1			T3	2		T7	2		T13	2
all_pins[3]	values[0x0]	2633731	1			T1	1		T2	1		T3	30
all_pins[3]	values[0x1]	177	1			T3	2		T7	5		T13	2
all_pins[3]	transitions[0x0=>0x1]	128	1			T3	1		T7	4		T13	2
all_pins[3]	transitions[0x1=>0x0]	136	1			T3	4		T7	3		T13	3
all_pins[4]	values[0x0]	2633723	1			T1	1		T2	1		T3	27
all_pins[4]	values[0x1]	185	1			T3	5		T7	4		T13	3
all_pins[4]	transitions[0x0=>0x1]	145	1			T3	4		T7	4		T13	2
all_pins[4]	transitions[0x1=>0x0]	1063	1			T3	5		T7	3		T13	2
all_pins[5]	values[0x0]	2632805	1			T1	1		T2	1		T3	26
all_pins[5]	values[0x1]	1103	1			T3	6		T7	3		T13	3
all_pins[5]	transitions[0x0=>0x1]	232	1			T3	5		T7	2		T13	3
all_pins[5]	transitions[0x1=>0x0]	18126	1			T3	4		T7	6		T13	3
all_pins[6]	values[0x0]	2614911	1			T1	1		T2	1		T3	27
all_pins[6]	values[0x1]	18997	1			T3	5		T7	7		T13	3
all_pins[6]	transitions[0x0=>0x1]	18944	1			T3	2		T7	4		T13	3
all_pins[6]	transitions[0x1=>0x0]	127	1			T3	3		T7	2		T17	2
all_pins[7]	values[0x0]	2633728	1			T1	1		T2	1		T3	26
all_pins[7]	values[0x1]	180	1			T3	6		T7	5		T17	3
all_pins[7]	transitions[0x0=>0x1]	136	1			T3	6		T7	3		T17	2
all_pins[7]	transitions[0x1=>0x0]	477	1			T3	11		T7	4		T13	5