Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16132

1

T1

2

T4

10

T7

84

auto[1]

11326

1

T2

18

T7

47

T13

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2643	1			T2	18		T11	18		T14	25
values[1]	4097	1			T7	20		T14	128		T45	2
values[2]	3438	1			T13	21		T14	27		T39	20
values[3]	2885	1			T4	10		T7	20		T14	51
values[4]	3858	1			T14	108		T16	98		T40	40
values[5]	2778	1			T44	4		T14	20		T16	45
values[6]	3839	1			T7	20		T14	25		T16	94
values[7]	3920	1			T1	2		T7	71		T13	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3618	1			T7	30		T13	21		T14	155
values[1]	3928	1			T13	26		T16	75		T40	40
values[2]	3143	1			T2	18		T7	20		T14	47
values[3]	3667	1			T1	2		T14	49		T16	23
values[4]	3480	1			T33	24		T44	4		T14	45
values[5]	2639	1			T11	18		T14	53		T16	100
values[6]	3642	1			T7	41		T14	60		T16	58
values[7]	3341	1			T4	10		T7	40		T39	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	151	1			T204	8		T155	17		T232	12
auto[0]	values[0]	values[1]	294	1			T231	14		T233	26		T234	22
auto[0]	values[0]	values[2]	120	1			T156	15		T183	57		T235	2
auto[0]	values[0]	values[3]	196	1			T16	17		T40	14		T41	17
auto[0]	values[0]	values[4]	203	1			T41	8		T171	14		T169	10
auto[0]	values[0]	values[5]	219	1			T11	18		T14	12		T236	4
auto[0]	values[0]	values[6]	225	1			T190	18		T237	10		T222	8
auto[0]	values[0]	values[7]	198	1			T186	8		T173	16		T74	37
auto[0]	values[1]	values[0]	276	1			T238	14		T186	14		T179	16
auto[0]	values[1]	values[1]	172	1			T228	6		T186	19		T173	12
auto[0]	values[1]	values[2]	286	1			T7	11		T14	13		T45	2
auto[0]	values[1]	values[3]	350	1			T14	25		T156	11		T153	13
auto[0]	values[1]	values[4]	190	1			T14	11		T41	8		T239	10
auto[0]	values[1]	values[5]	179	1			T14	19		T16	11		T153	13
auto[0]	values[1]	values[6]	363	1			T14	10		T32	13		T174	16
auto[0]	values[1]	values[7]	458	1			T16	11		T153	25		T154	109
auto[0]	values[2]	values[0]	350	1			T13	8		T14	8		T153	32
auto[0]	values[2]	values[1]	340	1			T16	13		T156	14		T153	16
auto[0]	values[2]	values[2]	189	1			T156	10		T240	14		T173	18
auto[0]	values[2]	values[3]	184	1			T32	15		T41	11		T19	13
auto[0]	values[2]	values[4]	189	1			T16	8		T19	13		T180	17
auto[0]	values[2]	values[5]	195	1			T32	9		T205	15		T155	43
auto[0]	values[2]	values[6]	334	1			T192	2		T205	7		T216	16
auto[0]	values[2]	values[7]	279	1			T39	13		T205	11		T74	32
auto[0]	values[3]	values[0]	207	1			T194	15		T169	67		T188	11
auto[0]	values[3]	values[1]	251	1			T16	12		T154	8		T222	10
auto[0]	values[3]	values[2]	141	1			T16	10		T156	11		T241	16
auto[0]	values[3]	values[3]	356	1			T14	13		T40	16		T242	71
auto[0]	values[3]	values[4]	270	1			T153	13		T171	17		T243	2
auto[0]	values[3]	values[5]	217	1			T171	6		T194	25		T170	15
auto[0]	values[3]	values[6]	193	1			T14	15		T46	12		T41	14
auto[0]	values[3]	values[7]	140	1			T4	10		T7	9		T244	2
auto[0]	values[4]	values[0]	348	1			T14	98		T222	14		T188	12
auto[0]	values[4]	values[1]	368	1			T40	36		T156	81		T245	12
auto[0]	values[4]	values[2]	263	1			T156	14		T246	20		T247	10
auto[0]	values[4]	values[3]	160	1			T156	10		T153	10		T222	11
auto[0]	values[4]	values[4]	300	1			T16	12		T155	9		T209	68
auto[0]	values[4]	values[5]	198	1			T16	8		T248	6		T194	13
auto[0]	values[4]	values[6]	223	1			T16	13		T155	13		T177	6
auto[0]	values[4]	values[7]	244	1			T249	4		T180	8		T199	6
auto[0]	values[5]	values[0]	120	1			T14	9		T16	9		T250	2
auto[0]	values[5]	values[1]	231	1			T153	11		T191	16		T251	4
auto[0]	values[5]	values[2]	245	1			T16	16		T40	16		T252	2
auto[0]	values[5]	values[3]	272	1			T155	15		T147	12		T169	9
auto[0]	values[5]	values[4]	178	1			T44	4		T153	17		T154	8
auto[0]	values[5]	values[5]	238	1			T253	18		T147	10		T169	11
auto[0]	values[5]	values[6]	84	1			T187	15		T254	6		T151	33
auto[0]	values[5]	values[7]	205	1			T205	29		T154	18		T167	10
auto[0]	values[6]	values[0]	388	1			T16	13		T40	9		T218	97
auto[0]	values[6]	values[1]	311	1			T19	5		T213	20		T184	22
auto[0]	values[6]	values[2]	317	1			T14	11		T218	8		T255	50
auto[0]	values[6]	values[3]	307	1			T41	14		T256	10		T257	8
auto[0]	values[6]	values[4]	235	1			T16	13		T194	58		T186	9
auto[0]	values[6]	values[5]	79	1			T16	7		T218	6		T188	11
auto[0]	values[6]	values[6]	201	1			T154	7		T171	12		T74	9
auto[0]	values[6]	values[7]	416	1			T7	11		T16	21		T194	14
auto[0]	values[7]	values[0]	324	1			T7	18		T32	34		T155	26
auto[0]	values[7]	values[1]	272	1			T13	17		T16	10		T153	16
auto[0]	values[7]	values[2]	261	1			T16	20		T34	14		T229	16
auto[0]	values[7]	values[3]	315	1			T1	2		T156	18		T258	22
auto[0]	values[7]	values[4]	490	1			T14	14		T230	4		T156	6
auto[0]	values[7]	values[5]	187	1			T16	20		T152	79		T169	11
auto[0]	values[7]	values[6]	394	1			T7	35		T40	34		T156	15
auto[0]	values[7]	values[7]	243	1			T16	15		T41	11		T259	16
auto[1]	values[0]	values[0]	140	1			T155	3		T208	11		T187	18
auto[1]	values[0]	values[1]	210	1			T194	52		T216	14		T173	5
auto[1]	values[0]	values[2]	66	1			T2	18		T156	6		T227	9
auto[1]	values[0]	values[3]	77	1			T16	6		T40	6		T41	3
auto[1]	values[0]	values[4]	174	1			T41	12		T101	18		T171	6
auto[1]	values[0]	values[5]	104	1			T14	13		T216	11		T147	6
auto[1]	values[0]	values[6]	83	1			T222	12		T219	9		T260	1
auto[1]	values[0]	values[7]	183	1			T261	16		T186	12		T173	4
auto[1]	values[1]	values[0]	207	1			T186	6		T168	32		T219	31
auto[1]	values[1]	values[1]	136	1			T43	20		T186	21		T173	10
auto[1]	values[1]	values[2]	171	1			T7	9		T14	9		T155	8
auto[1]	values[1]	values[3]	255	1			T14	4		T156	13		T153	7
auto[1]	values[1]	values[4]	292	1			T14	9		T41	12		T170	11
auto[1]	values[1]	values[5]	143	1			T14	9		T16	9		T153	21
auto[1]	values[1]	values[6]	395	1			T14	19		T32	34		T154	8
auto[1]	values[1]	values[7]	224	1			T16	12		T153	42		T154	7
auto[1]	values[2]	values[0]	153	1			T13	13		T14	19		T153	7
auto[1]	values[2]	values[1]	342	1			T16	12		T156	10		T153	4
auto[1]	values[2]	values[2]	212	1			T156	13		T173	22		T188	11
auto[1]	values[2]	values[3]	164	1			T32	5		T41	9		T19	14
auto[1]	values[2]	values[4]	178	1			T16	12		T19	7		T180	3
auto[1]	values[2]	values[5]	98	1			T32	11		T262	2		T205	5
auto[1]	values[2]	values[6]	102	1			T205	13		T216	4		T180	9
auto[1]	values[2]	values[7]	129	1			T39	7		T205	10		T74	34
auto[1]	values[3]	values[0]	133	1			T197	6		T194	5		T169	6
auto[1]	values[3]	values[1]	188	1			T16	18		T154	78		T222	10
auto[1]	values[3]	values[2]	92	1			T16	12		T156	22		T194	8
auto[1]	values[3]	values[3]	218	1			T14	7		T40	11		T155	57
auto[1]	values[3]	values[4]	95	1			T153	8		T171	6		T217	6
auto[1]	values[3]	values[5]	177	1			T171	18		T194	11		T170	8
auto[1]	values[3]	values[6]	147	1			T14	16		T46	8		T41	6
auto[1]	values[3]	values[7]	60	1			T7	11		T151	13		T200	9
auto[1]	values[4]	values[0]	334	1			T14	10		T222	6		T188	10
auto[1]	values[4]	values[1]	305	1			T40	4		T156	5		T188	59
auto[1]	values[4]	values[2]	155	1			T156	6		T208	10		T189	7
auto[1]	values[4]	values[3]	271	1			T156	10		T153	10		T222	12
auto[1]	values[4]	values[4]	142	1			T16	8		T155	11		T209	8
auto[1]	values[4]	values[5]	182	1			T16	12		T263	10		T194	42
auto[1]	values[4]	values[6]	173	1			T16	45		T155	7		T181	8
auto[1]	values[4]	values[7]	192	1			T71	10		T180	12		T199	14
auto[1]	values[5]	values[0]	102	1			T14	11		T16	11		T170	7
auto[1]	values[5]	values[1]	167	1			T153	9		T171	6		T168	9
auto[1]	values[5]	values[2]	278	1			T16	9		T40	8		T222	7
auto[1]	values[5]	values[3]	182	1			T155	41		T147	14		T169	12
auto[1]	values[5]	values[4]	130	1			T153	3		T154	48		T173	7
auto[1]	values[5]	values[5]	101	1			T253	2		T147	10		T169	9
auto[1]	values[5]	values[6]	135	1			T42	20		T187	30		T254	14
auto[1]	values[5]	values[7]	110	1			T205	5		T154	6		T167	10
auto[1]	values[6]	values[0]	180	1			T16	7		T40	11		T218	9
auto[1]	values[6]	values[1]	169	1			T19	35		T74	12		T172	19
auto[1]	values[6]	values[2]	144	1			T14	14		T218	12		T211	9
auto[1]	values[6]	values[3]	154	1			T41	6		T74	14		T170	3
auto[1]	values[6]	values[4]	163	1			T16	9		T194	51		T186	11
auto[1]	values[6]	values[5]	230	1			T16	13		T91	20		T218	32
auto[1]	values[6]	values[6]	386	1			T154	13		T171	13		T74	11
auto[1]	values[6]	values[7]	159	1			T7	9		T16	11		T194	6
auto[1]	values[7]	values[0]	205	1			T7	12		T32	6		T155	32
auto[1]	values[7]	values[1]	172	1			T13	9		T16	10		T153	4
auto[1]	values[7]	values[2]	203	1			T16	6		T194	6		T217	8
auto[1]	values[7]	values[3]	206	1			T156	23		T171	13		T147	6
auto[1]	values[7]	values[4]	251	1			T33	24		T14	11		T156	15
auto[1]	values[7]	values[5]	92	1			T16	20		T169	9		T208	6
auto[1]	values[7]	values[6]	204	1			T7	6		T40	10		T156	5
auto[1]	values[7]	values[7]	101	1			T16	5		T41	9		T209	15