Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	400	1			T7	1		T14	7		T16	4
auto[ReadAddrCrossIntoMailbox]	271	1			T7	2		T14	2		T16	4
auto[ReadAddrCrossOutOfMailbox]	309	1			T14	2		T16	6		T32	1
auto[ReadAddrCrossAllMailbox]	217	1			T7	2		T14	8		T16	6
auto[ReadAddrOutsideMailbox]	3328	1			T2	2		T7	15		T13	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2283

1

T2

1

T7

11

T13

3

auto[1]

2242

1

T2

1

T7

9

T13

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	773	1			T7	3		T13	2		T14	13
read_ops[0x0b]	728	1			T2	2		T7	2		T13	3
read_ops[0x3b]	762	1			T7	4		T13	2		T14	9
read_ops[0x6b]	744	1			T7	2		T13	1		T14	12
read_ops[0xbb]	736	1			T7	4		T33	2		T14	9
read_ops[0xeb]	782	1			T7	5		T13	2		T33	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T14	1		T32	1		T171	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T16	1		T41	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	34	1			T7	1		T194	1		T209	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T156	1		T205	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T222	1		T214	1		T209	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T40	2		T154	2		T222	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T156	3		T194	1		T240	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T14	1		T155	1		T222	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T13	1		T14	11		T16	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T7	2		T13	1		T16	7
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T40	1		T174	1		T154	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T16	1		T40	1		T174	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T14	1		T32	1		T156	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T16	2		T222	1		T147	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T16	2		T32	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T16	1		T41	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T32	1		T213	2		T147	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T16	2		T154	1		T213	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T2	1		T7	2		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	272	1			T2	1		T13	3		T14	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T14	1		T40	1		T153	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T7	1		T155	1		T213	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T155	1		T222	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T7	1		T16	1		T171	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T16	1		T205	1		T265	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T16	1		T40	1		T154	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T7	1		T41	1		T156	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T14	2		T16	2		T171	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T7	1		T13	2		T14	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T14	3		T39	2		T16	8
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T14	1		T16	1		T40	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T14	1		T16	1		T156	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T222	1		T209	1		T147	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T14	1		T16	1		T156	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T171	2		T186	1		T173	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T156	1		T154	1		T171	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T222	3		T171	1		T169	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T14	2		T41	1		T194	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T14	3		T16	9		T40	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T7	2		T13	1		T14	4
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T156	1		T153	1		T194	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T14	3		T222	1		T171	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T147	1		T211	2		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T180	1		T187	1		T181	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T40	1		T171	1		T194	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T14	1		T40	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T7	1		T14	2		T16	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T222	1		T188	1		T167	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	261	1			T7	2		T33	1		T14	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T7	1		T33	1		T16	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T156	1		T237	1		T19	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T156	1		T153	2		T205	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T154	1		T19	1		T147	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T40	1		T41	1		T266	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T14	1		T16	1		T155	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T240	2		T74	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T14	1		T74	2		T170	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T16	1		T40	1		T41	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	282	1			T7	3		T33	2		T14	6
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	285	1			T7	2		T13	2		T33	2