Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3204	1			T16	100		T32	20		T230	4
values[1]	3638	1			T11	18		T33	24		T244	2
values[2]	2969	1			T1	2		T7	20		T44	4
values[3]	3939	1			T7	20		T14	89		T16	45
values[4]	3762	1			T7	30		T13	47		T14	73
values[5]	3358	1			T4	10		T7	41		T14	133
values[6]	3544	1			T2	18		T7	20		T14	67
values[7]	3044	1			T14	25		T204	8		T16	87

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3535	1			T2	18		T14	54		T16	83
values[1]	3356	1			T1	2		T7	61		T14	60
values[2]	3538	1			T4	10		T7	30		T11	18
values[3]	3114	1			T7	20		T45	2		T16	62
values[4]	3308	1			T44	4		T16	20		T192	2
values[5]	3381	1			T16	70		T40	68		T41	20
values[6]	3299	1			T14	155		T39	20		T16	70
values[7]	3927	1			T7	20		T13	21		T14	73

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26799

1

T1

2

T2

18

T4

10

auto[1]

659

1

T7

3

T13

1

T33

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	369	1			T16	20		T177	6		T147	47
auto[0]	values[0]	values[1]	555	1			T16	57		T234	22		T169	21
auto[0]	values[0]	values[2]	317	1			T32	19		T216	20		T169	53
auto[0]	values[0]	values[3]	337	1			T230	4		T74	20		T267	16
auto[0]	values[0]	values[4]	584	1			T228	6		T155	53		T209	20
auto[0]	values[0]	values[5]	266	1			T168	32		T172	73		T202	10
auto[0]	values[0]	values[6]	332	1			T40	27		T190	18		T101	18
auto[0]	values[0]	values[7]	373	1			T16	21		T250	2		T74	39
auto[0]	values[1]	values[0]	322	1			T152	79		T261	16		T186	40
auto[0]	values[1]	values[1]	211	1			T156	21		T179	16		T268	54
auto[0]	values[1]	values[2]	566	1			T11	18		T33	22		T244	2
auto[0]	values[1]	values[3]	313	1			T188	19		T168	20		T187	43
auto[0]	values[1]	values[4]	621	1			T156	20		T153	20		T263	10
auto[0]	values[1]	values[5]	534	1			T40	41		T155	101		T171	24
auto[0]	values[1]	values[6]	302	1			T34	14		T253	18		T252	2
auto[0]	values[1]	values[7]	677	1			T222	20		T184	22		T209	56
auto[0]	values[2]	values[0]	457	1			T16	16		T156	20		T154	20
auto[0]	values[2]	values[1]	245	1			T1	2		T7	20		T91	20
auto[0]	values[2]	values[2]	376	1			T32	20		T156	20		T153	34
auto[0]	values[2]	values[3]	210	1			T46	20		T194	20		T172	26
auto[0]	values[2]	values[4]	430	1			T44	4		T16	20		T192	2
auto[0]	values[2]	values[5]	285	1			T155	20		T168	18		T269	8
auto[0]	values[2]	values[6]	437	1			T14	21		T39	20		T16	30
auto[0]	values[2]	values[7]	462	1			T191	16		T147	19		T71	10
auto[0]	values[3]	values[0]	535	1			T14	26		T194	85		T186	18
auto[0]	values[3]	values[1]	480	1			T14	60		T156	23		T153	20
auto[0]	values[3]	values[2]	478	1			T16	20		T41	20		T237	10
auto[0]	values[3]	values[3]	654	1			T222	20		T169	26		T188	42
auto[0]	values[3]	values[4]	404	1			T153	39		T194	51		T270	20
auto[0]	values[3]	values[5]	432	1			T16	25		T41	17		T154	24
auto[0]	values[3]	values[6]	361	1			T41	20		T156	32		T258	22
auto[0]	values[3]	values[7]	507	1			T7	20		T174	16		T155	19
auto[0]	values[4]	values[0]	616	1			T14	25		T41	20		T239	10
auto[0]	values[4]	values[1]	389	1			T155	69		T154	56		T222	21
auto[0]	values[4]	values[2]	432	1			T7	29		T13	25		T41	19
auto[0]	values[4]	values[3]	328	1			T16	20		T229	16		T153	59
auto[0]	values[4]	values[4]	358	1			T153	20		T209	20		T173	20
auto[0]	values[4]	values[5]	403	1			T156	106		T257	8		T215	16
auto[0]	values[4]	values[6]	437	1			T40	19		T153	38		T186	20
auto[0]	values[4]	values[7]	715	1			T13	21		T14	48		T32	47
auto[0]	values[5]	values[0]	204	1			T16	22		T171	42		T254	54
auto[0]	values[5]	values[1]	476	1			T7	40		T16	20		T186	20
auto[0]	values[5]	values[2]	416	1			T4	10		T233	26		T19	40
auto[0]	values[5]	values[3]	331	1			T45	2		T231	14		T153	20
auto[0]	values[5]	values[4]	327	1			T171	46		T271	20		T209	75
auto[0]	values[5]	values[5]	441	1			T16	20		T40	24		T155	43
auto[0]	values[5]	values[6]	597	1			T14	127		T214	20		T188	33
auto[0]	values[5]	values[7]	476	1			T16	24		T41	20		T209	20
auto[0]	values[6]	values[0]	500	1			T2	18		T16	20		T154	115
auto[0]	values[6]	values[1]	506	1			T242	71		T216	28		T173	20
auto[0]	values[6]	values[2]	460	1			T14	64		T16	32		T43	18
auto[0]	values[6]	values[3]	496	1			T7	19		T272	4		T262	2
auto[0]	values[6]	values[4]	288	1			T208	20		T220	22		T273	19
auto[0]	values[6]	values[5]	486	1			T205	31		T274	18		T172	30
auto[0]	values[6]	values[6]	406	1			T16	19		T205	20		T155	54
auto[0]	values[6]	values[7]	315	1			T16	21		T238	14		T181	20
auto[0]	values[7]	values[0]	437	1			T40	38		T42	18		T153	24
auto[0]	values[7]	values[1]	404	1			T74	34		T199	20		T178	31
auto[0]	values[7]	values[2]	406	1			T40	20		T165	12		T147	26
auto[0]	values[7]	values[3]	357	1			T16	39		T173	20		T180	20
auto[0]	values[7]	values[4]	235	1			T41	20		T187	20		T275	8
auto[0]	values[7]	values[5]	452	1			T16	25		T216	24		T218	106
auto[0]	values[7]	values[6]	354	1			T16	20		T156	19		T186	19
auto[0]	values[7]	values[7]	319	1			T14	24		T204	8		T156	21
auto[1]	values[0]	values[0]	16	1			T147	3		T173	7		T199	1
auto[1]	values[0]	values[1]	14	1			T16	1		T260	1		T276	1
auto[1]	values[0]	values[2]	4	1			T32	1		T217	2		T277	1
auto[1]	values[0]	values[3]	9	1			T208	2		T198	1		T200	3
auto[1]	values[0]	values[4]	7	1			T218	1		T219	2		T278	1
auto[1]	values[0]	values[5]	10	1			T168	2		T279	4		T175	2
auto[1]	values[0]	values[6]	2	1			T196	1		T131	1		-	-
auto[1]	values[0]	values[7]	9	1			T16	1		T168	2		T280	3
auto[1]	values[1]	values[0]	1	1			T276	1		-	-		-	-
auto[1]	values[1]	values[1]	3	1			T281	2		T282	1		-	-
auto[1]	values[1]	values[2]	22	1			T33	2		T155	2		T222	2
auto[1]	values[1]	values[3]	6	1			T188	1		T187	2		T283	1
auto[1]	values[1]	values[4]	15	1			T222	1		T74	1		T188	3
auto[1]	values[1]	values[5]	17	1			T40	3		T155	4		T171	1
auto[1]	values[1]	values[6]	17	1			T253	2		T168	1		T268	3
auto[1]	values[1]	values[7]	11	1			T209	2		T169	1		T168	1
auto[1]	values[2]	values[0]	11	1			T16	4		T156	1		T167	2
auto[1]	values[2]	values[1]	8	1			T32	1		T153	2		T155	4
auto[1]	values[2]	values[2]	12	1			T205	1		T171	3		T194	2
auto[1]	values[2]	values[3]	7	1			T151	1		T284	2		T285	4
auto[1]	values[2]	values[4]	10	1			T74	3		T181	1		T182	1
auto[1]	values[2]	values[5]	4	1			T168	2		T286	1		T51	1
auto[1]	values[2]	values[6]	4	1			T14	1		T287	1		T288	2
auto[1]	values[2]	values[7]	11	1			T147	1		T212	6		T289	2
auto[1]	values[3]	values[0]	19	1			T14	3		T194	2		T186	2
auto[1]	values[3]	values[1]	11	1			T194	2		T219	1		T181	1
auto[1]	values[3]	values[2]	7	1			T170	1		T286	1		T290	2
auto[1]	values[3]	values[3]	11	1			T291	2		T211	1		T217	1
auto[1]	values[3]	values[4]	7	1			T153	1		T170	2		T196	1
auto[1]	values[3]	values[5]	17	1			T41	3		T222	2		T186	2
auto[1]	values[3]	values[6]	10	1			T156	1		T264	2		T167	1
auto[1]	values[3]	values[7]	6	1			T155	1		T154	3		T292	1
auto[1]	values[4]	values[0]	17	1			T169	3		T219	3		T198	6
auto[1]	values[4]	values[1]	14	1			T222	1		T218	1		T188	4
auto[1]	values[4]	values[2]	8	1			T7	1		T13	1		T41	1
auto[1]	values[4]	values[3]	13	1			T153	2		T171	1		T167	2
auto[1]	values[4]	values[4]	7	1			T74	1		T172	1		T293	1
auto[1]	values[4]	values[5]	5	1			T294	2		T196	1		T295	1
auto[1]	values[4]	values[6]	7	1			T40	1		T153	1		T189	2
auto[1]	values[4]	values[7]	13	1			T222	2		T147	1		T188	1
auto[1]	values[5]	values[0]	6	1			T16	1		T171	2		T254	1
auto[1]	values[5]	values[1]	16	1			T7	1		T74	3		T170	3
auto[1]	values[5]	values[2]	9	1			T296	2		T297	2		T53	3
auto[1]	values[5]	values[3]	11	1			T153	1		T180	1		T187	1
auto[1]	values[5]	values[4]	8	1			T171	1		T209	1		T168	1
auto[1]	values[5]	values[5]	9	1			T155	1		T188	2		T289	1
auto[1]	values[5]	values[6]	13	1			T14	6		T188	1		T189	3
auto[1]	values[5]	values[7]	18	1			T16	2		T170	1		T167	3
auto[1]	values[6]	values[0]	8	1			T154	1		T194	1		T74	2
auto[1]	values[6]	values[1]	15	1			T182	1		T260	2		T298	2
auto[1]	values[6]	values[2]	13	1			T14	3		T43	2		T156	1
auto[1]	values[6]	values[3]	19	1			T7	1		T279	2		T254	5
auto[1]	values[6]	values[4]	4	1			T273	1		T51	3		-	-
auto[1]	values[6]	values[5]	9	1			T205	3		T182	1		T200	2
auto[1]	values[6]	values[6]	11	1			T16	1		T168	4		T299	4
auto[1]	values[6]	values[7]	8	1			T16	2		T278	3		T300	2
auto[1]	values[7]	values[0]	17	1			T40	2		T42	2		T154	2
auto[1]	values[7]	values[1]	9	1			T74	1		T178	1		T200	5
auto[1]	values[7]	values[2]	12	1			T175	1		T294	2		T301	1
auto[1]	values[7]	values[3]	12	1			T16	3		T187	3		T227	1
auto[1]	values[7]	values[4]	3	1			T182	1		T254	2		-	-
auto[1]	values[7]	values[5]	11	1			T216	3		T227	2		T302	2
auto[1]	values[7]	values[6]	9	1			T156	1		T186	1		T175	2
auto[1]	values[7]	values[7]	7	1			T14	1		T216	1		T172	2