Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	872	1			T3	27		T7	18		T13	10
all_values[1]	872	1			T3	27		T7	18		T13	10
all_values[2]	872	1			T3	27		T7	18		T13	10
all_values[3]	872	1			T3	27		T7	18		T13	10
all_values[4]	872	1			T3	27		T7	18		T13	10
all_values[5]	872	1			T3	27		T7	18		T13	10
all_values[6]	872	1			T3	27		T7	18		T13	10
all_values[7]	872	1			T3	27		T7	18		T13	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3713

1

T3

129

T7

71

T13

44

auto[1]

3263

1

T3

87

T7

73

T13

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2777

1

T3

88

T7

47

T13

30

auto[1]

4199

1

T3

128

T7

97

T13

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3932

1

T3

113

T7

72

T13

41

auto[1]

3044

1

T3

103

T7

72

T13

39

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T3	1		T7	1		T13	2
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T3	3		T7	1		T17	4
all_values[0]	auto[0]	auto[1]	auto[0]	154	1			T3	2		T7	3		T13	2
all_values[0]	auto[0]	auto[1]	auto[1]	75	1			T3	5		T7	2		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T3	10		T7	7		T13	1
all_values[0]	auto[1]	auto[1]	auto[1]	190	1			T3	6		T7	4		T13	4
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T3	7		T7	4		T13	1
all_values[1]	auto[0]	auto[0]	auto[1]	91	1			T3	3		T7	3		T13	1
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T3	2		T13	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T3	1		T7	3		T13	1
all_values[1]	auto[1]	auto[0]	auto[1]	227	1			T3	10		T7	3		T13	2
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T3	4		T7	5		T13	3
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T3	7		T17	5		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	80	1			T13	2		T17	3		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	158	1			T3	6		T7	3		T13	2
all_values[2]	auto[0]	auto[1]	auto[1]	85	1			T3	2		T7	2		T13	1
all_values[2]	auto[1]	auto[0]	auto[1]	209	1			T3	9		T7	6		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	177	1			T3	3		T7	7		T13	3
all_values[3]	auto[0]	auto[0]	auto[0]	194	1			T3	9		T7	7		T13	6
all_values[3]	auto[0]	auto[0]	auto[1]	86	1			T3	2		T7	1		T17	2
all_values[3]	auto[0]	auto[1]	auto[0]	145	1			T3	4		T7	2		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	78	1			T7	2		T13	1		T20	1
all_values[3]	auto[1]	auto[0]	auto[1]	214	1			T3	7		T7	1		T13	3
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T3	5		T7	5		T17	4
all_values[4]	auto[0]	auto[0]	auto[0]	178	1			T3	12		T7	5		T13	2
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T13	2		T17	4		T18	2
all_values[4]	auto[0]	auto[1]	auto[0]	180	1			T3	3		T7	3		T13	1
all_values[4]	auto[0]	auto[1]	auto[1]	78	1			T3	1		T7	2		T18	2
all_values[4]	auto[1]	auto[0]	auto[1]	198	1			T3	6		T7	5		T13	1
all_values[4]	auto[1]	auto[1]	auto[1]	172	1			T3	5		T7	3		T13	4
all_values[5]	auto[0]	auto[0]	auto[0]	240	1			T3	6		T7	5		T13	3
all_values[5]	auto[0]	auto[1]	auto[0]	238	1			T3	6		T7	3		T17	3
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T3	8		T7	5		T13	3
all_values[5]	auto[1]	auto[1]	auto[1]	192	1			T3	7		T7	5		T13	4
all_values[6]	auto[0]	auto[0]	auto[0]	159	1			T3	10		T7	2		T17	3
all_values[6]	auto[0]	auto[0]	auto[1]	90	1			T3	2		T7	1		T13	1
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T3	2		T7	3		T13	1
all_values[6]	auto[0]	auto[1]	auto[1]	99	1			T3	2		T7	4		T13	1
all_values[6]	auto[1]	auto[0]	auto[1]	210	1			T3	5		T7	6		T13	5
all_values[6]	auto[1]	auto[1]	auto[1]	182	1			T3	6		T7	2		T13	2
all_values[7]	auto[0]	auto[0]	auto[0]	206	1			T3	4		T7	1		T13	5
all_values[7]	auto[0]	auto[0]	auto[1]	82	1			T3	2		T7	3		T17	3
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T3	7		T7	5		T13	3
all_values[7]	auto[0]	auto[1]	auto[1]	72	1			T3	2		T7	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	200	1			T3	6		T7	4		T13	2
all_values[7]	auto[1]	auto[1]	auto[1]	158	1			T3	6		T7	4		T17	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal