Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1643

1

T6

13

T7

6

T9

4

auto[1]

1634

1

T6

6

T7

17

T9

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1740

1

T6

19

T7

14

T12

15

auto[1]

1537

1

T7

9

T9

12

T14

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2604

1

T6

13

T7

16

T9

12

auto[1]

673

1

T6

6

T7

7

T12

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	622	1			T6	3		T7	5		T9	1
valid[1]	712	1			T6	3		T7	9		T9	2
valid[2]	627	1			T6	2		T9	5		T12	1
valid[3]	666	1			T6	4		T7	3		T9	1
valid[4]	650	1			T6	7		T7	6		T9	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T7	1		T12	1		T14	1
auto[0]	auto[0]	valid[0]	auto[1]	149	1			T7	2		T9	1		T23	3
auto[0]	auto[0]	valid[1]	auto[0]	113	1			T6	1		T12	1		T16	3
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T7	1		T82	3		T83	3
auto[0]	auto[0]	valid[2]	auto[0]	105	1			T6	2		T31	2		T40	2
auto[0]	auto[0]	valid[2]	auto[1]	148	1			T9	1		T23	1		T82	1
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T6	3		T12	1		T16	1
auto[0]	auto[0]	valid[3]	auto[1]	143	1			T9	1		T15	1		T23	1
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T6	3		T16	1		T31	2
auto[0]	auto[0]	valid[4]	auto[1]	138	1			T7	2		T9	1		T14	1
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T6	1		T7	1		T12	2
auto[0]	auto[1]	valid[0]	auto[1]	153	1			T7	1		T14	1		T82	2
auto[0]	auto[1]	valid[1]	auto[0]	110	1			T7	1		T12	2		T16	4
auto[0]	auto[1]	valid[1]	auto[1]	173	1			T7	3		T9	2		T14	1
auto[0]	auto[1]	valid[2]	auto[0]	90	1			T12	1		T16	1		T48	1
auto[0]	auto[1]	valid[2]	auto[1]	141	1			T9	4		T23	1		T82	3
auto[0]	auto[1]	valid[3]	auto[0]	109	1			T7	2		T12	1		T13	1
auto[0]	auto[1]	valid[3]	auto[1]	166	1			T14	1		T23	1		T24	2
auto[0]	auto[1]	valid[4]	auto[0]	96	1			T6	3		T7	2		T12	2
auto[0]	auto[1]	valid[4]	auto[1]	163	1			T9	2		T24	1		T82	2
auto[1]	auto[0]	valid[0]	auto[0]	54	1			T6	2		T47	1		T48	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T6	1		T13	1		T16	2
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T16	1		T31	2		T314	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T12	1		T16	2		T31	1
auto[1]	auto[0]	valid[4]	auto[0]	69	1			T6	1		T12	1		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	53	1			T31	1		T40	1		T314	1
auto[1]	auto[1]	valid[1]	auto[0]	82	1			T6	1		T7	4		T12	1
auto[1]	auto[1]	valid[2]	auto[0]	66	1			T13	1		T16	2		T31	1
auto[1]	auto[1]	valid[3]	auto[0]	60	1			T6	1		T7	1		T40	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T7	2		T12	1		T31	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal