Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43756

1

T6

495

T7

383

T12

242

auto[1]

16142

1

T7

72

T9

106

T13

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

43784

1

T6

333

T7

302

T9

106

auto[1]

16114

1

T6

162

T7

153

T12

87

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	30833	1			T6	279		T7	230		T9	52
others[1]	5098	1			T6	41		T7	45		T9	5
others[2]	5021	1			T6	37		T7	51		T9	4
others[3]	5632	1			T6	36		T7	41		T9	13
interest[1]	3331	1			T6	26		T7	24		T9	11
interest[4]	20178	1			T6	174		T7	150		T9	32
interest[64]	9983	1			T6	76		T7	64		T9	21

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14178	1			T6	183		T7	119		T12	74
auto[0]	auto[0]	others[1]	2348	1			T6	33		T7	22		T12	10
auto[0]	auto[0]	others[2]	2364	1			T6	19		T7	31		T12	12
auto[0]	auto[0]	others[3]	2582	1			T6	23		T7	21		T12	14
auto[0]	auto[0]	interest[1]	1497	1			T6	17		T7	8		T12	16
auto[0]	auto[0]	interest[4]	9184	1			T6	116		T7	75		T12	45
auto[0]	auto[0]	interest[64]	4673	1			T6	58		T7	29		T12	29
auto[0]	auto[1]	others[0]	8389	1			T7	31		T9	52		T13	2
auto[0]	auto[1]	others[1]	1348	1			T7	11		T9	5		T13	1
auto[0]	auto[1]	others[2]	1295	1			T7	5		T9	4		T14	6
auto[0]	auto[1]	others[3]	1556	1			T7	6		T9	13		T13	1
auto[0]	auto[1]	interest[1]	926	1			T7	6		T9	11		T14	5
auto[0]	auto[1]	interest[4]	5565	1			T7	22		T9	32		T13	2
auto[0]	auto[1]	interest[64]	2628	1			T7	13		T9	21		T14	13
auto[1]	auto[0]	others[0]	8266	1			T6	96		T7	80		T12	41
auto[1]	auto[0]	others[1]	1402	1			T6	8		T7	12		T12	7
auto[1]	auto[0]	others[2]	1362	1			T6	18		T7	15		T12	8
auto[1]	auto[0]	others[3]	1494	1			T6	13		T7	14		T12	14
auto[1]	auto[0]	interest[1]	908	1			T6	9		T7	10		T12	7
auto[1]	auto[0]	interest[4]	5429	1			T6	58		T7	53		T12	26
auto[1]	auto[0]	interest[64]	2682	1			T6	18		T7	22		T12	10

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal