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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.10 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T114 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1111971029 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:51 PM PDT 24 305540996 ps
T1039 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1640793294 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:43 PM PDT 24 377369592 ps
T135 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1548655127 Jul 23 06:09:45 PM PDT 24 Jul 23 06:09:48 PM PDT 24 109378321 ps
T136 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.888553974 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:55 PM PDT 24 850627575 ps
T1040 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3824285272 Jul 23 06:09:48 PM PDT 24 Jul 23 06:09:49 PM PDT 24 23244518 ps
T115 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4084750334 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:16 PM PDT 24 1380677588 ps
T1041 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3253897368 Jul 23 06:09:55 PM PDT 24 Jul 23 06:09:59 PM PDT 24 16082997 ps
T99 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1247405419 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:39 PM PDT 24 65243062 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3042681978 Jul 23 06:09:16 PM PDT 24 Jul 23 06:09:21 PM PDT 24 223644381 ps
T1042 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3132956171 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:35 PM PDT 24 85806422 ps
T116 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3211831067 Jul 23 06:09:28 PM PDT 24 Jul 23 06:09:33 PM PDT 24 707047814 ps
T119 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1613663021 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:34 PM PDT 24 37865460 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3951673415 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:37 PM PDT 24 48961864 ps
T161 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.480555653 Jul 23 06:09:58 PM PDT 24 Jul 23 06:10:19 PM PDT 24 1305774568 ps
T100 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3267386265 Jul 23 06:09:54 PM PDT 24 Jul 23 06:10:01 PM PDT 24 182841229 ps
T120 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1709005970 Jul 23 06:09:24 PM PDT 24 Jul 23 06:09:28 PM PDT 24 36064989 ps
T1044 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2770088229 Jul 23 06:09:32 PM PDT 24 Jul 23 06:09:35 PM PDT 24 23338350 ps
T106 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.316373632 Jul 23 06:09:41 PM PDT 24 Jul 23 06:09:46 PM PDT 24 118877964 ps
T142 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.848070954 Jul 23 06:09:50 PM PDT 24 Jul 23 06:09:55 PM PDT 24 211715835 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1515431293 Jul 23 06:09:48 PM PDT 24 Jul 23 06:09:50 PM PDT 24 19806094 ps
T1046 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2820167517 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:00 PM PDT 24 108325968 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3133311663 Jul 23 06:09:39 PM PDT 24 Jul 23 06:09:42 PM PDT 24 23135115 ps
T105 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1767624502 Jul 23 06:09:21 PM PDT 24 Jul 23 06:09:24 PM PDT 24 62891617 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1881663973 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:47 PM PDT 24 2613021118 ps
T1049 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4047974288 Jul 23 06:09:55 PM PDT 24 Jul 23 06:09:58 PM PDT 24 17086432 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2016252382 Jul 23 06:09:52 PM PDT 24 Jul 23 06:09:54 PM PDT 24 24452234 ps
T1051 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2978020871 Jul 23 06:09:34 PM PDT 24 Jul 23 06:09:40 PM PDT 24 394649475 ps
T1052 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3915755882 Jul 23 06:09:32 PM PDT 24 Jul 23 06:09:38 PM PDT 24 87728556 ps
T121 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2363679483 Jul 23 06:09:42 PM PDT 24 Jul 23 06:09:45 PM PDT 24 100648156 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2770435135 Jul 23 06:09:40 PM PDT 24 Jul 23 06:09:44 PM PDT 24 78918909 ps
T1054 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4051962562 Jul 23 06:09:59 PM PDT 24 Jul 23 06:10:02 PM PDT 24 13917478 ps
T143 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3703702144 Jul 23 06:10:45 PM PDT 24 Jul 23 06:11:04 PM PDT 24 641134692 ps
T1055 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.791372757 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:48 PM PDT 24 42054971 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3980474351 Jul 23 06:09:41 PM PDT 24 Jul 23 06:09:44 PM PDT 24 85929358 ps
T1057 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1712527299 Jul 23 06:09:52 PM PDT 24 Jul 23 06:10:00 PM PDT 24 60710414 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1903041113 Jul 23 06:09:20 PM PDT 24 Jul 23 06:09:46 PM PDT 24 1215009467 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2483671992 Jul 23 06:09:42 PM PDT 24 Jul 23 06:09:46 PM PDT 24 75465249 ps
T1060 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.499187772 Jul 23 06:10:30 PM PDT 24 Jul 23 06:10:41 PM PDT 24 28754621 ps
T1061 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1939743741 Jul 23 06:09:45 PM PDT 24 Jul 23 06:10:05 PM PDT 24 1188333193 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3495772633 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:41 PM PDT 24 92271090 ps
T1063 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1002146570 Jul 23 06:09:50 PM PDT 24 Jul 23 06:09:53 PM PDT 24 53835168 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.683001311 Jul 23 06:09:25 PM PDT 24 Jul 23 06:09:47 PM PDT 24 1170630470 ps
T1064 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1997834936 Jul 23 06:10:01 PM PDT 24 Jul 23 06:10:05 PM PDT 24 28340621 ps
T1065 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3232461981 Jul 23 06:10:05 PM PDT 24 Jul 23 06:10:08 PM PDT 24 51797300 ps
T1066 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.256271669 Jul 23 06:09:50 PM PDT 24 Jul 23 06:09:53 PM PDT 24 26514877 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1671721739 Jul 23 06:09:17 PM PDT 24 Jul 23 06:09:43 PM PDT 24 10329088949 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1206590932 Jul 23 06:09:36 PM PDT 24 Jul 23 06:09:42 PM PDT 24 48112998 ps
T1068 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3888272949 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:56 PM PDT 24 18175540 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1308183051 Jul 23 06:09:55 PM PDT 24 Jul 23 06:10:05 PM PDT 24 390567099 ps
T1070 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.246441397 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:40 PM PDT 24 26751630 ps
T124 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.901493604 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:33 PM PDT 24 870692467 ps
T1071 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1638664546 Jul 23 06:09:28 PM PDT 24 Jul 23 06:09:33 PM PDT 24 107664907 ps
T1072 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1026068500 Jul 23 06:09:54 PM PDT 24 Jul 23 06:09:57 PM PDT 24 15864018 ps
T1073 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.267979663 Jul 23 06:09:22 PM PDT 24 Jul 23 06:09:32 PM PDT 24 202777179 ps
T125 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3370233203 Jul 23 06:09:43 PM PDT 24 Jul 23 06:09:46 PM PDT 24 26860524 ps
T1074 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4022225489 Jul 23 06:09:41 PM PDT 24 Jul 23 06:09:45 PM PDT 24 168825654 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1661967765 Jul 23 06:09:47 PM PDT 24 Jul 23 06:09:50 PM PDT 24 70662198 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.492745192 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:52 PM PDT 24 45342415 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2587104359 Jul 23 06:09:43 PM PDT 24 Jul 23 06:10:06 PM PDT 24 1003940997 ps
T126 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3957338354 Jul 23 06:09:21 PM PDT 24 Jul 23 06:09:24 PM PDT 24 124031171 ps
T1078 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.28849936 Jul 23 06:09:34 PM PDT 24 Jul 23 06:09:37 PM PDT 24 29121688 ps
T110 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3127463150 Jul 23 06:09:39 PM PDT 24 Jul 23 06:09:44 PM PDT 24 682188127 ps
T109 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1323587153 Jul 23 06:09:19 PM PDT 24 Jul 23 06:09:23 PM PDT 24 39697497 ps
T1079 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886396331 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:52 PM PDT 24 55146623 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1524385412 Jul 23 06:09:13 PM PDT 24 Jul 23 06:09:18 PM PDT 24 113712205 ps
T1081 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4002204717 Jul 23 06:09:43 PM PDT 24 Jul 23 06:09:50 PM PDT 24 274958437 ps
T107 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1399330456 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:34 PM PDT 24 181109975 ps
T127 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3163400726 Jul 23 06:09:23 PM PDT 24 Jul 23 06:09:26 PM PDT 24 58806564 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1202882228 Jul 23 06:09:43 PM PDT 24 Jul 23 06:09:45 PM PDT 24 39899121 ps
T144 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1226622902 Jul 23 06:09:40 PM PDT 24 Jul 23 06:10:04 PM PDT 24 3562585861 ps
T1083 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1020553401 Jul 23 06:09:34 PM PDT 24 Jul 23 06:09:38 PM PDT 24 68467056 ps
T128 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3876809968 Jul 23 06:09:23 PM PDT 24 Jul 23 06:09:58 PM PDT 24 547642481 ps
T145 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2032965487 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:38 PM PDT 24 58822626 ps
T1084 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4157749703 Jul 23 06:09:38 PM PDT 24 Jul 23 06:09:40 PM PDT 24 48903858 ps
T1085 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.779107795 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:40 PM PDT 24 132723201 ps
T1086 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.398672986 Jul 23 06:10:11 PM PDT 24 Jul 23 06:10:14 PM PDT 24 86333309 ps
T1087 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.995091637 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:33 PM PDT 24 257386554 ps
T1088 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2329723779 Jul 23 06:10:45 PM PDT 24 Jul 23 06:10:51 PM PDT 24 52291078 ps
T1089 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.892864701 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:35 PM PDT 24 96200971 ps
T1090 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1377084091 Jul 23 06:09:52 PM PDT 24 Jul 23 06:09:55 PM PDT 24 54458773 ps
T1091 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3795161637 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:38 PM PDT 24 272195299 ps
T1092 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1305474683 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:36 PM PDT 24 12412260 ps
T1093 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3280799279 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:34 PM PDT 24 74306356 ps
T146 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2299927248 Jul 23 06:09:36 PM PDT 24 Jul 23 06:09:41 PM PDT 24 367013341 ps
T1094 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1062662271 Jul 23 06:09:25 PM PDT 24 Jul 23 06:09:33 PM PDT 24 502286522 ps
T1095 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1760239037 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:36 PM PDT 24 139876841 ps
T159 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.73159645 Jul 23 06:09:25 PM PDT 24 Jul 23 06:09:32 PM PDT 24 387152584 ps
T129 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1922515862 Jul 23 06:09:57 PM PDT 24 Jul 23 06:10:02 PM PDT 24 52550038 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.457595387 Jul 23 06:09:14 PM PDT 24 Jul 23 06:09:17 PM PDT 24 86087745 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2410401139 Jul 23 06:09:51 PM PDT 24 Jul 23 06:09:55 PM PDT 24 76252893 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2274717495 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:40 PM PDT 24 14599449 ps
T1099 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.881600286 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:33 PM PDT 24 27203301 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.784566375 Jul 23 06:09:25 PM PDT 24 Jul 23 06:09:30 PM PDT 24 132371000 ps
T108 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2482036034 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:47 PM PDT 24 712483762 ps
T1101 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3601295339 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:39 PM PDT 24 1135938825 ps
T1102 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2967448882 Jul 23 06:10:48 PM PDT 24 Jul 23 06:10:53 PM PDT 24 12850677 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1174218961 Jul 23 06:09:55 PM PDT 24 Jul 23 06:09:58 PM PDT 24 17016038 ps
T1104 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4276201129 Jul 23 06:09:26 PM PDT 24 Jul 23 06:09:30 PM PDT 24 90972100 ps
T1105 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3193564908 Jul 23 06:09:38 PM PDT 24 Jul 23 06:09:41 PM PDT 24 18741300 ps
T1106 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.159133921 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:34 PM PDT 24 23891194 ps
T1107 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4268414755 Jul 23 06:09:52 PM PDT 24 Jul 23 06:09:54 PM PDT 24 24218601 ps
T1108 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1512499691 Jul 23 06:09:34 PM PDT 24 Jul 23 06:09:56 PM PDT 24 5135363801 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1818204128 Jul 23 06:09:19 PM PDT 24 Jul 23 06:09:28 PM PDT 24 77093892 ps
T1110 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3371162075 Jul 23 06:09:32 PM PDT 24 Jul 23 06:09:39 PM PDT 24 49694673 ps
T1111 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2760373848 Jul 23 06:09:51 PM PDT 24 Jul 23 06:09:55 PM PDT 24 85216511 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1306020538 Jul 23 06:09:40 PM PDT 24 Jul 23 06:09:45 PM PDT 24 122516283 ps
T1113 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1132509917 Jul 23 06:09:49 PM PDT 24 Jul 23 06:09:51 PM PDT 24 22816691 ps
T78 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1898381448 Jul 23 06:09:32 PM PDT 24 Jul 23 06:09:36 PM PDT 24 66584456 ps
T1114 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.194333700 Jul 23 06:10:30 PM PDT 24 Jul 23 06:10:45 PM PDT 24 103971276 ps
T1115 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1749668906 Jul 23 06:09:54 PM PDT 24 Jul 23 06:09:58 PM PDT 24 24645692 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.12087618 Jul 23 06:09:21 PM PDT 24 Jul 23 06:09:32 PM PDT 24 690192872 ps
T1117 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3012403642 Jul 23 06:09:29 PM PDT 24 Jul 23 06:09:33 PM PDT 24 91791883 ps
T79 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1222358092 Jul 23 06:09:16 PM PDT 24 Jul 23 06:09:18 PM PDT 24 20198775 ps
T1118 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4146275081 Jul 23 06:09:42 PM PDT 24 Jul 23 06:09:46 PM PDT 24 157942205 ps
T1119 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.394317232 Jul 23 06:09:22 PM PDT 24 Jul 23 06:09:24 PM PDT 24 11428911 ps
T80 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2251247152 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:33 PM PDT 24 25312959 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3844418306 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:00 PM PDT 24 17382248 ps
T1121 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.801558612 Jul 23 06:09:56 PM PDT 24 Jul 23 06:10:00 PM PDT 24 25702949 ps
T1122 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3770561674 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:41 PM PDT 24 115023632 ps
T1123 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4036058211 Jul 23 06:09:46 PM PDT 24 Jul 23 06:09:48 PM PDT 24 151310263 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.944321016 Jul 23 06:09:43 PM PDT 24 Jul 23 06:09:58 PM PDT 24 411284099 ps
T1125 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.568741274 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:37 PM PDT 24 98875567 ps
T1126 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1234834889 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:58 PM PDT 24 113367612 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.585777110 Jul 23 06:09:32 PM PDT 24 Jul 23 06:09:36 PM PDT 24 74406611 ps
T1128 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1348956878 Jul 23 06:09:36 PM PDT 24 Jul 23 06:09:39 PM PDT 24 10868558 ps
T1129 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3556579479 Jul 23 06:10:47 PM PDT 24 Jul 23 06:10:56 PM PDT 24 62438326 ps
T111 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1179742375 Jul 23 06:09:42 PM PDT 24 Jul 23 06:09:46 PM PDT 24 53754743 ps
T1130 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4292757480 Jul 23 06:09:37 PM PDT 24 Jul 23 06:09:42 PM PDT 24 147798737 ps
T1131 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2770813594 Jul 23 06:09:33 PM PDT 24 Jul 23 06:09:38 PM PDT 24 806671205 ps
T1132 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1534355122 Jul 23 06:09:40 PM PDT 24 Jul 23 06:09:46 PM PDT 24 83736165 ps
T1133 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2695614007 Jul 23 06:09:13 PM PDT 24 Jul 23 06:09:18 PM PDT 24 343216410 ps
T1134 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2244988750 Jul 23 06:09:53 PM PDT 24 Jul 23 06:09:56 PM PDT 24 13302026 ps
T1135 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1402233281 Jul 23 06:09:48 PM PDT 24 Jul 23 06:09:50 PM PDT 24 67511944 ps
T1136 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1622831455 Jul 23 06:09:57 PM PDT 24 Jul 23 06:10:06 PM PDT 24 39983510 ps
T1137 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4081118332 Jul 23 06:09:47 PM PDT 24 Jul 23 06:09:51 PM PDT 24 144588066 ps
T1138 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3966648642 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:34 PM PDT 24 36962488 ps
T1139 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4235632426 Jul 23 06:10:52 PM PDT 24 Jul 23 06:10:58 PM PDT 24 880123645 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2218742205 Jul 23 06:10:45 PM PDT 24 Jul 23 06:11:11 PM PDT 24 3740535238 ps
T160 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2906129353 Jul 23 06:09:25 PM PDT 24 Jul 23 06:09:46 PM PDT 24 5310914636 ps
T1141 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2941191328 Jul 23 06:09:45 PM PDT 24 Jul 23 06:09:48 PM PDT 24 15638007 ps
T1142 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.811503570 Jul 23 06:09:45 PM PDT 24 Jul 23 06:09:50 PM PDT 24 281491844 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2915865607 Jul 23 06:09:18 PM PDT 24 Jul 23 06:09:23 PM PDT 24 1980812714 ps
T1144 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1378646455 Jul 23 06:09:31 PM PDT 24 Jul 23 06:09:37 PM PDT 24 198022900 ps
T1145 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3088056260 Jul 23 06:09:35 PM PDT 24 Jul 23 06:09:46 PM PDT 24 1280223344 ps
T1146 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.937624198 Jul 23 06:09:50 PM PDT 24 Jul 23 06:09:55 PM PDT 24 62333675 ps
T1147 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.101151813 Jul 23 06:09:42 PM PDT 24 Jul 23 06:09:44 PM PDT 24 39329582 ps
T1148 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4266327585 Jul 23 06:10:38 PM PDT 24 Jul 23 06:10:55 PM PDT 24 628891083 ps
T1149 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.803131308 Jul 23 06:10:52 PM PDT 24 Jul 23 06:10:59 PM PDT 24 501882761 ps
T81 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3650211512 Jul 23 06:09:22 PM PDT 24 Jul 23 06:09:24 PM PDT 24 26443609 ps
T1150 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.721071037 Jul 23 06:10:50 PM PDT 24 Jul 23 06:10:58 PM PDT 24 114244127 ps
T1151 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1561286228 Jul 23 06:09:30 PM PDT 24 Jul 23 06:09:33 PM PDT 24 21759546 ps

Test location /workspace/coverage/default/28.spi_device_stress_all.298201817
Short name T7
Test name
Test status
Simulation time 11483495170 ps
CPU time 68.62 seconds
Started Jul 23 04:41:43 PM PDT 24
Finished Jul 23 04:42:52 PM PDT 24
Peak memory 257668 kb
Host smart-f33ca149-a0df-43df-a3c7-39c262a3baf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298201817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.298201817
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3579904052
Short name T14
Test name
Test status
Simulation time 23642115319 ps
CPU time 185.61 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:46:09 PM PDT 24
Peak memory 266736 kb
Host smart-4d1c9676-5038-4307-9ecc-4a4a80217e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579904052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3579904052
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2027800553
Short name T6
Test name
Test status
Simulation time 55723569511 ps
CPU time 494.28 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:49:00 PM PDT 24
Peak memory 267632 kb
Host smart-5a129ec3-2992-4efc-ac93-d2b37a972c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027800553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2027800553
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1535052879
Short name T93
Test name
Test status
Simulation time 633040825 ps
CPU time 13.32 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 216064 kb
Host smart-740b2202-d662-4596-84e3-a5686c4f6a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535052879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1535052879
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3434463486
Short name T16
Test name
Test status
Simulation time 219119317178 ps
CPU time 1079.33 seconds
Started Jul 23 04:41:05 PM PDT 24
Finished Jul 23 04:59:05 PM PDT 24
Peak memory 274540 kb
Host smart-4c85b58f-98fa-4d5e-92fa-41e6dc3bef4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434463486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3434463486
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4244293996
Short name T171
Test name
Test status
Simulation time 60920006572 ps
CPU time 506.23 seconds
Started Jul 23 04:41:56 PM PDT 24
Finished Jul 23 04:50:34 PM PDT 24
Peak memory 273960 kb
Host smart-2da78594-c659-46ca-adca-9140d688ab6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244293996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4244293996
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4203551622
Short name T62
Test name
Test status
Simulation time 33731338 ps
CPU time 0.74 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 216744 kb
Host smart-58010365-0501-42d2-aa43-2e1175c9939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203551622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4203551622
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.543707505
Short name T156
Test name
Test status
Simulation time 21287032325 ps
CPU time 267.22 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:46:13 PM PDT 24
Peak memory 258224 kb
Host smart-43b8155d-f9f2-48f2-b4df-966deb600a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543707505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.543707505
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3552088695
Short name T97
Test name
Test status
Simulation time 271751109 ps
CPU time 4.67 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 217288 kb
Host smart-053123f7-1ada-4051-862b-7364e78420e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552088695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3552088695
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1314556845
Short name T181
Test name
Test status
Simulation time 71925964113 ps
CPU time 690.13 seconds
Started Jul 23 04:42:44 PM PDT 24
Finished Jul 23 04:55:03 PM PDT 24
Peak memory 273040 kb
Host smart-c9d4e137-9b75-4500-a8ac-e2a20178270f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314556845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1314556845
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2171749290
Short name T170
Test name
Test status
Simulation time 402140650287 ps
CPU time 537.31 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:49:41 PM PDT 24
Peak memory 280120 kb
Host smart-377994b3-69e7-4782-9ff5-4cf58eebacaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171749290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2171749290
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2401892401
Short name T361
Test name
Test status
Simulation time 138136302 ps
CPU time 0.75 seconds
Started Jul 23 04:41:17 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 205392 kb
Host smart-ec280117-295c-4046-9da7-69f04c5678a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401892401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2401892401
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3486528485
Short name T138
Test name
Test status
Simulation time 29101699984 ps
CPU time 49.77 seconds
Started Jul 23 04:42:16 PM PDT 24
Finished Jul 23 04:43:20 PM PDT 24
Peak memory 233636 kb
Host smart-612d646f-9e31-465e-833d-bc39fd889305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486528485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3486528485
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2125673145
Short name T118
Test name
Test status
Simulation time 19847358 ps
CPU time 1.18 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 215896 kb
Host smart-7079a68c-7eeb-4aa2-94ee-8634eeb78641
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125673145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
125673145
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.378785025
Short name T74
Test name
Test status
Simulation time 67499096932 ps
CPU time 463.19 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:50:39 PM PDT 24
Peak memory 257856 kb
Host smart-766f75a5-812e-4433-8d70-5c3a8ecacb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378785025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.378785025
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3925884491
Short name T21
Test name
Test status
Simulation time 8628708733 ps
CPU time 125.03 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:45:32 PM PDT 24
Peak memory 266444 kb
Host smart-c1acd770-ae35-4ac8-9505-83870c52670c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925884491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3925884491
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.434163596
Short name T155
Test name
Test status
Simulation time 85896254101 ps
CPU time 110.93 seconds
Started Jul 23 04:40:53 PM PDT 24
Finished Jul 23 04:42:45 PM PDT 24
Peak memory 270136 kb
Host smart-6a724a72-d915-443f-9cea-225f3cdc83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434163596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.434163596
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2310567522
Short name T464
Test name
Test status
Simulation time 14537702 ps
CPU time 0.97 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 218616 kb
Host smart-3584ed82-24ca-41ae-ac73-2cce6c685052
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310567522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2310567522
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.894377075
Short name T182
Test name
Test status
Simulation time 9562415489 ps
CPU time 123.88 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:45:25 PM PDT 24
Peak memory 256868 kb
Host smart-31e7cd3c-8c15-4fcf-b5f5-7be306e64b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894377075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.894377075
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1570647246
Short name T168
Test name
Test status
Simulation time 26386175537 ps
CPU time 234.37 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:47:39 PM PDT 24
Peak memory 265592 kb
Host smart-fa117481-b12b-4089-b3a2-915216fd008e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570647246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1570647246
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2025770628
Short name T151
Test name
Test status
Simulation time 240705355566 ps
CPU time 327.74 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:45:49 PM PDT 24
Peak memory 267052 kb
Host smart-7d7b8587-d220-4b44-9525-f229d8fd4cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025770628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2025770628
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1740728361
Short name T64
Test name
Test status
Simulation time 339283963 ps
CPU time 0.95 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:18 PM PDT 24
Peak memory 235828 kb
Host smart-00a93a9c-68b6-4b1c-a501-7be59991e6c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740728361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1740728361
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3973733818
Short name T147
Test name
Test status
Simulation time 62686942191 ps
CPU time 170.08 seconds
Started Jul 23 04:42:53 PM PDT 24
Finished Jul 23 04:46:27 PM PDT 24
Peak memory 253904 kb
Host smart-7cc3deeb-1f2f-429d-996e-665e108997cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973733818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3973733818
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.610087328
Short name T158
Test name
Test status
Simulation time 25041734566 ps
CPU time 257.45 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:46:47 PM PDT 24
Peak memory 251836 kb
Host smart-e88336a5-20fc-4a43-955e-efed1789df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610087328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.610087328
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3629343955
Short name T186
Test name
Test status
Simulation time 218491320034 ps
CPU time 134.51 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:43:53 PM PDT 24
Peak memory 255488 kb
Host smart-0883b5e0-5d57-48a2-a90d-89803f5367d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629343955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3629343955
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1445518215
Short name T219
Test name
Test status
Simulation time 32615080885 ps
CPU time 73.52 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:42:46 PM PDT 24
Peak memory 256416 kb
Host smart-d658e7b0-bf2e-4972-a8d2-cc5350be7669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445518215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1445518215
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2718898860
Short name T273
Test name
Test status
Simulation time 235542573637 ps
CPU time 391.89 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:47:50 PM PDT 24
Peak memory 273520 kb
Host smart-c3b09e1b-3f78-45e7-9c92-7c26e4eb4dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718898860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2718898860
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2093242500
Short name T295
Test name
Test status
Simulation time 15498580617 ps
CPU time 136.37 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:44:27 PM PDT 24
Peak memory 273908 kb
Host smart-99e525f7-d83b-4ae1-a2f8-4fb078da4c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093242500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2093242500
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3646872857
Short name T4
Test name
Test status
Simulation time 1063812071 ps
CPU time 6.13 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 233584 kb
Host smart-2d073caf-c907-46b4-9db0-e765992523f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646872857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3646872857
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2449264495
Short name T49
Test name
Test status
Simulation time 71918251732 ps
CPU time 489.38 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:48:36 PM PDT 24
Peak memory 258204 kb
Host smart-b80f82c0-093a-4f13-9bed-53fbcd9e8290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449264495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2449264495
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3221032618
Short name T98
Test name
Test status
Simulation time 555045866 ps
CPU time 13.45 seconds
Started Jul 23 06:09:28 PM PDT 24
Finished Jul 23 06:09:43 PM PDT 24
Peak memory 216036 kb
Host smart-6c223316-432a-4df6-9c9a-a982068f28ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221032618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3221032618
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2590064523
Short name T113
Test name
Test status
Simulation time 292655365 ps
CPU time 7.77 seconds
Started Jul 23 06:09:19 PM PDT 24
Finished Jul 23 06:09:28 PM PDT 24
Peak memory 216640 kb
Host smart-e9c7c19f-a2a2-4b2d-adfc-5b7bca33ee48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590064523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2590064523
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1816104160
Short name T312
Test name
Test status
Simulation time 459302853 ps
CPU time 13.94 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 239028 kb
Host smart-86156847-e811-46a0-bd51-858df0dbc19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816104160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1816104160
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2299909791
Short name T40
Test name
Test status
Simulation time 3649306764 ps
CPU time 76.84 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:42:02 PM PDT 24
Peak memory 252172 kb
Host smart-3c79f3fe-733d-4734-b0d7-10bf36337255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299909791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2299909791
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3021754042
Short name T173
Test name
Test status
Simulation time 41633170741 ps
CPU time 373.07 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:47:14 PM PDT 24
Peak memory 253200 kb
Host smart-656cc36c-38b3-4917-95d3-34c6f40ad85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021754042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3021754042
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1221191787
Short name T341
Test name
Test status
Simulation time 156535173 ps
CPU time 1.03 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 207012 kb
Host smart-d3081b2d-b7ee-406e-8ba3-e15d3cc64347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221191787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1221191787
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1564351813
Short name T200
Test name
Test status
Simulation time 67655730805 ps
CPU time 285.53 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:45:05 PM PDT 24
Peak memory 255972 kb
Host smart-38dae1d8-3e8b-46bd-a9e6-7215919bfa31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564351813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1564351813
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.923931718
Short name T309
Test name
Test status
Simulation time 281650164 ps
CPU time 5.43 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:54 PM PDT 24
Peak memory 225344 kb
Host smart-8f7876d6-3214-40d1-b670-76142d117f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923931718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.923931718
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1588636919
Short name T32
Test name
Test status
Simulation time 6922950104 ps
CPU time 68.6 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:43:14 PM PDT 24
Peak memory 249972 kb
Host smart-d4d2d4fe-0ab4-4cf5-80f9-6ea775e2feae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588636919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1588636919
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2319737439
Short name T196
Test name
Test status
Simulation time 140952041073 ps
CPU time 320.28 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:46:05 PM PDT 24
Peak memory 265580 kb
Host smart-f09eb5b7-fdc3-46c6-8799-9ae2735fd177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319737439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2319737439
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2901120101
Short name T276
Test name
Test status
Simulation time 15963246721 ps
CPU time 140.74 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:43:05 PM PDT 24
Peak memory 258168 kb
Host smart-129da187-9280-4bce-bfa6-c981a1e35169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901120101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2901120101
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.305787826
Short name T87
Test name
Test status
Simulation time 1016744869 ps
CPU time 5.94 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 220092 kb
Host smart-39c1080d-1249-4157-9034-6775bc3787f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=305787826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.305787826
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2137805210
Short name T91
Test name
Test status
Simulation time 3068117327 ps
CPU time 6.05 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 225360 kb
Host smart-d4a00553-e1ef-484f-b154-ee8bac9de281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137805210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2137805210
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2632483679
Short name T26
Test name
Test status
Simulation time 46689736358 ps
CPU time 448.05 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:48:09 PM PDT 24
Peak memory 269724 kb
Host smart-77b14ded-685d-4c30-ae29-9a1c7c28c398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632483679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2632483679
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1767624502
Short name T105
Test name
Test status
Simulation time 62891617 ps
CPU time 1.95 seconds
Started Jul 23 06:09:21 PM PDT 24
Finished Jul 23 06:09:24 PM PDT 24
Peak memory 216288 kb
Host smart-879f1f9e-1b20-4242-be24-b336f471eda6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767624502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
767624502
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2056312298
Short name T296
Test name
Test status
Simulation time 4596052279 ps
CPU time 8.61 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:52 PM PDT 24
Peak memory 225564 kb
Host smart-986bee74-3888-4c25-8f90-f9b1fc417d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056312298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2056312298
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1889757464
Short name T180
Test name
Test status
Simulation time 3719388892 ps
CPU time 89.7 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:42:46 PM PDT 24
Peak memory 268236 kb
Host smart-9ecad6f6-a4b2-487d-820e-a99b189272fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889757464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1889757464
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3224781077
Short name T315
Test name
Test status
Simulation time 3835529706 ps
CPU time 25.27 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:48 PM PDT 24
Peak memory 217332 kb
Host smart-26b28228-92db-481c-8a09-5220bddc0c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224781077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3224781077
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.525482844
Short name T301
Test name
Test status
Simulation time 6492287485 ps
CPU time 9.76 seconds
Started Jul 23 04:41:27 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 236428 kb
Host smart-913445d0-20dc-4a0c-adc7-b4048e10ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525482844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.525482844
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1952319483
Short name T307
Test name
Test status
Simulation time 2321142150 ps
CPU time 10.71 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:42:00 PM PDT 24
Peak memory 225412 kb
Host smart-c22020ef-72eb-4cf6-a038-cc8585be17be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952319483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1952319483
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.22947163
Short name T282
Test name
Test status
Simulation time 55264629490 ps
CPU time 517.12 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:51:01 PM PDT 24
Peak memory 265620 kb
Host smart-c7ddfe1c-37be-4255-9145-b09578e39db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22947163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.22947163
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1828156654
Short name T328
Test name
Test status
Simulation time 48161890160 ps
CPU time 141.09 seconds
Started Jul 23 04:42:50 PM PDT 24
Finished Jul 23 04:45:56 PM PDT 24
Peak memory 255888 kb
Host smart-aeb225ad-d0ce-463d-9dcb-ddccba4d2c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828156654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1828156654
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2682449490
Short name T35
Test name
Test status
Simulation time 1619696089 ps
CPU time 28.09 seconds
Started Jul 23 04:41:21 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 240168 kb
Host smart-75abe086-42cb-4ab4-83cd-dc43e5d9a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682449490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2682449490
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3650211512
Short name T81
Test name
Test status
Simulation time 26443609 ps
CPU time 0.98 seconds
Started Jul 23 06:09:22 PM PDT 24
Finished Jul 23 06:09:24 PM PDT 24
Peak memory 207616 kb
Host smart-34dc7791-e56b-460d-b190-8fdf4248dfe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650211512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3650211512
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2482036034
Short name T108
Test name
Test status
Simulation time 712483762 ps
CPU time 16.02 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:47 PM PDT 24
Peak memory 216144 kb
Host smart-03d82d2d-d7db-448a-8984-91d1223015ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482036034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2482036034
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.944321016
Short name T1124
Test name
Test status
Simulation time 411284099 ps
CPU time 13.68 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 216080 kb
Host smart-90cc9d8e-4eee-4d4c-8d3e-f0c7380eb555
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944321016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.944321016
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1903041113
Short name T1058
Test name
Test status
Simulation time 1215009467 ps
CPU time 25.52 seconds
Started Jul 23 06:09:20 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 207808 kb
Host smart-1ab72bc7-1889-48b2-8418-22351c80be8e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903041113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1903041113
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1222358092
Short name T79
Test name
Test status
Simulation time 20198775 ps
CPU time 1.12 seconds
Started Jul 23 06:09:16 PM PDT 24
Finished Jul 23 06:09:18 PM PDT 24
Peak memory 207828 kb
Host smart-8ce5ea75-36a7-462f-82b3-c6e8e5d871d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222358092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1222358092
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4276201129
Short name T1104
Test name
Test status
Simulation time 90972100 ps
CPU time 2.46 seconds
Started Jul 23 06:09:26 PM PDT 24
Finished Jul 23 06:09:30 PM PDT 24
Peak memory 218272 kb
Host smart-7814f5db-e8a0-4a0c-b9fb-770b8ea9cf45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276201129 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.4276201129
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1818204128
Short name T1109
Test name
Test status
Simulation time 77093892 ps
CPU time 1.97 seconds
Started Jul 23 06:09:19 PM PDT 24
Finished Jul 23 06:09:28 PM PDT 24
Peak memory 216108 kb
Host smart-1f6ed1be-2aa4-4de1-925a-b3c5845ad1ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818204128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
818204128
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1515431293
Short name T1045
Test name
Test status
Simulation time 19806094 ps
CPU time 0.73 seconds
Started Jul 23 06:09:48 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 204536 kb
Host smart-94c6ef72-d4ae-4700-878b-3465cb5609fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515431293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
515431293
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.585777110
Short name T1127
Test name
Test status
Simulation time 74406611 ps
CPU time 1.33 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:36 PM PDT 24
Peak memory 216028 kb
Host smart-bd08bc46-78f7-4a61-84db-0981db9b3a94
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585777110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.585777110
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3133311663
Short name T1047
Test name
Test status
Simulation time 23135115 ps
CPU time 0.66 seconds
Started Jul 23 06:09:39 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 204428 kb
Host smart-c258f953-18c3-4882-ab0a-a2d6c0b35417
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133311663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3133311663
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1524385412
Short name T1080
Test name
Test status
Simulation time 113712205 ps
CPU time 3.14 seconds
Started Jul 23 06:09:13 PM PDT 24
Finished Jul 23 06:09:18 PM PDT 24
Peak memory 215936 kb
Host smart-d4378a2c-3f8c-47aa-9f16-6f8770331b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524385412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1524385412
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3088056260
Short name T1145
Test name
Test status
Simulation time 1280223344 ps
CPU time 8.36 seconds
Started Jul 23 06:09:35 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 207828 kb
Host smart-f9dac8ba-1ac2-4ba9-89aa-9e43a6d21b4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088056260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3088056260
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.12087618
Short name T1116
Test name
Test status
Simulation time 690192872 ps
CPU time 11.02 seconds
Started Jul 23 06:09:21 PM PDT 24
Finished Jul 23 06:09:32 PM PDT 24
Peak memory 216044 kb
Host smart-ec6a3240-bc35-4d2f-bcbe-a136624436fa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12087618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_
bit_bash.12087618
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3211831067
Short name T116
Test name
Test status
Simulation time 707047814 ps
CPU time 3.96 seconds
Started Jul 23 06:09:28 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 218892 kb
Host smart-e462e650-35a7-4b2c-9e41-ba780e704336
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211831067 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3211831067
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3163400726
Short name T127
Test name
Test status
Simulation time 58806564 ps
CPU time 2.13 seconds
Started Jul 23 06:09:23 PM PDT 24
Finished Jul 23 06:09:26 PM PDT 24
Peak memory 215968 kb
Host smart-5bd79ad6-4093-460e-ab8a-04d9708f1f19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163400726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
163400726
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3951673415
Short name T1043
Test name
Test status
Simulation time 48961864 ps
CPU time 0.75 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 204472 kb
Host smart-289ec6f9-8bf1-48e9-8946-906d866bfe39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951673415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
951673415
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3957338354
Short name T126
Test name
Test status
Simulation time 124031171 ps
CPU time 2.04 seconds
Started Jul 23 06:09:21 PM PDT 24
Finished Jul 23 06:09:24 PM PDT 24
Peak memory 216072 kb
Host smart-f3949d71-26af-4c49-a2bb-3de922f88799
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957338354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3957338354
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.152688856
Short name T1034
Test name
Test status
Simulation time 19392247 ps
CPU time 0.65 seconds
Started Jul 23 06:09:28 PM PDT 24
Finished Jul 23 06:09:30 PM PDT 24
Peak memory 204436 kb
Host smart-b966cb19-4e52-46c1-abe9-4f59028384d7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152688856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.152688856
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1638664546
Short name T1071
Test name
Test status
Simulation time 107664907 ps
CPU time 3.57 seconds
Started Jul 23 06:09:28 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 216024 kb
Host smart-f005d5a9-785c-4d5c-bd2a-d12e96b16b12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638664546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1638664546
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.784566375
Short name T1100
Test name
Test status
Simulation time 132371000 ps
CPU time 3.2 seconds
Started Jul 23 06:09:25 PM PDT 24
Finished Jul 23 06:09:30 PM PDT 24
Peak memory 216292 kb
Host smart-548b7b01-2d75-43e4-9e89-f9319079ed6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784566375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.784566375
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3568853710
Short name T92
Test name
Test status
Simulation time 1123215935 ps
CPU time 14.42 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 216516 kb
Host smart-21815f31-eb0d-4397-a406-b36ff2646e4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568853710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3568853710
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.398672986
Short name T1086
Test name
Test status
Simulation time 86333309 ps
CPU time 1.55 seconds
Started Jul 23 06:10:11 PM PDT 24
Finished Jul 23 06:10:14 PM PDT 24
Peak memory 216140 kb
Host smart-e30052fd-0465-4426-b10e-18b1348ec2a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398672986 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.398672986
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1020553401
Short name T1083
Test name
Test status
Simulation time 68467056 ps
CPU time 1.28 seconds
Started Jul 23 06:09:34 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 219944 kb
Host smart-ca4c5763-f8dd-44aa-b7f4-d4f025d3fd93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020553401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1020553401
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3844418306
Short name T1120
Test name
Test status
Simulation time 17382248 ps
CPU time 0.75 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 204760 kb
Host smart-62e5b9f0-e27b-4192-815d-e0f99ec7b348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844418306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3844418306
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4002204717
Short name T1081
Test name
Test status
Simulation time 274958437 ps
CPU time 2.83 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 215984 kb
Host smart-d47de0d1-cfdd-4324-87f1-133bf330422d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002204717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4002204717
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3127463150
Short name T110
Test name
Test status
Simulation time 682188127 ps
CPU time 3.41 seconds
Started Jul 23 06:09:39 PM PDT 24
Finished Jul 23 06:09:44 PM PDT 24
Peak memory 216276 kb
Host smart-031dda60-fb43-42d5-ac30-cdd70b6d7d15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127463150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3127463150
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3703702144
Short name T143
Test name
Test status
Simulation time 641134692 ps
CPU time 13.62 seconds
Started Jul 23 06:10:45 PM PDT 24
Finished Jul 23 06:11:04 PM PDT 24
Peak memory 215956 kb
Host smart-11272fd2-f12f-4b88-a0a1-93fe47cc0c20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703702144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3703702144
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2770435135
Short name T1053
Test name
Test status
Simulation time 78918909 ps
CPU time 2.54 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:09:44 PM PDT 24
Peak memory 218200 kb
Host smart-3c140de1-7f17-453b-bb85-6fddf471d2a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770435135 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2770435135
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2760373848
Short name T1111
Test name
Test status
Simulation time 85216511 ps
CPU time 1.83 seconds
Started Jul 23 06:09:51 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 216060 kb
Host smart-5557ca99-f81f-4c1f-bf21-c77a83f00be6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760373848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2760373848
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2016252382
Short name T1050
Test name
Test status
Simulation time 24452234 ps
CPU time 0.72 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:09:54 PM PDT 24
Peak memory 204484 kb
Host smart-a3974594-3c7c-43bb-93ff-e9b177644ac5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016252382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2016252382
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.888553974
Short name T136
Test name
Test status
Simulation time 850627575 ps
CPU time 4.27 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 215964 kb
Host smart-a2d70ac3-9a8e-47a0-a657-dc279ba16894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888553974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.888553974
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.892864701
Short name T1089
Test name
Test status
Simulation time 96200971 ps
CPU time 2.76 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:35 PM PDT 24
Peak memory 216344 kb
Host smart-c90a8764-9fa4-455b-95c3-2397b861ba69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892864701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.892864701
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1308183051
Short name T1069
Test name
Test status
Simulation time 390567099 ps
CPU time 6.97 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:10:05 PM PDT 24
Peak memory 216392 kb
Host smart-aa1108ac-0d84-423e-9b59-c50490149b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308183051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1308183051
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2027310927
Short name T112
Test name
Test status
Simulation time 211275915 ps
CPU time 3.75 seconds
Started Jul 23 06:09:41 PM PDT 24
Finished Jul 23 06:09:52 PM PDT 24
Peak memory 217092 kb
Host smart-750229e6-6ad1-4362-b98c-c2b1dba465a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027310927 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2027310927
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1613663021
Short name T119
Test name
Test status
Simulation time 37865460 ps
CPU time 2.54 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 215916 kb
Host smart-421fb7cc-6a1f-48c1-aa53-82a0dccf0940
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613663021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1613663021
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3132956171
Short name T1042
Test name
Test status
Simulation time 85806422 ps
CPU time 0.74 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:35 PM PDT 24
Peak memory 204436 kb
Host smart-11372fca-72d8-49df-ba77-ab16c431c64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132956171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3132956171
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3495772633
Short name T1062
Test name
Test status
Simulation time 92271090 ps
CPU time 1.67 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:41 PM PDT 24
Peak memory 216048 kb
Host smart-8b27012d-2266-4833-b57b-c87b3ab0b5f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495772633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3495772633
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3267386265
Short name T100
Test name
Test status
Simulation time 182841229 ps
CPU time 4.23 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:10:01 PM PDT 24
Peak memory 217232 kb
Host smart-5df8b4d2-d21e-4c36-b676-788cb0d7bacd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267386265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3267386265
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2032965487
Short name T145
Test name
Test status
Simulation time 58822626 ps
CPU time 1.71 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 216160 kb
Host smart-fee8f09a-f1d4-409c-9f07-72137fa1bd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032965487 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2032965487
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.937624198
Short name T1146
Test name
Test status
Simulation time 62333675 ps
CPU time 2.06 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 215976 kb
Host smart-802ac544-78c4-4464-8e35-8ec7267f9c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937624198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.937624198
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2770088229
Short name T1044
Test name
Test status
Simulation time 23338350 ps
CPU time 0.68 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:35 PM PDT 24
Peak memory 204464 kb
Host smart-dc608cf7-bfc7-48e7-8f87-fffe542d452c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770088229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2770088229
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1206590932
Short name T1067
Test name
Test status
Simulation time 48112998 ps
CPU time 3.15 seconds
Started Jul 23 06:09:36 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 216000 kb
Host smart-c835117a-69a7-4675-942f-27126d7a446a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206590932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1206590932
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3371162075
Short name T1110
Test name
Test status
Simulation time 49694673 ps
CPU time 3.37 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:39 PM PDT 24
Peak memory 216184 kb
Host smart-4941bd5d-c985-4125-aba9-41efd36d3801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371162075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3371162075
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1385568354
Short name T95
Test name
Test status
Simulation time 28699172 ps
CPU time 1.79 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 217128 kb
Host smart-82885af4-5e9e-4019-b983-ae8cf4612950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385568354 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1385568354
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3966648642
Short name T1138
Test name
Test status
Simulation time 36962488 ps
CPU time 1.33 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 216060 kb
Host smart-9dbde820-339a-4f4c-915c-78c10a73d276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966648642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3966648642
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3585381117
Short name T1038
Test name
Test status
Simulation time 14694728 ps
CPU time 0.71 seconds
Started Jul 23 06:10:09 PM PDT 24
Finished Jul 23 06:10:11 PM PDT 24
Peak memory 204808 kb
Host smart-925cde47-552f-4778-b398-f4725502780f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585381117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3585381117
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.848070954
Short name T142
Test name
Test status
Simulation time 211715835 ps
CPU time 4.27 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 215988 kb
Host smart-8d3c29ff-e8fd-4294-9738-49b0834901f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848070954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.848070954
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1247405419
Short name T99
Test name
Test status
Simulation time 65243062 ps
CPU time 3.6 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:39 PM PDT 24
Peak memory 216264 kb
Host smart-56a0ac5f-9f31-4ff5-a8c1-e272ebdec8b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247405419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1247405419
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2587104359
Short name T1077
Test name
Test status
Simulation time 1003940997 ps
CPU time 22.32 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 216164 kb
Host smart-49d1d487-430e-4248-86bd-501f1fa8ae3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587104359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2587104359
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1997834936
Short name T1064
Test name
Test status
Simulation time 28340621 ps
CPU time 1.83 seconds
Started Jul 23 06:10:01 PM PDT 24
Finished Jul 23 06:10:05 PM PDT 24
Peak memory 216084 kb
Host smart-26e15b06-d2a8-49c7-826b-e7f27d512bd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997834936 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1997834936
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1234834889
Short name T1126
Test name
Test status
Simulation time 113367612 ps
CPU time 2.44 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 207952 kb
Host smart-b84bbb81-8d8f-464d-9c1a-4caa389b6163
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234834889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1234834889
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2274717495
Short name T1098
Test name
Test status
Simulation time 14599449 ps
CPU time 0.74 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 204836 kb
Host smart-93c60530-b76b-44d8-af13-a4884e51bd2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274717495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2274717495
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1665065778
Short name T134
Test name
Test status
Simulation time 60912697 ps
CPU time 3.64 seconds
Started Jul 23 06:09:36 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 216012 kb
Host smart-76897a12-f24b-4d88-bd73-a5fc5dc48880
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665065778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1665065778
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.811503570
Short name T1142
Test name
Test status
Simulation time 281491844 ps
CPU time 3.42 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 217096 kb
Host smart-809113c5-486a-48d8-b642-4641dc148af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811503570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.811503570
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4084750334
Short name T115
Test name
Test status
Simulation time 1380677588 ps
CPU time 15.77 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:16 PM PDT 24
Peak memory 216060 kb
Host smart-cf1f3710-43b4-4ca4-b3a7-013ff2c4ce9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084750334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4084750334
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.197189844
Short name T94
Test name
Test status
Simulation time 64699708 ps
CPU time 4.34 seconds
Started Jul 23 06:09:35 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 219124 kb
Host smart-f520d558-dd81-4158-9317-0ef1e6b688db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197189844 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.197189844
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1402233281
Short name T1135
Test name
Test status
Simulation time 67511944 ps
CPU time 1.26 seconds
Started Jul 23 06:09:48 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 207848 kb
Host smart-ca1d9d47-f036-460a-90f5-96c7fc35218a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402233281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1402233281
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1348956878
Short name T1128
Test name
Test status
Simulation time 10868558 ps
CPU time 0.7 seconds
Started Jul 23 06:09:36 PM PDT 24
Finished Jul 23 06:09:39 PM PDT 24
Peak memory 204452 kb
Host smart-dbacb2c3-e94f-4d73-841d-466343165799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348956878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1348956878
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4146275081
Short name T1118
Test name
Test status
Simulation time 157942205 ps
CPU time 2.78 seconds
Started Jul 23 06:09:42 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 216448 kb
Host smart-9525e011-9190-4e6a-8a7c-0915c51739d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146275081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4146275081
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4292757480
Short name T1130
Test name
Test status
Simulation time 147798737 ps
CPU time 2.61 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 216284 kb
Host smart-a739bf84-f751-4ad5-b6b5-320df7941338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292757480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4292757480
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1939743741
Short name T1061
Test name
Test status
Simulation time 1188333193 ps
CPU time 18.22 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:10:05 PM PDT 24
Peak memory 216016 kb
Host smart-727ea180-ad06-4bc1-afc9-7d95691b7dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939743741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1939743741
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2483671992
Short name T1059
Test name
Test status
Simulation time 75465249 ps
CPU time 2.49 seconds
Started Jul 23 06:09:42 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 217164 kb
Host smart-afec4774-0c19-4a89-8614-bd26940e96eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483671992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2483671992
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1922515862
Short name T129
Test name
Test status
Simulation time 52550038 ps
CPU time 1.78 seconds
Started Jul 23 06:09:57 PM PDT 24
Finished Jul 23 06:10:02 PM PDT 24
Peak memory 216052 kb
Host smart-58ec9bbc-848e-45ee-a85c-ad48be15c411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922515862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1922515862
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3886396331
Short name T1079
Test name
Test status
Simulation time 55146623 ps
CPU time 0.76 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:52 PM PDT 24
Peak memory 204796 kb
Host smart-4b992d35-401d-400a-b763-eb5ee5b73853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886396331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3886396331
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3980474351
Short name T1056
Test name
Test status
Simulation time 85929358 ps
CPU time 1.65 seconds
Started Jul 23 06:09:41 PM PDT 24
Finished Jul 23 06:09:44 PM PDT 24
Peak memory 215952 kb
Host smart-90264633-8edf-448e-9e8c-b614587deed1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980474351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3980474351
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1534355122
Short name T1132
Test name
Test status
Simulation time 83736165 ps
CPU time 4.77 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 216240 kb
Host smart-611ec0aa-6662-475b-8ff5-608c5434c05d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534355122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1534355122
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1111971029
Short name T114
Test name
Test status
Simulation time 305540996 ps
CPU time 18.6 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:51 PM PDT 24
Peak memory 216064 kb
Host smart-ed22c190-b3cd-45c7-92a8-a36aabbeffbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111971029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1111971029
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1378646455
Short name T1144
Test name
Test status
Simulation time 198022900 ps
CPU time 4.01 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 218040 kb
Host smart-a8a2364b-0b13-4ca2-bad0-43b4f6d34725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378646455 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1378646455
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.901493604
Short name T124
Test name
Test status
Simulation time 870692467 ps
CPU time 1.99 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 216096 kb
Host smart-1ab4644d-1f50-46ef-b6de-1c519233cfcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901493604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.901493604
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2820167517
Short name T1046
Test name
Test status
Simulation time 108325968 ps
CPU time 0.75 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 204448 kb
Host smart-13729a71-679f-46e8-a2b6-21d19096e442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820167517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2820167517
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1215915348
Short name T133
Test name
Test status
Simulation time 59614700 ps
CPU time 3.5 seconds
Started Jul 23 06:09:44 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 216068 kb
Host smart-918a011a-6f8a-4c9d-9c04-f327ac84c612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215915348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1215915348
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1881663973
Short name T1048
Test name
Test status
Simulation time 2613021118 ps
CPU time 12.93 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:47 PM PDT 24
Peak memory 216144 kb
Host smart-f270a7c2-b905-4059-bd77-6fa17d3a7a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881663973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1881663973
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2770813594
Short name T1131
Test name
Test status
Simulation time 806671205 ps
CPU time 2.53 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 217336 kb
Host smart-9a4be8a6-96e8-4fe6-988a-1073985248b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770813594 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2770813594
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3370233203
Short name T125
Test name
Test status
Simulation time 26860524 ps
CPU time 1.88 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 207700 kb
Host smart-fc1baee1-c2a9-4b63-b2c3-eb59199e8a39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370233203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3370233203
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3648798945
Short name T1029
Test name
Test status
Simulation time 25050719 ps
CPU time 0.71 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 204388 kb
Host smart-6de3a48b-f1c0-476a-8a81-d198bb76a220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648798945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3648798945
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1548655127
Short name T135
Test name
Test status
Simulation time 109378321 ps
CPU time 1.75 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 216256 kb
Host smart-2d6f1389-3a6b-4877-a993-12162305b0e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548655127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1548655127
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.316373632
Short name T106
Test name
Test status
Simulation time 118877964 ps
CPU time 4.03 seconds
Started Jul 23 06:09:41 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 216196 kb
Host smart-35f89e46-fb5c-43e4-ade9-7b4a380cec1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316373632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.316373632
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.480555653
Short name T161
Test name
Test status
Simulation time 1305774568 ps
CPU time 18.35 seconds
Started Jul 23 06:09:58 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 216164 kb
Host smart-0b53fbb9-02a0-4416-9dcb-ec37b651c84c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480555653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.480555653
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2218742205
Short name T1140
Test name
Test status
Simulation time 3740535238 ps
CPU time 20.8 seconds
Started Jul 23 06:10:45 PM PDT 24
Finished Jul 23 06:11:11 PM PDT 24
Peak memory 215900 kb
Host smart-f1495348-d6b9-4aad-a1ee-fefcb35f8cdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218742205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2218742205
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3245578830
Short name T1036
Test name
Test status
Simulation time 4815061796 ps
CPU time 25.31 seconds
Started Jul 23 06:09:21 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 208004 kb
Host smart-47df8991-5610-4c6d-8e8c-d0859a36325a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245578830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3245578830
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1898381448
Short name T78
Test name
Test status
Simulation time 66584456 ps
CPU time 1.22 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:36 PM PDT 24
Peak memory 207752 kb
Host smart-0b22fd88-a634-4601-89ce-9433f46b632b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898381448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1898381448
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2915865607
Short name T1143
Test name
Test status
Simulation time 1980812714 ps
CPU time 3.41 seconds
Started Jul 23 06:09:18 PM PDT 24
Finished Jul 23 06:09:23 PM PDT 24
Peak memory 217908 kb
Host smart-e63d90b7-1c79-4f86-9904-94e8dbcd1a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915865607 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2915865607
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1174218961
Short name T1103
Test name
Test status
Simulation time 17016038 ps
CPU time 0.74 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 204472 kb
Host smart-2363b2ff-e475-4efd-8bc9-1be95eb5a5f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174218961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
174218961
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2363679483
Short name T121
Test name
Test status
Simulation time 100648156 ps
CPU time 1.74 seconds
Started Jul 23 06:09:42 PM PDT 24
Finished Jul 23 06:09:45 PM PDT 24
Peak memory 216112 kb
Host smart-eca8da06-135c-41ea-9728-6db9625e5252
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363679483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2363679483
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.881600286
Short name T1099
Test name
Test status
Simulation time 27203301 ps
CPU time 0.63 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 204412 kb
Host smart-68181b40-28a5-4e4a-90d8-ba086c0e6970
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881600286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.881600286
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3795161637
Short name T1091
Test name
Test status
Simulation time 272195299 ps
CPU time 3.76 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 216088 kb
Host smart-8c87ab6a-62ac-40f7-ada5-a94dc36b673d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795161637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3795161637
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2695614007
Short name T1133
Test name
Test status
Simulation time 343216410 ps
CPU time 2.79 seconds
Started Jul 23 06:09:13 PM PDT 24
Finished Jul 23 06:09:18 PM PDT 24
Peak memory 216360 kb
Host smart-32cab0f7-b4ef-4ac7-bb6c-ed09c1bd136a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695614007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
695614007
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1062662271
Short name T1094
Test name
Test status
Simulation time 502286522 ps
CPU time 6.26 seconds
Started Jul 23 06:09:25 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 216040 kb
Host smart-5dc4151e-d61b-4370-8969-f2e9b25b5de0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062662271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1062662271
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1305474683
Short name T1092
Test name
Test status
Simulation time 12412260 ps
CPU time 0.69 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:36 PM PDT 24
Peak memory 204512 kb
Host smart-43a47fcb-3b95-40fa-b3d0-6aa25def0672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305474683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1305474683
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.159133921
Short name T1106
Test name
Test status
Simulation time 23891194 ps
CPU time 0.68 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 204524 kb
Host smart-cfbc0b51-3113-4c65-8521-c02398f68ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159133921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.159133921
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4157749703
Short name T1084
Test name
Test status
Simulation time 48903858 ps
CPU time 0.71 seconds
Started Jul 23 06:09:38 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 204800 kb
Host smart-e7668c50-0e53-401e-a993-0f8c4721e654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157749703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4157749703
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.101151813
Short name T1147
Test name
Test status
Simulation time 39329582 ps
CPU time 0.73 seconds
Started Jul 23 06:09:42 PM PDT 24
Finished Jul 23 06:09:44 PM PDT 24
Peak memory 204504 kb
Host smart-1ed38539-6ddd-4f1d-9bfe-d92410d0f19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101151813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.101151813
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.791372757
Short name T1055
Test name
Test status
Simulation time 42054971 ps
CPU time 0.71 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 204848 kb
Host smart-46e593aa-2429-416e-a438-cc57a4b50221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791372757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.791372757
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.246441397
Short name T1070
Test name
Test status
Simulation time 26751630 ps
CPU time 0.7 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 204544 kb
Host smart-636e3fd3-7581-43a6-92e8-92ef20c02138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246441397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.246441397
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1002146570
Short name T1063
Test name
Test status
Simulation time 53835168 ps
CPU time 0.8 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:09:53 PM PDT 24
Peak memory 205008 kb
Host smart-e9ae9bd1-b6d6-482e-a2a3-236fff6d7285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002146570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1002146570
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1026068500
Short name T1072
Test name
Test status
Simulation time 15864018 ps
CPU time 0.77 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:09:57 PM PDT 24
Peak memory 204844 kb
Host smart-7ef3304c-794f-49b1-9e0c-7dfa301cde6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026068500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1026068500
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2306218912
Short name T1033
Test name
Test status
Simulation time 48974088 ps
CPU time 0.76 seconds
Started Jul 23 06:09:47 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 204508 kb
Host smart-dd7ea267-0f75-41f3-a3cd-c777e28f01ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306218912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2306218912
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3232461981
Short name T1065
Test name
Test status
Simulation time 51797300 ps
CPU time 0.73 seconds
Started Jul 23 06:10:05 PM PDT 24
Finished Jul 23 06:10:08 PM PDT 24
Peak memory 204504 kb
Host smart-a0733ff5-275d-450c-a3c0-3685a9fa20d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232461981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3232461981
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1671721739
Short name T123
Test name
Test status
Simulation time 10329088949 ps
CPU time 24.11 seconds
Started Jul 23 06:09:17 PM PDT 24
Finished Jul 23 06:09:43 PM PDT 24
Peak memory 216048 kb
Host smart-1e0fd39b-47dc-4804-b499-dc175dd6ff03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671721739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1671721739
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3876809968
Short name T128
Test name
Test status
Simulation time 547642481 ps
CPU time 34.32 seconds
Started Jul 23 06:09:23 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 216052 kb
Host smart-7645048b-4e84-4659-a217-011bcd3e79e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876809968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3876809968
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.457595387
Short name T1096
Test name
Test status
Simulation time 86087745 ps
CPU time 0.97 seconds
Started Jul 23 06:09:14 PM PDT 24
Finished Jul 23 06:09:17 PM PDT 24
Peak memory 207516 kb
Host smart-27b5ed81-c0c1-43c3-b4f7-adfb9662fa9b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457595387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.457595387
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2410401139
Short name T1097
Test name
Test status
Simulation time 76252893 ps
CPU time 1.82 seconds
Started Jul 23 06:09:51 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 216068 kb
Host smart-041f60ec-4590-49b6-8558-24595e26fd2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410401139 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2410401139
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4081118332
Short name T1137
Test name
Test status
Simulation time 144588066 ps
CPU time 2.45 seconds
Started Jul 23 06:09:47 PM PDT 24
Finished Jul 23 06:09:51 PM PDT 24
Peak memory 216044 kb
Host smart-3e3a6edc-a6ef-40df-8bca-2cd43d1a9c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081118332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
081118332
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2329723779
Short name T1088
Test name
Test status
Simulation time 52291078 ps
CPU time 0.72 seconds
Started Jul 23 06:10:45 PM PDT 24
Finished Jul 23 06:10:51 PM PDT 24
Peak memory 204284 kb
Host smart-3d516cdd-97f9-46f8-aa5b-70609bfcb837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329723779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
329723779
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.995091637
Short name T1087
Test name
Test status
Simulation time 257386554 ps
CPU time 2.07 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 216060 kb
Host smart-939397ff-e2c8-49bc-b374-f954640da9c4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995091637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.995091637
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3280799279
Short name T1093
Test name
Test status
Simulation time 74306356 ps
CPU time 0.67 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 204396 kb
Host smart-fdc048b1-7b0f-4242-836d-75f85ac0ccd0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280799279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3280799279
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4022225489
Short name T1074
Test name
Test status
Simulation time 168825654 ps
CPU time 2.67 seconds
Started Jul 23 06:09:41 PM PDT 24
Finished Jul 23 06:09:45 PM PDT 24
Peak memory 215984 kb
Host smart-985713a4-240c-45aa-99f4-8b0c3b3a4c93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022225489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4022225489
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1773560971
Short name T96
Test name
Test status
Simulation time 80213845 ps
CPU time 1.55 seconds
Started Jul 23 06:09:38 PM PDT 24
Finished Jul 23 06:09:42 PM PDT 24
Peak memory 216232 kb
Host smart-82650df9-14b1-4638-ac1b-1591be79cc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773560971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
773560971
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.4047974288
Short name T1049
Test name
Test status
Simulation time 17086432 ps
CPU time 0.71 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 204824 kb
Host smart-e33292ba-a5de-4e50-82a1-a0f3bcbbb496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047974288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
4047974288
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3193564908
Short name T1105
Test name
Test status
Simulation time 18741300 ps
CPU time 0.72 seconds
Started Jul 23 06:09:38 PM PDT 24
Finished Jul 23 06:09:41 PM PDT 24
Peak memory 204512 kb
Host smart-b0b1138d-66e3-4076-aa9c-c26bf1be71bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193564908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3193564908
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1749668906
Short name T1115
Test name
Test status
Simulation time 24645692 ps
CPU time 0.72 seconds
Started Jul 23 06:09:54 PM PDT 24
Finished Jul 23 06:09:58 PM PDT 24
Peak memory 204836 kb
Host smart-6ab21a68-cbcc-4f31-a3ed-7fab9654e77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749668906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1749668906
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4268414755
Short name T1107
Test name
Test status
Simulation time 24218601 ps
CPU time 0.74 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:09:54 PM PDT 24
Peak memory 204516 kb
Host smart-97ad579d-94aa-4e60-9aa4-c5632b2a06b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268414755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4268414755
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1132509917
Short name T1113
Test name
Test status
Simulation time 22816691 ps
CPU time 0.69 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:51 PM PDT 24
Peak memory 204484 kb
Host smart-5e53d735-b299-4c68-a16f-567b118a85ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132509917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1132509917
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.801558612
Short name T1121
Test name
Test status
Simulation time 25702949 ps
CPU time 0.76 seconds
Started Jul 23 06:09:56 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 204836 kb
Host smart-6fc82440-5474-4746-95f3-3c44452f1dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801558612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.801558612
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1712527299
Short name T1057
Test name
Test status
Simulation time 60710414 ps
CPU time 0.74 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:10:00 PM PDT 24
Peak memory 204484 kb
Host smart-7b757961-d3e5-4856-bd1e-e51386de4b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712527299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1712527299
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2941191328
Short name T1141
Test name
Test status
Simulation time 15638007 ps
CPU time 0.74 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 204380 kb
Host smart-4bd193bd-ca4d-4f75-a0f0-2ecab1b7c6b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941191328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2941191328
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4051962562
Short name T1054
Test name
Test status
Simulation time 13917478 ps
CPU time 0.76 seconds
Started Jul 23 06:09:59 PM PDT 24
Finished Jul 23 06:10:02 PM PDT 24
Peak memory 204480 kb
Host smart-adbade63-1d4c-423f-8b9b-93322b91e25f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051962562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4051962562
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3824285272
Short name T1040
Test name
Test status
Simulation time 23244518 ps
CPU time 0.69 seconds
Started Jul 23 06:09:48 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 204472 kb
Host smart-29273880-71d4-4536-82d1-0bbeeb67ec91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824285272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3824285272
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.683001311
Short name T122
Test name
Test status
Simulation time 1170630470 ps
CPU time 20.13 seconds
Started Jul 23 06:09:25 PM PDT 24
Finished Jul 23 06:09:47 PM PDT 24
Peak memory 217084 kb
Host smart-7e1eafbb-09f9-446d-82c6-484fc6f5f8f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683001311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.683001311
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1640793294
Short name T1039
Test name
Test status
Simulation time 377369592 ps
CPU time 11.32 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:43 PM PDT 24
Peak memory 207808 kb
Host smart-c57df9f1-c263-4ca0-84d2-7d16b137f0b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640793294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1640793294
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2251247152
Short name T80
Test name
Test status
Simulation time 25312959 ps
CPU time 1 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 207544 kb
Host smart-34ba5e3c-363e-42cc-b275-68e99b1ecb99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251247152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2251247152
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.499187772
Short name T1060
Test name
Test status
Simulation time 28754621 ps
CPU time 1.97 seconds
Started Jul 23 06:10:30 PM PDT 24
Finished Jul 23 06:10:41 PM PDT 24
Peak memory 215572 kb
Host smart-44031120-9658-4835-9cf1-ed8d675cadb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499187772 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.499187772
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1709005970
Short name T120
Test name
Test status
Simulation time 36064989 ps
CPU time 2.26 seconds
Started Jul 23 06:09:24 PM PDT 24
Finished Jul 23 06:09:28 PM PDT 24
Peak memory 216004 kb
Host smart-99c2464f-2320-4ee1-aacd-0844c0bd6053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709005970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
709005970
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1202882228
Short name T1082
Test name
Test status
Simulation time 39899121 ps
CPU time 0.7 seconds
Started Jul 23 06:09:43 PM PDT 24
Finished Jul 23 06:09:45 PM PDT 24
Peak memory 204496 kb
Host smart-949321da-5b5d-44b4-ab57-74f6c2815fb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202882228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
202882228
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1096026052
Short name T117
Test name
Test status
Simulation time 130881564 ps
CPU time 1.26 seconds
Started Jul 23 06:09:23 PM PDT 24
Finished Jul 23 06:09:25 PM PDT 24
Peak memory 216060 kb
Host smart-9a5e8a02-e12b-44ce-a47a-c8eb41a68157
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096026052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1096026052
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2967448882
Short name T1102
Test name
Test status
Simulation time 12850677 ps
CPU time 0.64 seconds
Started Jul 23 06:10:48 PM PDT 24
Finished Jul 23 06:10:53 PM PDT 24
Peak memory 204172 kb
Host smart-53a26715-b80c-4127-809f-f55877dec4db
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967448882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2967448882
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3042681978
Short name T137
Test name
Test status
Simulation time 223644381 ps
CPU time 3.56 seconds
Started Jul 23 06:09:16 PM PDT 24
Finished Jul 23 06:09:21 PM PDT 24
Peak memory 216088 kb
Host smart-4d3234ec-3638-4b81-8ebe-24b6a7c3e79c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042681978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3042681978
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1323587153
Short name T109
Test name
Test status
Simulation time 39697497 ps
CPU time 2.71 seconds
Started Jul 23 06:09:19 PM PDT 24
Finished Jul 23 06:09:23 PM PDT 24
Peak memory 217476 kb
Host smart-ac5e5180-f7f6-41c7-9726-9720f39734e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323587153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
323587153
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3601295339
Short name T1101
Test name
Test status
Simulation time 1135938825 ps
CPU time 7.27 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:39 PM PDT 24
Peak memory 217212 kb
Host smart-d1dd2a93-e440-4aa2-8a8e-339b4d50fa68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601295339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3601295339
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.256271669
Short name T1066
Test name
Test status
Simulation time 26514877 ps
CPU time 0.71 seconds
Started Jul 23 06:09:50 PM PDT 24
Finished Jul 23 06:09:53 PM PDT 24
Peak memory 204524 kb
Host smart-11cab88b-9002-436a-bc90-f449da754662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256271669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.256271669
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3872254804
Short name T1031
Test name
Test status
Simulation time 25841882 ps
CPU time 0.7 seconds
Started Jul 23 06:09:45 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 204488 kb
Host smart-829ae954-6848-4c38-a946-767e09a53383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872254804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3872254804
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3888272949
Short name T1068
Test name
Test status
Simulation time 18175540 ps
CPU time 0.71 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 204496 kb
Host smart-05205602-5f9f-49cc-9dc5-534158c3ba25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888272949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3888272949
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2025705212
Short name T1032
Test name
Test status
Simulation time 17391284 ps
CPU time 0.75 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:49 PM PDT 24
Peak memory 204576 kb
Host smart-64e8e6fc-b1ff-43bf-93c7-791304646778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025705212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2025705212
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1914481766
Short name T1030
Test name
Test status
Simulation time 17513037 ps
CPU time 0.76 seconds
Started Jul 23 06:09:44 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 204820 kb
Host smart-6c11f7fe-c5f8-4ff4-8958-113479b8395b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914481766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1914481766
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.4036058211
Short name T1123
Test name
Test status
Simulation time 151310263 ps
CPU time 0.7 seconds
Started Jul 23 06:09:46 PM PDT 24
Finished Jul 23 06:09:48 PM PDT 24
Peak memory 204840 kb
Host smart-18578c1d-544e-4ae5-a718-0cec16637771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036058211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
4036058211
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3253897368
Short name T1041
Test name
Test status
Simulation time 16082997 ps
CPU time 0.7 seconds
Started Jul 23 06:09:55 PM PDT 24
Finished Jul 23 06:09:59 PM PDT 24
Peak memory 204484 kb
Host smart-08aa6559-9f36-4a01-a243-4b4c1d144885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253897368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3253897368
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1377084091
Short name T1090
Test name
Test status
Simulation time 54458773 ps
CPU time 0.72 seconds
Started Jul 23 06:09:52 PM PDT 24
Finished Jul 23 06:09:55 PM PDT 24
Peak memory 204520 kb
Host smart-6bd8ec94-7cec-4bed-96ca-cee64ed23861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377084091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1377084091
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2244988750
Short name T1134
Test name
Test status
Simulation time 13302026 ps
CPU time 0.76 seconds
Started Jul 23 06:09:53 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 204532 kb
Host smart-1a9aaf21-167f-47a5-9ebc-6f3903e47218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244988750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2244988750
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.484428802
Short name T1037
Test name
Test status
Simulation time 13447177 ps
CPU time 0.77 seconds
Started Jul 23 06:09:35 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 204540 kb
Host smart-59bf7dab-8ef2-4db0-843b-5ac839c79bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484428802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.484428802
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.803131308
Short name T1149
Test name
Test status
Simulation time 501882761 ps
CPU time 2.53 seconds
Started Jul 23 06:10:52 PM PDT 24
Finished Jul 23 06:10:59 PM PDT 24
Peak memory 216888 kb
Host smart-3db022c0-f196-446a-a525-ec2332555a1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803131308 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.803131308
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.4235632426
Short name T1139
Test name
Test status
Simulation time 880123645 ps
CPU time 1.93 seconds
Started Jul 23 06:10:52 PM PDT 24
Finished Jul 23 06:10:58 PM PDT 24
Peak memory 215764 kb
Host smart-4b3cac13-dd51-4816-8310-64d49434a6bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235632426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.4
235632426
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.28849936
Short name T1078
Test name
Test status
Simulation time 29121688 ps
CPU time 0.78 seconds
Started Jul 23 06:09:34 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 204536 kb
Host smart-9490ba76-b42b-4a92-83aa-18d581386a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28849936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.28849936
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2978020871
Short name T1051
Test name
Test status
Simulation time 394649475 ps
CPU time 3.4 seconds
Started Jul 23 06:09:34 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 215996 kb
Host smart-3571f7df-8bac-45b7-b15e-9505a4a4afc2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978020871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2978020871
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1179742375
Short name T111
Test name
Test status
Simulation time 53754743 ps
CPU time 3.25 seconds
Started Jul 23 06:09:42 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 216244 kb
Host smart-5a1a45df-1977-472c-9e6c-6aeeb51100be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179742375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
179742375
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1512499691
Short name T1108
Test name
Test status
Simulation time 5135363801 ps
CPU time 19.54 seconds
Started Jul 23 06:09:34 PM PDT 24
Finished Jul 23 06:09:56 PM PDT 24
Peak memory 216140 kb
Host smart-d2f734cd-4a2d-483c-b806-9551a46b53a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512499691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1512499691
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2299927248
Short name T146
Test name
Test status
Simulation time 367013341 ps
CPU time 2.65 seconds
Started Jul 23 06:09:36 PM PDT 24
Finished Jul 23 06:09:41 PM PDT 24
Peak memory 217700 kb
Host smart-7140b8de-8281-476c-8c4f-9f1764894b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299927248 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2299927248
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1760239037
Short name T1095
Test name
Test status
Simulation time 139876841 ps
CPU time 1.85 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:36 PM PDT 24
Peak memory 207820 kb
Host smart-af322ad1-d19c-431f-9364-9beaa6c46897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760239037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
760239037
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.492745192
Short name T1076
Test name
Test status
Simulation time 45342415 ps
CPU time 0.69 seconds
Started Jul 23 06:09:49 PM PDT 24
Finished Jul 23 06:09:52 PM PDT 24
Peak memory 204832 kb
Host smart-29b2071e-e2d3-47d6-9c5a-5a7c97b0c3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492745192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.492745192
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3990835425
Short name T132
Test name
Test status
Simulation time 103296395 ps
CPU time 2.83 seconds
Started Jul 23 06:09:31 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 216060 kb
Host smart-3b07494e-82a8-4809-b564-6df1b88c0c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990835425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3990835425
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.73159645
Short name T159
Test name
Test status
Simulation time 387152584 ps
CPU time 4.68 seconds
Started Jul 23 06:09:25 PM PDT 24
Finished Jul 23 06:09:32 PM PDT 24
Peak memory 216220 kb
Host smart-423773c4-673d-42b5-8f96-762a53676c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73159645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.73159645
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.194333700
Short name T1114
Test name
Test status
Simulation time 103971276 ps
CPU time 6.11 seconds
Started Jul 23 06:10:30 PM PDT 24
Finished Jul 23 06:10:45 PM PDT 24
Peak memory 214592 kb
Host smart-22dc2591-da46-4183-9085-537f01568494
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194333700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.194333700
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.267979663
Short name T1073
Test name
Test status
Simulation time 202777179 ps
CPU time 3.34 seconds
Started Jul 23 06:09:22 PM PDT 24
Finished Jul 23 06:09:32 PM PDT 24
Peak memory 218868 kb
Host smart-ee35ddde-c7d4-4e1f-8f08-3fdce76c433e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267979663 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.267979663
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.568741274
Short name T1125
Test name
Test status
Simulation time 98875567 ps
CPU time 1.4 seconds
Started Jul 23 06:09:33 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 207864 kb
Host smart-6e0754b8-539a-4099-8f73-9d197b158417
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568741274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.568741274
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.394317232
Short name T1119
Test name
Test status
Simulation time 11428911 ps
CPU time 0.7 seconds
Started Jul 23 06:09:22 PM PDT 24
Finished Jul 23 06:09:24 PM PDT 24
Peak memory 204852 kb
Host smart-1cc27969-c1d1-4d20-8f62-59c3ee16e04b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394317232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.394317232
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.721071037
Short name T1150
Test name
Test status
Simulation time 114244127 ps
CPU time 3.56 seconds
Started Jul 23 06:10:50 PM PDT 24
Finished Jul 23 06:10:58 PM PDT 24
Peak memory 215836 kb
Host smart-dfe6c99e-b6aa-4ab7-9aa1-05fc17cb1fdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721071037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.721071037
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3012403642
Short name T1117
Test name
Test status
Simulation time 91791883 ps
CPU time 2.92 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 216252 kb
Host smart-2cf1e93e-225b-4ffc-b06f-2c2fee6928c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012403642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
012403642
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2906129353
Short name T160
Test name
Test status
Simulation time 5310914636 ps
CPU time 19.14 seconds
Started Jul 23 06:09:25 PM PDT 24
Finished Jul 23 06:09:46 PM PDT 24
Peak memory 216140 kb
Host smart-6593e693-5c9d-4849-8702-a42aa5ab355a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906129353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2906129353
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3915755882
Short name T1052
Test name
Test status
Simulation time 87728556 ps
CPU time 2.92 seconds
Started Jul 23 06:09:32 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 217156 kb
Host smart-9e9fc7fb-e0e3-47dd-8edc-d4546ce37523
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915755882 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3915755882
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1661967765
Short name T1075
Test name
Test status
Simulation time 70662198 ps
CPU time 2.13 seconds
Started Jul 23 06:09:47 PM PDT 24
Finished Jul 23 06:09:50 PM PDT 24
Peak memory 215972 kb
Host smart-a59a1b7f-ed82-4fff-bd97-0f4276becbb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661967765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
661967765
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3691791039
Short name T1035
Test name
Test status
Simulation time 12685342 ps
CPU time 0.73 seconds
Started Jul 23 06:09:35 PM PDT 24
Finished Jul 23 06:09:38 PM PDT 24
Peak memory 204868 kb
Host smart-842ded52-ef95-4b8b-9884-0cd6d860240e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691791039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
691791039
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3770561674
Short name T1122
Test name
Test status
Simulation time 115023632 ps
CPU time 1.89 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:41 PM PDT 24
Peak memory 216024 kb
Host smart-fb24ba54-9da7-4db0-b82f-274f43e5929e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770561674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3770561674
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1622831455
Short name T1136
Test name
Test status
Simulation time 39983510 ps
CPU time 1.72 seconds
Started Jul 23 06:09:57 PM PDT 24
Finished Jul 23 06:10:06 PM PDT 24
Peak memory 216200 kb
Host smart-c8277f5d-b24a-47e6-8c36-81a8cc12505e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622831455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
622831455
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4266327585
Short name T1148
Test name
Test status
Simulation time 628891083 ps
CPU time 11.35 seconds
Started Jul 23 06:10:38 PM PDT 24
Finished Jul 23 06:10:55 PM PDT 24
Peak memory 215688 kb
Host smart-bf8a6c19-3055-46e6-8f54-154c30dfddb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266327585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4266327585
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1306020538
Short name T1112
Test name
Test status
Simulation time 122516283 ps
CPU time 3.21 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:09:45 PM PDT 24
Peak memory 218924 kb
Host smart-b70d89f3-098a-4b44-9d55-d359f327d891
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306020538 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1306020538
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.779107795
Short name T1085
Test name
Test status
Simulation time 132723201 ps
CPU time 1.28 seconds
Started Jul 23 06:09:37 PM PDT 24
Finished Jul 23 06:09:40 PM PDT 24
Peak memory 207880 kb
Host smart-497e14ee-f010-43c6-9b88-c5b297443089
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779107795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.779107795
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1561286228
Short name T1151
Test name
Test status
Simulation time 21759546 ps
CPU time 0.68 seconds
Started Jul 23 06:09:30 PM PDT 24
Finished Jul 23 06:09:33 PM PDT 24
Peak memory 204776 kb
Host smart-3806030b-3b1b-414a-8735-6fddb631134c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561286228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
561286228
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3556579479
Short name T1129
Test name
Test status
Simulation time 62438326 ps
CPU time 3.66 seconds
Started Jul 23 06:10:47 PM PDT 24
Finished Jul 23 06:10:56 PM PDT 24
Peak memory 215856 kb
Host smart-93b0aebd-6a65-4e89-a2c8-665dbebe5aff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556579479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3556579479
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1399330456
Short name T107
Test name
Test status
Simulation time 181109975 ps
CPU time 4.12 seconds
Started Jul 23 06:09:29 PM PDT 24
Finished Jul 23 06:09:34 PM PDT 24
Peak memory 216308 kb
Host smart-4612811d-9d47-42ef-ae61-6c36b4988ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399330456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
399330456
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1226622902
Short name T144
Test name
Test status
Simulation time 3562585861 ps
CPU time 22.44 seconds
Started Jul 23 06:09:40 PM PDT 24
Finished Jul 23 06:10:04 PM PDT 24
Peak memory 216196 kb
Host smart-e3ed2052-53c1-4a70-9b16-a630e4258615
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226622902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1226622902
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3081301845
Short name T751
Test name
Test status
Simulation time 37530184 ps
CPU time 0.75 seconds
Started Jul 23 04:40:18 PM PDT 24
Finished Jul 23 04:40:22 PM PDT 24
Peak memory 205992 kb
Host smart-c6e196e9-5a8e-4023-a9a5-59a80e3e5a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081301845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
081301845
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4136814614
Short name T822
Test name
Test status
Simulation time 91104853 ps
CPU time 2.59 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 233620 kb
Host smart-f36bcb15-0c33-4053-8fe2-e56334901a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136814614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4136814614
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3744676489
Short name T987
Test name
Test status
Simulation time 70818168 ps
CPU time 0.81 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:19 PM PDT 24
Peak memory 207476 kb
Host smart-d4ac611d-d576-492d-a94c-4cf3b298ed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744676489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3744676489
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3704509522
Short name T216
Test name
Test status
Simulation time 96789889012 ps
CPU time 159.48 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:42:55 PM PDT 24
Peak memory 251252 kb
Host smart-bdedee45-5efc-4d82-9627-136e39d10355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704509522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3704509522
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.774607678
Short name T325
Test name
Test status
Simulation time 10009585880 ps
CPU time 56.57 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 252380 kb
Host smart-d6040a0e-052f-48c6-870a-021ab903f8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774607678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.774607678
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2545939230
Short name T890
Test name
Test status
Simulation time 84351871057 ps
CPU time 216.09 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 253376 kb
Host smart-7444a94a-2504-40ac-83ad-d7f25e599aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545939230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2545939230
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.2951440116
Short name T85
Test name
Test status
Simulation time 1771884221 ps
CPU time 37.17 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 251372 kb
Host smart-62228553-917d-44cc-a751-aa13953a9724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951440116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.2951440116
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.413009782
Short name T994
Test name
Test status
Simulation time 7964572507 ps
CPU time 22.62 seconds
Started Jul 23 04:40:09 PM PDT 24
Finished Jul 23 04:40:34 PM PDT 24
Peak memory 225516 kb
Host smart-1a8834ee-ac01-42e1-a1bf-3ab0a4bad4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413009782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.413009782
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2174560328
Short name T892
Test name
Test status
Simulation time 1563463453 ps
CPU time 11.41 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:30 PM PDT 24
Peak memory 241216 kb
Host smart-9ba267bd-28bc-4e0b-8a4f-59338ac088be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174560328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2174560328
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2995024318
Short name T731
Test name
Test status
Simulation time 31834005 ps
CPU time 1.02 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:17 PM PDT 24
Peak memory 217284 kb
Host smart-b9d88910-361b-446e-90bb-f8175c22a56d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995024318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2995024318
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1072998288
Short name T404
Test name
Test status
Simulation time 782958516 ps
CPU time 3.48 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 233556 kb
Host smart-43a1be8f-b45b-4299-bc93-f0f8c133f8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072998288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1072998288
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1099369916
Short name T913
Test name
Test status
Simulation time 2255103345 ps
CPU time 4.58 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 225400 kb
Host smart-5cd826d7-8201-40e4-bcfa-90ca21e7741f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099369916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1099369916
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.659503048
Short name T637
Test name
Test status
Simulation time 846159273 ps
CPU time 10.78 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 220796 kb
Host smart-2dabc17c-0ac4-42f3-a94c-83ddb56f5346
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659503048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.659503048
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1193611345
Short name T803
Test name
Test status
Simulation time 2977061458 ps
CPU time 26.82 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:40:46 PM PDT 24
Peak memory 221120 kb
Host smart-d39e8bc4-d43a-4388-b7f3-13a8701171dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193611345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1193611345
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2511258216
Short name T594
Test name
Test status
Simulation time 14214610 ps
CPU time 0.75 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 206248 kb
Host smart-0b025e46-887d-482d-b841-9b9fa4cea808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511258216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2511258216
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2797350139
Short name T371
Test name
Test status
Simulation time 94843671 ps
CPU time 1.76 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:20 PM PDT 24
Peak memory 216976 kb
Host smart-02acab10-1df9-4a05-bcfb-46756503d8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797350139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2797350139
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1769386308
Short name T696
Test name
Test status
Simulation time 12733141 ps
CPU time 0.67 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:18 PM PDT 24
Peak memory 206204 kb
Host smart-8d7b6bb3-3c65-4588-80a3-3306e189c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769386308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1769386308
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1556937221
Short name T10
Test name
Test status
Simulation time 119098359 ps
CPU time 2.53 seconds
Started Jul 23 04:40:18 PM PDT 24
Finished Jul 23 04:40:24 PM PDT 24
Peak memory 225020 kb
Host smart-1a1fe7c6-e9ce-4d32-89fb-9c8febbbb984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556937221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1556937221
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1286296037
Short name T664
Test name
Test status
Simulation time 13914618 ps
CPU time 0.74 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:16 PM PDT 24
Peak memory 205932 kb
Host smart-10150064-1f56-4735-a131-1ef393439a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286296037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
286296037
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.785530630
Short name T746
Test name
Test status
Simulation time 213210336 ps
CPU time 4.01 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:22 PM PDT 24
Peak memory 225284 kb
Host smart-736094fd-68e9-47ee-9132-b0a621c5d934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785530630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.785530630
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1527147630
Short name T614
Test name
Test status
Simulation time 41223957 ps
CPU time 0.8 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:15 PM PDT 24
Peak memory 206156 kb
Host smart-ecbf29dc-5e45-4ae2-a4c4-fec5ca1db415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527147630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1527147630
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2200593907
Short name T185
Test name
Test status
Simulation time 17159397952 ps
CPU time 47.22 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 237676 kb
Host smart-28c2d83d-596e-48aa-9ddf-c203b765178e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200593907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2200593907
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.647278628
Short name T885
Test name
Test status
Simulation time 20682070176 ps
CPU time 46.12 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 251712 kb
Host smart-5560661d-9c62-4c74-84ef-b8c1303d6eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647278628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.647278628
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.380002415
Short name T923
Test name
Test status
Simulation time 47080653598 ps
CPU time 362.09 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:46:22 PM PDT 24
Peak memory 253104 kb
Host smart-bc794cae-ac36-462c-bc66-f81a256068d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380002415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
380002415
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3446157716
Short name T141
Test name
Test status
Simulation time 182498674 ps
CPU time 3.87 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 233520 kb
Host smart-d4a54558-b454-478d-a7e9-f8b3b8ac5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446157716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3446157716
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2038267745
Short name T821
Test name
Test status
Simulation time 10734586634 ps
CPU time 37 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:51 PM PDT 24
Peak memory 237704 kb
Host smart-462c2b4c-3504-4013-9468-8c485c791914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038267745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2038267745
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3339536646
Short name T333
Test name
Test status
Simulation time 508528695 ps
CPU time 7.92 seconds
Started Jul 23 04:40:10 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 225400 kb
Host smart-93bff8c1-1254-4767-9cb1-1f3af7486180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339536646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3339536646
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2940446359
Short name T204
Test name
Test status
Simulation time 3940448684 ps
CPU time 7.95 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:27 PM PDT 24
Peak memory 233576 kb
Host smart-1f00b9a1-aa18-406f-abac-70e79356b4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940446359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2940446359
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2212913851
Short name T997
Test name
Test status
Simulation time 29629886 ps
CPU time 1.06 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:22 PM PDT 24
Peak memory 217228 kb
Host smart-fa0f468a-44cc-4505-9374-85efbc2ec37c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212913851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2212913851
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3716895449
Short name T928
Test name
Test status
Simulation time 60828855621 ps
CPU time 28.24 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 04:40:50 PM PDT 24
Peak memory 241372 kb
Host smart-16fcc21e-53d0-4c52-ae6e-9b44d0e44aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716895449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3716895449
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3653166004
Short name T267
Test name
Test status
Simulation time 202772324 ps
CPU time 3.72 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:20 PM PDT 24
Peak memory 233576 kb
Host smart-483cfe0d-2d4e-4766-9e15-e70d9f9b431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653166004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3653166004
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3876135559
Short name T1015
Test name
Test status
Simulation time 2188183352 ps
CPU time 5.55 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 223376 kb
Host smart-31e86c72-3821-45e4-8cc5-c26b0d27a14c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876135559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3876135559
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.27099996
Short name T63
Test name
Test status
Simulation time 34276831 ps
CPU time 0.93 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 235832 kb
Host smart-5058fd6d-9813-43a0-882b-a301c07b978f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27099996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.27099996
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3335472485
Short name T217
Test name
Test status
Simulation time 11041388651 ps
CPU time 136.57 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:42:37 PM PDT 24
Peak memory 250128 kb
Host smart-6ef314c4-b8fa-4dd2-b6e2-8a6cf0e39ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335472485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3335472485
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2237697087
Short name T612
Test name
Test status
Simulation time 30857704640 ps
CPU time 41.46 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 217348 kb
Host smart-4898c58d-8ca1-4465-a11f-d5172a3b2f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237697087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2237697087
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2854473880
Short name T345
Test name
Test status
Simulation time 354080420 ps
CPU time 1.84 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:17 PM PDT 24
Peak memory 208604 kb
Host smart-4400163c-19b9-4001-86e9-64349a218e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854473880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2854473880
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.842211417
Short name T433
Test name
Test status
Simulation time 222355780 ps
CPU time 1.32 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:17 PM PDT 24
Peak memory 217096 kb
Host smart-36c11486-08bd-4dd7-8652-ba9f2b1ddd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842211417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.842211417
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1952111223
Short name T814
Test name
Test status
Simulation time 110078939 ps
CPU time 1 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:15 PM PDT 24
Peak memory 207708 kb
Host smart-e810909d-735a-4432-a7c0-c85af27eec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952111223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1952111223
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2429981462
Short name T684
Test name
Test status
Simulation time 1013774884 ps
CPU time 4.49 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:40:24 PM PDT 24
Peak memory 233544 kb
Host smart-583c2f42-29a6-4d7b-bfab-395c4a0b3d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429981462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2429981462
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3491253541
Short name T844
Test name
Test status
Simulation time 34690798 ps
CPU time 0.71 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 206036 kb
Host smart-597b8e07-bbc0-4af4-a877-2f5aee10f44b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491253541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3491253541
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.118602002
Short name T1000
Test name
Test status
Simulation time 2068880831 ps
CPU time 19.78 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 233188 kb
Host smart-4b465273-1d3f-4b23-84f5-df02ee8472b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118602002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.118602002
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1129942797
Short name T364
Test name
Test status
Simulation time 17502003 ps
CPU time 0.79 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 207156 kb
Host smart-49965656-8f0c-45c8-b4b1-ad667fcfaa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129942797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1129942797
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3326902554
Short name T864
Test name
Test status
Simulation time 31972123933 ps
CPU time 71.38 seconds
Started Jul 23 04:40:42 PM PDT 24
Finished Jul 23 04:41:57 PM PDT 24
Peak memory 250024 kb
Host smart-e428100d-4345-4790-b7b6-1b7515ac2258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326902554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3326902554
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.279677916
Short name T283
Test name
Test status
Simulation time 48534626461 ps
CPU time 93.5 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:42:31 PM PDT 24
Peak memory 249992 kb
Host smart-f6abcba1-fbbf-4199-9468-01eb4eba4be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279677916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.279677916
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2314095012
Short name T469
Test name
Test status
Simulation time 1616722050 ps
CPU time 15.59 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 238140 kb
Host smart-98c55a40-b397-4ca0-8bd0-d8bfdc7d6832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314095012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2314095012
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3327714084
Short name T871
Test name
Test status
Simulation time 89083268508 ps
CPU time 238.68 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:44:45 PM PDT 24
Peak memory 249968 kb
Host smart-3376fd2e-844d-4aa2-ae8e-706056f23071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327714084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3327714084
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3699263695
Short name T192
Test name
Test status
Simulation time 844083998 ps
CPU time 4.8 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:51 PM PDT 24
Peak memory 233568 kb
Host smart-283a9c3b-ca73-42c3-a4d8-9e4c891f74bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699263695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3699263695
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2759188005
Short name T859
Test name
Test status
Simulation time 6269955361 ps
CPU time 34.94 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 241480 kb
Host smart-d1880743-bcd8-480e-8c53-f446100e143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759188005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2759188005
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1916219112
Short name T804
Test name
Test status
Simulation time 40174740 ps
CPU time 1.05 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 217292 kb
Host smart-e067ff84-0cc3-4515-a247-5eea37fd318f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916219112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1916219112
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2009377916
Short name T894
Test name
Test status
Simulation time 24610553460 ps
CPU time 8.98 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 233720 kb
Host smart-2dfc9842-0e5c-49fd-bfaf-2cdcc40b3042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009377916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2009377916
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1271053714
Short name T139
Test name
Test status
Simulation time 1489670871 ps
CPU time 20.51 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:41:08 PM PDT 24
Peak memory 220956 kb
Host smart-b02ab656-e965-486a-a2b6-be188ecd4ea4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1271053714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1271053714
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1589991469
Short name T3
Test name
Test status
Simulation time 117282526 ps
CPU time 1.1 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 208352 kb
Host smart-8a0f508e-2dee-4112-bc6a-4b6e6c7b295c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589991469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1589991469
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1684674075
Short name T503
Test name
Test status
Simulation time 10144842334 ps
CPU time 13.03 seconds
Started Jul 23 04:40:45 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 217168 kb
Host smart-eb300acc-ba8c-4fec-8627-fa2cbfd47907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684674075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1684674075
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1419555995
Short name T778
Test name
Test status
Simulation time 36378808305 ps
CPU time 15.38 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 218236 kb
Host smart-b86a9a98-fb6c-4523-add0-ffff7c7611bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419555995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1419555995
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2846184681
Short name T75
Test name
Test status
Simulation time 614815428 ps
CPU time 1.86 seconds
Started Jul 23 04:40:43 PM PDT 24
Finished Jul 23 04:40:49 PM PDT 24
Peak memory 216504 kb
Host smart-cfdd3049-9cc7-4e3e-87a4-0b0d5e17f8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846184681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2846184681
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1867427891
Short name T718
Test name
Test status
Simulation time 19067189 ps
CPU time 0.78 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 206664 kb
Host smart-00a70ad5-cb76-41c5-866e-f729600dc168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867427891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1867427891
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3187771570
Short name T785
Test name
Test status
Simulation time 2781805559 ps
CPU time 10.63 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 225484 kb
Host smart-4fec6acb-4404-4ee7-b2f2-214b8d362c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187771570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3187771570
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.353256642
Short name T515
Test name
Test status
Simulation time 20250788 ps
CPU time 0.7 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 206024 kb
Host smart-fdef4a5f-5f37-444e-a4aa-882f9266d6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353256642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.353256642
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1452969582
Short name T606
Test name
Test status
Simulation time 203818631 ps
CPU time 2.87 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 233488 kb
Host smart-0b029a04-d15a-4dc0-8d2b-144cc5f10eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452969582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1452969582
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1653306271
Short name T795
Test name
Test status
Simulation time 16336000 ps
CPU time 0.82 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 207164 kb
Host smart-4a5fae3e-afd3-43fe-ae52-96d4affb88f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653306271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1653306271
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.763840433
Short name T692
Test name
Test status
Simulation time 20871965509 ps
CPU time 85.49 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:42:27 PM PDT 24
Peak memory 241852 kb
Host smart-1058b94d-b9b7-43a9-9e7c-5fb2df4db534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763840433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.763840433
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1732366329
Short name T611
Test name
Test status
Simulation time 23500549331 ps
CPU time 83.25 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 250180 kb
Host smart-0e726d7b-8872-4d37-9fb5-28324225355a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732366329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1732366329
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2339804120
Short name T702
Test name
Test status
Simulation time 103650974 ps
CPU time 2.22 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:01 PM PDT 24
Peak memory 225364 kb
Host smart-3733669a-d68c-4e1f-8d3c-b6d1be3bfa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339804120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2339804120
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.160166037
Short name T287
Test name
Test status
Simulation time 24229797335 ps
CPU time 112.01 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 266312 kb
Host smart-391d20af-6fd0-43c9-a691-0063f7dbf8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160166037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.160166037
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1158507607
Short name T174
Test name
Test status
Simulation time 1844948427 ps
CPU time 13.35 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 233516 kb
Host smart-035cc09d-b980-4720-8923-45132d18615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158507607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1158507607
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2110526605
Short name T860
Test name
Test status
Simulation time 34545158193 ps
CPU time 47.78 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 233560 kb
Host smart-cb90c2fc-a1f8-4c50-9c30-4e916bd50f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110526605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2110526605
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.366860315
Short name T929
Test name
Test status
Simulation time 461833788 ps
CPU time 2.26 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 224596 kb
Host smart-1c10d179-accd-402d-8dae-4d9dde9e104d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366860315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.366860315
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1303809233
Short name T224
Test name
Test status
Simulation time 969015004 ps
CPU time 4.83 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 225292 kb
Host smart-db6eb567-004c-42fd-9be3-a3062ae44f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303809233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1303809233
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1373943424
Short name T737
Test name
Test status
Simulation time 1937720175 ps
CPU time 6.77 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 221204 kb
Host smart-5d844a6a-8fee-4b2a-ab29-7d42d51c685e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1373943424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1373943424
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.849396814
Short name T705
Test name
Test status
Simulation time 17923704978 ps
CPU time 135.47 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 264340 kb
Host smart-f4e9ff8d-bdf5-409e-a9a8-09459333e07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849396814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.849396814
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2203626088
Short name T670
Test name
Test status
Simulation time 315917924 ps
CPU time 3.41 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 219420 kb
Host smart-fa33dd07-cb95-4e91-8542-8e174d493d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203626088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2203626088
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3137053955
Short name T550
Test name
Test status
Simulation time 5875354809 ps
CPU time 7.67 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:41:11 PM PDT 24
Peak memory 217156 kb
Host smart-563094dc-d180-459e-b715-571d04440e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137053955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3137053955
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1585919258
Short name T810
Test name
Test status
Simulation time 499982350 ps
CPU time 3.89 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 217044 kb
Host smart-b8335052-b592-47de-b99d-248a07d2eea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585919258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1585919258
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_upload.1299838164
Short name T797
Test name
Test status
Simulation time 25982464899 ps
CPU time 25.17 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:21 PM PDT 24
Peak memory 233560 kb
Host smart-6400bab3-bf11-48b5-8b55-2614e05ef29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299838164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1299838164
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2088807273
Short name T927
Test name
Test status
Simulation time 46053367 ps
CPU time 0.77 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:41:04 PM PDT 24
Peak memory 205476 kb
Host smart-4cbaf86f-c6d1-43e8-88d4-d6f7cb0eb8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088807273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2088807273
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2024313014
Short name T749
Test name
Test status
Simulation time 15033209671 ps
CPU time 23.96 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:26 PM PDT 24
Peak memory 225464 kb
Host smart-b0cc68db-acff-4b08-95aa-edc9438c64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024313014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2024313014
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2842859846
Short name T591
Test name
Test status
Simulation time 29721864 ps
CPU time 0.81 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:40:58 PM PDT 24
Peak memory 206068 kb
Host smart-3cfbad0a-c8af-424c-b319-201b77ac5f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842859846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2842859846
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.330746770
Short name T422
Test name
Test status
Simulation time 357794384732 ps
CPU time 164.86 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 254020 kb
Host smart-4beb5100-0439-4602-8c3c-ecbc339cc2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330746770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.330746770
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2185754000
Short name T193
Test name
Test status
Simulation time 77757961447 ps
CPU time 347.58 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:46:50 PM PDT 24
Peak memory 252388 kb
Host smart-375b4b6c-044f-428d-a80e-0c41266f541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185754000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2185754000
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1866338448
Short name T946
Test name
Test status
Simulation time 9430718735 ps
CPU time 83.64 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:42:27 PM PDT 24
Peak memory 250160 kb
Host smart-e0170023-b3af-4054-9ea3-286545b83f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866338448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1866338448
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1653301307
Short name T304
Test name
Test status
Simulation time 225479034 ps
CPU time 5.89 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:10 PM PDT 24
Peak memory 233660 kb
Host smart-8fcf2171-4f6f-45bd-9a8d-81e2afa90b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653301307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1653301307
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3294527524
Short name T253
Test name
Test status
Simulation time 4453169334 ps
CPU time 17.39 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:41:21 PM PDT 24
Peak memory 237468 kb
Host smart-07249845-2feb-4221-bbd6-fcfe59bde776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294527524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3294527524
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2831473668
Short name T827
Test name
Test status
Simulation time 429937103 ps
CPU time 2.45 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 225316 kb
Host smart-996426cd-4f81-409b-8761-98cc5c8ba07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831473668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2831473668
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3232610206
Short name T190
Test name
Test status
Simulation time 2390193030 ps
CPU time 12.13 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 240848 kb
Host smart-ca8b6887-67ce-492b-a9b8-59f0fd8b9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232610206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3232610206
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2023741294
Short name T998
Test name
Test status
Simulation time 54944967 ps
CPU time 1.05 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 218632 kb
Host smart-0fb1ed89-db32-4398-96f7-34c8958e685d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023741294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2023741294
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4248068826
Short name T494
Test name
Test status
Simulation time 13242034182 ps
CPU time 11.82 seconds
Started Jul 23 04:41:02 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 238436 kb
Host smart-72126368-2f06-4b02-8965-af76471e7245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248068826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4248068826
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1471308290
Short name T978
Test name
Test status
Simulation time 6566974939 ps
CPU time 8.8 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:13 PM PDT 24
Peak memory 225320 kb
Host smart-d2d4bef8-1a9e-42a4-b9d7-053b5ceafd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471308290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1471308290
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3214782185
Short name T831
Test name
Test status
Simulation time 462684177 ps
CPU time 3.46 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 219724 kb
Host smart-d79ab510-e267-4762-81ee-0e4da1d9be88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3214782185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3214782185
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.101056228
Short name T491
Test name
Test status
Simulation time 159967901 ps
CPU time 0.92 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:41:08 PM PDT 24
Peak memory 206320 kb
Host smart-4e9bb87e-d903-4424-b2c8-c1e1ded4d101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101056228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.101056228
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3343035836
Short name T992
Test name
Test status
Simulation time 2212708956 ps
CPU time 11.48 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 217156 kb
Host smart-f60663c3-f366-463b-a992-c180440ff5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343035836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3343035836
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1205444759
Short name T581
Test name
Test status
Simulation time 955602924 ps
CPU time 2.65 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 217140 kb
Host smart-0e808008-1efb-4c99-a00f-5dd2683f24a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205444759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1205444759
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3183281605
Short name T996
Test name
Test status
Simulation time 868711892 ps
CPU time 3.09 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 217156 kb
Host smart-758d03ec-d600-44cd-ad94-0b87b701bba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183281605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3183281605
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4200233524
Short name T70
Test name
Test status
Simulation time 272275616 ps
CPU time 0.81 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:40:59 PM PDT 24
Peak memory 206768 kb
Host smart-ddd3f658-f1be-40bc-9422-b0437b64de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200233524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4200233524
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2462964922
Short name T255
Test name
Test status
Simulation time 6549412329 ps
CPU time 21.18 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 233652 kb
Host smart-76cfef72-24f2-4953-ac44-d75f2effac89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462964922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2462964922
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1573213781
Short name T393
Test name
Test status
Simulation time 13749988 ps
CPU time 0.66 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 205968 kb
Host smart-c5e28824-c59f-47ff-995e-dbec711d9c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573213781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1573213781
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4213087107
Short name T774
Test name
Test status
Simulation time 833677733 ps
CPU time 4.05 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 225356 kb
Host smart-78202af2-6634-4818-bce2-f361825f8200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213087107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4213087107
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2583526186
Short name T466
Test name
Test status
Simulation time 13661517 ps
CPU time 0.75 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 206144 kb
Host smart-5422a46b-9e22-41d0-bb5e-705a428b3e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583526186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2583526186
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4078044494
Short name T153
Test name
Test status
Simulation time 47416407083 ps
CPU time 327.03 seconds
Started Jul 23 04:40:59 PM PDT 24
Finished Jul 23 04:46:31 PM PDT 24
Peak memory 255076 kb
Host smart-4c5a0afb-97f9-41a2-a8bc-180ab9bbc056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078044494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4078044494
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3258174117
Short name T813
Test name
Test status
Simulation time 3318010113 ps
CPU time 72.71 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:42:15 PM PDT 24
Peak memory 251524 kb
Host smart-c7ab432c-b627-41f8-9726-b10e9d988fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258174117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3258174117
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3232534305
Short name T798
Test name
Test status
Simulation time 15591606637 ps
CPU time 76.53 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 252168 kb
Host smart-9d5acd0e-a693-487b-8434-a96e33e102b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232534305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3232534305
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4147581311
Short name T546
Test name
Test status
Simulation time 1093661977 ps
CPU time 3.14 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:41:01 PM PDT 24
Peak memory 225380 kb
Host smart-271c94c4-be50-41e6-bd5a-f75982785665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147581311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4147581311
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2055684301
Short name T777
Test name
Test status
Simulation time 189749413054 ps
CPU time 135.23 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:43:13 PM PDT 24
Peak memory 250036 kb
Host smart-123b097f-89fb-4328-8b0b-c2e4cffecafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055684301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2055684301
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.55301870
Short name T610
Test name
Test status
Simulation time 2991313176 ps
CPU time 24.35 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:27 PM PDT 24
Peak memory 225404 kb
Host smart-4a2f18ba-3317-41e9-a257-2bd2d2eb9f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55301870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.55301870
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2288887774
Short name T691
Test name
Test status
Simulation time 9468325956 ps
CPU time 65.57 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:42:09 PM PDT 24
Peak memory 241796 kb
Host smart-35f24029-ee28-4be1-bc5a-906bb8a4a0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288887774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2288887774
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1717162662
Short name T456
Test name
Test status
Simulation time 30478186 ps
CPU time 1.06 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 217340 kb
Host smart-d6c49a6a-c3ad-4d1b-ac56-db649ecf653c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717162662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1717162662
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.4054079769
Short name T907
Test name
Test status
Simulation time 3856538754 ps
CPU time 12.32 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 241400 kb
Host smart-f014a93e-ce8a-41c2-b830-416d2a545455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054079769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.4054079769
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3290935274
Short name T866
Test name
Test status
Simulation time 7109572032 ps
CPU time 6.71 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:08 PM PDT 24
Peak memory 233636 kb
Host smart-0b8140f5-acd2-4f30-bb8d-031c067a5225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290935274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3290935274
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2965752261
Short name T620
Test name
Test status
Simulation time 2614822661 ps
CPU time 6.54 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 223972 kb
Host smart-ae18e12d-7375-4284-8d53-28ff1516e42b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2965752261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2965752261
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3060788465
Short name T178
Test name
Test status
Simulation time 193412772510 ps
CPU time 456.94 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:48:39 PM PDT 24
Peak memory 256028 kb
Host smart-cc23f4ee-1af6-40e1-9e8a-adde7b89b276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060788465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3060788465
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3505872567
Short name T522
Test name
Test status
Simulation time 2527698374 ps
CPU time 12.26 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 217176 kb
Host smart-81a8346a-dd0c-4795-99fa-3780a55f9e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505872567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3505872567
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.816008390
Short name T384
Test name
Test status
Simulation time 6910479862 ps
CPU time 19.57 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 217260 kb
Host smart-4e076853-398b-4ba9-9628-6e4837a41e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816008390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.816008390
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.327422881
Short name T849
Test name
Test status
Simulation time 117765462 ps
CPU time 2.16 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 217136 kb
Host smart-f57ddacc-9816-42e2-bdda-3444ab855e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327422881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.327422881
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3693504545
Short name T336
Test name
Test status
Simulation time 44581715 ps
CPU time 0.73 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 206664 kb
Host smart-fbf5cc77-3fa5-4adc-a54e-bba059dd2873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693504545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3693504545
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1246442355
Short name T461
Test name
Test status
Simulation time 967028187 ps
CPU time 8.14 seconds
Started Jul 23 04:41:02 PM PDT 24
Finished Jul 23 04:41:13 PM PDT 24
Peak memory 233548 kb
Host smart-f190901d-5f35-4b37-a0b2-57c3c787844a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246442355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1246442355
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3168484058
Short name T381
Test name
Test status
Simulation time 15341512 ps
CPU time 0.74 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 206304 kb
Host smart-6679c95a-d10f-4441-95f8-d0a94fce9647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168484058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3168484058
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3027876782
Short name T768
Test name
Test status
Simulation time 126531609 ps
CPU time 2.91 seconds
Started Jul 23 04:40:57 PM PDT 24
Finished Jul 23 04:41:04 PM PDT 24
Peak memory 225396 kb
Host smart-c86e0824-5ad7-4309-82f0-e028210a1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027876782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3027876782
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.688676991
Short name T334
Test name
Test status
Simulation time 85325239 ps
CPU time 0.77 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:40:56 PM PDT 24
Peak memory 207420 kb
Host smart-6b848467-a38e-4829-a027-0d7534ca5e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688676991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.688676991
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3188164317
Short name T904
Test name
Test status
Simulation time 17790586797 ps
CPU time 62.64 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:42:01 PM PDT 24
Peak memory 251844 kb
Host smart-7ae5037a-05fb-494c-8caf-c341ccd32c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188164317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3188164317
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1927598254
Short name T783
Test name
Test status
Simulation time 11594236381 ps
CPU time 99.52 seconds
Started Jul 23 04:40:53 PM PDT 24
Finished Jul 23 04:42:34 PM PDT 24
Peak memory 250048 kb
Host smart-d97a460e-34a0-4ea0-811e-d7d8b39fe0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927598254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1927598254
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3058015628
Short name T922
Test name
Test status
Simulation time 19811076679 ps
CPU time 28.91 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 220432 kb
Host smart-8b64f960-7a71-442f-8f8b-ef0f5ca5268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058015628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3058015628
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2492776939
Short name T980
Test name
Test status
Simulation time 220804626 ps
CPU time 3.83 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 238020 kb
Host smart-2c414904-cb27-4803-b733-d68685a682c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492776939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2492776939
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1877600690
Short name T265
Test name
Test status
Simulation time 8010127182 ps
CPU time 60.69 seconds
Started Jul 23 04:40:53 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 235436 kb
Host smart-2ea76cb4-87bc-4674-a5d5-ec67c1040e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877600690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1877600690
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1260519978
Short name T979
Test name
Test status
Simulation time 345643945 ps
CPU time 3.04 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:41:01 PM PDT 24
Peak memory 225392 kb
Host smart-0650e06f-a836-4c4f-9874-5b43af6db8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260519978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1260519978
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.339024422
Short name T872
Test name
Test status
Simulation time 491000831 ps
CPU time 7.19 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:08 PM PDT 24
Peak memory 233596 kb
Host smart-79f3c264-5535-41e3-9c24-d92cf3ccfdb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339024422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.339024422
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2707479766
Short name T600
Test name
Test status
Simulation time 47351577 ps
CPU time 1.02 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:01 PM PDT 24
Peak memory 217308 kb
Host smart-a6697eec-6e14-4ebc-8c5b-619cc769d3de
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707479766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2707479766
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1683068073
Short name T480
Test name
Test status
Simulation time 181855149 ps
CPU time 1.96 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:40:59 PM PDT 24
Peak memory 224528 kb
Host smart-a9835ebb-1b6e-42a4-837d-4bf221971887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683068073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1683068073
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1412297901
Short name T921
Test name
Test status
Simulation time 288253898 ps
CPU time 3.61 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 223736 kb
Host smart-1a0d4070-35f6-4d86-a318-354141599f6f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1412297901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1412297901
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.611779286
Short name T1004
Test name
Test status
Simulation time 141855949 ps
CPU time 1.06 seconds
Started Jul 23 04:40:52 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 208120 kb
Host smart-1402b4e2-2f50-48de-a1f9-53ad32b388c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611779286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.611779286
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.310411100
Short name T815
Test name
Test status
Simulation time 1329111247 ps
CPU time 14.31 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:15 PM PDT 24
Peak memory 217332 kb
Host smart-2f74a04c-39ff-4301-9098-4a38ce6009df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310411100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.310411100
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2933705524
Short name T512
Test name
Test status
Simulation time 776477058 ps
CPU time 5.14 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:05 PM PDT 24
Peak memory 217056 kb
Host smart-383762c9-dc28-4977-a2b4-f3e4141053a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933705524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2933705524
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.793488656
Short name T582
Test name
Test status
Simulation time 568359704 ps
CPU time 6.44 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 217156 kb
Host smart-b699480f-bad0-43b5-8f61-242814ea4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793488656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.793488656
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1347076835
Short name T563
Test name
Test status
Simulation time 41930306 ps
CPU time 0.77 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:04 PM PDT 24
Peak memory 206724 kb
Host smart-3f51d173-74e6-4d86-a3e4-fbe811a8b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347076835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1347076835
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.253211255
Short name T513
Test name
Test status
Simulation time 160449415 ps
CPU time 2.54 seconds
Started Jul 23 04:41:00 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 224960 kb
Host smart-3a508731-27c6-4307-85e6-ac05273e26f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253211255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.253211255
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.976524491
Short name T245
Test name
Test status
Simulation time 190548668 ps
CPU time 3.3 seconds
Started Jul 23 04:40:52 PM PDT 24
Finished Jul 23 04:40:56 PM PDT 24
Peak memory 225464 kb
Host smart-f9595479-3ea8-4c46-a787-1f1d21145398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976524491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.976524491
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1742829735
Short name T919
Test name
Test status
Simulation time 17135547 ps
CPU time 0.79 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 207160 kb
Host smart-6abcd3e9-d2a4-4060-afd6-367fd10c0d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742829735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1742829735
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1521161805
Short name T950
Test name
Test status
Simulation time 165044589406 ps
CPU time 401.58 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:47:37 PM PDT 24
Peak memory 250096 kb
Host smart-fde80b4a-b668-43d5-a9db-3752165b5b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521161805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1521161805
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3389433362
Short name T669
Test name
Test status
Simulation time 83843790209 ps
CPU time 201.28 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:44:33 PM PDT 24
Peak memory 253576 kb
Host smart-96590f59-9432-4412-bb64-68d4cfb1408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389433362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3389433362
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.754525966
Short name T407
Test name
Test status
Simulation time 2103860271 ps
CPU time 23.65 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 240016 kb
Host smart-317bbd7b-35a7-4435-852f-e7731308c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754525966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.754525966
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2206127209
Short name T463
Test name
Test status
Simulation time 71735626473 ps
CPU time 245.51 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:45:04 PM PDT 24
Peak memory 255244 kb
Host smart-8e11de10-bd41-437e-85f0-31003f3a95bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206127209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2206127209
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2947154142
Short name T982
Test name
Test status
Simulation time 12815519251 ps
CPU time 25.3 seconds
Started Jul 23 04:40:58 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 233636 kb
Host smart-a29f12fe-3d20-4e08-ae97-a7932bda4025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947154142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2947154142
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1315752126
Short name T203
Test name
Test status
Simulation time 16241352643 ps
CPU time 27.08 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:41:26 PM PDT 24
Peak memory 225436 kb
Host smart-715f00d6-18f0-45d8-a185-375ad32aded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315752126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1315752126
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1425393164
Short name T694
Test name
Test status
Simulation time 50615945 ps
CPU time 1.05 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:40:59 PM PDT 24
Peak memory 217324 kb
Host smart-c88db9ee-ac2e-4108-9fb3-f18c3b4777db
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425393164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1425393164
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.9142697
Short name T835
Test name
Test status
Simulation time 1765249655 ps
CPU time 8.18 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 241088 kb
Host smart-ede48f90-cbb8-47b0-828a-9dfef9a3503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9142697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.9142697
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1847819971
Short name T720
Test name
Test status
Simulation time 637313364 ps
CPU time 2.51 seconds
Started Jul 23 04:40:55 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 225292 kb
Host smart-39f71e1b-12b9-4a67-988c-90b07ad65060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847819971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1847819971
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4262345170
Short name T973
Test name
Test status
Simulation time 18085383678 ps
CPU time 149.44 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:43:40 PM PDT 24
Peak memory 233688 kb
Host smart-41051a73-c93b-498d-b2c9-8e1e92374ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262345170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4262345170
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3847511719
Short name T937
Test name
Test status
Simulation time 19948452 ps
CPU time 0.72 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 206344 kb
Host smart-fc53fa4e-533d-40f9-9370-5045e4bd118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847511719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3847511719
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2164057073
Short name T83
Test name
Test status
Simulation time 10355991918 ps
CPU time 7.55 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 217260 kb
Host smart-3aa1721a-e8bc-4b0c-8103-d572a8a60d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164057073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2164057073
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2937561100
Short name T551
Test name
Test status
Simulation time 73346612 ps
CPU time 1.35 seconds
Started Jul 23 04:41:01 PM PDT 24
Finished Jul 23 04:41:06 PM PDT 24
Peak memory 217028 kb
Host smart-ed671f8f-bdd1-4512-ad99-8fe9aa71c618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937561100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2937561100
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.4191975836
Short name T790
Test name
Test status
Simulation time 51150660 ps
CPU time 0.89 seconds
Started Jul 23 04:40:56 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 207764 kb
Host smart-2eff1060-024b-49d9-816f-b82443980956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191975836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.4191975836
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2770353119
Short name T152
Test name
Test status
Simulation time 17457438409 ps
CPU time 11.94 seconds
Started Jul 23 04:40:54 PM PDT 24
Finished Jul 23 04:41:07 PM PDT 24
Peak memory 240964 kb
Host smart-79d2be44-8296-4251-a331-a8d3fc8aca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770353119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2770353119
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2060241587
Short name T1007
Test name
Test status
Simulation time 32522594 ps
CPU time 0.73 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:41:08 PM PDT 24
Peak memory 206016 kb
Host smart-742ec844-2837-411e-a224-ea2ec6bb66ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060241587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2060241587
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.441097256
Short name T947
Test name
Test status
Simulation time 66764324 ps
CPU time 2.75 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:41:10 PM PDT 24
Peak memory 233580 kb
Host smart-6d43232d-c133-4a05-aea9-787ab86fbb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441097256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.441097256
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3566110779
Short name T430
Test name
Test status
Simulation time 47957216 ps
CPU time 0.72 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 206464 kb
Host smart-786991e4-e2e3-461a-ba7d-c7614db1c269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566110779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3566110779
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.860613883
Short name T209
Test name
Test status
Simulation time 4435764481 ps
CPU time 59.07 seconds
Started Jul 23 04:41:25 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 250228 kb
Host smart-6587edd1-e68c-467a-9744-55a038fea3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860613883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.860613883
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1287253758
Short name T621
Test name
Test status
Simulation time 20124517871 ps
CPU time 228.83 seconds
Started Jul 23 04:41:07 PM PDT 24
Finished Jul 23 04:44:57 PM PDT 24
Peak memory 257720 kb
Host smart-ea14be17-7b01-4003-8824-12af9027e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287253758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1287253758
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.4091292804
Short name T586
Test name
Test status
Simulation time 772398503 ps
CPU time 12.18 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 225384 kb
Host smart-77a9bb47-892d-487b-ab6f-3f99aed378fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091292804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.4091292804
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1964042597
Short name T399
Test name
Test status
Simulation time 21274669697 ps
CPU time 162.83 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:43:57 PM PDT 24
Peak memory 251616 kb
Host smart-2c5bc317-9b27-44f2-8412-a3e8dc28076b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964042597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1964042597
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4125824265
Short name T968
Test name
Test status
Simulation time 110843209 ps
CPU time 2.2 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 233176 kb
Host smart-47d0a66b-0be7-4e72-893a-6458e0aead6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125824265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4125824265
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3571872758
Short name T932
Test name
Test status
Simulation time 178179058 ps
CPU time 2.52 seconds
Started Jul 23 04:41:08 PM PDT 24
Finished Jul 23 04:41:11 PM PDT 24
Peak memory 225348 kb
Host smart-b75c825f-5573-4fa3-beb2-a87dccec89c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571872758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3571872758
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3649214713
Short name T914
Test name
Test status
Simulation time 27868632 ps
CPU time 1.12 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 217360 kb
Host smart-a491b8bd-2dc3-4087-aff3-cad22a68b358
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649214713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3649214713
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.490991122
Short name T71
Test name
Test status
Simulation time 5629965761 ps
CPU time 14.8 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 233588 kb
Host smart-83180dda-4265-4125-a8c1-c34ea3519ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490991122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.490991122
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2841030940
Short name T659
Test name
Test status
Simulation time 12018462377 ps
CPU time 15.8 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 233504 kb
Host smart-bb87b1f8-07ea-4446-9339-e2ea8f9a7166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841030940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2841030940
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.37357747
Short name T140
Test name
Test status
Simulation time 19264961616 ps
CPU time 13.87 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 222988 kb
Host smart-e5e8d228-1fc1-4d85-868a-fa9c7ea05f0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=37357747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.37357747
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1660221304
Short name T17
Test name
Test status
Simulation time 305953012 ps
CPU time 0.95 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 207364 kb
Host smart-f3160cbb-8e5d-4a23-9d77-8d4c31543445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660221304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1660221304
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.163846635
Short name T735
Test name
Test status
Simulation time 9615559801 ps
CPU time 17.49 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 217192 kb
Host smart-5c70658f-1f14-4da6-9e45-0ac4fe6fb59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163846635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.163846635
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1839398679
Short name T580
Test name
Test status
Simulation time 370548876 ps
CPU time 2.98 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:41:10 PM PDT 24
Peak memory 217004 kb
Host smart-8c5c1976-5f95-48fb-9103-7d06cc278c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839398679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1839398679
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3675222061
Short name T487
Test name
Test status
Simulation time 205852457 ps
CPU time 2.1 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:21 PM PDT 24
Peak memory 217172 kb
Host smart-98e3ae32-68ee-4bcd-b32e-34608ff5430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675222061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3675222061
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3990580884
Short name T339
Test name
Test status
Simulation time 47095137 ps
CPU time 0.89 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:41:15 PM PDT 24
Peak memory 207788 kb
Host smart-fbab3968-e0f2-4b63-9c12-b9d65ea1fdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990580884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3990580884
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.4114768630
Short name T514
Test name
Test status
Simulation time 2774833987 ps
CPU time 12.15 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 233536 kb
Host smart-c92c570a-5c76-4be7-8f29-fb9af44e4d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114768630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4114768630
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2932161508
Short name T518
Test name
Test status
Simulation time 54393365 ps
CPU time 0.75 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:18 PM PDT 24
Peak memory 206000 kb
Host smart-4db1f6e7-d8b8-49ae-8ddf-1c2b41cabcbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932161508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2932161508
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1229310177
Short name T863
Test name
Test status
Simulation time 9222474013 ps
CPU time 14.39 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 225412 kb
Host smart-8c404026-3dc3-475e-95ed-60c0d5848771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229310177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1229310177
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.422328673
Short name T566
Test name
Test status
Simulation time 23963648 ps
CPU time 0.79 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:17 PM PDT 24
Peak memory 207120 kb
Host smart-58edaccf-12b2-4da9-b70c-2543ecaaae00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422328673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.422328673
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3356037135
Short name T672
Test name
Test status
Simulation time 98493528654 ps
CPU time 153.6 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 250168 kb
Host smart-3b1abcb6-2b74-4457-a657-ccf41ef78074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356037135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3356037135
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.720844726
Short name T767
Test name
Test status
Simulation time 1037075999 ps
CPU time 9.11 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 238676 kb
Host smart-8709d033-7503-4bdf-8650-9d6e50118c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720844726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.720844726
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1924947794
Short name T293
Test name
Test status
Simulation time 9747479549 ps
CPU time 51.37 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 240644 kb
Host smart-59be7635-72e1-4b46-aafd-2ce52ec3c058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924947794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1924947794
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1015499279
Short name T311
Test name
Test status
Simulation time 13452470970 ps
CPU time 46.44 seconds
Started Jul 23 04:41:08 PM PDT 24
Finished Jul 23 04:41:56 PM PDT 24
Peak memory 225544 kb
Host smart-2d079d90-940f-446d-bcee-8f7f47df230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015499279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1015499279
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3956480354
Short name T676
Test name
Test status
Simulation time 21360691327 ps
CPU time 158.22 seconds
Started Jul 23 04:41:17 PM PDT 24
Finished Jul 23 04:43:57 PM PDT 24
Peak memory 259416 kb
Host smart-6170e97a-19be-47fb-8ee7-29c3aed6fe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956480354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3956480354
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2407270235
Short name T525
Test name
Test status
Simulation time 1026791001 ps
CPU time 7.92 seconds
Started Jul 23 04:41:05 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 225392 kb
Host smart-e026f3e5-4951-40bb-945f-0de859f88698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407270235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2407270235
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2618109065
Short name T662
Test name
Test status
Simulation time 9154406636 ps
CPU time 59.03 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:42:17 PM PDT 24
Peak memory 234560 kb
Host smart-296ee18b-cabe-4594-9096-1a79f23d217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618109065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2618109065
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2234475541
Short name T603
Test name
Test status
Simulation time 292684265 ps
CPU time 1.14 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 217328 kb
Host smart-f6be3179-df65-497f-8de2-967d98b3beb6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234475541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2234475541
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1254492151
Short name T101
Test name
Test status
Simulation time 1288157271 ps
CPU time 11.59 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 249596 kb
Host smart-6b28096f-c9f8-4586-96e3-4f6a40b23f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254492151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1254492151
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1141326730
Short name T58
Test name
Test status
Simulation time 8870750077 ps
CPU time 24.59 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 233592 kb
Host smart-98958c8c-fdff-432e-8329-89e852169bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141326730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1141326730
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1214686860
Short name T725
Test name
Test status
Simulation time 2239559553 ps
CPU time 12.38 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:30 PM PDT 24
Peak memory 222860 kb
Host smart-2bbb0266-289a-4641-9d1b-6cca3b58ceb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1214686860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1214686860
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2067402072
Short name T519
Test name
Test status
Simulation time 6699460768 ps
CPU time 9.12 seconds
Started Jul 23 04:41:24 PM PDT 24
Finished Jul 23 04:41:34 PM PDT 24
Peak memory 217192 kb
Host smart-d3ddf304-a707-4340-b4fa-11af5d1295a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067402072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2067402072
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2151831672
Short name T382
Test name
Test status
Simulation time 350529105 ps
CPU time 1.66 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 208688 kb
Host smart-1589525e-d6d8-4c86-a439-0644e25f8a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151831672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2151831672
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1602557390
Short name T342
Test name
Test status
Simulation time 36221743 ps
CPU time 1.08 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 208784 kb
Host smart-25b22178-a9f8-47f8-9e65-b532c99adcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602557390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1602557390
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3775449687
Short name T468
Test name
Test status
Simulation time 64183522 ps
CPU time 0.9 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:41:15 PM PDT 24
Peak memory 206748 kb
Host smart-09a297e4-4698-47c0-a126-dfdd8899f20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775449687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3775449687
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2149069965
Short name T457
Test name
Test status
Simulation time 8174585649 ps
CPU time 10.69 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 225388 kb
Host smart-d2be5226-2996-43f1-b443-eda270e655b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149069965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2149069965
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1646136536
Short name T506
Test name
Test status
Simulation time 32381979 ps
CPU time 0.72 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 205920 kb
Host smart-36c3bbc1-ee4c-40cc-b83c-0b97961d9b09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646136536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1646136536
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2045642869
Short name T414
Test name
Test status
Simulation time 1656197673 ps
CPU time 4.52 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 225364 kb
Host smart-0baac73c-5154-4479-97f8-b774e8f07067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045642869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2045642869
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.107383779
Short name T340
Test name
Test status
Simulation time 36712500 ps
CPU time 0.79 seconds
Started Jul 23 04:41:17 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 207136 kb
Host smart-4fb52592-ffe8-4e5b-8610-063a63823ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107383779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.107383779
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3833475518
Short name T205
Test name
Test status
Simulation time 152773314309 ps
CPU time 228.4 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:45:02 PM PDT 24
Peak memory 251636 kb
Host smart-5d6e24f9-f8f8-43d7-8b62-5ef789ea9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833475518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3833475518
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3692827379
Short name T227
Test name
Test status
Simulation time 12331025442 ps
CPU time 193 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:44:35 PM PDT 24
Peak memory 273612 kb
Host smart-be398711-cb51-4d13-9a51-0256d01cdd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692827379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3692827379
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2624787083
Short name T36
Test name
Test status
Simulation time 110702908 ps
CPU time 3.13 seconds
Started Jul 23 04:41:25 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 225308 kb
Host smart-e7d47a2e-7995-420d-94f5-5f66512a35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624787083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2624787083
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3457942121
Short name T875
Test name
Test status
Simulation time 62690336727 ps
CPU time 126.88 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 250060 kb
Host smart-f84dfac0-8cfb-43f0-a2b0-ee2eaa4e847c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457942121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3457942121
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3541278062
Short name T346
Test name
Test status
Simulation time 6015970506 ps
CPU time 30.87 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:41:43 PM PDT 24
Peak memory 225364 kb
Host smart-89f82a7e-4dcc-4238-9e7f-2c4e877ef213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541278062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3541278062
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1072497896
Short name T350
Test name
Test status
Simulation time 8129928225 ps
CPU time 24.81 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 239780 kb
Host smart-a6cbe700-966b-47d7-8fe1-128bfb0714e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072497896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1072497896
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3977370575
Short name T533
Test name
Test status
Simulation time 26992671 ps
CPU time 1.11 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 217248 kb
Host smart-1a3fc324-816c-44a8-8e9b-115a6ab9942d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977370575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3977370575
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1246170420
Short name T554
Test name
Test status
Simulation time 742332989 ps
CPU time 3.73 seconds
Started Jul 23 04:41:07 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 233488 kb
Host smart-042dcd9f-66d2-492e-a71d-482d8149413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246170420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1246170420
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1600822959
Short name T257
Test name
Test status
Simulation time 966173590 ps
CPU time 8.49 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:30 PM PDT 24
Peak memory 240988 kb
Host smart-8dcd27cf-51e2-4347-8dd5-f8a61a24c83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600822959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1600822959
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.114921207
Short name T476
Test name
Test status
Simulation time 157722943 ps
CPU time 3.39 seconds
Started Jul 23 04:41:23 PM PDT 24
Finished Jul 23 04:41:27 PM PDT 24
Peak memory 221260 kb
Host smart-332a4729-14ff-4ee6-bf2f-00b4172e3928
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=114921207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.114921207
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3801800044
Short name T782
Test name
Test status
Simulation time 179896645 ps
CPU time 1.04 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 207632 kb
Host smart-cf991eb1-d4b6-47c4-ae50-db459dc5d7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801800044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3801800044
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2532042318
Short name T941
Test name
Test status
Simulation time 8165973929 ps
CPU time 19.19 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 217132 kb
Host smart-2580bbf7-3f1e-4440-9678-8b18002abee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532042318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2532042318
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.116929833
Short name T501
Test name
Test status
Simulation time 1990759263 ps
CPU time 3.68 seconds
Started Jul 23 04:41:07 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 217200 kb
Host smart-8fc091f7-1c13-4f86-b578-d80eacce1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116929833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.116929833
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2469776118
Short name T953
Test name
Test status
Simulation time 53244524 ps
CPU time 0.83 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 206692 kb
Host smart-c514443f-7e57-4574-91e5-595e97bb21df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469776118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2469776118
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.773567853
Short name T259
Test name
Test status
Simulation time 1551069961 ps
CPU time 6.04 seconds
Started Jul 23 04:41:08 PM PDT 24
Finished Jul 23 04:41:15 PM PDT 24
Peak memory 225408 kb
Host smart-6244a500-1304-45b6-9090-e9c9fb80a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773567853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.773567853
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3703901778
Short name T972
Test name
Test status
Simulation time 17005386 ps
CPU time 0.74 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 205936 kb
Host smart-9211a6c4-6a77-4217-9382-ee10e5906098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703901778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3703901778
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3246555246
Short name T248
Test name
Test status
Simulation time 8564366665 ps
CPU time 16.6 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 225436 kb
Host smart-1c020214-29f1-4ce7-8e8c-26c686bf1a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246555246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3246555246
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2680521746
Short name T344
Test name
Test status
Simulation time 27315393 ps
CPU time 0.78 seconds
Started Jul 23 04:41:17 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 207088 kb
Host smart-9a1e75fb-7877-4ca9-b84d-6e4e8baab649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680521746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2680521746
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1788449652
Short name T683
Test name
Test status
Simulation time 2311747207 ps
CPU time 28.39 seconds
Started Jul 23 04:41:10 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 250016 kb
Host smart-4825f36b-1065-4467-85e6-ddbb4b6afbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788449652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1788449652
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1513613401
Short name T208
Test name
Test status
Simulation time 28960581646 ps
CPU time 227.05 seconds
Started Jul 23 04:41:06 PM PDT 24
Finished Jul 23 04:44:54 PM PDT 24
Peak memory 250184 kb
Host smart-44e86002-a465-4f36-90cd-8689417fcee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513613401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1513613401
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.272777931
Short name T1010
Test name
Test status
Simulation time 799644171 ps
CPU time 18.79 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 241812 kb
Host smart-4674ea04-648b-48d7-823b-93fd3431e489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272777931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.272777931
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2232540899
Short name T958
Test name
Test status
Simulation time 6352720159 ps
CPU time 6.71 seconds
Started Jul 23 04:41:07 PM PDT 24
Finished Jul 23 04:41:15 PM PDT 24
Peak memory 225540 kb
Host smart-8af7155d-623c-4453-ad6f-b13aa539226c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232540899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2232540899
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.131332422
Short name T211
Test name
Test status
Simulation time 47517328403 ps
CPU time 157.15 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:43:49 PM PDT 24
Peak memory 250016 kb
Host smart-f3c5985b-5f22-4c9b-8cb0-466582795b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131332422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.131332422
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2818090880
Short name T942
Test name
Test status
Simulation time 33670203075 ps
CPU time 30.06 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 233564 kb
Host smart-f3ad88ba-c8a5-4d50-8b1f-5f5a9e850084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818090880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2818090880
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1444423738
Short name T858
Test name
Test status
Simulation time 4325057663 ps
CPU time 31.2 seconds
Started Jul 23 04:41:08 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 219828 kb
Host smart-7394de2d-69a6-43a6-a0f8-73044a0d6945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444423738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1444423738
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1667359741
Short name T660
Test name
Test status
Simulation time 105562440 ps
CPU time 0.97 seconds
Started Jul 23 04:41:10 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 218500 kb
Host smart-155a89ca-3a6a-407b-80b5-f1f4b4999c8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667359741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1667359741
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.483036325
Short name T264
Test name
Test status
Simulation time 2795993681 ps
CPU time 6.88 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:23 PM PDT 24
Peak memory 236136 kb
Host smart-618fd57b-621f-40ea-97aa-9bce0c88ab9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483036325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.483036325
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.253788456
Short name T809
Test name
Test status
Simulation time 350510288 ps
CPU time 4.13 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:41:19 PM PDT 24
Peak memory 233640 kb
Host smart-7c624fd6-0ffa-433b-b475-826c0c332f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253788456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.253788456
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.797614170
Short name T103
Test name
Test status
Simulation time 545454779 ps
CPU time 6.26 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:27 PM PDT 24
Peak memory 219908 kb
Host smart-d9fbaae7-2134-4eaa-953a-d72b606d2bee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797614170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.797614170
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.828150719
Short name T1013
Test name
Test status
Simulation time 54907515256 ps
CPU time 125.19 seconds
Started Jul 23 04:41:11 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 257368 kb
Host smart-224481ee-eb06-455d-90db-5727e47779c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828150719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.828150719
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1963862013
Short name T319
Test name
Test status
Simulation time 1292740425 ps
CPU time 10.75 seconds
Started Jul 23 04:41:10 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 219860 kb
Host smart-6105a2cc-2458-469d-a096-f7f1b7eb6acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963862013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1963862013
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.629400189
Short name T392
Test name
Test status
Simulation time 772237670 ps
CPU time 5.65 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 217156 kb
Host smart-5181ecde-1666-42bf-b710-3ce814d7ecd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629400189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.629400189
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1605002256
Short name T765
Test name
Test status
Simulation time 95274471 ps
CPU time 3.15 seconds
Started Jul 23 04:41:17 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 217056 kb
Host smart-d7804b3a-a4d1-4ed1-9e62-59f888083788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605002256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1605002256
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2845981120
Short name T910
Test name
Test status
Simulation time 68305626 ps
CPU time 0.9 seconds
Started Jul 23 04:41:22 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 206688 kb
Host smart-60023970-1679-4846-805b-29112eee8c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845981120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2845981120
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.153766860
Short name T1019
Test name
Test status
Simulation time 1915134461 ps
CPU time 5.04 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 233512 kb
Host smart-6a775c30-5e5c-47a9-bd2a-8d78c68b9647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153766860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.153766860
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1978957118
Short name T60
Test name
Test status
Simulation time 28155124 ps
CPU time 0.72 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 206344 kb
Host smart-9645ad44-016c-49ee-bf43-b23e5473e6b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978957118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
978957118
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.887785926
Short name T687
Test name
Test status
Simulation time 703305277 ps
CPU time 6.32 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 233492 kb
Host smart-2f148d51-2510-4abc-89c9-9a3ce695f15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887785926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.887785926
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3223679980
Short name T335
Test name
Test status
Simulation time 49006616 ps
CPU time 0.76 seconds
Started Jul 23 04:40:18 PM PDT 24
Finished Jul 23 04:40:22 PM PDT 24
Peak memory 207192 kb
Host smart-2f1788f4-6644-4fac-af52-d505f8dc031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223679980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3223679980
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.75993208
Short name T376
Test name
Test status
Simulation time 7196979078 ps
CPU time 90.39 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 257744 kb
Host smart-f7ca5419-67cd-424b-9fb4-2e0d27cdda58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75993208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.75993208
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.750521164
Short name T400
Test name
Test status
Simulation time 11819453476 ps
CPU time 114.26 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:42:18 PM PDT 24
Peak memory 241492 kb
Host smart-42f87a94-4c43-4fd6-8dcd-dd172a1e5d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750521164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
750521164
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2811212315
Short name T1008
Test name
Test status
Simulation time 1544659015 ps
CPU time 7.98 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 233540 kb
Host smart-12a2fd96-b50e-4de9-9d9d-e8e4c9bf0a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811212315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2811212315
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3648994152
Short name T86
Test name
Test status
Simulation time 9613385791 ps
CPU time 68.18 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 254384 kb
Host smart-ad65200c-980c-4910-8ad4-474af9827cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648994152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3648994152
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.812981943
Short name T34
Test name
Test status
Simulation time 12992820711 ps
CPU time 26.68 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 233668 kb
Host smart-d8d63e57-dd1e-487f-8a5b-91cec2e92b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812981943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.812981943
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1143076717
Short name T983
Test name
Test status
Simulation time 1481073028 ps
CPU time 8.53 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 233516 kb
Host smart-f35d0c8b-33fa-4d00-96b0-15eae68be49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143076717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1143076717
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1789717460
Short name T557
Test name
Test status
Simulation time 15934977 ps
CPU time 1.1 seconds
Started Jul 23 04:40:20 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 217328 kb
Host smart-8588ab42-9876-4555-a3e7-7a6294079a90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789717460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1789717460
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2027840688
Short name T825
Test name
Test status
Simulation time 136096212 ps
CPU time 3.38 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:40:19 PM PDT 24
Peak memory 233648 kb
Host smart-d45cbab2-1271-4f14-bbc5-584daa802e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027840688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2027840688
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2368531634
Short name T590
Test name
Test status
Simulation time 413583789 ps
CPU time 2.57 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 04:40:24 PM PDT 24
Peak memory 233164 kb
Host smart-2a3403b5-33b8-498a-9092-101a380735be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368531634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2368531634
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3223588077
Short name T723
Test name
Test status
Simulation time 178000305 ps
CPU time 4.87 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 223208 kb
Host smart-38879b5a-2e5e-48f9-bbfe-d01a8d4f1707
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3223588077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3223588077
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2896737888
Short name T66
Test name
Test status
Simulation time 246068554 ps
CPU time 1.07 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 235824 kb
Host smart-1830d90a-a083-4627-8313-580bf8f7f37d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896737888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2896737888
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.975515219
Short name T27
Test name
Test status
Simulation time 39588059209 ps
CPU time 260.72 seconds
Started Jul 23 04:40:11 PM PDT 24
Finished Jul 23 04:44:35 PM PDT 24
Peak memory 264580 kb
Host smart-798d05f2-e403-4014-8ed1-e0182ea18153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975515219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.975515219
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2823498615
Short name T349
Test name
Test status
Simulation time 19123819 ps
CPU time 0.75 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 04:40:23 PM PDT 24
Peak memory 206340 kb
Host smart-ab1f6549-bbd5-4201-975a-3215cb4dc79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823498615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2823498615
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2143729089
Short name T354
Test name
Test status
Simulation time 8715523069 ps
CPU time 6.19 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:27 PM PDT 24
Peak memory 217168 kb
Host smart-637a0d47-8877-4510-84b8-7789f920eca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143729089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2143729089
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1019148210
Short name T986
Test name
Test status
Simulation time 289474792 ps
CPU time 1.64 seconds
Started Jul 23 04:40:12 PM PDT 24
Finished Jul 23 04:40:18 PM PDT 24
Peak memory 209068 kb
Host smart-1148afbf-cd01-4cd6-b61a-40f45a1bd7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019148210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1019148210
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.139560677
Short name T402
Test name
Test status
Simulation time 46718890 ps
CPU time 0.69 seconds
Started Jul 23 04:40:13 PM PDT 24
Finished Jul 23 04:40:19 PM PDT 24
Peak memory 206684 kb
Host smart-5e5f0c9e-6620-4110-9a8e-dc335e0a335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139560677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.139560677
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.928709338
Short name T446
Test name
Test status
Simulation time 3063347973 ps
CPU time 9.63 seconds
Started Jul 23 04:40:19 PM PDT 24
Finished Jul 23 04:40:32 PM PDT 24
Peak memory 225396 kb
Host smart-a0bb88dc-4e9a-45ad-b703-81580b1c1efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928709338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.928709338
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1418074772
Short name T630
Test name
Test status
Simulation time 44179445 ps
CPU time 0.77 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:17 PM PDT 24
Peak memory 205396 kb
Host smart-40f60228-3462-4f2f-95d8-8725b6abc94a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418074772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1418074772
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3160565083
Short name T930
Test name
Test status
Simulation time 1722923944 ps
CPU time 11.81 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 225272 kb
Host smart-18997886-7db2-4677-8bf7-be41efd1a66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160565083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3160565083
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2383663728
Short name T558
Test name
Test status
Simulation time 17183718 ps
CPU time 0.78 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 206224 kb
Host smart-4c792d58-0d7e-4b93-a786-b87815555dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383663728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2383663728
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.636940368
Short name T496
Test name
Test status
Simulation time 102143306167 ps
CPU time 173.81 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:44:08 PM PDT 24
Peak memory 252196 kb
Host smart-b54371bc-b581-4e35-a68a-5661566c5450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636940368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.636940368
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2599831266
Short name T154
Test name
Test status
Simulation time 3737308677 ps
CPU time 61.76 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 250004 kb
Host smart-a1fb167e-0bcc-4379-ba99-cbb370d7200f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599831266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2599831266
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1780093762
Short name T169
Test name
Test status
Simulation time 16370969558 ps
CPU time 84.74 seconds
Started Jul 23 04:41:07 PM PDT 24
Finished Jul 23 04:42:33 PM PDT 24
Peak memory 257772 kb
Host smart-483ae35a-9c25-40f5-b383-3adfdc361335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780093762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1780093762
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.57996769
Short name T836
Test name
Test status
Simulation time 171384467 ps
CPU time 7.72 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:23 PM PDT 24
Peak memory 250044 kb
Host smart-2aafd09c-1009-4ebc-a80b-4ea68274e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57996769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.57996769
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3715517746
Short name T870
Test name
Test status
Simulation time 702950143 ps
CPU time 4.33 seconds
Started Jul 23 04:41:08 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 225524 kb
Host smart-3df3ffa0-7869-4a51-8c44-818140a09fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715517746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3715517746
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2246254966
Short name T747
Test name
Test status
Simulation time 26243795351 ps
CPU time 69.05 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:42:28 PM PDT 24
Peak memory 241780 kb
Host smart-bffbe1fd-2c8a-43a8-bd97-a9e5896a43c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246254966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2246254966
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1329490156
Short name T42
Test name
Test status
Simulation time 74280338066 ps
CPU time 17.37 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 225344 kb
Host smart-4dc67228-b6c5-422a-bbf9-499b870cac82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329490156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1329490156
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.572448564
Short name T11
Test name
Test status
Simulation time 24018747362 ps
CPU time 17.82 seconds
Started Jul 23 04:41:09 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 225576 kb
Host smart-6c5913e4-c1c1-40c0-b360-e8193e94315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572448564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.572448564
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3381022174
Short name T823
Test name
Test status
Simulation time 1973920207 ps
CPU time 26.64 seconds
Started Jul 23 04:41:12 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 220796 kb
Host smart-8a3506da-3266-4eec-8028-1670cdc436a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3381022174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3381022174
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.484756777
Short name T302
Test name
Test status
Simulation time 24024744455 ps
CPU time 72.46 seconds
Started Jul 23 04:41:16 PM PDT 24
Finished Jul 23 04:42:31 PM PDT 24
Peak memory 256100 kb
Host smart-cdbd73bf-1943-4ca3-87e1-14365fb26d93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484756777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.484756777
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2902043815
Short name T779
Test name
Test status
Simulation time 4482645986 ps
CPU time 23.25 seconds
Started Jul 23 04:41:13 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 217192 kb
Host smart-bbbdacc0-be26-41cd-8de6-af41a8dcd145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902043815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2902043815
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.758936703
Short name T1016
Test name
Test status
Simulation time 2599730850 ps
CPU time 8.09 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 217124 kb
Host smart-06d6ff00-5e37-4135-a79d-ad31e514f30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758936703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.758936703
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2323295620
Short name T744
Test name
Test status
Simulation time 863059360 ps
CPU time 2.69 seconds
Started Jul 23 04:41:10 PM PDT 24
Finished Jul 23 04:41:13 PM PDT 24
Peak memory 217096 kb
Host smart-ca1c77e2-b637-448d-bf14-86fb203cb4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323295620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2323295620
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.104563558
Short name T421
Test name
Test status
Simulation time 18927553 ps
CPU time 0.71 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:20 PM PDT 24
Peak memory 206732 kb
Host smart-03df885a-17f2-44da-aa25-0834b8c5b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104563558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.104563558
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1327712304
Short name T229
Test name
Test status
Simulation time 900332670 ps
CPU time 8.45 seconds
Started Jul 23 04:41:23 PM PDT 24
Finished Jul 23 04:41:33 PM PDT 24
Peak memory 240688 kb
Host smart-97e89fe0-1ff8-45b8-ae5a-878748eed3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327712304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1327712304
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1114307803
Short name T61
Test name
Test status
Simulation time 32712687 ps
CPU time 0.73 seconds
Started Jul 23 04:41:25 PM PDT 24
Finished Jul 23 04:41:27 PM PDT 24
Peak memory 205888 kb
Host smart-77f17389-f5a7-4ea9-97db-355f1e41c9d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114307803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1114307803
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.907998200
Short name T865
Test name
Test status
Simulation time 1615332625 ps
CPU time 20.6 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 225344 kb
Host smart-a23da8b2-16da-4a02-a4ae-929cc443fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907998200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.907998200
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1248176546
Short name T485
Test name
Test status
Simulation time 28267599 ps
CPU time 0.82 seconds
Started Jul 23 04:41:14 PM PDT 24
Finished Jul 23 04:41:17 PM PDT 24
Peak memory 206156 kb
Host smart-aa6f22db-a41b-4e92-8f5f-80e42bf7a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248176546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1248176546
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1920263990
Short name T5
Test name
Test status
Simulation time 9492322246 ps
CPU time 57.91 seconds
Started Jul 23 04:41:22 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 250068 kb
Host smart-b61cf1f5-0f09-484a-8e71-181dc99b8416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920263990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1920263990
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1767214534
Short name T548
Test name
Test status
Simulation time 10467540740 ps
CPU time 55.23 seconds
Started Jul 23 04:41:23 PM PDT 24
Finished Jul 23 04:42:20 PM PDT 24
Peak memory 252784 kb
Host smart-7cd45575-4adf-4ceb-90d0-2b88c413d70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767214534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1767214534
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3343731629
Short name T157
Test name
Test status
Simulation time 139854089653 ps
CPU time 227.36 seconds
Started Jul 23 04:41:24 PM PDT 24
Finished Jul 23 04:45:12 PM PDT 24
Peak memory 265824 kb
Host smart-2c0da1e9-0a00-49df-955a-bae0bbc6f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343731629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3343731629
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.4278532841
Short name T524
Test name
Test status
Simulation time 237360097 ps
CPU time 9.23 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 252292 kb
Host smart-15910d27-01a3-4d15-b5b4-49dff75fd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278532841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.4278532841
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3046007860
Short name T572
Test name
Test status
Simulation time 40641484864 ps
CPU time 267.73 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:45:59 PM PDT 24
Peak memory 258128 kb
Host smart-b5291400-a8f3-4429-9c70-ab5eb00681d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046007860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3046007860
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.706995405
Short name T602
Test name
Test status
Simulation time 46365417 ps
CPU time 2.48 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:24 PM PDT 24
Peak memory 225376 kb
Host smart-d449d5e8-9268-4680-a6a5-ecee14c9a145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706995405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.706995405
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2181936663
Short name T802
Test name
Test status
Simulation time 294173266 ps
CPU time 2.34 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 233176 kb
Host smart-db880329-46b4-43d7-a091-ecac35dd8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181936663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2181936663
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2988737029
Short name T43
Test name
Test status
Simulation time 1309153908 ps
CPU time 8.22 seconds
Started Jul 23 04:41:27 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 233516 kb
Host smart-64d6c28e-7244-44eb-9b0f-c2efe2c3bdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988737029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2988737029
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3419065223
Short name T634
Test name
Test status
Simulation time 288080832 ps
CPU time 4.99 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 233484 kb
Host smart-0dd67b26-224c-49bf-8972-1ab41c399e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419065223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3419065223
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2467750532
Short name T709
Test name
Test status
Simulation time 919941847 ps
CPU time 10.72 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 221644 kb
Host smart-3b7662ce-15fd-474c-892c-1350b873b752
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2467750532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2467750532
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1632521865
Short name T149
Test name
Test status
Simulation time 121992903 ps
CPU time 1.1 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 207808 kb
Host smart-b4eb66b8-25f6-4e0b-b7b8-2d9496ba3b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632521865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1632521865
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1911486369
Short name T940
Test name
Test status
Simulation time 3206195259 ps
CPU time 16.38 seconds
Started Jul 23 04:41:15 PM PDT 24
Finished Jul 23 04:41:33 PM PDT 24
Peak memory 217188 kb
Host smart-5c273923-d697-4d2e-b4ac-db46cd10badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911486369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1911486369
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3037990792
Short name T674
Test name
Test status
Simulation time 31462853036 ps
CPU time 15.88 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 217176 kb
Host smart-a326ffdc-4030-466c-b94c-90cedfdf0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037990792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3037990792
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1879276785
Short name T455
Test name
Test status
Simulation time 13735834 ps
CPU time 0.7 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:22 PM PDT 24
Peak memory 206464 kb
Host smart-546e52ef-ed70-40bb-8433-366f018add97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879276785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1879276785
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.507962505
Short name T754
Test name
Test status
Simulation time 98638726 ps
CPU time 0.98 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 207636 kb
Host smart-bc30f816-988d-4f19-bd1d-af1755bec73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507962505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.507962505
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4228579809
Short name T415
Test name
Test status
Simulation time 13808752199 ps
CPU time 17.81 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 233676 kb
Host smart-23747b02-63bb-4067-977c-04434c7aad49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228579809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4228579809
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2661533764
Short name T642
Test name
Test status
Simulation time 61339417 ps
CPU time 0.72 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 205396 kb
Host smart-9825a9af-e559-4a7f-b9e4-dca94f3ca025
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661533764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2661533764
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.456308722
Short name T246
Test name
Test status
Simulation time 1356473537 ps
CPU time 4.33 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:34 PM PDT 24
Peak memory 225328 kb
Host smart-7c920b63-e544-4238-8591-a8a1d7151fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456308722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.456308722
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2155077073
Short name T459
Test name
Test status
Simulation time 80838784 ps
CPU time 0.76 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 206136 kb
Host smart-84eb395e-8727-4058-b0a2-f763888e93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155077073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2155077073
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1750105928
Short name T631
Test name
Test status
Simulation time 7860298365 ps
CPU time 15.82 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:53 PM PDT 24
Peak memory 225416 kb
Host smart-5a032f61-e08f-4b42-a7e5-7704dca925ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750105928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1750105928
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1886669539
Short name T787
Test name
Test status
Simulation time 6449571965 ps
CPU time 55.24 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:42:17 PM PDT 24
Peak memory 250096 kb
Host smart-b4619f5f-fd25-46f4-8378-f9bee63f660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886669539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1886669539
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2859740355
Short name T1022
Test name
Test status
Simulation time 12633101932 ps
CPU time 29.91 seconds
Started Jul 23 04:41:24 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 225480 kb
Host smart-64b5b66d-5fdf-4020-b4dd-295bd96614ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859740355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2859740355
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2019674524
Short name T655
Test name
Test status
Simulation time 593704381 ps
CPU time 6.62 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 233604 kb
Host smart-fefa68d4-b6a1-481c-b54e-9c3cc40e0c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019674524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2019674524
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.41499834
Short name T1002
Test name
Test status
Simulation time 3194841345 ps
CPU time 40.48 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:42:02 PM PDT 24
Peak memory 241840 kb
Host smart-88f755ab-9be3-41b3-b7ae-2f749e5ea7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41499834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.41499834
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3641350595
Short name T237
Test name
Test status
Simulation time 4729060294 ps
CPU time 12.14 seconds
Started Jul 23 04:41:18 PM PDT 24
Finished Jul 23 04:41:32 PM PDT 24
Peak memory 233628 kb
Host smart-e7a26bb9-a9ef-4e16-9945-98d1dd3ba3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641350595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3641350595
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.309061584
Short name T763
Test name
Test status
Simulation time 27968472435 ps
CPU time 118.11 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 249948 kb
Host smart-803084fc-fd7b-4dbd-ac56-90f718ebde86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309061584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.309061584
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4007654814
Short name T291
Test name
Test status
Simulation time 11088915043 ps
CPU time 13.79 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 225416 kb
Host smart-b310603f-8371-4a51-9666-1a546655bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007654814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4007654814
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1124253535
Short name T483
Test name
Test status
Simulation time 52190909226 ps
CPU time 18.38 seconds
Started Jul 23 04:41:21 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 233700 kb
Host smart-217d28a2-4c25-491d-a43a-7bc7463fb7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124253535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1124253535
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1735853512
Short name T377
Test name
Test status
Simulation time 1308283879 ps
CPU time 15.19 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 223120 kb
Host smart-1760b07b-bd69-4086-8899-4cf3266ddb6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1735853512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1735853512
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2425251429
Short name T277
Test name
Test status
Simulation time 422124872050 ps
CPU time 1008.41 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:58:27 PM PDT 24
Peak memory 299240 kb
Host smart-56f37d7e-d2e1-48bd-ab86-047ae87c98e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425251429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2425251429
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4082018275
Short name T419
Test name
Test status
Simulation time 14207361766 ps
CPU time 12.21 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 217320 kb
Host smart-2b455c20-eba3-42a1-8e21-265bcd899f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082018275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4082018275
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3387927454
Short name T891
Test name
Test status
Simulation time 4407369847 ps
CPU time 4.97 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 217180 kb
Host smart-ab471da3-919a-43bb-8a57-0015e2163218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387927454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3387927454
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3694713652
Short name T386
Test name
Test status
Simulation time 182916073 ps
CPU time 1.29 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 208896 kb
Host smart-72a742dd-1152-4be7-89bb-5132e711523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694713652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3694713652
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2249464428
Short name T423
Test name
Test status
Simulation time 236006089 ps
CPU time 0.81 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 206612 kb
Host smart-c4f4f020-31b4-4a08-a96f-2871b42059bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249464428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2249464428
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.254022384
Short name T473
Test name
Test status
Simulation time 687789140 ps
CPU time 7.78 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:46 PM PDT 24
Peak memory 225412 kb
Host smart-512d715a-a276-444d-a626-8c6aefdad9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254022384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.254022384
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3825256492
Short name T995
Test name
Test status
Simulation time 40106529 ps
CPU time 0.68 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 206052 kb
Host smart-1594b3e9-fd51-455a-80b6-a8a8d40562cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825256492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3825256492
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2130902030
Short name T379
Test name
Test status
Simulation time 956219772 ps
CPU time 9.98 seconds
Started Jul 23 04:41:22 PM PDT 24
Finished Jul 23 04:41:33 PM PDT 24
Peak memory 233628 kb
Host smart-3f64c81d-e679-4d00-a8f6-45ac135c313d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130902030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2130902030
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3711695410
Short name T857
Test name
Test status
Simulation time 76263977 ps
CPU time 0.73 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 205992 kb
Host smart-a5704f6e-7871-47ab-a1f5-d5c9893f6bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711695410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3711695410
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.828955201
Short name T874
Test name
Test status
Simulation time 9963627673 ps
CPU time 48 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 241852 kb
Host smart-1ef9da3b-b73e-4e05-991d-2a867685ccb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828955201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.828955201
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1896405905
Short name T488
Test name
Test status
Simulation time 37329452373 ps
CPU time 324.57 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:46:55 PM PDT 24
Peak memory 266360 kb
Host smart-790a5a74-aa54-4f15-909b-a4da1028b19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896405905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1896405905
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2835897974
Short name T194
Test name
Test status
Simulation time 78907726083 ps
CPU time 157.56 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:44:16 PM PDT 24
Peak memory 274344 kb
Host smart-edae9db8-61c1-4537-8d42-2512151bf199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835897974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2835897974
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3127223412
Short name T305
Test name
Test status
Simulation time 4215087211 ps
CPU time 38.94 seconds
Started Jul 23 04:41:19 PM PDT 24
Finished Jul 23 04:42:00 PM PDT 24
Peak memory 240580 kb
Host smart-7a5c79ab-2ce9-4f44-b975-7c53a01b7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127223412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3127223412
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1985221726
Short name T680
Test name
Test status
Simulation time 464304787 ps
CPU time 3.41 seconds
Started Jul 23 04:41:20 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 228816 kb
Host smart-4664f90d-e6cb-4e72-94f9-b68ddc0ea9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985221726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1985221726
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2317286885
Short name T523
Test name
Test status
Simulation time 323314474 ps
CPU time 3.29 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:30 PM PDT 24
Peak memory 225312 kb
Host smart-1f0801a1-8a20-47f0-960c-5dcd0a140c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317286885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2317286885
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1542575203
Short name T262
Test name
Test status
Simulation time 1235163485 ps
CPU time 4.96 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 225268 kb
Host smart-2e69f4e9-b746-40a0-92d1-e2c032891176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542575203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1542575203
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.983506824
Short name T532
Test name
Test status
Simulation time 8122585790 ps
CPU time 8.34 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 233604 kb
Host smart-71f36683-3021-4ada-9b32-75892dcb3772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983506824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.983506824
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3749071924
Short name T716
Test name
Test status
Simulation time 96997076 ps
CPU time 4.14 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 223672 kb
Host smart-59ee12f1-8113-4244-b042-3c13a0c2e45a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3749071924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3749071924
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4178033749
Short name T699
Test name
Test status
Simulation time 59115624004 ps
CPU time 513.45 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:50:12 PM PDT 24
Peak memory 266924 kb
Host smart-facc3047-d9c3-4d07-8c45-fbbb9f692d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178033749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4178033749
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3890029411
Short name T685
Test name
Test status
Simulation time 929048987 ps
CPU time 7.88 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 217116 kb
Host smart-2a22577a-f45f-47cb-8382-61eeb8f50479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890029411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3890029411
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.893378842
Short name T888
Test name
Test status
Simulation time 2278285705 ps
CPU time 2.97 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 217120 kb
Host smart-20db594a-d16e-4980-ba3e-ff79e43e42f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893378842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.893378842
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2810056987
Short name T378
Test name
Test status
Simulation time 494899299 ps
CPU time 1.89 seconds
Started Jul 23 04:41:24 PM PDT 24
Finished Jul 23 04:41:26 PM PDT 24
Peak memory 217116 kb
Host smart-abae7ad9-28f0-4198-9938-71213d59922c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810056987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2810056987
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3494703756
Short name T583
Test name
Test status
Simulation time 100988850 ps
CPU time 0.98 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 207700 kb
Host smart-b930f058-3311-45cd-ba9b-e07632bc8cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494703756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3494703756
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.14122644
Short name T651
Test name
Test status
Simulation time 737996457 ps
CPU time 3.79 seconds
Started Jul 23 04:41:22 PM PDT 24
Finished Jul 23 04:41:27 PM PDT 24
Peak memory 225296 kb
Host smart-1d08d668-ba9d-46e7-aad4-caa51cd52b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14122644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.14122644
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4159184236
Short name T755
Test name
Test status
Simulation time 40508525 ps
CPU time 0.7 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 205928 kb
Host smart-73817ac3-5a46-41d5-806d-0c9f90a26823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159184236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4159184236
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3111475443
Short name T820
Test name
Test status
Simulation time 27859023671 ps
CPU time 21.61 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:54 PM PDT 24
Peak memory 225444 kb
Host smart-33c767c8-4739-428e-b855-10f1c39110de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111475443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3111475443
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.697607587
Short name T976
Test name
Test status
Simulation time 26269137 ps
CPU time 0.81 seconds
Started Jul 23 04:41:23 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 207128 kb
Host smart-f3a9d73f-597b-4fdd-ab0e-63c068104d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697607587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.697607587
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1577695833
Short name T210
Test name
Test status
Simulation time 5460104933 ps
CPU time 81.21 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:42:59 PM PDT 24
Peak memory 253436 kb
Host smart-f0f2bbc3-6e64-4f64-8a98-d5674cae613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577695833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1577695833
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1263237463
Short name T130
Test name
Test status
Simulation time 8888334489 ps
CPU time 104.53 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 252372 kb
Host smart-2139dcfb-2a9d-4b32-bdc0-860774dc9600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263237463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1263237463
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.291414970
Short name T733
Test name
Test status
Simulation time 3378510358 ps
CPU time 5.26 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 236276 kb
Host smart-c23995e8-4a81-43af-bbcc-cea491c00493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291414970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.291414970
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2676796723
Short name T89
Test name
Test status
Simulation time 4270137684 ps
CPU time 54.54 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:42:33 PM PDT 24
Peak memory 257556 kb
Host smart-e14c0479-85ee-4461-8bac-62e60ae19344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676796723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2676796723
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3453192590
Short name T45
Test name
Test status
Simulation time 443772686 ps
CPU time 2.49 seconds
Started Jul 23 04:41:26 PM PDT 24
Finished Jul 23 04:41:30 PM PDT 24
Peak memory 225184 kb
Host smart-6f982f30-d907-493f-bde2-ec42536bf348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453192590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3453192590
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2875393732
Short name T788
Test name
Test status
Simulation time 1218793373 ps
CPU time 7.84 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 225332 kb
Host smart-97b54e5e-6696-4ef6-a3ff-c06dd08310d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875393732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2875393732
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1990749046
Short name T781
Test name
Test status
Simulation time 230752284 ps
CPU time 3.88 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 225348 kb
Host smart-b983621f-5714-4643-b50a-a893f2d230ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990749046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1990749046
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.523083921
Short name T764
Test name
Test status
Simulation time 6032380129 ps
CPU time 7.94 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:47 PM PDT 24
Peak memory 233576 kb
Host smart-fe9fbce3-e0a0-427b-8393-94c38365df13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523083921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.523083921
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3260863304
Short name T943
Test name
Test status
Simulation time 1122366047 ps
CPU time 7.19 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:46 PM PDT 24
Peak memory 220156 kb
Host smart-c3798b09-ff9e-4189-89a7-b71df9926551
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260863304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3260863304
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.432988826
Short name T25
Test name
Test status
Simulation time 29464758488 ps
CPU time 162.12 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:44:15 PM PDT 24
Peak memory 266564 kb
Host smart-68076f06-87eb-4abb-a1dc-a2e9e00df0d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432988826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.432988826
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.292442220
Short name T740
Test name
Test status
Simulation time 12165190886 ps
CPU time 23.72 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:59 PM PDT 24
Peak memory 217280 kb
Host smart-4bdb00b0-12a4-431f-8bfe-956845d28922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292442220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.292442220
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2209007980
Short name T389
Test name
Test status
Simulation time 14991453629 ps
CPU time 9.71 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:47 PM PDT 24
Peak memory 217188 kb
Host smart-3250594b-3b4d-40ac-93b8-65b7c63816f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209007980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2209007980
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1154803474
Short name T650
Test name
Test status
Simulation time 40624308 ps
CPU time 0.87 seconds
Started Jul 23 04:41:27 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 207240 kb
Host smart-83b17a1e-c4f2-4635-b974-d00cfa8b13b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154803474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1154803474
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1986953634
Short name T598
Test name
Test status
Simulation time 53966330 ps
CPU time 0.72 seconds
Started Jul 23 04:41:24 PM PDT 24
Finished Jul 23 04:41:25 PM PDT 24
Peak memory 206652 kb
Host smart-0df8a3f9-607b-4da1-b9df-a96903321672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986953634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1986953634
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2617438669
Short name T249
Test name
Test status
Simulation time 483812354 ps
CPU time 2.16 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 225256 kb
Host smart-a4720a45-4cb3-4f46-bffa-ce890d618ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617438669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2617438669
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4240589729
Short name T504
Test name
Test status
Simulation time 170447079 ps
CPU time 0.72 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 205660 kb
Host smart-3cc52830-e240-47e5-bd93-17909cb003f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240589729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4240589729
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3291461790
Short name T231
Test name
Test status
Simulation time 669460313 ps
CPU time 4.33 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 233540 kb
Host smart-004a2303-7b80-432e-8acb-6e3b6b8810c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291461790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3291461790
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3363238493
Short name T959
Test name
Test status
Simulation time 262231916 ps
CPU time 0.77 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 207228 kb
Host smart-ac284655-a4fe-41f3-b624-d3f91fb76878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363238493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3363238493
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1262043803
Short name T938
Test name
Test status
Simulation time 2185845684 ps
CPU time 28.39 seconds
Started Jul 23 04:41:42 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 237744 kb
Host smart-335d5ee2-b416-44bd-8e04-e584fbefdb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262043803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1262043803
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1919795302
Short name T490
Test name
Test status
Simulation time 5277500805 ps
CPU time 20.64 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 218544 kb
Host smart-4de9edde-e921-48b8-8b40-e462a04289e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919795302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1919795302
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.411674049
Short name T416
Test name
Test status
Simulation time 5321935167 ps
CPU time 56.06 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:42:31 PM PDT 24
Peak memory 241944 kb
Host smart-b139922e-1149-440d-938a-35f1de08e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411674049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.411674049
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4151194892
Short name T931
Test name
Test status
Simulation time 211520428 ps
CPU time 4.55 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 233576 kb
Host smart-c73f8d0a-406e-49a5-998c-c794708434b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151194892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4151194892
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3938639012
Short name T895
Test name
Test status
Simulation time 58728404870 ps
CPU time 115 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 252132 kb
Host smart-5808b3cc-3c3d-4522-848b-8a9e6ad89c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938639012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3938639012
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.8989417
Short name T578
Test name
Test status
Simulation time 300107905 ps
CPU time 3.45 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 225372 kb
Host smart-9168762d-2183-4483-bb30-445eeb782e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8989417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.8989417
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2166932429
Short name T855
Test name
Test status
Simulation time 10748646445 ps
CPU time 29.65 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:42:01 PM PDT 24
Peak memory 241144 kb
Host smart-1cc9c6b9-3982-4b77-80c4-557777b700f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166932429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2166932429
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2158102514
Short name T877
Test name
Test status
Simulation time 4410312393 ps
CPU time 8.4 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:44 PM PDT 24
Peak memory 241372 kb
Host smart-655d64c0-2693-4a22-8a08-942cb0c7cdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158102514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2158102514
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1202837439
Short name T796
Test name
Test status
Simulation time 16792185338 ps
CPU time 14.07 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:48 PM PDT 24
Peak memory 225404 kb
Host smart-2efc928a-0170-40b1-b678-e06212667eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202837439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1202837439
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3096747310
Short name T76
Test name
Test status
Simulation time 4094769645 ps
CPU time 12.74 seconds
Started Jul 23 04:41:42 PM PDT 24
Finished Jul 23 04:41:56 PM PDT 24
Peak memory 223796 kb
Host smart-2cda3d51-b73c-4456-beae-48526d123237
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3096747310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3096747310
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3843390735
Short name T150
Test name
Test status
Simulation time 27760530340 ps
CPU time 120.43 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 258200 kb
Host smart-b9dc9f05-9b0e-427a-bd69-826ac3ce90dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843390735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3843390735
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3545933666
Short name T944
Test name
Test status
Simulation time 282499871 ps
CPU time 2.72 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:34 PM PDT 24
Peak memory 217056 kb
Host smart-063d630c-6965-4f04-9bb8-62db4da79a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545933666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3545933666
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3543689723
Short name T363
Test name
Test status
Simulation time 969475023 ps
CPU time 4.62 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 217132 kb
Host smart-b5f4e3fd-956e-4cc0-9f31-e1379659e4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543689723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3543689723
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2033978374
Short name T481
Test name
Test status
Simulation time 261016939 ps
CPU time 1.61 seconds
Started Jul 23 04:41:42 PM PDT 24
Finished Jul 23 04:41:45 PM PDT 24
Peak memory 208744 kb
Host smart-6c7f42e1-273f-4a6c-ae2f-4760a3ce86b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033978374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2033978374
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3415196267
Short name T618
Test name
Test status
Simulation time 183885448 ps
CPU time 0.94 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 206668 kb
Host smart-0f8366d2-9962-4075-9519-24d24c39a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415196267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3415196267
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3797506267
Short name T589
Test name
Test status
Simulation time 11306307041 ps
CPU time 10.51 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:45 PM PDT 24
Peak memory 233608 kb
Host smart-92687fb5-ec48-471b-9ef3-e0706a7a374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797506267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3797506267
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3283283281
Short name T343
Test name
Test status
Simulation time 15977522 ps
CPU time 0.74 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 206356 kb
Host smart-1473e89a-ac22-42d1-bbe6-15bc7bd13b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283283281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3283283281
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3413791342
Short name T232
Test name
Test status
Simulation time 420819562 ps
CPU time 2.84 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 233496 kb
Host smart-a737199e-e9f0-4808-bcf7-e1ad3582aa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413791342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3413791342
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3357746811
Short name T818
Test name
Test status
Simulation time 78872845 ps
CPU time 0.8 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 207260 kb
Host smart-e11d4dff-cf5a-4c9c-a7da-d50ea4e03783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357746811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3357746811
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.205495294
Short name T812
Test name
Test status
Simulation time 60431275 ps
CPU time 1 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:35 PM PDT 24
Peak memory 216804 kb
Host smart-10d360cc-89c7-4678-beb8-d88d824d3967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205495294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.205495294
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2875714472
Short name T575
Test name
Test status
Simulation time 6325434999 ps
CPU time 65.14 seconds
Started Jul 23 04:41:34 PM PDT 24
Finished Jul 23 04:42:42 PM PDT 24
Peak memory 251044 kb
Host smart-df7911e0-a76b-46aa-849a-0f3a2d630b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875714472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2875714472
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.4266403884
Short name T212
Test name
Test status
Simulation time 7756446949 ps
CPU time 48.76 seconds
Started Jul 23 04:41:36 PM PDT 24
Finished Jul 23 04:42:27 PM PDT 24
Peak memory 251068 kb
Host smart-76dcbbbc-a1fe-44b1-af8f-1afb5d1de38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266403884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.4266403884
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1779056908
Short name T587
Test name
Test status
Simulation time 2319323533 ps
CPU time 8.76 seconds
Started Jul 23 04:41:42 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 225356 kb
Host smart-35895fe1-1543-45cc-bc6c-16be2090842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779056908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1779056908
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3718798906
Short name T241
Test name
Test status
Simulation time 1374571098 ps
CPU time 11.7 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 233272 kb
Host smart-fb8754b6-c402-48d8-97f3-5fc7d37ff88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718798906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3718798906
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1451336591
Short name T653
Test name
Test status
Simulation time 31896248 ps
CPU time 2.5 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 233136 kb
Host smart-8ea2ca75-d1f4-4035-8dab-72482a55ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451336591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1451336591
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.68540586
Short name T884
Test name
Test status
Simulation time 3190371969 ps
CPU time 10.1 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 225292 kb
Host smart-c98e2554-77be-42f2-8b81-2ab0b58e91c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68540586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.68540586
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1559437232
Short name T837
Test name
Test status
Simulation time 561331268 ps
CPU time 2.84 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 225380 kb
Host smart-289f4db1-1660-4f01-a2eb-b63e9d193aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559437232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1559437232
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3106802382
Short name T499
Test name
Test status
Simulation time 1463470570 ps
CPU time 7.59 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 219876 kb
Host smart-baf66be0-0b88-410d-96e3-7d1575f589c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3106802382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3106802382
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1823499911
Short name T948
Test name
Test status
Simulation time 37809472693 ps
CPU time 189.97 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:44:41 PM PDT 24
Peak memory 251104 kb
Host smart-dfb17f49-932e-4a31-9a1a-c6eacbfbc6ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823499911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1823499911
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1240358725
Short name T819
Test name
Test status
Simulation time 2210218239 ps
CPU time 32.54 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:42:07 PM PDT 24
Peak memory 220264 kb
Host smart-4ae02343-8b49-4560-92fa-238e133eb6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240358725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1240358725
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3062775264
Short name T686
Test name
Test status
Simulation time 1933872785 ps
CPU time 4.65 seconds
Started Jul 23 04:41:39 PM PDT 24
Finished Jul 23 04:41:45 PM PDT 24
Peak memory 216940 kb
Host smart-f390bd1e-2c12-4188-8498-6e62c0a4adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062775264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3062775264
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3641102006
Short name T56
Test name
Test status
Simulation time 26794861 ps
CPU time 1.07 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:31 PM PDT 24
Peak memory 208648 kb
Host smart-c1a1a993-ba21-4042-8885-a434f12ea8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641102006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3641102006
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4129577465
Short name T841
Test name
Test status
Simulation time 133688900 ps
CPU time 0.72 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 206588 kb
Host smart-d55e0d77-4eb7-4e2d-9543-3298555726ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129577465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4129577465
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2761604526
Short name T1023
Test name
Test status
Simulation time 747864844 ps
CPU time 7.29 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 219044 kb
Host smart-3aba4875-908e-4a00-9d8a-eecd53180578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761604526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2761604526
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1880138399
Short name T906
Test name
Test status
Simulation time 20733415 ps
CPU time 0.73 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 205772 kb
Host smart-8c4039cd-7de4-4a3f-96bf-ecc3d4f5f3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880138399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1880138399
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1359008235
Short name T961
Test name
Test status
Simulation time 1631233214 ps
CPU time 9.62 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:44 PM PDT 24
Peak memory 225316 kb
Host smart-fb15ff1d-40e1-4c2a-9657-4b06ab3fc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359008235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1359008235
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4139057552
Short name T330
Test name
Test status
Simulation time 21829367 ps
CPU time 0.75 seconds
Started Jul 23 04:41:39 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 207076 kb
Host smart-eaf7f643-9b9d-4d44-bd04-f02b5b2e3648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139057552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4139057552
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3767461061
Short name T1026
Test name
Test status
Simulation time 40771282910 ps
CPU time 75.45 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:42:48 PM PDT 24
Peak memory 249984 kb
Host smart-cdc62fee-ec18-4c50-929e-f845563e8c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767461061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3767461061
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1197799096
Short name T187
Test name
Test status
Simulation time 12452741977 ps
CPU time 70.56 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:42:45 PM PDT 24
Peak memory 255308 kb
Host smart-8c4084bf-a941-4116-8fa1-ce798a37fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197799096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1197799096
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3556633614
Short name T794
Test name
Test status
Simulation time 13940273795 ps
CPU time 76.44 seconds
Started Jul 23 04:41:29 PM PDT 24
Finished Jul 23 04:42:48 PM PDT 24
Peak memory 257324 kb
Host smart-d9d418c4-772c-4bf4-911e-261133773a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556633614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3556633614
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3633474790
Short name T313
Test name
Test status
Simulation time 6100577108 ps
CPU time 20.05 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 225476 kb
Host smart-bd75013b-6b61-40f1-98cd-b6bb5ede0787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633474790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3633474790
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2007420026
Short name T956
Test name
Test status
Simulation time 135556277366 ps
CPU time 132.86 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 252560 kb
Host smart-6891b399-c6e5-48cf-8676-6fb25b45abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007420026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2007420026
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4256814111
Short name T682
Test name
Test status
Simulation time 286234824 ps
CPU time 3.99 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 219784 kb
Host smart-9e4d8541-7594-4988-9ebd-f1fffa8bebcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256814111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4256814111
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1964977194
Short name T775
Test name
Test status
Simulation time 634289838 ps
CPU time 5.83 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 233636 kb
Host smart-f94b5487-da4d-4102-96e0-0947d8107095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964977194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1964977194
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4111029087
Short name T2
Test name
Test status
Simulation time 375803718 ps
CPU time 3.26 seconds
Started Jul 23 04:41:35 PM PDT 24
Finished Jul 23 04:41:41 PM PDT 24
Peak memory 225188 kb
Host smart-49fe1c73-8ccb-42dd-81c4-a2b0ad9d797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111029087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4111029087
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.206020173
Short name T486
Test name
Test status
Simulation time 3601046728 ps
CPU time 13.84 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 241752 kb
Host smart-15fe043d-5f71-44e0-85fe-fd95937a9cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206020173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.206020173
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2680323882
Short name T805
Test name
Test status
Simulation time 132884458 ps
CPU time 4.6 seconds
Started Jul 23 04:41:32 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 223840 kb
Host smart-032a20b3-fedc-47a1-8a76-9ea5cbec6886
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2680323882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2680323882
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3205412262
Short name T176
Test name
Test status
Simulation time 73555135717 ps
CPU time 746.47 seconds
Started Jul 23 04:41:43 PM PDT 24
Finished Jul 23 04:54:10 PM PDT 24
Peak memory 273764 kb
Host smart-a15ba06f-62ef-4c9a-8a5b-da79ad0ea0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205412262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3205412262
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.72672039
Short name T632
Test name
Test status
Simulation time 6613836506 ps
CPU time 35.63 seconds
Started Jul 23 04:41:38 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 217116 kb
Host smart-d84b3ab8-55c3-40ba-bc65-51ab0947bfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72672039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.72672039
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.295096915
Short name T708
Test name
Test status
Simulation time 2422734966 ps
CPU time 6.71 seconds
Started Jul 23 04:41:28 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 217128 kb
Host smart-fc996340-9acb-425f-b5b8-bfbe44ed9373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295096915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.295096915
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1618367974
Short name T451
Test name
Test status
Simulation time 1452697992 ps
CPU time 5.91 seconds
Started Jul 23 04:41:30 PM PDT 24
Finished Jul 23 04:41:39 PM PDT 24
Peak memory 217220 kb
Host smart-5b3b3fa8-a264-4336-a223-67748e315bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618367974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1618367974
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.904792698
Short name T949
Test name
Test status
Simulation time 255197223 ps
CPU time 0.94 seconds
Started Jul 23 04:41:33 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 206652 kb
Host smart-47e0573b-d1ba-4d2d-aae9-bc911f9bc8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904792698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.904792698
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3492197861
Short name T571
Test name
Test status
Simulation time 512402348 ps
CPU time 8.06 seconds
Started Jul 23 04:41:31 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 241052 kb
Host smart-d233eb97-d6bf-4d37-8b51-7844315a2ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492197861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3492197861
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1995224533
Short name T348
Test name
Test status
Simulation time 168752298 ps
CPU time 0.71 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 206300 kb
Host smart-a9f254c4-032e-4492-9ccd-0989f8b1f39d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995224533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1995224533
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3174426162
Short name T1009
Test name
Test status
Simulation time 32632618 ps
CPU time 2.3 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 233608 kb
Host smart-ba507909-e89f-415e-862f-807cbb96b80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174426162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3174426162
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2098882509
Short name T848
Test name
Test status
Simulation time 24159238 ps
CPU time 0.73 seconds
Started Jul 23 04:41:43 PM PDT 24
Finished Jul 23 04:41:45 PM PDT 24
Peak memory 206072 kb
Host smart-61667339-2a64-451d-ad9c-337d4a4745ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098882509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2098882509
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2594160413
Short name T280
Test name
Test status
Simulation time 22201635955 ps
CPU time 152.08 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:44:19 PM PDT 24
Peak memory 252212 kb
Host smart-4d692f14-ee83-44e5-9cc6-8e272f8a4b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594160413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2594160413
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.820530324
Short name T300
Test name
Test status
Simulation time 13644767567 ps
CPU time 75.35 seconds
Started Jul 23 04:41:49 PM PDT 24
Finished Jul 23 04:43:07 PM PDT 24
Peak memory 250972 kb
Host smart-f1e3a177-7eed-4c8e-9368-71aee7cf1c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820530324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.820530324
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.4240894435
Short name T673
Test name
Test status
Simulation time 38068157 ps
CPU time 0.76 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 218124 kb
Host smart-fd582937-0680-4855-9273-4d0dc4421bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240894435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.4240894435
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1597859091
Short name T743
Test name
Test status
Simulation time 26139985220 ps
CPU time 34.8 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:42:20 PM PDT 24
Peak memory 240608 kb
Host smart-7a45d3d9-5027-48ae-bade-18bcb3fd3cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597859091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1597859091
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3968030643
Short name T164
Test name
Test status
Simulation time 4973683674 ps
CPU time 54.81 seconds
Started Jul 23 04:41:52 PM PDT 24
Finished Jul 23 04:42:48 PM PDT 24
Peak memory 251900 kb
Host smart-1f62ef5d-b1e3-49f0-8227-636025c6e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968030643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3968030643
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1515049609
Short name T202
Test name
Test status
Simulation time 6004540192 ps
CPU time 14.83 seconds
Started Jul 23 04:41:52 PM PDT 24
Finished Jul 23 04:42:08 PM PDT 24
Peak memory 225468 kb
Host smart-19476386-d6c2-426e-8fc7-4603a5762b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515049609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1515049609
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.6399460
Short name T266
Test name
Test status
Simulation time 9205982467 ps
CPU time 59.64 seconds
Started Jul 23 04:41:50 PM PDT 24
Finished Jul 23 04:42:51 PM PDT 24
Peak memory 241580 kb
Host smart-7e3ffabd-2be2-4f6d-8047-d85bac97be38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6399460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.6399460
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2686927185
Short name T539
Test name
Test status
Simulation time 408460850 ps
CPU time 7.94 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:56 PM PDT 24
Peak memory 241812 kb
Host smart-ebacca28-f2e3-4bb7-bed0-226e338a6c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686927185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2686927185
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1206007568
Short name T275
Test name
Test status
Simulation time 3232507784 ps
CPU time 6.47 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 225484 kb
Host smart-b145ee04-1ce3-4285-8a3b-eb6abec8bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206007568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1206007568
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2128704820
Short name T38
Test name
Test status
Simulation time 289238373 ps
CPU time 6.59 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 223860 kb
Host smart-ee157180-ec41-447b-ab9e-5196b96a8aa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2128704820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2128704820
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.612110262
Short name T981
Test name
Test status
Simulation time 416738577 ps
CPU time 4.97 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 217152 kb
Host smart-2e85f949-a11c-4ec1-9010-26dd3e85f16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612110262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.612110262
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2157099930
Short name T707
Test name
Test status
Simulation time 6132224562 ps
CPU time 5.81 seconds
Started Jul 23 04:41:42 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 217028 kb
Host smart-729b8215-98d5-42bf-a053-ebfb6331130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157099930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2157099930
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4014274381
Short name T478
Test name
Test status
Simulation time 14244066 ps
CPU time 0.85 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 207728 kb
Host smart-cd406d3f-06c2-4bd6-9020-c9843c15bd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014274381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4014274381
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3010139427
Short name T535
Test name
Test status
Simulation time 16288898 ps
CPU time 0.75 seconds
Started Jul 23 04:41:52 PM PDT 24
Finished Jul 23 04:41:54 PM PDT 24
Peak memory 206512 kb
Host smart-016e1801-abdd-4449-a6a6-751452fd355d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010139427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3010139427
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2356807430
Short name T239
Test name
Test status
Simulation time 75321660888 ps
CPU time 24.99 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:42:15 PM PDT 24
Peak memory 233560 kb
Host smart-9b6ca046-f6b0-459c-93ec-804ada800713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356807430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2356807430
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1824443299
Short name T843
Test name
Test status
Simulation time 30783728 ps
CPU time 0.65 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 206032 kb
Host smart-517161b4-5368-4371-8d28-377ce93dff00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824443299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1824443299
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3164458342
Short name T896
Test name
Test status
Simulation time 1826454558 ps
CPU time 17.01 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:42:07 PM PDT 24
Peak memory 225452 kb
Host smart-7ab86e86-c28b-41e2-8af5-689eb49816f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164458342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3164458342
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.890247705
Short name T329
Test name
Test status
Simulation time 25239223 ps
CPU time 0.75 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 207160 kb
Host smart-0378cd42-06fb-42ec-b448-10a51edd3289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890247705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.890247705
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.665638981
Short name T218
Test name
Test status
Simulation time 3717426660 ps
CPU time 22.24 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:42:08 PM PDT 24
Peak memory 253360 kb
Host smart-9225f7fd-c583-4b3b-a9fa-3837051cd2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665638981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.665638981
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3823848282
Short name T750
Test name
Test status
Simulation time 3406847877 ps
CPU time 83.34 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 257860 kb
Host smart-bb7bac40-2941-495e-b51e-fd240ad5e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823848282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3823848282
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3756499942
Short name T771
Test name
Test status
Simulation time 1406953494 ps
CPU time 32.81 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:42:18 PM PDT 24
Peak memory 250244 kb
Host smart-142b76ad-86f9-4881-96a9-2136ee3f519d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756499942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3756499942
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.631888038
Short name T250
Test name
Test status
Simulation time 655393392 ps
CPU time 3.84 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 233544 kb
Host smart-464125b8-a8c5-445f-a419-898d854bbe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631888038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.631888038
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3743221098
Short name T552
Test name
Test status
Simulation time 3640174884 ps
CPU time 6.74 seconds
Started Jul 23 04:41:48 PM PDT 24
Finished Jul 23 04:41:57 PM PDT 24
Peak memory 236132 kb
Host smart-313eff17-55fb-4045-8f62-dc8145f1703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743221098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3743221098
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2512516370
Short name T615
Test name
Test status
Simulation time 116155385 ps
CPU time 2.55 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 233540 kb
Host smart-d55519d2-ce95-4e76-bd7d-e09e98309562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512516370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2512516370
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2574071990
Short name T238
Test name
Test status
Simulation time 3013958360 ps
CPU time 11.16 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:42:00 PM PDT 24
Peak memory 233556 kb
Host smart-f55d014e-336a-4324-85f9-9150689d380e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574071990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2574071990
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1024050239
Short name T681
Test name
Test status
Simulation time 628409652 ps
CPU time 3.6 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 219532 kb
Host smart-32995cc9-9d2d-4d99-9ae2-ef35de17c956
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024050239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1024050239
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3787780695
Short name T298
Test name
Test status
Simulation time 12204677720 ps
CPU time 110.03 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:43:37 PM PDT 24
Peak memory 251196 kb
Host smart-02237b3f-0baa-40d1-bc2b-05dcef8ebeca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787780695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3787780695
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1368990415
Short name T424
Test name
Test status
Simulation time 1776219826 ps
CPU time 14.82 seconds
Started Jul 23 04:41:48 PM PDT 24
Finished Jul 23 04:42:05 PM PDT 24
Peak memory 217184 kb
Host smart-dadb5967-d921-4dce-a030-2bc1d56b290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368990415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1368990415
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2275868337
Short name T449
Test name
Test status
Simulation time 348662030 ps
CPU time 1.17 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 208624 kb
Host smart-4e7f2f42-c83d-46f9-9ad7-01f104c70530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275868337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2275868337
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.989072303
Short name T68
Test name
Test status
Simulation time 143510841 ps
CPU time 1.26 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:49 PM PDT 24
Peak memory 217024 kb
Host smart-cb875ca1-24f1-490c-8482-7b0bc283710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989072303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.989072303
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.872059988
Short name T355
Test name
Test status
Simulation time 104922836 ps
CPU time 0.91 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 206668 kb
Host smart-b8d69d94-8a45-4df2-a3f4-5976b69a7601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872059988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.872059988
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3531793928
Short name T534
Test name
Test status
Simulation time 981051539 ps
CPU time 5.45 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:53 PM PDT 24
Peak memory 233656 kb
Host smart-0096a4cd-0cb0-4b21-adeb-b7b318feb60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531793928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3531793928
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3628423090
Short name T553
Test name
Test status
Simulation time 11658395 ps
CPU time 0.79 seconds
Started Jul 23 04:40:31 PM PDT 24
Finished Jul 23 04:40:33 PM PDT 24
Peak memory 205860 kb
Host smart-aa2ba276-9e9d-472f-b786-4ae95e04387e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628423090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
628423090
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3781748096
Short name T824
Test name
Test status
Simulation time 258595274 ps
CPU time 5.68 seconds
Started Jul 23 04:40:21 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 233720 kb
Host smart-86469a36-818c-4ad3-af4a-ce1294d6378d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781748096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3781748096
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4099632235
Short name T862
Test name
Test status
Simulation time 33357449 ps
CPU time 0.77 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:40:25 PM PDT 24
Peak memory 207204 kb
Host smart-75ba0400-ace4-4c2e-b3d2-defef1c4d0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099632235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4099632235
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1532805140
Short name T214
Test name
Test status
Simulation time 874786553 ps
CPU time 5.5 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 225424 kb
Host smart-6bc542ce-be6f-4fd6-9384-2c46e89a950b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532805140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1532805140
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3287155429
Short name T761
Test name
Test status
Simulation time 3548652463 ps
CPU time 49.07 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:41:16 PM PDT 24
Peak memory 250212 kb
Host smart-3ef629ec-1795-4bb8-97c2-0e9308fc02ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287155429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3287155429
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.728008916
Short name T268
Test name
Test status
Simulation time 253539402638 ps
CPU time 370.28 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:46:37 PM PDT 24
Peak memory 274052 kb
Host smart-2174dcc4-eab9-4674-a4d1-428e2f3da997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728008916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
728008916
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3914124381
Short name T448
Test name
Test status
Simulation time 4419740038 ps
CPU time 10.12 seconds
Started Jul 23 04:40:31 PM PDT 24
Finished Jul 23 04:40:42 PM PDT 24
Peak memory 225348 kb
Host smart-0191fe30-d43c-496c-84aa-298ca88ee46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914124381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3914124381
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3557996864
Short name T162
Test name
Test status
Simulation time 778870964 ps
CPU time 5.12 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:30 PM PDT 24
Peak memory 241860 kb
Host smart-a4ec25a0-3e7d-46d2-985b-f7124b97bb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557996864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3557996864
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2210543508
Short name T830
Test name
Test status
Simulation time 108289201 ps
CPU time 3.18 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 225324 kb
Host smart-975c936b-d16c-442c-acd3-d78a47d1ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210543508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2210543508
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1519607939
Short name T719
Test name
Test status
Simulation time 637798722 ps
CPU time 5.41 seconds
Started Jul 23 04:40:21 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 233552 kb
Host smart-a7768424-6516-4d42-ad2d-c777a0f2c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519607939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1519607939
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.4094547180
Short name T29
Test name
Test status
Simulation time 28613526 ps
CPU time 1.02 seconds
Started Jul 23 04:40:15 PM PDT 24
Finished Jul 23 04:40:21 PM PDT 24
Peak memory 218556 kb
Host smart-6a7195a2-ae9a-4db9-a730-518107d7d42a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094547180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.4094547180
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.615589401
Short name T955
Test name
Test status
Simulation time 121622162960 ps
CPU time 33.54 seconds
Started Jul 23 04:40:16 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 241764 kb
Host smart-7587619f-6e73-4dd0-b2c1-b610c4660ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615589401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
615589401
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2597182817
Short name T274
Test name
Test status
Simulation time 516429504 ps
CPU time 6.8 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:40:26 PM PDT 24
Peak memory 239672 kb
Host smart-ff8478b1-6f31-4037-aeea-2e79f5567e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597182817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2597182817
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1495937589
Short name T102
Test name
Test status
Simulation time 4145626793 ps
CPU time 21.38 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:40:59 PM PDT 24
Peak memory 222884 kb
Host smart-c7a72031-8b9e-404c-9c4b-d0c84ef55cdf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495937589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1495937589
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.994475943
Short name T65
Test name
Test status
Simulation time 116255348 ps
CPU time 1.22 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 235812 kb
Host smart-bf217248-7033-45b0-9ba0-0b4d4cbbedab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994475943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.994475943
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4036079196
Short name T20
Test name
Test status
Simulation time 58118726 ps
CPU time 1.01 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:26 PM PDT 24
Peak memory 207668 kb
Host smart-eb87d0cd-4742-42c2-acd7-0833e4786a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036079196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4036079196
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.418826521
Short name T916
Test name
Test status
Simulation time 18556901 ps
CPU time 0.7 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:40:25 PM PDT 24
Peak memory 206332 kb
Host smart-37a04b76-10bd-40ca-be1d-74d2fc721e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418826521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.418826521
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2378333815
Short name T540
Test name
Test status
Simulation time 1543820146 ps
CPU time 4.84 seconds
Started Jul 23 04:40:14 PM PDT 24
Finished Jul 23 04:40:24 PM PDT 24
Peak memory 217076 kb
Host smart-f66657b1-66a2-401c-b7db-afa127bb2d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378333815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2378333815
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2849878297
Short name T636
Test name
Test status
Simulation time 48866951 ps
CPU time 1.46 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 217104 kb
Host smart-b5251318-1c2a-47f2-9a17-617046516171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849878297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2849878297
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.820222449
Short name T842
Test name
Test status
Simulation time 200815730 ps
CPU time 0.81 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 206720 kb
Host smart-141d633a-d5f5-48fd-a81e-3be0c100dc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820222449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.820222449
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.131785009
Short name T975
Test name
Test status
Simulation time 2872502706 ps
CPU time 9.77 seconds
Started Jul 23 04:40:21 PM PDT 24
Finished Jul 23 04:40:33 PM PDT 24
Peak memory 225396 kb
Host smart-62984593-9bcc-48cf-94b8-d0f193118ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131785009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.131785009
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1843775472
Short name T432
Test name
Test status
Simulation time 15528562 ps
CPU time 0.71 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 206088 kb
Host smart-2f6e4f21-346c-4450-a7f0-b57cb7cfeeee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843775472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1843775472
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2341897926
Short name T398
Test name
Test status
Simulation time 89029908 ps
CPU time 2.43 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 233584 kb
Host smart-25fc8484-9326-468d-9e83-27308846ccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341897926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2341897926
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.222336167
Short name T648
Test name
Test status
Simulation time 15609054 ps
CPU time 0.78 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 206140 kb
Host smart-a31b3f78-0267-4e85-90e8-61fd4c0c620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222336167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.222336167
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3655103967
Short name T646
Test name
Test status
Simulation time 1105669519 ps
CPU time 8.39 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 241760 kb
Host smart-affaf12d-bb8c-4942-9481-642a7d2798f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655103967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3655103967
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4218847021
Short name T741
Test name
Test status
Simulation time 8780712570 ps
CPU time 59.69 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 250044 kb
Host smart-567d1155-6d97-4288-9063-6c2054cba614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218847021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4218847021
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2200688568
Short name T538
Test name
Test status
Simulation time 6777764195 ps
CPU time 52.14 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:42:37 PM PDT 24
Peak memory 251560 kb
Host smart-f191deee-73a6-470d-8563-c77b97d9cb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200688568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2200688568
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3352270561
Short name T225
Test name
Test status
Simulation time 11462509220 ps
CPU time 26.53 seconds
Started Jul 23 04:41:44 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 225412 kb
Host smart-dd709fad-bd60-4c73-acfc-145652c91368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352270561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3352270561
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1007561319
Short name T471
Test name
Test status
Simulation time 439191376 ps
CPU time 7.57 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:41:54 PM PDT 24
Peak memory 223444 kb
Host smart-ac0a2f33-8421-449e-b02d-212d4852737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007561319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1007561319
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3902941963
Short name T299
Test name
Test status
Simulation time 8670391799 ps
CPU time 14.06 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:42:02 PM PDT 24
Peak memory 234624 kb
Host smart-ec12bb64-adb3-403d-abd5-7c9aba9661c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902941963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3902941963
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1158654918
Short name T967
Test name
Test status
Simulation time 35243795 ps
CPU time 2.25 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:51 PM PDT 24
Peak memory 233592 kb
Host smart-8e78fcf3-8466-45bf-9c0e-4e35521c6719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158654918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1158654918
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.255832728
Short name T484
Test name
Test status
Simulation time 454617912 ps
CPU time 4.72 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 224104 kb
Host smart-b928b594-391e-49a3-92a0-e6f73e4752b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=255832728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.255832728
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.623086959
Short name T411
Test name
Test status
Simulation time 136699061 ps
CPU time 0.94 seconds
Started Jul 23 04:41:56 PM PDT 24
Finished Jul 23 04:42:08 PM PDT 24
Peak memory 207592 kb
Host smart-3e86c991-f472-4c5e-b7a1-24852d128098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623086959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.623086959
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.886896071
Short name T911
Test name
Test status
Simulation time 2911817001 ps
CPU time 13.07 seconds
Started Jul 23 04:41:45 PM PDT 24
Finished Jul 23 04:42:00 PM PDT 24
Peak memory 217164 kb
Host smart-286e233a-1fb2-4652-ab64-f8c0a6255d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886896071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.886896071
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1995970381
Short name T9
Test name
Test status
Simulation time 406321102 ps
CPU time 2.57 seconds
Started Jul 23 04:41:46 PM PDT 24
Finished Jul 23 04:41:50 PM PDT 24
Peak memory 217128 kb
Host smart-707062d9-dd5b-4ff0-8907-acb3253bbcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995970381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1995970381
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2284931496
Short name T688
Test name
Test status
Simulation time 1242430147 ps
CPU time 2.82 seconds
Started Jul 23 04:41:43 PM PDT 24
Finished Jul 23 04:41:47 PM PDT 24
Peak memory 217200 kb
Host smart-c7351f4e-b40e-47ca-816e-0f09896c0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284931496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2284931496
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2689826981
Short name T638
Test name
Test status
Simulation time 176937136 ps
CPU time 0.82 seconds
Started Jul 23 04:41:52 PM PDT 24
Finished Jul 23 04:41:54 PM PDT 24
Peak memory 206516 kb
Host smart-65323537-5e52-450c-baa9-a98bb7350085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689826981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2689826981
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3114586291
Short name T773
Test name
Test status
Simulation time 397047999 ps
CPU time 4.91 seconds
Started Jul 23 04:41:47 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 233596 kb
Host smart-a798c958-98a9-47e7-82fb-9dd7bc4f3e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114586291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3114586291
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1003751211
Short name T397
Test name
Test status
Simulation time 35247680 ps
CPU time 0.67 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 205188 kb
Host smart-5ac09fe0-cedf-47a2-a944-f93340c4bc39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003751211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1003751211
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2466685357
Short name T807
Test name
Test status
Simulation time 152751255 ps
CPU time 2.35 seconds
Started Jul 23 04:41:54 PM PDT 24
Finished Jul 23 04:42:03 PM PDT 24
Peak memory 225424 kb
Host smart-06b958ea-ac70-4679-959a-4671d3450853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466685357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2466685357
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2536739276
Short name T438
Test name
Test status
Simulation time 18087705 ps
CPU time 0.82 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 207112 kb
Host smart-dd75e5f3-cc78-4b99-bf5d-e3886ccac7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536739276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2536739276
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2170221537
Short name T374
Test name
Test status
Simulation time 4027502431 ps
CPU time 14.94 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 240280 kb
Host smart-fc296481-6368-48a1-8f0d-9254343811ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170221537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2170221537
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3693944842
Short name T290
Test name
Test status
Simulation time 34080323559 ps
CPU time 224.76 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:45:55 PM PDT 24
Peak memory 267724 kb
Host smart-7fb829e4-cea8-4424-bb04-4cce6bd3f64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693944842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3693944842
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1731830082
Short name T1028
Test name
Test status
Simulation time 13788118302 ps
CPU time 198.72 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:45:24 PM PDT 24
Peak memory 273548 kb
Host smart-e881568b-9de0-4577-8eb7-edb75d010222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731830082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1731830082
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1227058874
Short name T839
Test name
Test status
Simulation time 786942014 ps
CPU time 16.75 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 241820 kb
Host smart-9820733e-bd35-4848-8e86-6fc64fa1ae70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227058874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1227058874
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.4247899152
Short name T285
Test name
Test status
Simulation time 305196752366 ps
CPU time 496.94 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:50:26 PM PDT 24
Peak memory 267612 kb
Host smart-c02187d3-4f8b-4dbc-ba18-264708c609dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247899152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.4247899152
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4043681602
Short name T235
Test name
Test status
Simulation time 1502383919 ps
CPU time 4.43 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 233704 kb
Host smart-40e1265d-a1fe-42c9-8c26-2dcbb57989ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043681602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4043681602
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2570070299
Short name T240
Test name
Test status
Simulation time 931553440 ps
CPU time 8.05 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 233576 kb
Host smart-7e9b6276-53e6-444a-8a50-c40f4415f4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570070299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2570070299
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3580245949
Short name T734
Test name
Test status
Simulation time 21858259914 ps
CPU time 17.18 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:27 PM PDT 24
Peak memory 225644 kb
Host smart-69eb598d-c65a-4414-8524-0d3c3b5cc5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580245949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3580245949
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3382167672
Short name T1024
Test name
Test status
Simulation time 5132649197 ps
CPU time 17.21 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 239512 kb
Host smart-5309418e-8268-4141-88eb-7855fa230cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382167672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3382167672
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2535381035
Short name T88
Test name
Test status
Simulation time 169296970 ps
CPU time 4.78 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 223028 kb
Host smart-da4aaa32-4413-48b3-bea5-a2adad778a2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2535381035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2535381035
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1630858989
Short name T520
Test name
Test status
Simulation time 620360131 ps
CPU time 5.21 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 217044 kb
Host smart-4c98b929-edac-48a2-907c-38ff423d4b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630858989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1630858989
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.202363770
Short name T521
Test name
Test status
Simulation time 16157476824 ps
CPU time 12.28 seconds
Started Jul 23 04:41:54 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 218296 kb
Host smart-06540df0-2d5f-43fa-b790-12c2fdf56e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202363770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.202363770
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1848399758
Short name T549
Test name
Test status
Simulation time 180130076 ps
CPU time 1.56 seconds
Started Jul 23 04:41:54 PM PDT 24
Finished Jul 23 04:42:04 PM PDT 24
Peak memory 217052 kb
Host smart-aa888d10-a2b9-46f4-ae59-47de35717e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848399758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1848399758
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3087932226
Short name T409
Test name
Test status
Simulation time 15967482 ps
CPU time 0.73 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:06 PM PDT 24
Peak memory 206772 kb
Host smart-1f5e236a-ed6a-49d0-8419-39f1408a299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087932226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3087932226
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3922528144
Short name T1017
Test name
Test status
Simulation time 2518049371 ps
CPU time 10.79 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 235628 kb
Host smart-6bab27df-ee7a-4b3d-91cd-fd572d9be241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922528144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3922528144
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3246324617
Short name T367
Test name
Test status
Simulation time 80512558 ps
CPU time 0.72 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 205412 kb
Host smart-798f38ce-f367-4622-a7e3-36440eab9165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246324617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3246324617
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2667755727
Short name T868
Test name
Test status
Simulation time 15614287953 ps
CPU time 29.65 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 225480 kb
Host smart-d0859c64-2d77-491a-8de3-f91e3c485a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667755727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2667755727
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2557628339
Short name T508
Test name
Test status
Simulation time 55753751 ps
CPU time 0.79 seconds
Started Jul 23 04:41:54 PM PDT 24
Finished Jul 23 04:42:02 PM PDT 24
Peak memory 207168 kb
Host smart-c3c18a7a-f159-43f2-86ef-39e21d954a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557628339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2557628339
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3112068411
Short name T984
Test name
Test status
Simulation time 15635443586 ps
CPU time 125.4 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:44:16 PM PDT 24
Peak memory 255524 kb
Host smart-49beafd5-0ab2-487f-b107-9ae8c0f0fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112068411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3112068411
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3180042436
Short name T12
Test name
Test status
Simulation time 30715226268 ps
CPU time 139.57 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:44:30 PM PDT 24
Peak memory 257352 kb
Host smart-9c5bd6b0-a75f-4570-af8c-1ca0ffbcc1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180042436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3180042436
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3751816890
Short name T853
Test name
Test status
Simulation time 59614353468 ps
CPU time 168.36 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:45:00 PM PDT 24
Peak memory 252448 kb
Host smart-710a0329-468a-4a7b-be1e-461138acce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751816890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3751816890
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1652682862
Short name T793
Test name
Test status
Simulation time 2363494487 ps
CPU time 20.21 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 225684 kb
Host smart-a418696e-3158-4f2a-83e8-7c4390c5a3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652682862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1652682862
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3020298175
Short name T444
Test name
Test status
Simulation time 69870844246 ps
CPU time 121.18 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:44:05 PM PDT 24
Peak memory 250056 kb
Host smart-3a72e0ea-b5cf-48a0-b7a5-141be2cf4453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020298175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3020298175
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3214260760
Short name T880
Test name
Test status
Simulation time 1682610557 ps
CPU time 16.35 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 233548 kb
Host smart-0eef1625-b71e-44fb-a3f0-e37e415f04b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214260760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3214260760
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2643369783
Short name T412
Test name
Test status
Simulation time 5763505505 ps
CPU time 62.9 seconds
Started Jul 23 04:41:54 PM PDT 24
Finished Jul 23 04:43:04 PM PDT 24
Peak memory 233712 kb
Host smart-0a423934-ffae-41cb-b4c9-510acc8ec84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643369783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2643369783
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.651574590
Short name T526
Test name
Test status
Simulation time 1700904077 ps
CPU time 4.77 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 225320 kb
Host smart-b880439f-1c8c-45f2-9be5-22059bb4d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651574590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.651574590
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3503662189
Short name T206
Test name
Test status
Simulation time 98189168 ps
CPU time 2.78 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 233352 kb
Host smart-8499d48e-281a-41fa-b9fd-277d2015f06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503662189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3503662189
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2881778466
Short name T555
Test name
Test status
Simulation time 2734628415 ps
CPU time 11.27 seconds
Started Jul 23 04:41:56 PM PDT 24
Finished Jul 23 04:42:17 PM PDT 24
Peak memory 222896 kb
Host smart-bd9f6193-01c1-4e2a-83e6-ab72867c6ff2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2881778466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2881778466
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1492264430
Short name T13
Test name
Test status
Simulation time 38435954178 ps
CPU time 98.59 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 241672 kb
Host smart-3ca7588e-d9a0-4b86-9600-0aede99f7adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492264430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1492264430
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3459959455
Short name T608
Test name
Test status
Simulation time 772307326 ps
CPU time 11.46 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 217204 kb
Host smart-3cec2c41-c674-418e-94bf-20a7fbab1f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459959455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3459959455
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1171192277
Short name T545
Test name
Test status
Simulation time 1958361198 ps
CPU time 4.08 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:15 PM PDT 24
Peak memory 217144 kb
Host smart-1c23c2ea-33a7-4798-96e9-2be30f733e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171192277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1171192277
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3707191405
Short name T360
Test name
Test status
Simulation time 30711543 ps
CPU time 1.8 seconds
Started Jul 23 04:41:56 PM PDT 24
Finished Jul 23 04:42:08 PM PDT 24
Peak memory 217096 kb
Host smart-e5ee7a0b-d16e-406c-aef5-fb1f953fba5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707191405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3707191405
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3389208362
Short name T561
Test name
Test status
Simulation time 185202414 ps
CPU time 0.91 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:07 PM PDT 24
Peak memory 206720 kb
Host smart-bdec927f-288c-4578-8218-a83ab7dca48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389208362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3389208362
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2959939301
Short name T701
Test name
Test status
Simulation time 872461202 ps
CPU time 5.03 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 225396 kb
Host smart-4bcf53bc-c8be-402e-8a7e-60187577cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959939301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2959939301
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3709256103
Short name T536
Test name
Test status
Simulation time 12717663 ps
CPU time 0.7 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 205388 kb
Host smart-965a9b4f-4469-4dfb-8a2a-7b10a16ec7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709256103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3709256103
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1117168371
Short name T502
Test name
Test status
Simulation time 76806874 ps
CPU time 2.29 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 225300 kb
Host smart-bee0620e-1a60-4195-8a52-c50d2e336a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117168371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1117168371
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.177502584
Short name T663
Test name
Test status
Simulation time 87493091 ps
CPU time 0.76 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:07 PM PDT 24
Peak memory 206112 kb
Host smart-b9aaaf95-a45b-4f77-ad4d-2105918da5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177502584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.177502584
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3291201964
Short name T39
Test name
Test status
Simulation time 13507098452 ps
CPU time 44.74 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:58 PM PDT 24
Peak memory 239264 kb
Host smart-984399a5-3e39-4bc8-9248-215688416f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291201964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3291201964
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1109056793
Short name T260
Test name
Test status
Simulation time 33808223312 ps
CPU time 358.75 seconds
Started Jul 23 04:42:01 PM PDT 24
Finished Jul 23 04:48:10 PM PDT 24
Peak memory 270072 kb
Host smart-704465ef-c283-4596-aa22-c014655307c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109056793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1109056793
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1242173193
Short name T531
Test name
Test status
Simulation time 33044627996 ps
CPU time 93.44 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:43:44 PM PDT 24
Peak memory 250092 kb
Host smart-a753e022-e190-4d83-862c-4ab430a2a0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242173193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1242173193
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.923465190
Short name T104
Test name
Test status
Simulation time 32982692805 ps
CPU time 34.02 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:43 PM PDT 24
Peak memory 233656 kb
Host smart-2a1a8682-642a-453e-8ed3-d71fae2a5198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923465190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.923465190
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3525191840
Short name T284
Test name
Test status
Simulation time 146056816585 ps
CPU time 274.35 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:46:45 PM PDT 24
Peak memory 257248 kb
Host smart-978b4080-ca12-47c4-a7d9-408685e6071f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525191840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3525191840
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.989354608
Short name T228
Test name
Test status
Simulation time 247335621 ps
CPU time 3.36 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 233580 kb
Host smart-e2dc33d4-bacd-4b72-a429-b835de33b120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989354608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.989354608
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3105692523
Short name T912
Test name
Test status
Simulation time 2412350705 ps
CPU time 30.58 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 241272 kb
Host smart-2d4d2674-cd5d-4fc8-b0ea-b4c2e76c775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105692523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3105692523
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1429274923
Short name T516
Test name
Test status
Simulation time 14286033981 ps
CPU time 11.47 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:23 PM PDT 24
Peak memory 233640 kb
Host smart-68453fe4-f956-4557-9010-2d0522974899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429274923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1429274923
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1780246772
Short name T861
Test name
Test status
Simulation time 112105548 ps
CPU time 2.8 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 233600 kb
Host smart-7febbbb7-ec1b-4087-be19-9008bba8c57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780246772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1780246772
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3114738087
Short name T671
Test name
Test status
Simulation time 218854496 ps
CPU time 5.18 seconds
Started Jul 23 04:42:02 PM PDT 24
Finished Jul 23 04:42:18 PM PDT 24
Peak memory 223788 kb
Host smart-6c42f1e5-cdc1-4a9e-9d28-7cc942678824
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3114738087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3114738087
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1277780562
Short name T69
Test name
Test status
Simulation time 4521337162 ps
CPU time 58.38 seconds
Started Jul 23 04:42:01 PM PDT 24
Finished Jul 23 04:43:10 PM PDT 24
Peak memory 249608 kb
Host smart-2847a42b-4b25-4550-9e37-45a69b310160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277780562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1277780562
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3071044994
Short name T703
Test name
Test status
Simulation time 4719398434 ps
CPU time 25.84 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:35 PM PDT 24
Peak memory 217172 kb
Host smart-d90693e9-08a3-43cb-be30-d883b358b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071044994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3071044994
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.688480791
Short name T898
Test name
Test status
Simulation time 6702397490 ps
CPU time 19.18 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 217152 kb
Host smart-da6f1b47-daff-4fab-b9dd-500959db6e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688480791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.688480791
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1273112126
Short name T426
Test name
Test status
Simulation time 53268034 ps
CPU time 1.09 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 208660 kb
Host smart-dbb028e1-ddb4-4e34-9ad6-42609685b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273112126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1273112126
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2785088709
Short name T368
Test name
Test status
Simulation time 24098874 ps
CPU time 0.76 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 206820 kb
Host smart-62ed08a6-e718-41c8-8f6b-f6e358a2a11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785088709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2785088709
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3625315823
Short name T391
Test name
Test status
Simulation time 13017789783 ps
CPU time 18.77 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 225388 kb
Host smart-7857646b-8a58-4179-8db6-901d5b0252af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625315823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3625315823
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1854461648
Short name T697
Test name
Test status
Simulation time 28787023 ps
CPU time 0.7 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 205396 kb
Host smart-5c0322af-ba04-477f-b860-b964497c203f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854461648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1854461648
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1535423505
Short name T166
Test name
Test status
Simulation time 577293225 ps
CPU time 5.85 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:15 PM PDT 24
Peak memory 225372 kb
Host smart-05b2bd09-b21e-4a83-a8f5-5ddd23d7e763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535423505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1535423505
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1318836138
Short name T881
Test name
Test status
Simulation time 67037978 ps
CPU time 0.78 seconds
Started Jul 23 04:42:02 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 207152 kb
Host smart-ba9d24ba-3226-45fc-8a5c-27269ca21bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318836138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1318836138
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1039585892
Short name T700
Test name
Test status
Simulation time 4273128638 ps
CPU time 57.53 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 250072 kb
Host smart-a1859a16-40bc-4f9f-b928-9b149b1376b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039585892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1039585892
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2624979313
Short name T570
Test name
Test status
Simulation time 53868419483 ps
CPU time 249.54 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:46:21 PM PDT 24
Peak memory 274052 kb
Host smart-78fc8a72-f32e-4e79-a4b1-19c185f10fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624979313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2624979313
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1763418227
Short name T362
Test name
Test status
Simulation time 124000801 ps
CPU time 3.87 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:17 PM PDT 24
Peak memory 230072 kb
Host smart-dfce6023-61b1-476c-8b69-4d6be599efa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763418227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1763418227
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2090002607
Short name T918
Test name
Test status
Simulation time 38816800379 ps
CPU time 78.1 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:43:29 PM PDT 24
Peak memory 241312 kb
Host smart-5186740c-32bb-49f5-b141-598ece8582c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090002607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2090002607
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2133163417
Short name T847
Test name
Test status
Simulation time 848553065 ps
CPU time 8.67 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 225296 kb
Host smart-221432a3-b92e-490c-b975-a802963c7080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133163417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2133163417
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2792335241
Short name T730
Test name
Test status
Simulation time 1151164707 ps
CPU time 9.98 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 233452 kb
Host smart-5f205dd4-1589-46d7-94cf-eb656d45be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792335241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2792335241
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.322186990
Short name T925
Test name
Test status
Simulation time 528433356 ps
CPU time 2.6 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 233420 kb
Host smart-cbd0df3c-992f-4770-927a-a1228ddb8e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322186990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.322186990
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.211247197
Short name T556
Test name
Test status
Simulation time 5174769579 ps
CPU time 16.6 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 233580 kb
Host smart-4e4d3a76-b284-4596-bc60-49a8882dcd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211247197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.211247197
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1148945600
Short name T440
Test name
Test status
Simulation time 5075345761 ps
CPU time 13.78 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 222596 kb
Host smart-0e95b493-f2ef-421c-8242-84f579050265
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1148945600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1148945600
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2238755951
Short name T579
Test name
Test status
Simulation time 53927249 ps
CPU time 1.23 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 208052 kb
Host smart-5656a93f-e8b2-405f-939c-9691344d2bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238755951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2238755951
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4183722751
Short name T643
Test name
Test status
Simulation time 1020847262 ps
CPU time 5.16 seconds
Started Jul 23 04:42:01 PM PDT 24
Finished Jul 23 04:42:17 PM PDT 24
Peak memory 217120 kb
Host smart-4b49f5a1-8970-42c0-8281-cb73169545bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183722751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4183722751
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2855842927
Short name T356
Test name
Test status
Simulation time 27228831 ps
CPU time 0.69 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:14 PM PDT 24
Peak memory 206236 kb
Host smart-722b4d0c-2fa2-4535-9f01-729edca65ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855842927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2855842927
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2086214846
Short name T780
Test name
Test status
Simulation time 49357037 ps
CPU time 1.62 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:10 PM PDT 24
Peak memory 217052 kb
Host smart-14f7954b-5b5a-4546-b119-96cac8bf0362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086214846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2086214846
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2042742717
Short name T509
Test name
Test status
Simulation time 53483337 ps
CPU time 0.68 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 205816 kb
Host smart-84f5475e-44ed-4886-a635-e79d234e6eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042742717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2042742717
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3002548752
Short name T789
Test name
Test status
Simulation time 1655342913 ps
CPU time 5.07 seconds
Started Jul 23 04:42:01 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 241116 kb
Host smart-446bf224-1310-4c7f-8a05-8dcb6133f862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002548752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3002548752
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.40456161
Short name T728
Test name
Test status
Simulation time 38139017 ps
CPU time 0.7 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 206256 kb
Host smart-0b800482-483d-4a18-a95a-3508c0ef81ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40456161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.40456161
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2578236071
Short name T380
Test name
Test status
Simulation time 19852506 ps
CPU time 0.77 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:11 PM PDT 24
Peak memory 207552 kb
Host smart-61e61df9-9ab5-4cc7-ae04-9d2f432b14ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578236071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2578236071
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1476475
Short name T607
Test name
Test status
Simulation time 23816095912 ps
CPU time 46.44 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:43:16 PM PDT 24
Peak memory 234984 kb
Host smart-8acc88c0-4398-4e80-ac27-52e0cafe2f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1476475
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2931594345
Short name T279
Test name
Test status
Simulation time 180856540014 ps
CPU time 457.28 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:49:55 PM PDT 24
Peak memory 269800 kb
Host smart-7e0f402b-2a2f-45ff-bf7f-b1c99a7cf71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931594345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2931594345
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3898730342
Short name T832
Test name
Test status
Simulation time 205461954 ps
CPU time 2.52 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 233548 kb
Host smart-e174a765-cd85-4750-b301-69cfd3f9da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898730342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3898730342
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2892780549
Short name T331
Test name
Test status
Simulation time 72353723 ps
CPU time 0.82 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:23 PM PDT 24
Peak memory 216488 kb
Host smart-b208e296-b867-451f-8441-424f1e29b1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892780549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2892780549
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.46329293
Short name T908
Test name
Test status
Simulation time 503606926 ps
CPU time 5.64 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:16 PM PDT 24
Peak memory 225520 kb
Host smart-aeab258c-bf9c-4a52-a07b-4e72fed6f759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46329293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.46329293
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1777717064
Short name T689
Test name
Test status
Simulation time 6531441100 ps
CPU time 12.26 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:23 PM PDT 24
Peak memory 225492 kb
Host smart-b6553dac-2d29-4c1d-ac87-b72029bd12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777717064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1777717064
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.64681600
Short name T281
Test name
Test status
Simulation time 759361984 ps
CPU time 7.44 seconds
Started Jul 23 04:41:55 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 233524 kb
Host smart-2be92f78-5687-4cad-9335-1386c104da49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64681600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.64681600
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.274836897
Short name T1005
Test name
Test status
Simulation time 106608480 ps
CPU time 2.3 seconds
Started Jul 23 04:42:00 PM PDT 24
Finished Jul 23 04:42:13 PM PDT 24
Peak memory 223772 kb
Host smart-4f413640-9e3c-498e-b3f4-7d1836c623ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274836897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.274836897
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3581302227
Short name T770
Test name
Test status
Simulation time 673657184 ps
CPU time 8.2 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:28 PM PDT 24
Peak memory 221708 kb
Host smart-79634068-9d9a-4e44-81a3-16844be058fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3581302227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3581302227
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3094214028
Short name T791
Test name
Test status
Simulation time 38099439 ps
CPU time 0.9 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:24 PM PDT 24
Peak memory 206640 kb
Host smart-231a4399-0f60-41f7-bcb6-8e8766151070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094214028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3094214028
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3568825444
Short name T505
Test name
Test status
Simulation time 6386832118 ps
CPU time 39.72 seconds
Started Jul 23 04:41:57 PM PDT 24
Finished Jul 23 04:42:48 PM PDT 24
Peak memory 217212 kb
Host smart-77dd06cc-61ea-4591-a18f-da8f24e298a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568825444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3568825444
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.707571580
Short name T977
Test name
Test status
Simulation time 20958931051 ps
CPU time 10.65 seconds
Started Jul 23 04:41:58 PM PDT 24
Finished Jul 23 04:42:20 PM PDT 24
Peak memory 217240 kb
Host smart-7abb8c78-99a0-47f3-a77c-1691ba811b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707571580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.707571580
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2699426180
Short name T403
Test name
Test status
Simulation time 68809889 ps
CPU time 1.73 seconds
Started Jul 23 04:42:03 PM PDT 24
Finished Jul 23 04:42:15 PM PDT 24
Peak memory 208656 kb
Host smart-679ae217-49d3-4fd1-95dd-553c47f4d6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699426180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2699426180
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2654019008
Short name T387
Test name
Test status
Simulation time 78517486 ps
CPU time 0.81 seconds
Started Jul 23 04:41:59 PM PDT 24
Finished Jul 23 04:42:12 PM PDT 24
Peak memory 206660 kb
Host smart-60d017c4-1dd2-490e-bc86-5e495720e15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654019008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2654019008
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3003830687
Short name T727
Test name
Test status
Simulation time 1698947182 ps
CPU time 3.86 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:24 PM PDT 24
Peak memory 225252 kb
Host smart-2db4abb6-ea6f-486f-b3fb-1ca851ddbcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003830687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3003830687
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3715296435
Short name T644
Test name
Test status
Simulation time 15242842 ps
CPU time 0.73 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 206268 kb
Host smart-e6f693f5-280c-4e57-81cc-8b7f02df55ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715296435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3715296435
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1106744649
Short name T445
Test name
Test status
Simulation time 552196072 ps
CPU time 2.19 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 233140 kb
Host smart-c5b386be-c7b1-4044-85e4-d95949305a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106744649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1106744649
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2445101359
Short name T792
Test name
Test status
Simulation time 35276326 ps
CPU time 0.78 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:19 PM PDT 24
Peak memory 207192 kb
Host smart-a0db99c0-17f7-4460-9486-b222b5a66547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445101359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2445101359
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1045097814
Short name T286
Test name
Test status
Simulation time 239170990069 ps
CPU time 151.2 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:44:52 PM PDT 24
Peak memory 256968 kb
Host smart-0f181cdf-d365-4743-89e0-3ad9ec6807ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045097814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1045097814
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2451879809
Short name T288
Test name
Test status
Simulation time 94910705052 ps
CPU time 312.2 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:47:34 PM PDT 24
Peak memory 254436 kb
Host smart-f39bce3d-3556-4b3f-b889-1350359dabc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451879809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2451879809
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1742460021
Short name T661
Test name
Test status
Simulation time 55617053632 ps
CPU time 33.38 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:56 PM PDT 24
Peak memory 218468 kb
Host smart-4d9cf5e8-90e8-469b-b2c6-228a2b9b1cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742460021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1742460021
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1891839183
Short name T878
Test name
Test status
Simulation time 3260223943 ps
CPU time 11.48 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:32 PM PDT 24
Peak memory 234724 kb
Host smart-90e5119d-dec8-40c8-9ea4-1832369b4b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891839183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1891839183
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3779000264
Short name T46
Test name
Test status
Simulation time 1784570845 ps
CPU time 14.4 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:35 PM PDT 24
Peak memory 225384 kb
Host smart-2ef2b98b-ceee-469b-a203-a896c595c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779000264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3779000264
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.60762861
Short name T752
Test name
Test status
Simulation time 86980926 ps
CPU time 3.15 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 233632 kb
Host smart-c2ad5823-5857-46e4-9885-1e86b1fd6126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60762861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.60762861
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1299979765
Short name T529
Test name
Test status
Simulation time 21907318530 ps
CPU time 52.51 seconds
Started Jul 23 04:42:08 PM PDT 24
Finished Jul 23 04:43:09 PM PDT 24
Peak memory 233636 kb
Host smart-8eb1a838-0649-48f3-bd53-5c39d161b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299979765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1299979765
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3590000060
Short name T220
Test name
Test status
Simulation time 7771276224 ps
CPU time 21.23 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:39 PM PDT 24
Peak memory 233632 kb
Host smart-2d09b043-f457-4f07-bc35-3396192dd254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590000060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3590000060
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1684400803
Short name T597
Test name
Test status
Simulation time 169497285 ps
CPU time 3.93 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:42:32 PM PDT 24
Peak memory 233624 kb
Host smart-62cdb5a4-f87a-4611-9acc-4599006a9f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684400803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1684400803
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2558999574
Short name T8
Test name
Test status
Simulation time 5035870908 ps
CPU time 8.8 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:31 PM PDT 24
Peak memory 221112 kb
Host smart-99279091-d811-4b6d-be9f-72b7d999f317
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2558999574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2558999574
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1167437205
Short name T297
Test name
Test status
Simulation time 42150119022 ps
CPU time 328.79 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:47:49 PM PDT 24
Peak memory 274128 kb
Host smart-4121b9d4-ed34-434b-b986-bd0850ab9fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167437205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1167437205
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3725747274
Short name T939
Test name
Test status
Simulation time 12708310 ps
CPU time 0.7 seconds
Started Jul 23 04:42:14 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 206372 kb
Host smart-e6e009f7-5a25-4808-9f53-6c5316e00c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725747274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3725747274
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.138354808
Short name T951
Test name
Test status
Simulation time 2006967101 ps
CPU time 3.8 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:24 PM PDT 24
Peak memory 216984 kb
Host smart-788ae4f3-35de-4076-9abc-2121d1dd4e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138354808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.138354808
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2638661776
Short name T452
Test name
Test status
Simulation time 67691208 ps
CPU time 1.32 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:24 PM PDT 24
Peak memory 217100 kb
Host smart-d60def1c-ea03-4bdc-9dae-9da88e600492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638661776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2638661776
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.148166324
Short name T359
Test name
Test status
Simulation time 98454960 ps
CPU time 1 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:20 PM PDT 24
Peak memory 207252 kb
Host smart-0e08a5d4-7ca8-49f0-8bcf-0d957fcbd5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148166324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.148166324
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.918674707
Short name T854
Test name
Test status
Simulation time 110403125 ps
CPU time 2.31 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 224908 kb
Host smart-7b38722b-e863-426e-a3f1-7ec31fc99468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918674707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.918674707
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1062881838
Short name T467
Test name
Test status
Simulation time 95597807 ps
CPU time 0.79 seconds
Started Jul 23 04:42:14 PM PDT 24
Finished Jul 23 04:42:27 PM PDT 24
Peak memory 205408 kb
Host smart-c855dcbe-2d84-46ce-a685-1a5eabdc5571
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062881838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1062881838
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1884192734
Short name T530
Test name
Test status
Simulation time 11243175623 ps
CPU time 27.03 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:45 PM PDT 24
Peak memory 233644 kb
Host smart-8f2c9a9b-f893-4033-8133-8505acc7c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884192734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1884192734
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1281977446
Short name T619
Test name
Test status
Simulation time 14132185 ps
CPU time 0.73 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:42:23 PM PDT 24
Peak memory 207240 kb
Host smart-deff09f3-40be-4fb2-9565-254a8098d264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281977446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1281977446
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3275002651
Short name T817
Test name
Test status
Simulation time 9058743222 ps
CPU time 17.86 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:42 PM PDT 24
Peak memory 250012 kb
Host smart-a3fa3ec4-bba2-49a7-ab11-f2e6d42adb52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275002651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3275002651
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.177162168
Short name T623
Test name
Test status
Simulation time 14045646357 ps
CPU time 46.77 seconds
Started Jul 23 04:42:12 PM PDT 24
Finished Jul 23 04:43:09 PM PDT 24
Peak memory 250056 kb
Host smart-9b2b31b2-5a63-4022-a9e7-60801370249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177162168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.177162168
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3346394442
Short name T454
Test name
Test status
Simulation time 76245340944 ps
CPU time 130.39 seconds
Started Jul 23 04:42:14 PM PDT 24
Finished Jul 23 04:44:36 PM PDT 24
Peak memory 250112 kb
Host smart-3bf0f9da-f394-4250-9d83-753051699448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346394442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3346394442
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2578651486
Short name T388
Test name
Test status
Simulation time 276775546 ps
CPU time 2.97 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 225372 kb
Host smart-315ae2b7-f420-4c21-a1ee-8c0abb9bf8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578651486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2578651486
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2885520243
Short name T90
Test name
Test status
Simulation time 3194285391 ps
CPU time 39.18 seconds
Started Jul 23 04:42:08 PM PDT 24
Finished Jul 23 04:42:56 PM PDT 24
Peak memory 241800 kb
Host smart-fa0e6810-7175-43b4-8c94-be2490d237e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885520243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2885520243
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.242027164
Short name T957
Test name
Test status
Simulation time 371693428 ps
CPU time 5.66 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 225312 kb
Host smart-f345735c-1f62-4ffc-be83-25d38daabad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242027164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.242027164
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.632012294
Short name T668
Test name
Test status
Simulation time 1628656100 ps
CPU time 22.8 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 233724 kb
Host smart-c5a51dbd-4481-455f-b496-67b0829f94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632012294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.632012294
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1750295542
Short name T33
Test name
Test status
Simulation time 1434777032 ps
CPU time 6.18 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:28 PM PDT 24
Peak memory 233608 kb
Host smart-ecdc7642-7fd8-49e1-b109-94efb33f92d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750295542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1750295542
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3296227472
Short name T808
Test name
Test status
Simulation time 3050745336 ps
CPU time 10.5 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:31 PM PDT 24
Peak memory 225340 kb
Host smart-67288469-fb34-4fff-8bdf-0b2f45eb6a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296227472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3296227472
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4141869656
Short name T647
Test name
Test status
Simulation time 3153846337 ps
CPU time 13.62 seconds
Started Jul 23 04:42:17 PM PDT 24
Finished Jul 23 04:42:47 PM PDT 24
Peak memory 220656 kb
Host smart-deb31f84-f493-480b-bafd-596b8a63ff2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4141869656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4141869656
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4127353664
Short name T294
Test name
Test status
Simulation time 36661925462 ps
CPU time 243.29 seconds
Started Jul 23 04:42:14 PM PDT 24
Finished Jul 23 04:46:28 PM PDT 24
Peak memory 254252 kb
Host smart-eeaf8fe5-c434-499d-b910-7f3888679bb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127353664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4127353664
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1437419652
Short name T909
Test name
Test status
Simulation time 1365823048 ps
CPU time 22.29 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:44 PM PDT 24
Peak memory 216992 kb
Host smart-1ba04a88-3664-4d98-9464-c5f80d565c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437419652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1437419652
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.848459678
Short name T337
Test name
Test status
Simulation time 451569269 ps
CPU time 1.82 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 208628 kb
Host smart-7272a56e-ccc5-4a3b-94f1-525e54fa8770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848459678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.848459678
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3684893206
Short name T338
Test name
Test status
Simulation time 32240610 ps
CPU time 0.72 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 206192 kb
Host smart-37ecd8ee-fa47-4619-a75f-71ecc52cb0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684893206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3684893206
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.157353722
Short name T628
Test name
Test status
Simulation time 31814799 ps
CPU time 0.81 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 206720 kb
Host smart-17275e70-4b1e-4faa-a30a-7c8205b74be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157353722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.157353722
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.128863280
Short name T183
Test name
Test status
Simulation time 3854373296 ps
CPU time 6.75 seconds
Started Jul 23 04:42:09 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 231964 kb
Host smart-aa91d5ce-d943-4a30-9d76-bf98b915abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128863280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.128863280
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1540557340
Short name T966
Test name
Test status
Simulation time 19071276 ps
CPU time 0.7 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 205980 kb
Host smart-58a92a42-c517-49b1-938e-283b843afb18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540557340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1540557340
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3937668580
Short name T272
Test name
Test status
Simulation time 182794700 ps
CPU time 3.93 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:28 PM PDT 24
Peak memory 233556 kb
Host smart-71256d8f-311f-4fb4-bcda-719ee0ace2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937668580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3937668580
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3891487326
Short name T729
Test name
Test status
Simulation time 39256373 ps
CPU time 0.78 seconds
Started Jul 23 04:42:11 PM PDT 24
Finished Jul 23 04:42:22 PM PDT 24
Peak memory 207556 kb
Host smart-890a9435-cb75-448b-b473-790fde2cfc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891487326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3891487326
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3408975330
Short name T706
Test name
Test status
Simulation time 10956796655 ps
CPU time 39.53 seconds
Started Jul 23 04:42:16 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 238736 kb
Host smart-c6fe2ddc-d2e1-45bd-b59a-d61beffd1af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408975330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3408975330
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3152442929
Short name T592
Test name
Test status
Simulation time 2658955331 ps
CPU time 42 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:43:12 PM PDT 24
Peak memory 250112 kb
Host smart-b19d051a-dfa8-4f8a-99f0-5ec29d9718da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152442929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3152442929
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2990083156
Short name T413
Test name
Test status
Simulation time 26665830069 ps
CPU time 178.62 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:45:27 PM PDT 24
Peak memory 250440 kb
Host smart-60a38fdb-42b5-4e47-94d9-6e0b3d8c682d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990083156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2990083156
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3479002185
Short name T247
Test name
Test status
Simulation time 328336925 ps
CPU time 6.66 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 233480 kb
Host smart-ac4063db-9d79-40fb-8cdf-3038a1a4da4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479002185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3479002185
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1423520433
Short name T191
Test name
Test status
Simulation time 2923367064 ps
CPU time 14.47 seconds
Started Jul 23 04:42:10 PM PDT 24
Finished Jul 23 04:42:34 PM PDT 24
Peak memory 241004 kb
Host smart-7873926d-374d-45eb-b7b1-8591eb0656cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423520433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1423520433
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2981351319
Short name T616
Test name
Test status
Simulation time 7967324939 ps
CPU time 22.59 seconds
Started Jul 23 04:42:17 PM PDT 24
Finished Jul 23 04:42:55 PM PDT 24
Peak memory 225428 kb
Host smart-f1580dc1-28f8-47e9-8861-983e22830511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981351319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2981351319
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3518822328
Short name T184
Test name
Test status
Simulation time 8879344483 ps
CPU time 22.44 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:42:52 PM PDT 24
Peak memory 241300 kb
Host smart-e0a564d3-3833-47a5-9344-f7eb438df8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518822328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3518822328
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2913028843
Short name T527
Test name
Test status
Simulation time 1567805071 ps
CPU time 12.53 seconds
Started Jul 23 04:42:16 PM PDT 24
Finished Jul 23 04:42:45 PM PDT 24
Peak memory 222784 kb
Host smart-737d1654-80b5-46da-befd-94dab500bbd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2913028843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2913028843
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.47091880
Short name T320
Test name
Test status
Simulation time 15987609918 ps
CPU time 87.41 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 255344 kb
Host smart-5e6a7735-5c88-496a-83fc-e7688d7e61a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47091880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress
_all.47091880
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4129700156
Short name T418
Test name
Test status
Simulation time 10522169084 ps
CPU time 31.99 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:56 PM PDT 24
Peak memory 220928 kb
Host smart-440a5fbb-3747-4dc2-b7e5-78bf24aade61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129700156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4129700156
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3039700955
Short name T846
Test name
Test status
Simulation time 544367963 ps
CPU time 1.06 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:26 PM PDT 24
Peak memory 207860 kb
Host smart-4dcf946c-3835-4653-857c-22406da015d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039700955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3039700955
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3413158988
Short name T474
Test name
Test status
Simulation time 129020708 ps
CPU time 1.06 seconds
Started Jul 23 04:42:13 PM PDT 24
Finished Jul 23 04:42:25 PM PDT 24
Peak memory 207752 kb
Host smart-f2328641-e237-4d04-b800-375455956854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413158988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3413158988
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3406231019
Short name T742
Test name
Test status
Simulation time 188860163 ps
CPU time 0.88 seconds
Started Jul 23 04:42:15 PM PDT 24
Finished Jul 23 04:42:30 PM PDT 24
Peak memory 206720 kb
Host smart-81f9066f-cb0e-4dd8-8a66-e91220eaece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406231019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3406231019
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2327252571
Short name T495
Test name
Test status
Simulation time 646813512 ps
CPU time 3.21 seconds
Started Jul 23 04:42:18 PM PDT 24
Finished Jul 23 04:42:38 PM PDT 24
Peak memory 233532 kb
Host smart-be95faaa-892e-4b66-bf91-2dee3c8cbd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327252571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2327252571
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3428509877
Short name T601
Test name
Test status
Simulation time 16919362 ps
CPU time 0.7 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:49 PM PDT 24
Peak memory 206032 kb
Host smart-3d05d59e-be39-413c-aefd-1794f2ecb958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428509877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3428509877
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3214953676
Short name T816
Test name
Test status
Simulation time 2720942917 ps
CPU time 6.62 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 233512 kb
Host smart-6f95436a-7d58-47c5-9cb6-0b61adf18d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214953676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3214953676
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2420047247
Short name T826
Test name
Test status
Simulation time 16710119 ps
CPU time 0.77 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:43:06 PM PDT 24
Peak memory 207168 kb
Host smart-5d3d6692-ac9c-4c6b-b1c1-4d39090145b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420047247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2420047247
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4051573817
Short name T886
Test name
Test status
Simulation time 38146532408 ps
CPU time 382.32 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 264332 kb
Host smart-f9b23ac8-a507-4e38-8ff5-e7a191d2c1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051573817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4051573817
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.192618972
Short name T51
Test name
Test status
Simulation time 38723751793 ps
CPU time 162.34 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:45:46 PM PDT 24
Peak memory 266528 kb
Host smart-5cfdd9e6-3487-4154-ac3b-0a34f3185b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192618972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.192618972
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1328907007
Short name T310
Test name
Test status
Simulation time 316384754 ps
CPU time 8.68 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:59 PM PDT 24
Peak memory 225404 kb
Host smart-c6815bd7-cd4d-4578-b6e5-a3cad279e81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328907007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1328907007
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3749544047
Short name T41
Test name
Test status
Simulation time 48252941705 ps
CPU time 179.36 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:46:09 PM PDT 24
Peak memory 255360 kb
Host smart-b443d9b4-33fe-4484-a539-6800196d6508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749544047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3749544047
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2208900844
Short name T845
Test name
Test status
Simulation time 1453689369 ps
CPU time 5.81 seconds
Started Jul 23 04:42:24 PM PDT 24
Finished Jul 23 04:43:04 PM PDT 24
Peak memory 225304 kb
Host smart-9070a0b5-dd0b-4b48-9b18-8799f1ba13a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208900844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2208900844
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.244075450
Short name T352
Test name
Test status
Simulation time 29047636 ps
CPU time 2.04 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:58 PM PDT 24
Peak memory 225052 kb
Host smart-17288f3e-8b29-4db2-8070-a666e67db43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244075450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.244075450
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4136371229
Short name T408
Test name
Test status
Simulation time 4289046288 ps
CPU time 15.85 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:43:04 PM PDT 24
Peak memory 225360 kb
Host smart-bbfacc79-2d89-4f7f-8725-d1b456add04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136371229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4136371229
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3028441930
Short name T851
Test name
Test status
Simulation time 2564599158 ps
CPU time 14.97 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 225428 kb
Host smart-00d68359-5a4b-4932-9e51-da7397abcff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028441930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3028441930
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1334141000
Short name T626
Test name
Test status
Simulation time 3176100007 ps
CPU time 7.09 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:58 PM PDT 24
Peak memory 222856 kb
Host smart-b764d39b-6144-48dc-ae44-b3f13a4d0e84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1334141000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1334141000
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1149913816
Short name T963
Test name
Test status
Simulation time 34246714014 ps
CPU time 290.24 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:47:41 PM PDT 24
Peak memory 254968 kb
Host smart-1d3fa798-6ee0-43bb-bad3-833a34a456ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149913816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1149913816
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4096669254
Short name T431
Test name
Test status
Simulation time 51500530624 ps
CPU time 19.44 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:43:05 PM PDT 24
Peak memory 221064 kb
Host smart-9af44d4d-43eb-4b4e-ad8a-40b2e15083cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096669254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4096669254
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4235509837
Short name T353
Test name
Test status
Simulation time 482259835 ps
CPU time 2.41 seconds
Started Jul 23 04:42:19 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 217164 kb
Host smart-a133becf-541e-4958-91f6-e7b4a9b0521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235509837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4235509837
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2591160843
Short name T482
Test name
Test status
Simulation time 94869590 ps
CPU time 1.46 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:48 PM PDT 24
Peak memory 216996 kb
Host smart-c3ded11d-25e4-4209-a3b4-fbbd8cf14607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591160843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2591160843
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1999540255
Short name T654
Test name
Test status
Simulation time 162004449 ps
CPU time 0.93 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:50 PM PDT 24
Peak memory 207696 kb
Host smart-25be6795-60eb-4a79-af51-b6dfd081778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999540255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1999540255
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1865979250
Short name T244
Test name
Test status
Simulation time 90467558 ps
CPU time 2.41 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 225444 kb
Host smart-2a8dc75b-d557-4b72-a281-4dcdb712e3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865979250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1865979250
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.4110525924
Short name T850
Test name
Test status
Simulation time 34725627 ps
CPU time 0.71 seconds
Started Jul 23 04:40:26 PM PDT 24
Finished Jul 23 04:40:30 PM PDT 24
Peak memory 206084 kb
Host smart-250e04cf-e624-4efa-ae4d-00b447b577e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110525924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.4
110525924
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1456475860
Short name T497
Test name
Test status
Simulation time 379585494 ps
CPU time 5.8 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:33 PM PDT 24
Peak memory 225268 kb
Host smart-bc792835-34f8-445a-bb11-1d4f3dcb3ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456475860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1456475860
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2149247964
Short name T715
Test name
Test status
Simulation time 44185992 ps
CPU time 0.75 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 207140 kb
Host smart-154bca2c-5f99-434e-894f-dca52407b024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149247964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2149247964
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.282857960
Short name T77
Test name
Test status
Simulation time 16198964288 ps
CPU time 71.92 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:41:40 PM PDT 24
Peak memory 265980 kb
Host smart-2da0b22c-c50d-442a-87fc-48c37f6d1579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282857960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.282857960
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3505469814
Short name T324
Test name
Test status
Simulation time 3303122727 ps
CPU time 11.79 seconds
Started Jul 23 04:40:29 PM PDT 24
Finished Jul 23 04:40:42 PM PDT 24
Peak memory 218428 kb
Host smart-35514054-e94d-4bd8-8027-67967d364cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505469814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3505469814
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2094466507
Short name T48
Test name
Test status
Simulation time 102247052148 ps
CPU time 189.67 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:43:36 PM PDT 24
Peak memory 250056 kb
Host smart-49ec3be6-b3dc-4e1c-af15-116362487c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094466507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2094466507
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3259958537
Short name T308
Test name
Test status
Simulation time 13883665250 ps
CPU time 44.98 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 235624 kb
Host smart-2384120c-a018-4f52-a5ca-78bd15191134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259958537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3259958537
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.737271968
Short name T828
Test name
Test status
Simulation time 17589920222 ps
CPU time 70.67 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:41:38 PM PDT 24
Peak memory 255924 kb
Host smart-73824d46-7794-44cf-957c-eefba912d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737271968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
737271968
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3211349861
Short name T920
Test name
Test status
Simulation time 675416155 ps
CPU time 2.43 seconds
Started Jul 23 04:40:30 PM PDT 24
Finished Jul 23 04:40:33 PM PDT 24
Peak memory 225344 kb
Host smart-16458ffe-7bd0-430b-ae74-cd90f697f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211349861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3211349861
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3867691912
Short name T428
Test name
Test status
Simulation time 586018218 ps
CPU time 9.93 seconds
Started Jul 23 04:40:32 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 233504 kb
Host smart-b5708053-17f3-42eb-b0ca-da6f2b11b73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867691912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3867691912
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.965994840
Short name T28
Test name
Test status
Simulation time 41487740 ps
CPU time 1.05 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 217308 kb
Host smart-0019c006-a3c1-45f7-840e-a07657e3a190
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965994840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.965994840
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2317774562
Short name T263
Test name
Test status
Simulation time 9060864535 ps
CPU time 15.11 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:40:39 PM PDT 24
Peak memory 225508 kb
Host smart-d9fe2246-8fd8-4c69-951e-9e2cd7fff49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317774562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2317774562
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2258987424
Short name T1
Test name
Test status
Simulation time 73320414 ps
CPU time 2.27 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:30 PM PDT 24
Peak memory 225324 kb
Host smart-a70121e8-b222-4c89-b06c-ec5c839c658f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258987424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2258987424
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3151054357
Short name T564
Test name
Test status
Simulation time 1811200169 ps
CPU time 7.82 seconds
Started Jul 23 04:40:30 PM PDT 24
Finished Jul 23 04:40:39 PM PDT 24
Peak memory 222812 kb
Host smart-8b276fc6-fea2-4a8e-8120-1effd69368ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151054357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3151054357
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3017945970
Short name T67
Test name
Test status
Simulation time 200475334 ps
CPU time 1.02 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 236208 kb
Host smart-b8e0ab4c-7920-4ea7-b3dd-3d2cbda4427f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017945970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3017945970
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2766638512
Short name T148
Test name
Test status
Simulation time 61325447163 ps
CPU time 124.47 seconds
Started Jul 23 04:40:29 PM PDT 24
Finished Jul 23 04:42:35 PM PDT 24
Peak memory 241124 kb
Host smart-1f0a309f-28f9-4595-9080-58d44648cc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766638512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2766638512
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3528673914
Short name T318
Test name
Test status
Simulation time 1018081775 ps
CPU time 7.82 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:34 PM PDT 24
Peak memory 219960 kb
Host smart-1b37e36f-66d2-49e7-a885-581fe817a76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528673914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3528673914
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2036593943
Short name T394
Test name
Test status
Simulation time 14363894244 ps
CPU time 9.78 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 216864 kb
Host smart-a6d20ddb-ab5e-4c4f-81de-205df19f073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036593943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2036593943
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2097013938
Short name T472
Test name
Test status
Simulation time 128062625 ps
CPU time 2.11 seconds
Started Jul 23 04:40:32 PM PDT 24
Finished Jul 23 04:40:35 PM PDT 24
Peak memory 217040 kb
Host smart-b007d5db-a064-40e5-9be5-97871e6b22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097013938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2097013938
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.818115203
Short name T15
Test name
Test status
Simulation time 47529700 ps
CPU time 0.75 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 206672 kb
Host smart-5c85040d-d8d2-49a6-9896-ca8b9a3830b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818115203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.818115203
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1753087043
Short name T383
Test name
Test status
Simulation time 284498966 ps
CPU time 3.52 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:40:41 PM PDT 24
Peak memory 225120 kb
Host smart-8678ff9f-e90c-478a-9143-b917eb6a9bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753087043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1753087043
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.805135633
Short name T429
Test name
Test status
Simulation time 14338868 ps
CPU time 0.73 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 206024 kb
Host smart-39dc930a-504f-444a-adec-0aa9719b29bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805135633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.805135633
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.603285195
Short name T447
Test name
Test status
Simulation time 65734329 ps
CPU time 2.29 seconds
Started Jul 23 04:42:24 PM PDT 24
Finished Jul 23 04:43:00 PM PDT 24
Peak memory 233604 kb
Host smart-563ad5e0-db58-436f-88bf-df879e9bc6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603285195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.603285195
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.908770536
Short name T887
Test name
Test status
Simulation time 49807870 ps
CPU time 0.75 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 207540 kb
Host smart-e39ec95a-57e7-4528-bcbc-e30f5238246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908770536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.908770536
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.2202407334
Short name T289
Test name
Test status
Simulation time 7740417922 ps
CPU time 56.86 seconds
Started Jul 23 04:42:20 PM PDT 24
Finished Jul 23 04:43:39 PM PDT 24
Peak memory 263508 kb
Host smart-7e6af131-c24d-4574-82b3-2a446ae508e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202407334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.2202407334
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3431689792
Short name T195
Test name
Test status
Simulation time 6347144417 ps
CPU time 95.5 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:44:32 PM PDT 24
Peak memory 250132 kb
Host smart-c9d66d0d-e75c-4a94-bda3-bae2efc50a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431689792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3431689792
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3227170937
Short name T222
Test name
Test status
Simulation time 143824385919 ps
CPU time 356.98 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 256464 kb
Host smart-ed8aa7f6-6459-4608-9378-8de314fceb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227170937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3227170937
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.718029388
Short name T595
Test name
Test status
Simulation time 7969283224 ps
CPU time 47.06 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 250840 kb
Host smart-9b98a7ae-4496-447f-90c0-e5e3dcdeef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718029388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.718029388
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.884258260
Short name T437
Test name
Test status
Simulation time 4135039568 ps
CPU time 30.32 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:43:19 PM PDT 24
Peak memory 225408 kb
Host smart-4bd89d63-bf5c-4222-859e-4f215c5825b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884258260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.884258260
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.730762985
Short name T226
Test name
Test status
Simulation time 2312984024 ps
CPU time 3.26 seconds
Started Jul 23 04:42:24 PM PDT 24
Finished Jul 23 04:43:01 PM PDT 24
Peak memory 220712 kb
Host smart-68d07f42-0d4f-4c9a-a680-46983abd3bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730762985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.730762985
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.609065621
Short name T698
Test name
Test status
Simulation time 3232776466 ps
CPU time 7.22 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:54 PM PDT 24
Peak memory 225516 kb
Host smart-8d885b8d-60e9-42c5-b02c-ccf2e02e3e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609065621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.609065621
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2709687545
Short name T924
Test name
Test status
Simulation time 222356535 ps
CPU time 2.76 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:59 PM PDT 24
Peak memory 233448 kb
Host smart-d51a287d-3a09-486b-a9be-b79a9cefd38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709687545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2709687545
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3913437775
Short name T439
Test name
Test status
Simulation time 3532934243 ps
CPU time 11.35 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:04 PM PDT 24
Peak memory 241576 kb
Host smart-e5cebb6b-e016-4448-9fc4-5d3aed2b3fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913437775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3913437775
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.113024013
Short name T588
Test name
Test status
Simulation time 113979598 ps
CPU time 4.06 seconds
Started Jul 23 04:42:28 PM PDT 24
Finished Jul 23 04:43:16 PM PDT 24
Peak memory 220732 kb
Host smart-e3127679-aa1d-483b-b754-45709ad52958
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=113024013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.113024013
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3347281931
Short name T172
Test name
Test status
Simulation time 245305043305 ps
CPU time 492.98 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:51:00 PM PDT 24
Peak memory 270776 kb
Host smart-35acc29f-c20b-43c5-aa8b-ed212f90ece9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347281931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3347281931
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3122423117
Short name T314
Test name
Test status
Simulation time 3586973272 ps
CPU time 10.46 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 220640 kb
Host smart-a747c1a8-c4d4-45e1-ab1c-edded34f3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122423117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3122423117
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3447215914
Short name T613
Test name
Test status
Simulation time 4834866352 ps
CPU time 16.76 seconds
Started Jul 23 04:42:20 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 217144 kb
Host smart-bb9e7081-5d72-4076-bbef-c7e7567f5c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447215914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3447215914
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.809279201
Short name T565
Test name
Test status
Simulation time 99285786 ps
CPU time 1.09 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 208668 kb
Host smart-65f33031-657b-43fd-8286-5830144b1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809279201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.809279201
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1518501599
Short name T401
Test name
Test status
Simulation time 25502878 ps
CPU time 0.73 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 206820 kb
Host smart-4dbf3a38-dd1b-4f7d-b435-dd07f5df8f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518501599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1518501599
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.219257396
Short name T882
Test name
Test status
Simulation time 1135765900 ps
CPU time 2.86 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:59 PM PDT 24
Peak memory 233592 kb
Host smart-c439732a-d18c-4081-bbee-2850185843de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219257396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.219257396
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1762766883
Short name T59
Test name
Test status
Simulation time 22588777 ps
CPU time 0.71 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 205956 kb
Host smart-3f466a04-35cb-47d2-89ce-b8f3da69441d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762766883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1762766883
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4128252117
Short name T635
Test name
Test status
Simulation time 6847472444 ps
CPU time 4.7 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 225364 kb
Host smart-b16f269f-e894-4660-8b41-dcf47cb366f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128252117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4128252117
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1331598039
Short name T745
Test name
Test status
Simulation time 36686749 ps
CPU time 0.74 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:08 PM PDT 24
Peak memory 206204 kb
Host smart-9e92bb13-690b-4b94-a985-f6c52a5c5d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331598039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1331598039
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3600544007
Short name T726
Test name
Test status
Simulation time 50781384671 ps
CPU time 66.33 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:43:52 PM PDT 24
Peak memory 256236 kb
Host smart-636da3b4-0019-4f64-8dff-ea1a4e0386db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600544007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3600544007
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2202401357
Short name T748
Test name
Test status
Simulation time 7034974924 ps
CPU time 75.48 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:44:04 PM PDT 24
Peak memory 250056 kb
Host smart-10d084af-b09b-403d-97e2-ff342c28407e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202401357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2202401357
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2641318589
Short name T1018
Test name
Test status
Simulation time 1576226197 ps
CPU time 5.06 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:52 PM PDT 24
Peak memory 239180 kb
Host smart-cc576fdc-26fd-4333-8508-60b76dc513fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641318589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2641318589
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1648020355
Short name T167
Test name
Test status
Simulation time 203444853144 ps
CPU time 363.46 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:48:52 PM PDT 24
Peak memory 254016 kb
Host smart-f09ad3e4-6ef6-4705-bf00-af504f930c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648020355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1648020355
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.370495245
Short name T829
Test name
Test status
Simulation time 3039470629 ps
CPU time 7.25 seconds
Started Jul 23 04:42:20 PM PDT 24
Finished Jul 23 04:42:49 PM PDT 24
Peak memory 225424 kb
Host smart-bf34671b-a991-433f-b8a0-777216087133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370495245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.370495245
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1622032157
Short name T649
Test name
Test status
Simulation time 1531004443 ps
CPU time 6.94 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:00 PM PDT 24
Peak memory 235232 kb
Host smart-7cd05b06-02eb-4d74-bba6-57c849fce575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622032157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1622032157
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1984289308
Short name T811
Test name
Test status
Simulation time 438782700 ps
CPU time 4.89 seconds
Started Jul 23 04:42:24 PM PDT 24
Finished Jul 23 04:43:03 PM PDT 24
Peak memory 236700 kb
Host smart-3d66f198-edec-447b-9cfe-e915f2db7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984289308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1984289308
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1049950699
Short name T717
Test name
Test status
Simulation time 20046096750 ps
CPU time 10.92 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:57 PM PDT 24
Peak memory 225436 kb
Host smart-eb2afee3-8ccf-4bfb-b644-ddc2767919e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049950699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1049950699
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2756378226
Short name T970
Test name
Test status
Simulation time 2498231506 ps
CPU time 6.59 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:43:07 PM PDT 24
Peak memory 221108 kb
Host smart-fef4cf3e-669d-4726-80b2-db3675c69121
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2756378226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2756378226
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1294193461
Short name T131
Test name
Test status
Simulation time 53948103822 ps
CPU time 102.59 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:44:46 PM PDT 24
Peak memory 256560 kb
Host smart-65a74625-72a4-489d-8ebd-2f68885382cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294193461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1294193461
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.676373367
Short name T999
Test name
Test status
Simulation time 21251975 ps
CPU time 0.7 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:54 PM PDT 24
Peak memory 206028 kb
Host smart-b594d896-8c3f-4ddc-acbf-a5554b1a2dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676373367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.676373367
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.480727333
Short name T834
Test name
Test status
Simulation time 2067151706 ps
CPU time 2.73 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:53 PM PDT 24
Peak memory 217140 kb
Host smart-63b26cc9-5472-4c7a-87a9-c194d4680347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480727333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.480727333
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1069454152
Short name T327
Test name
Test status
Simulation time 71425241 ps
CPU time 1.06 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:54 PM PDT 24
Peak memory 208628 kb
Host smart-bdf18884-d9e1-414a-8478-b543d2246a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069454152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1069454152
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3139973766
Short name T704
Test name
Test status
Simulation time 212897258 ps
CPU time 0.99 seconds
Started Jul 23 04:42:20 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 207764 kb
Host smart-9dd710f5-975a-4745-9995-c86ed74f1fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139973766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3139973766
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3191108218
Short name T201
Test name
Test status
Simulation time 17469180129 ps
CPU time 7.39 seconds
Started Jul 23 04:42:22 PM PDT 24
Finished Jul 23 04:42:58 PM PDT 24
Peak memory 233556 kb
Host smart-e84bbaeb-4c83-4a9e-b2ca-706cb29a9d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191108218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3191108218
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2456205630
Short name T442
Test name
Test status
Simulation time 13053625 ps
CPU time 0.7 seconds
Started Jul 23 04:42:21 PM PDT 24
Finished Jul 23 04:42:49 PM PDT 24
Peak memory 205964 kb
Host smart-33b275d0-7ef7-4d56-bb3e-3e697b781470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456205630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2456205630
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1812133013
Short name T537
Test name
Test status
Simulation time 4029437286 ps
CPU time 6.59 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 233580 kb
Host smart-5fce3070-3b23-4c79-b010-c42390b4df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812133013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1812133013
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.938174088
Short name T584
Test name
Test status
Simulation time 15344869 ps
CPU time 0.78 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:24 PM PDT 24
Peak memory 207444 kb
Host smart-ad930007-ba5e-4843-ad1c-9be2227b7278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938174088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.938174088
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1784265973
Short name T292
Test name
Test status
Simulation time 177917876292 ps
CPU time 286.51 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:48:10 PM PDT 24
Peak memory 257348 kb
Host smart-5494a5b5-ab5e-436d-b6f6-7696f688033d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784265973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1784265973
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3690196587
Short name T323
Test name
Test status
Simulation time 3457457001 ps
CPU time 31.29 seconds
Started Jul 23 04:42:24 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 240100 kb
Host smart-06275bc1-4246-427f-94e0-29eab13872f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690196587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3690196587
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3278140252
Short name T559
Test name
Test status
Simulation time 5485778492 ps
CPU time 59.64 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:44:09 PM PDT 24
Peak memory 253752 kb
Host smart-f3272bdd-ef1c-4788-a0d6-f121c142f826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278140252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3278140252
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.322760805
Short name T710
Test name
Test status
Simulation time 141744820 ps
CPU time 3.6 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 225400 kb
Host smart-a6f61a92-d483-4c81-9d75-0734cfc424d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322760805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.322760805
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1900725105
Short name T163
Test name
Test status
Simulation time 1396378402 ps
CPU time 28.98 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 251400 kb
Host smart-45cc0fd2-c664-49de-af55-ee6cf2225d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900725105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1900725105
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1174888021
Short name T604
Test name
Test status
Simulation time 282211544 ps
CPU time 3.32 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:56 PM PDT 24
Peak memory 225304 kb
Host smart-23460aa1-07f7-40a1-88be-100c3554300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174888021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1174888021
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1492323163
Short name T952
Test name
Test status
Simulation time 539822398 ps
CPU time 10.98 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:18 PM PDT 24
Peak memory 241436 kb
Host smart-006e5271-3051-4e2e-bef8-9e3b5a0b3713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492323163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1492323163
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1696787402
Short name T493
Test name
Test status
Simulation time 13828047155 ps
CPU time 14.55 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 233584 kb
Host smart-ae430638-6e9b-44a5-8248-798d0cb6adf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696787402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1696787402
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1475958832
Short name T721
Test name
Test status
Simulation time 20878594507 ps
CPU time 13.15 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 233576 kb
Host smart-6935f4bc-501a-41e4-a9c6-938b391b75dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475958832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1475958832
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.866990891
Short name T876
Test name
Test status
Simulation time 76040266 ps
CPU time 3.62 seconds
Started Jul 23 04:42:28 PM PDT 24
Finished Jul 23 04:43:16 PM PDT 24
Peak memory 223716 kb
Host smart-4e8574e1-12b1-421c-ba73-7b40a6db4f5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866990891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.866990891
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1951459413
Short name T969
Test name
Test status
Simulation time 273999708 ps
CPU time 0.97 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 207524 kb
Host smart-bf10bd79-5db0-4afb-b8ca-92811ff18b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951459413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1951459413
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1514956594
Short name T498
Test name
Test status
Simulation time 803639976 ps
CPU time 4.17 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:00 PM PDT 24
Peak memory 217172 kb
Host smart-6747ef7c-e8c6-4594-b4fc-6cb663664419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514956594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1514956594
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2666749410
Short name T974
Test name
Test status
Simulation time 1508732365 ps
CPU time 4.93 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:29 PM PDT 24
Peak memory 217064 kb
Host smart-75402e88-d2a3-4154-9510-ea681d40062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666749410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2666749410
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3614549694
Short name T625
Test name
Test status
Simulation time 45368190 ps
CPU time 1.43 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 217108 kb
Host smart-0885734e-301f-4b96-b9d6-fef5487c4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614549694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3614549694
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4077003895
Short name T84
Test name
Test status
Simulation time 65287327 ps
CPU time 0.72 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 206592 kb
Host smart-6659f562-c6cb-4d0e-bbdc-38e205e96e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077003895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4077003895
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.904407057
Short name T215
Test name
Test status
Simulation time 665191318 ps
CPU time 3.97 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:14 PM PDT 24
Peak memory 233520 kb
Host smart-16d05bd9-0bac-4de0-b072-dcaec5b5f838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904407057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.904407057
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3955656548
Short name T573
Test name
Test status
Simulation time 37234976 ps
CPU time 0.74 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:22 PM PDT 24
Peak memory 206004 kb
Host smart-4976079d-332c-4a8f-b177-140ec465854a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955656548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3955656548
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1536304084
Short name T256
Test name
Test status
Simulation time 245873682 ps
CPU time 5.26 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:27 PM PDT 24
Peak memory 233596 kb
Host smart-72ed07ba-e3a3-49f6-b1e8-17ddedbfe85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536304084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1536304084
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4000108442
Short name T405
Test name
Test status
Simulation time 16271937 ps
CPU time 0.76 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:22 PM PDT 24
Peak memory 206476 kb
Host smart-4e1e6cc2-0f3e-4b4b-9e81-3507321d67be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000108442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4000108442
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.107000584
Short name T656
Test name
Test status
Simulation time 532979856 ps
CPU time 12.66 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:27 PM PDT 24
Peak memory 241800 kb
Host smart-c064ffec-ebd7-497f-9314-3a1dd935630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107000584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.107000584
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1813111499
Short name T427
Test name
Test status
Simulation time 8500104889 ps
CPU time 18.5 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:40 PM PDT 24
Peak memory 225488 kb
Host smart-b1a2f8f7-d5f8-4a47-af9b-d23b28629023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813111499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1813111499
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.406693248
Short name T769
Test name
Test status
Simulation time 2169134174 ps
CPU time 38.18 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:50 PM PDT 24
Peak memory 249920 kb
Host smart-5d69b899-c3c9-4223-8890-63b904046c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406693248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.406693248
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2237871685
Short name T223
Test name
Test status
Simulation time 922282144 ps
CPU time 7.47 seconds
Started Jul 23 04:42:25 PM PDT 24
Finished Jul 23 04:43:11 PM PDT 24
Peak memory 225456 kb
Host smart-84ea7f32-b726-426d-a2ec-bf47400493a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237871685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2237871685
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.592712465
Short name T1021
Test name
Test status
Simulation time 54006079141 ps
CPU time 129.63 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:45:03 PM PDT 24
Peak memory 253712 kb
Host smart-b9bf16f5-e34b-4516-8f16-4e746392d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592712465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.592712465
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3086139892
Short name T57
Test name
Test status
Simulation time 3051998130 ps
CPU time 25.45 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 233660 kb
Host smart-7cadbbcb-1f20-4378-81f9-5073ccc06721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086139892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3086139892
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.413280513
Short name T883
Test name
Test status
Simulation time 5674683065 ps
CPU time 12.48 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:43:10 PM PDT 24
Peak memory 233648 kb
Host smart-6a637588-f9cf-41c4-81aa-ac78dc378d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413280513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.413280513
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3650116984
Short name T453
Test name
Test status
Simulation time 4087293269 ps
CPU time 4.52 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:10 PM PDT 24
Peak memory 225164 kb
Host smart-108981a9-aa6c-4e75-9e1f-92e8d19d805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650116984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3650116984
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1276489017
Short name T1020
Test name
Test status
Simulation time 27313178243 ps
CPU time 18.68 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:33 PM PDT 24
Peak memory 233680 kb
Host smart-ac12129f-fe4c-4f99-8da2-b89cfebbcf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276489017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1276489017
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.815180414
Short name T37
Test name
Test status
Simulation time 2112262514 ps
CPU time 10.67 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 220176 kb
Host smart-40a9ce6f-b5bf-4e26-bb86-e30c3713b11b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815180414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.815180414
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1475416520
Short name T316
Test name
Test status
Simulation time 62463850453 ps
CPU time 48.67 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:58 PM PDT 24
Peak memory 217168 kb
Host smart-243a6669-e5f9-4182-995c-93ea3d56280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475416520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1475416520
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2840043027
Short name T576
Test name
Test status
Simulation time 439786107 ps
CPU time 2.35 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 217112 kb
Host smart-b51aa1a0-95bf-42a1-89fa-00f849ea1486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840043027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2840043027
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1831104158
Short name T370
Test name
Test status
Simulation time 66300485 ps
CPU time 1.27 seconds
Started Jul 23 04:42:26 PM PDT 24
Finished Jul 23 04:43:07 PM PDT 24
Peak memory 216836 kb
Host smart-61087169-6081-4e22-b50d-f7f06a1131fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831104158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1831104158
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4038011921
Short name T24
Test name
Test status
Simulation time 106351201 ps
CPU time 0.76 seconds
Started Jul 23 04:42:23 PM PDT 24
Finished Jul 23 04:42:54 PM PDT 24
Peak memory 206692 kb
Host smart-24214500-6bbe-4aa0-b9f8-74b01e5e7909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038011921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4038011921
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3852490889
Short name T242
Test name
Test status
Simulation time 141925251 ps
CPU time 2.76 seconds
Started Jul 23 04:42:28 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 225412 kb
Host smart-c5ad3b3b-9f93-4669-8067-fb969174fcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852490889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3852490889
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1671175263
Short name T373
Test name
Test status
Simulation time 37655594 ps
CPU time 0.72 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:21 PM PDT 24
Peak memory 206376 kb
Host smart-5330e983-814d-44cb-b43a-3ffa549e3553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671175263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1671175263
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2445222895
Short name T230
Test name
Test status
Simulation time 277450460 ps
CPU time 2.36 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:34 PM PDT 24
Peak memory 225404 kb
Host smart-a772696a-b29b-417a-9e8b-96620fe5a840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445222895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2445222895
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1034306149
Short name T443
Test name
Test status
Simulation time 31191921 ps
CPU time 0.77 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:20 PM PDT 24
Peak memory 207172 kb
Host smart-269f8ee6-eaf0-4627-957d-f40a105e03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034306149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1034306149
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1932895607
Short name T917
Test name
Test status
Simulation time 97037931110 ps
CPU time 118.93 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:45:20 PM PDT 24
Peak memory 256424 kb
Host smart-7f5d6119-5965-42cb-a961-0e3d1339ccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932895607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1932895607
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1718445276
Short name T53
Test name
Test status
Simulation time 4571953404 ps
CPU time 18.91 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:41 PM PDT 24
Peak memory 241740 kb
Host smart-42d864b0-f529-48f8-9da0-f95988cf8bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718445276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1718445276
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3783064092
Short name T410
Test name
Test status
Simulation time 12224847336 ps
CPU time 113.61 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:45:26 PM PDT 24
Peak memory 258292 kb
Host smart-fa084a50-23e1-40ec-a541-72dc71f13537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783064092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3783064092
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4036394304
Short name T869
Test name
Test status
Simulation time 638495388 ps
CPU time 16.45 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 233632 kb
Host smart-64b7b088-96fb-4936-8e86-2ad7dd10ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036394304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4036394304
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.833997875
Short name T435
Test name
Test status
Simulation time 12449614206 ps
CPU time 90.13 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:44:48 PM PDT 24
Peak memory 254280 kb
Host smart-aab9d4c7-b241-4c3b-8455-6055d2ff47f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833997875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.833997875
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1950318024
Short name T652
Test name
Test status
Simulation time 341808351 ps
CPU time 4.58 seconds
Started Jul 23 04:42:28 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 233632 kb
Host smart-aaa40a2f-e31d-4216-b110-ce32cf940a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950318024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1950318024
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3891145906
Short name T574
Test name
Test status
Simulation time 8159268356 ps
CPU time 55.86 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:44:28 PM PDT 24
Peak memory 249476 kb
Host smart-50d2e2ec-5fb7-4f52-9c06-4ff79c843359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891145906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3891145906
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2360369972
Short name T425
Test name
Test status
Simulation time 31121789 ps
CPU time 2.28 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 233228 kb
Host smart-d16fd5ba-e836-4f39-a553-98d24b203aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360369972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2360369972
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3020427040
Short name T271
Test name
Test status
Simulation time 3107483296 ps
CPU time 11.38 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 233668 kb
Host smart-22441300-4fa1-4314-af87-012657d37581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020427040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3020427040
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1210305577
Short name T915
Test name
Test status
Simulation time 965505703 ps
CPU time 8 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:24 PM PDT 24
Peak memory 221148 kb
Host smart-f8f81b76-6215-4794-b519-ad752d8fbc22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1210305577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1210305577
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2742275495
Short name T596
Test name
Test status
Simulation time 63186373 ps
CPU time 1.09 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:19 PM PDT 24
Peak memory 208672 kb
Host smart-d1e59924-9092-435d-ac34-f9ea7dbcedc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742275495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2742275495
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.787826375
Short name T678
Test name
Test status
Simulation time 5453702074 ps
CPU time 8.67 seconds
Started Jul 23 04:42:27 PM PDT 24
Finished Jul 23 04:43:19 PM PDT 24
Peak memory 217244 kb
Host smart-82537977-367b-4c54-92f3-aef211ca4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787826375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.787826375
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3744456236
Short name T1014
Test name
Test status
Simulation time 1385372490 ps
CPU time 1.63 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:16 PM PDT 24
Peak memory 208700 kb
Host smart-2c71b59b-cefa-4f49-a43e-64f4b1174345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744456236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3744456236
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3290651176
Short name T965
Test name
Test status
Simulation time 51606319 ps
CPU time 1.22 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 208872 kb
Host smart-2a3ad095-bcf3-4a76-a748-fbd245fcc7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290651176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3290651176
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3688904418
Short name T507
Test name
Test status
Simulation time 142898372 ps
CPU time 0.79 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:19 PM PDT 24
Peak memory 206680 kb
Host smart-bd1d02a7-ba63-4f85-9973-6434972f2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688904418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3688904418
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1116250526
Short name T962
Test name
Test status
Simulation time 3162775719 ps
CPU time 7.82 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:24 PM PDT 24
Peak memory 225436 kb
Host smart-d10565ac-3e48-4b28-a39c-40e558ff58fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116250526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1116250526
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1725950507
Short name T677
Test name
Test status
Simulation time 43199857 ps
CPU time 0.74 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:33 PM PDT 24
Peak memory 205456 kb
Host smart-cc9402ad-ae8b-4b11-82c5-411c59b3502f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725950507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1725950507
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1003330825
Short name T577
Test name
Test status
Simulation time 320977566 ps
CPU time 4.01 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:36 PM PDT 24
Peak memory 225348 kb
Host smart-1a3f3940-2439-4298-8f26-b93fa028a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003330825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1003330825
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.185281585
Short name T933
Test name
Test status
Simulation time 41632872 ps
CPU time 0.78 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 206472 kb
Host smart-9728a079-c0ce-480c-8f59-2e0335adabbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185281585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.185281585
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3283526294
Short name T585
Test name
Test status
Simulation time 22452128273 ps
CPU time 180.87 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:46:33 PM PDT 24
Peak memory 256012 kb
Host smart-b846bd24-a4e7-43a9-a478-ad5e75e27c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283526294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3283526294
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1132142868
Short name T175
Test name
Test status
Simulation time 38554040761 ps
CPU time 395.57 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:49:58 PM PDT 24
Peak memory 260856 kb
Host smart-1d9a66ff-23e1-4c62-bc74-14ffff57b327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132142868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1132142868
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.22146183
Short name T189
Test name
Test status
Simulation time 21842980153 ps
CPU time 77.53 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:44:39 PM PDT 24
Peak memory 242020 kb
Host smart-c2966124-f181-442d-803a-5d63d5bb35ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22146183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.22146183
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.913145543
Short name T303
Test name
Test status
Simulation time 4997488419 ps
CPU time 32.52 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:55 PM PDT 24
Peak memory 225436 kb
Host smart-bad03aa4-30d4-45d1-a3f7-491c9df3a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913145543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.913145543
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.625487306
Short name T460
Test name
Test status
Simulation time 10592832157 ps
CPU time 80.53 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:44:39 PM PDT 24
Peak memory 241076 kb
Host smart-95f8b21b-e94d-49a3-9a87-d7309ee17ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625487306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.625487306
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2786233430
Short name T179
Test name
Test status
Simulation time 3720828578 ps
CPU time 30.65 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 233644 kb
Host smart-b8f62b99-8b16-44e9-9a57-b2c4360d48d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786233430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2786233430
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2211517395
Short name T760
Test name
Test status
Simulation time 681348997 ps
CPU time 17.22 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 250588 kb
Host smart-fa76dc87-63bd-4a30-879a-73ffd4388e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211517395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2211517395
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4107961863
Short name T609
Test name
Test status
Simulation time 1220928010 ps
CPU time 7.13 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 233636 kb
Host smart-6c7eb2a3-4f80-429f-8ebc-386f4b062320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107961863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4107961863
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1765916181
Short name T722
Test name
Test status
Simulation time 940472640 ps
CPU time 4.52 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:27 PM PDT 24
Peak memory 225356 kb
Host smart-88492ce0-329a-4ee6-ab3f-d0d401ff66c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765916181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1765916181
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2284315426
Short name T641
Test name
Test status
Simulation time 128472224 ps
CPU time 4.01 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 223356 kb
Host smart-78a70435-ac1f-4bfb-9fa3-c002e1ec7527
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284315426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2284315426
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3960932995
Short name T22
Test name
Test status
Simulation time 70365849 ps
CPU time 0.98 seconds
Started Jul 23 04:42:28 PM PDT 24
Finished Jul 23 04:43:13 PM PDT 24
Peak memory 207552 kb
Host smart-59046e2e-47ef-415f-9611-27a80d3c01e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960932995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3960932995
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3983271087
Short name T322
Test name
Test status
Simulation time 2517019284 ps
CPU time 17.29 seconds
Started Jul 23 04:42:34 PM PDT 24
Finished Jul 23 04:43:43 PM PDT 24
Peak memory 220804 kb
Host smart-39848129-b7fe-4944-9c29-e9665ef88f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983271087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3983271087
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.724233107
Short name T954
Test name
Test status
Simulation time 38544801 ps
CPU time 0.71 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 206280 kb
Host smart-96b2c55c-980a-4d1f-927e-d974ed6ef2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724233107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.724233107
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2751898534
Short name T605
Test name
Test status
Simulation time 12226808 ps
CPU time 0.71 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:18 PM PDT 24
Peak memory 206192 kb
Host smart-e86238aa-283c-4264-a932-dcd57b2e588d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751898534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2751898534
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2220148595
Short name T724
Test name
Test status
Simulation time 32084306 ps
CPU time 0.68 seconds
Started Jul 23 04:42:29 PM PDT 24
Finished Jul 23 04:43:17 PM PDT 24
Peak memory 206276 kb
Host smart-d68fb326-dd97-46f9-8041-06afb94edbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220148595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2220148595
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.477721391
Short name T599
Test name
Test status
Simulation time 9943190178 ps
CPU time 29.72 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:46 PM PDT 24
Peak memory 241560 kb
Host smart-3e6b0de9-0819-4734-ab35-21e7fb9d5b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477721391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.477721391
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1245794923
Short name T73
Test name
Test status
Simulation time 72611295 ps
CPU time 0.7 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:28 PM PDT 24
Peak memory 205412 kb
Host smart-30c5d78e-8069-45cb-a51b-ff31b2966bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245794923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1245794923
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4022982369
Short name T879
Test name
Test status
Simulation time 64217005 ps
CPU time 2.13 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:20 PM PDT 24
Peak memory 225320 kb
Host smart-30c993a6-1638-4a7e-8d03-bca4a2f00dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022982369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4022982369
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1436230302
Short name T989
Test name
Test status
Simulation time 17629728 ps
CPU time 0.76 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:24 PM PDT 24
Peak memory 207160 kb
Host smart-bf0b2bab-023e-4738-88d6-b7bf967403f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436230302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1436230302
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.634164216
Short name T357
Test name
Test status
Simulation time 7426807503 ps
CPU time 13.52 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:42 PM PDT 24
Peak memory 225364 kb
Host smart-76f1c31c-2c68-4a56-a8e4-eac75e3e64e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634164216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.634164216
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1599984680
Short name T434
Test name
Test status
Simulation time 59170961325 ps
CPU time 292.51 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:48:21 PM PDT 24
Peak memory 255152 kb
Host smart-a63ed4cc-8e10-4957-a374-82eee9943db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599984680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1599984680
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3901845075
Short name T465
Test name
Test status
Simulation time 28461233197 ps
CPU time 98.15 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:45:07 PM PDT 24
Peak memory 252428 kb
Host smart-cea4fbe0-939a-4efc-9122-fb5a83379070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901845075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3901845075
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2474975138
Short name T544
Test name
Test status
Simulation time 4371058684 ps
CPU time 52.08 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:44:20 PM PDT 24
Peak memory 250024 kb
Host smart-fd1b06d8-7411-4f43-9529-ed11e28f0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474975138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2474975138
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2845233443
Short name T243
Test name
Test status
Simulation time 456588818 ps
CPU time 5.14 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:37 PM PDT 24
Peak memory 233588 kb
Host smart-17ea29e0-da5a-4f5a-8111-9ec562a20766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845233443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2845233443
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2022439654
Short name T640
Test name
Test status
Simulation time 8763110563 ps
CPU time 65.28 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:44:34 PM PDT 24
Peak memory 233588 kb
Host smart-6cd9a6a4-2af6-406e-8af2-a59ad650efa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022439654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2022439654
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.253468451
Short name T629
Test name
Test status
Simulation time 795051513 ps
CPU time 5.48 seconds
Started Jul 23 04:42:30 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 225316 kb
Host smart-bc2caa5a-3341-42d0-8f9d-ca9324997083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253468451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.253468451
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4204831717
Short name T714
Test name
Test status
Simulation time 4570325662 ps
CPU time 14.55 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:35 PM PDT 24
Peak memory 241676 kb
Host smart-76cdce7d-8dc4-41fb-a8e1-a20803067353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204831717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4204831717
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3263521425
Short name T441
Test name
Test status
Simulation time 474391002 ps
CPU time 3.71 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 220672 kb
Host smart-b8d290a3-4199-48a7-bf53-790eda943a53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3263521425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3263521425
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3920402686
Short name T934
Test name
Test status
Simulation time 32506302753 ps
CPU time 296.93 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:48:18 PM PDT 24
Peak memory 250164 kb
Host smart-dfefe64f-e13f-4779-ac87-d333be543629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920402686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3920402686
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2988767347
Short name T658
Test name
Test status
Simulation time 711013813 ps
CPU time 2.89 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 217076 kb
Host smart-018cf2e3-5f73-4269-a101-a1eeadd31eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988767347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2988767347
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2861634964
Short name T695
Test name
Test status
Simulation time 3617082070 ps
CPU time 5.84 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 217052 kb
Host smart-08b411aa-b6a5-4343-b441-b3fb74fcd7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861634964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2861634964
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2960075950
Short name T766
Test name
Test status
Simulation time 18984381 ps
CPU time 0.75 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 206740 kb
Host smart-dc680630-2baf-42f3-ace9-2b190314105f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960075950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2960075950
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.515301488
Short name T385
Test name
Test status
Simulation time 139668406 ps
CPU time 0.93 seconds
Started Jul 23 04:42:32 PM PDT 24
Finished Jul 23 04:43:23 PM PDT 24
Peak memory 206660 kb
Host smart-6d9d9e28-3cbe-4d6e-b172-d88eb89cb1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515301488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.515301488
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3233235099
Short name T1011
Test name
Test status
Simulation time 3958931603 ps
CPU time 5.83 seconds
Started Jul 23 04:42:31 PM PDT 24
Finished Jul 23 04:43:27 PM PDT 24
Peak memory 233624 kb
Host smart-456a33e8-5590-4d44-a8f1-669aa0034aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233235099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3233235099
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2590559746
Short name T351
Test name
Test status
Simulation time 40550535 ps
CPU time 0.7 seconds
Started Jul 23 04:42:40 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 205900 kb
Host smart-5dd131ad-5392-4ff6-b80d-601b6555b591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590559746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2590559746
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2768332749
Short name T756
Test name
Test status
Simulation time 31565194 ps
CPU time 1.98 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 224884 kb
Host smart-d2d16669-7f12-48a9-a974-64c9491e5926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768332749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2768332749
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2252194336
Short name T1001
Test name
Test status
Simulation time 52447198 ps
CPU time 0.8 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:24 PM PDT 24
Peak memory 207580 kb
Host smart-498e3cc4-f166-4c93-a015-fa866ba28d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252194336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2252194336
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3988584203
Short name T713
Test name
Test status
Simulation time 31147559347 ps
CPU time 160.17 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:46:21 PM PDT 24
Peak memory 250032 kb
Host smart-4f24def8-7010-4625-bc1d-662a76379047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988584203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3988584203
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3377907977
Short name T759
Test name
Test status
Simulation time 78385422227 ps
CPU time 151.37 seconds
Started Jul 23 04:42:38 PM PDT 24
Finished Jul 23 04:46:02 PM PDT 24
Peak memory 255220 kb
Host smart-d4adb131-19e8-4dab-8c1d-f1f6cfbf9bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377907977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3377907977
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1932372557
Short name T306
Test name
Test status
Simulation time 1232307780 ps
CPU time 13.63 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:41 PM PDT 24
Peak memory 233576 kb
Host smart-9004778f-fae4-444d-843b-423574cb4af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932372557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1932372557
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1615537021
Short name T278
Test name
Test status
Simulation time 11199862126 ps
CPU time 38.13 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:44:19 PM PDT 24
Peak memory 238480 kb
Host smart-e53025b1-03dc-4cee-b001-86501bb23a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615537021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1615537021
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.207403936
Short name T757
Test name
Test status
Simulation time 503929686 ps
CPU time 2.89 seconds
Started Jul 23 04:42:35 PM PDT 24
Finished Jul 23 04:43:29 PM PDT 24
Peak memory 225344 kb
Host smart-e006f750-c186-4014-bf73-8553f852f0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207403936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.207403936
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1076669262
Short name T852
Test name
Test status
Simulation time 1505411494 ps
CPU time 5.5 seconds
Started Jul 23 04:42:35 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 233628 kb
Host smart-b1ca9ebd-477f-4f3c-b23e-e52443bb490f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076669262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1076669262
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2248478175
Short name T269
Test name
Test status
Simulation time 932305910 ps
CPU time 5.54 seconds
Started Jul 23 04:42:35 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 225264 kb
Host smart-a10c517a-cf46-465d-bb32-f25effb924c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248478175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2248478175
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3105731067
Short name T270
Test name
Test status
Simulation time 3608400993 ps
CPU time 13.42 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:40 PM PDT 24
Peak memory 253024 kb
Host smart-cbcb6ead-8503-42a7-9d44-533218341350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105731067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3105731067
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1120326778
Short name T945
Test name
Test status
Simulation time 677718731 ps
CPU time 4.84 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 221400 kb
Host smart-50655d95-f2b8-40bc-ac7e-f976d1881a6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1120326778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1120326778
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3648152410
Short name T19
Test name
Test status
Simulation time 4816490628 ps
CPU time 30.9 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 233288 kb
Host smart-0285b463-8ce4-4846-83cd-72fa4a6ab248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648152410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3648152410
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3611746083
Short name T321
Test name
Test status
Simulation time 14648248963 ps
CPU time 20.77 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:43:51 PM PDT 24
Peak memory 217040 kb
Host smart-870d6e45-4718-4743-9d27-ee21f94e3485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611746083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3611746083
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4174216769
Short name T82
Test name
Test status
Simulation time 13826502840 ps
CPU time 16.82 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 217016 kb
Host smart-33073c3b-b68b-447c-9ef7-7d97f13abd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174216769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4174216769
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2874528711
Short name T893
Test name
Test status
Simulation time 374493701 ps
CPU time 1.68 seconds
Started Jul 23 04:42:35 PM PDT 24
Finished Jul 23 04:43:28 PM PDT 24
Peak memory 217104 kb
Host smart-34b81380-22a0-4c20-bc6f-a62954f1f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874528711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2874528711
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.162646451
Short name T347
Test name
Test status
Simulation time 120158982 ps
CPU time 0.94 seconds
Started Jul 23 04:42:33 PM PDT 24
Finished Jul 23 04:43:25 PM PDT 24
Peak memory 206668 kb
Host smart-f0a658ec-d36c-425f-80e6-83d73ef79d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162646451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.162646451
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2598436060
Short name T233
Test name
Test status
Simulation time 2724277837 ps
CPU time 12.68 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:41 PM PDT 24
Peak memory 233576 kb
Host smart-206ed522-2500-4220-8129-938b61d593ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598436060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2598436060
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.275713522
Short name T366
Test name
Test status
Simulation time 44643196 ps
CPU time 0.71 seconds
Started Jul 23 04:43:06 PM PDT 24
Finished Jul 23 04:43:43 PM PDT 24
Peak memory 206036 kb
Host smart-6d0a459d-18ca-4a5c-8d2c-256d7e4cbb37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275713522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.275713522
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1306866259
Short name T470
Test name
Test status
Simulation time 31421793 ps
CPU time 2.21 seconds
Started Jul 23 04:43:15 PM PDT 24
Finished Jul 23 04:43:47 PM PDT 24
Peak memory 225364 kb
Host smart-a283e7b0-a144-4c9a-a9c3-1f59a0a2a36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306866259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1306866259
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1758094046
Short name T867
Test name
Test status
Simulation time 272543009 ps
CPU time 0.83 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 207144 kb
Host smart-662effee-9246-4420-a666-8701217fca3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758094046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1758094046
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2542173273
Short name T420
Test name
Test status
Simulation time 16358903214 ps
CPU time 130.33 seconds
Started Jul 23 04:43:14 PM PDT 24
Finished Jul 23 04:45:55 PM PDT 24
Peak memory 249976 kb
Host smart-4e598c8b-5025-41b3-ab77-ed4cea94f99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542173273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2542173273
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.916430553
Short name T207
Test name
Test status
Simulation time 3521991634 ps
CPU time 58.47 seconds
Started Jul 23 04:42:38 PM PDT 24
Finished Jul 23 04:44:28 PM PDT 24
Peak memory 250108 kb
Host smart-e1798f78-f2a5-4c97-a11a-f2927cd9f148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916430553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.916430553
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2994154378
Short name T31
Test name
Test status
Simulation time 97287107120 ps
CPU time 175.16 seconds
Started Jul 23 04:42:40 PM PDT 24
Finished Jul 23 04:46:26 PM PDT 24
Peak memory 241948 kb
Host smart-335f5cc5-18f5-446e-8bdd-ade931b0631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994154378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2994154378
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.4156692767
Short name T395
Test name
Test status
Simulation time 437621075 ps
CPU time 2.86 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 225392 kb
Host smart-80708026-a890-4add-a0d8-046a92712c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156692767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.4156692767
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3798739714
Short name T738
Test name
Test status
Simulation time 11522468 ps
CPU time 0.77 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:30 PM PDT 24
Peak memory 216640 kb
Host smart-3e5b8e75-b013-490d-81f4-8b885d38dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798739714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3798739714
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2334158059
Short name T889
Test name
Test status
Simulation time 1154072771 ps
CPU time 12.8 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:43:54 PM PDT 24
Peak memory 219664 kb
Host smart-8fcbd7a4-6863-4798-987e-4eb4f445ccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334158059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2334158059
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.640592413
Short name T236
Test name
Test status
Simulation time 6763105733 ps
CPU time 24.68 seconds
Started Jul 23 04:42:47 PM PDT 24
Finished Jul 23 04:43:59 PM PDT 24
Peak memory 250268 kb
Host smart-aa9c2fc0-a75c-43cc-9954-d72c89e8907a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640592413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.640592413
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.156337290
Short name T261
Test name
Test status
Simulation time 1343149509 ps
CPU time 3.74 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:43:34 PM PDT 24
Peak memory 233608 kb
Host smart-01e879e6-ff6d-4332-8102-dfc88cbc172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156337290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.156337290
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3422784840
Short name T258
Test name
Test status
Simulation time 43865925127 ps
CPU time 30 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:44:01 PM PDT 24
Peak memory 225476 kb
Host smart-f9b57795-cf46-4ff6-8bc4-0576e3711cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422784840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3422784840
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2059577591
Short name T390
Test name
Test status
Simulation time 5763120803 ps
CPU time 8.28 seconds
Started Jul 23 04:44:25 PM PDT 24
Finished Jul 23 04:44:39 PM PDT 24
Peak memory 221716 kb
Host smart-ad5bf94a-0f41-4ffd-9b38-06f71ee60f96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059577591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2059577591
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1475950156
Short name T528
Test name
Test status
Simulation time 4190213480 ps
CPU time 10.2 seconds
Started Jul 23 04:42:36 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 217272 kb
Host smart-d6800f8b-f1e4-4483-b12f-1df87fdd7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475950156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1475950156
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.141714479
Short name T679
Test name
Test status
Simulation time 8291742672 ps
CPU time 8.49 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:36 PM PDT 24
Peak memory 217176 kb
Host smart-bb453257-37d1-4275-b234-ae6f1727f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141714479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.141714479
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2509997849
Short name T667
Test name
Test status
Simulation time 69500362 ps
CPU time 1.02 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 207716 kb
Host smart-00e0e360-f121-46fc-9cea-f8c6202360f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509997849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2509997849
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3532957894
Short name T690
Test name
Test status
Simulation time 30695022 ps
CPU time 0.81 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 206820 kb
Host smart-fe9da4d6-5631-4a50-ae71-394337e994e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532957894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3532957894
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1286008846
Short name T477
Test name
Test status
Simulation time 468253912 ps
CPU time 6.66 seconds
Started Jul 23 04:42:38 PM PDT 24
Finished Jul 23 04:43:36 PM PDT 24
Peak memory 241748 kb
Host smart-6523207e-591b-4a74-9afe-9227a70f4f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286008846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1286008846
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.267193189
Short name T901
Test name
Test status
Simulation time 29694418 ps
CPU time 0.7 seconds
Started Jul 23 04:42:43 PM PDT 24
Finished Jul 23 04:43:33 PM PDT 24
Peak memory 206028 kb
Host smart-d8675186-27be-4873-90af-d0d6fb8dee91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267193189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.267193189
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.773518068
Short name T511
Test name
Test status
Simulation time 2059184768 ps
CPU time 19.12 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 233584 kb
Host smart-a5a37851-d4f0-4465-b3d8-84cf004c0855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773518068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.773518068
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3402990936
Short name T985
Test name
Test status
Simulation time 16212501 ps
CPU time 0.76 seconds
Started Jul 23 04:42:43 PM PDT 24
Finished Jul 23 04:43:33 PM PDT 24
Peak memory 206168 kb
Host smart-e3be0417-d92c-49d6-a840-d9269cb6023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402990936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3402990936
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2221193561
Short name T560
Test name
Test status
Simulation time 1047417302 ps
CPU time 4.74 seconds
Started Jul 23 04:42:56 PM PDT 24
Finished Jul 23 04:43:43 PM PDT 24
Peak memory 235760 kb
Host smart-e408b026-f9ac-46d5-8a4f-fdd63b3a87c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221193561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2221193561
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2217800140
Short name T188
Test name
Test status
Simulation time 19423094356 ps
CPU time 229.47 seconds
Started Jul 23 04:42:44 PM PDT 24
Finished Jul 23 04:47:22 PM PDT 24
Peak memory 266076 kb
Host smart-3813ed22-7ae5-4fef-973e-ead3f855ab9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217800140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2217800140
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2739441816
Short name T479
Test name
Test status
Simulation time 440826092 ps
CPU time 7.53 seconds
Started Jul 23 04:43:05 PM PDT 24
Finished Jul 23 04:43:49 PM PDT 24
Peak memory 233584 kb
Host smart-9fdfb1f9-bd6a-4d1d-b546-537c7c557425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739441816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2739441816
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2921518944
Short name T712
Test name
Test status
Simulation time 7897611443 ps
CPU time 53 seconds
Started Jul 23 04:42:50 PM PDT 24
Finished Jul 23 04:44:28 PM PDT 24
Peak memory 240804 kb
Host smart-fdc21c01-c090-4523-b1de-a6874defaac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921518944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2921518944
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1811053350
Short name T739
Test name
Test status
Simulation time 369005862 ps
CPU time 3.37 seconds
Started Jul 23 04:42:52 PM PDT 24
Finished Jul 23 04:43:40 PM PDT 24
Peak memory 225344 kb
Host smart-cb63c679-9c0f-4131-af94-bd20685469f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811053350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1811053350
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1646004538
Short name T1012
Test name
Test status
Simulation time 2048483897 ps
CPU time 20.43 seconds
Started Jul 23 04:42:41 PM PDT 24
Finished Jul 23 04:43:52 PM PDT 24
Peak memory 225360 kb
Host smart-aa8fa2b6-65db-44a1-bc28-a5809f5616fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646004538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1646004538
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.45151402
Short name T617
Test name
Test status
Simulation time 3870836079 ps
CPU time 13.55 seconds
Started Jul 23 04:42:37 PM PDT 24
Finished Jul 23 04:43:42 PM PDT 24
Peak memory 233652 kb
Host smart-478c3f80-a50d-4c51-9a02-82b6a36e2103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45151402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.45151402
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3615678847
Short name T732
Test name
Test status
Simulation time 1854868431 ps
CPU time 8.1 seconds
Started Jul 23 04:42:38 PM PDT 24
Finished Jul 23 04:43:38 PM PDT 24
Peak memory 241556 kb
Host smart-f82b3d6d-4c36-48b3-ac6e-6eeac8d32e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615678847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3615678847
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.615309380
Short name T450
Test name
Test status
Simulation time 9549223991 ps
CPU time 6.08 seconds
Started Jul 23 04:42:45 PM PDT 24
Finished Jul 23 04:43:39 PM PDT 24
Peak memory 223996 kb
Host smart-6c04378e-e06d-44e0-8e55-17336cd4e5b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615309380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.615309380
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3479970373
Short name T799
Test name
Test status
Simulation time 787873871 ps
CPU time 7.63 seconds
Started Jul 23 04:42:42 PM PDT 24
Finished Jul 23 04:43:40 PM PDT 24
Peak memory 220688 kb
Host smart-1ba06077-8c83-4cdb-8fd7-6f2d692d4768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479970373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3479970373
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2879551993
Short name T375
Test name
Test status
Simulation time 7318208870 ps
CPU time 13.99 seconds
Started Jul 23 04:42:39 PM PDT 24
Finished Jul 23 04:43:44 PM PDT 24
Peak memory 217216 kb
Host smart-f755c836-24ee-4299-8458-0692bd196f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879551993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2879551993
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2732919455
Short name T406
Test name
Test status
Simulation time 237404885 ps
CPU time 1.93 seconds
Started Jul 23 04:42:38 PM PDT 24
Finished Jul 23 04:43:31 PM PDT 24
Peak memory 217156 kb
Host smart-b453c6fa-a90e-4555-aaec-281edcc0c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732919455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2732919455
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.128133264
Short name T541
Test name
Test status
Simulation time 52168173 ps
CPU time 0.9 seconds
Started Jul 23 04:42:40 PM PDT 24
Finished Jul 23 04:43:32 PM PDT 24
Peak memory 206644 kb
Host smart-0e767a0a-ce5a-4953-b52c-34322fd9b662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128133264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.128133264
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1127482328
Short name T44
Test name
Test status
Simulation time 2814007414 ps
CPU time 7.55 seconds
Started Jul 23 04:43:04 PM PDT 24
Finished Jul 23 04:43:49 PM PDT 24
Peak memory 225320 kb
Host smart-7741f6de-4ed5-4f26-99d7-80cda1a047e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127482328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1127482328
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2018513347
Short name T517
Test name
Test status
Simulation time 14247468 ps
CPU time 0.7 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 206248 kb
Host smart-32412464-ebe6-4e37-9515-26b32dc7f97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018513347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
018513347
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3153369943
Short name T991
Test name
Test status
Simulation time 2348187313 ps
CPU time 23.42 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:50 PM PDT 24
Peak memory 233556 kb
Host smart-cbfd6638-3e0b-43c1-a8b6-716a28ed28a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153369943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3153369943
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3187927552
Short name T838
Test name
Test status
Simulation time 148494934 ps
CPU time 0.81 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:28 PM PDT 24
Peak memory 207160 kb
Host smart-105791ad-c705-40c1-8f20-20d79dc38f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187927552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3187927552
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1980405359
Short name T50
Test name
Test status
Simulation time 594278556 ps
CPU time 4.71 seconds
Started Jul 23 04:40:30 PM PDT 24
Finished Jul 23 04:40:36 PM PDT 24
Peak memory 241724 kb
Host smart-46e4e256-26b7-4222-8fd8-2f06f7e8e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980405359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1980405359
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2993005989
Short name T489
Test name
Test status
Simulation time 15444829756 ps
CPU time 39.75 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:41:18 PM PDT 24
Peak memory 238288 kb
Host smart-18e61905-7e70-4559-bea1-30b398623aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993005989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2993005989
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4198303949
Short name T543
Test name
Test status
Simulation time 17954337128 ps
CPU time 59.7 seconds
Started Jul 23 04:40:29 PM PDT 24
Finished Jul 23 04:41:30 PM PDT 24
Peak memory 256668 kb
Host smart-5cb70dfb-8765-4943-a1f9-6039cfa7ba06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198303949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4198303949
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3893223120
Short name T758
Test name
Test status
Simulation time 741526275 ps
CPU time 5.36 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:30 PM PDT 24
Peak memory 233636 kb
Host smart-b4bfc759-5b7c-487e-a903-27225f9916c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893223120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3893223120
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1192183714
Short name T665
Test name
Test status
Simulation time 9880878131 ps
CPU time 59.4 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:41:37 PM PDT 24
Peak memory 241760 kb
Host smart-e5bf8836-1a4a-404a-babf-5d7652a46456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192183714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1192183714
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1985550002
Short name T1025
Test name
Test status
Simulation time 107421681 ps
CPU time 2.41 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:40:40 PM PDT 24
Peak memory 233156 kb
Host smart-c7dd2a8a-1186-469d-a92a-684306421f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985550002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1985550002
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1034432937
Short name T960
Test name
Test status
Simulation time 361353540 ps
CPU time 9.03 seconds
Started Jul 23 04:40:28 PM PDT 24
Finished Jul 23 04:40:39 PM PDT 24
Peak memory 239952 kb
Host smart-726c8c30-b416-4003-9453-abf33466c2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034432937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1034432937
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2779591738
Short name T633
Test name
Test status
Simulation time 26362026 ps
CPU time 1.07 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:26 PM PDT 24
Peak memory 217336 kb
Host smart-16bcb8fc-2ba1-471e-8b5b-6fc45773653c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779591738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2779591738
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2801594202
Short name T568
Test name
Test status
Simulation time 115362657 ps
CPU time 2.43 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 225368 kb
Host smart-4cd4b106-921b-445e-9fcd-dd6ac77874fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801594202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2801594202
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.794922369
Short name T252
Test name
Test status
Simulation time 2437689477 ps
CPU time 5.69 seconds
Started Jul 23 04:40:36 PM PDT 24
Finished Jul 23 04:40:44 PM PDT 24
Peak memory 233568 kb
Host smart-c8625f02-408f-4e4e-9701-fe3cce6a9f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794922369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.794922369
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.851499171
Short name T396
Test name
Test status
Simulation time 93180664 ps
CPU time 3.99 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 221396 kb
Host smart-1dae6cd6-01e2-49d0-baac-fc12eedec5e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=851499171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.851499171
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2212981747
Short name T639
Test name
Test status
Simulation time 5380247751 ps
CPU time 14.38 seconds
Started Jul 23 04:40:25 PM PDT 24
Finished Jul 23 04:40:42 PM PDT 24
Peak memory 217268 kb
Host smart-8b8f7cb6-c046-4b87-879f-87bbd5848f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212981747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2212981747
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.497522264
Short name T369
Test name
Test status
Simulation time 904627528 ps
CPU time 4.14 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 217060 kb
Host smart-c29b3c99-2f6b-4b18-b229-9fc5057dca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497522264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.497522264
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2809944053
Short name T899
Test name
Test status
Simulation time 64994633 ps
CPU time 1.2 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:40:39 PM PDT 24
Peak memory 217040 kb
Host smart-ce572fee-7292-4002-a60e-c1fa48a058c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809944053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2809944053
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1988445144
Short name T23
Test name
Test status
Simulation time 133866533 ps
CPU time 0.84 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:40:25 PM PDT 24
Peak memory 206768 kb
Host smart-43631f05-6880-448a-87b1-ece0843baa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988445144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1988445144
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2767251515
Short name T372
Test name
Test status
Simulation time 969113882 ps
CPU time 4.83 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:31 PM PDT 24
Peak memory 220464 kb
Host smart-e453cd63-c66c-422a-870c-dae15b02cdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767251515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2767251515
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3690612711
Short name T569
Test name
Test status
Simulation time 12342929 ps
CPU time 0.71 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:46 PM PDT 24
Peak memory 206312 kb
Host smart-c7e1f4c4-cc62-4f28-9f31-6d429ad0ea0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690612711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
690612711
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3988937142
Short name T234
Test name
Test status
Simulation time 129889672 ps
CPU time 3.59 seconds
Started Jul 23 04:40:30 PM PDT 24
Finished Jul 23 04:40:35 PM PDT 24
Peak memory 225300 kb
Host smart-a9077e03-4f27-4905-a395-7ddb87ea8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988937142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3988937142
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2688696220
Short name T988
Test name
Test status
Simulation time 49692513 ps
CPU time 0.83 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:27 PM PDT 24
Peak memory 207460 kb
Host smart-52fcb24e-13ac-42c9-893c-d4377bf47822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688696220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2688696220
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2038859048
Short name T54
Test name
Test status
Simulation time 11547259499 ps
CPU time 74.04 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:42:00 PM PDT 24
Peak memory 250104 kb
Host smart-23da3e79-7062-4928-9471-ccb3ceae0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038859048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2038859048
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1827605561
Short name T221
Test name
Test status
Simulation time 173243255 ps
CPU time 3.89 seconds
Started Jul 23 04:40:31 PM PDT 24
Finished Jul 23 04:40:36 PM PDT 24
Peak memory 225288 kb
Host smart-0dbbe2e1-e21a-440d-a6e0-94ff6248ef58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827605561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1827605561
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1010296317
Short name T198
Test name
Test status
Simulation time 13552587659 ps
CPU time 70.67 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 264576 kb
Host smart-7f13116f-a843-45fe-927a-64c222ced144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010296317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1010296317
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3494704873
Short name T492
Test name
Test status
Simulation time 1845612886 ps
CPU time 18.4 seconds
Started Jul 23 04:40:32 PM PDT 24
Finished Jul 23 04:40:51 PM PDT 24
Peak memory 233448 kb
Host smart-dce6198b-ffb2-4b32-8133-e6b35fa0d3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494704873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3494704873
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.633850240
Short name T213
Test name
Test status
Simulation time 15307044986 ps
CPU time 141.43 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:42:47 PM PDT 24
Peak memory 240804 kb
Host smart-ae302c50-1be4-4e4f-8c30-9718ad2f0aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633850240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.633850240
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.574306064
Short name T622
Test name
Test status
Simulation time 45357396 ps
CPU time 1.09 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:27 PM PDT 24
Peak memory 217304 kb
Host smart-f4424dab-4149-48a8-81fe-4c0bed5950f3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574306064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.574306064
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.12450176
Short name T72
Test name
Test status
Simulation time 33133434 ps
CPU time 2.41 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 233188 kb
Host smart-8bb4730f-2e0a-49b8-a882-109282597cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12450176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.12450176
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2795966427
Short name T358
Test name
Test status
Simulation time 1307705201 ps
CPU time 3.61 seconds
Started Jul 23 04:40:30 PM PDT 24
Finished Jul 23 04:40:35 PM PDT 24
Peak memory 225276 kb
Host smart-83507a72-b8e4-449f-a923-694ca98eab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795966427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2795966427
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1957175249
Short name T903
Test name
Test status
Simulation time 2047590761 ps
CPU time 6.84 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 219844 kb
Host smart-66a28a58-cad4-4ec1-8cd1-295f9806138d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957175249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1957175249
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.809031039
Short name T786
Test name
Test status
Simulation time 40582211 ps
CPU time 1.01 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:45 PM PDT 24
Peak memory 208628 kb
Host smart-a91c767d-26a4-4f3d-9912-1b12b1a9bf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809031039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.809031039
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.275614196
Short name T902
Test name
Test status
Simulation time 1519468440 ps
CPU time 19.47 seconds
Started Jul 23 04:40:32 PM PDT 24
Finished Jul 23 04:40:53 PM PDT 24
Peak memory 217276 kb
Host smart-7864cf7a-fcc4-4bed-bba1-5af651ec03d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275614196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.275614196
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3457357742
Short name T806
Test name
Test status
Simulation time 2128014051 ps
CPU time 8.05 seconds
Started Jul 23 04:40:24 PM PDT 24
Finished Jul 23 04:40:34 PM PDT 24
Peak memory 217344 kb
Host smart-d5f5f657-2a8d-41ac-a26b-b5905c26a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457357742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3457357742
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1618614142
Short name T326
Test name
Test status
Simulation time 381108073 ps
CPU time 12.9 seconds
Started Jul 23 04:40:31 PM PDT 24
Finished Jul 23 04:40:45 PM PDT 24
Peak memory 216956 kb
Host smart-c0d55c26-3a33-45cd-8ec6-1981717fc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618614142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1618614142
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.980976923
Short name T856
Test name
Test status
Simulation time 56769878 ps
CPU time 0.74 seconds
Started Jul 23 04:40:23 PM PDT 24
Finished Jul 23 04:40:27 PM PDT 24
Peak memory 206704 kb
Host smart-ef1fcbdf-35b0-4ea2-a848-e2b66707a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980976923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.980976923
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1903299800
Short name T593
Test name
Test status
Simulation time 1075070596 ps
CPU time 6.37 seconds
Started Jul 23 04:40:22 PM PDT 24
Finished Jul 23 04:40:29 PM PDT 24
Peak memory 233600 kb
Host smart-4b718460-fd07-4ea1-a901-83f339a1094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903299800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1903299800
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.321236025
Short name T926
Test name
Test status
Simulation time 15256211 ps
CPU time 0.78 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 206028 kb
Host smart-c29b2a98-1b99-4825-b81f-22455eded4f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321236025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.321236025
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3835326276
Short name T936
Test name
Test status
Simulation time 885043338 ps
CPU time 3.81 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:40:42 PM PDT 24
Peak memory 233452 kb
Host smart-4c686694-7452-4d5d-94df-75630af6fc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835326276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3835326276
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1721372653
Short name T675
Test name
Test status
Simulation time 173437194 ps
CPU time 0.81 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:44 PM PDT 24
Peak memory 207204 kb
Host smart-0b13ede4-e824-4e72-9ccf-4b987509dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721372653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1721372653
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3332170538
Short name T500
Test name
Test status
Simulation time 30807498398 ps
CPU time 119.02 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:42:41 PM PDT 24
Peak memory 250128 kb
Host smart-fd3b6352-3448-42ef-bb55-c6e78e9ee239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332170538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3332170538
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.264576680
Short name T562
Test name
Test status
Simulation time 81616074605 ps
CPU time 183.64 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:43:48 PM PDT 24
Peak memory 250060 kb
Host smart-a9d07daa-0fa4-418c-9680-51bc8d2f3640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264576680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.264576680
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1534802850
Short name T801
Test name
Test status
Simulation time 3121328213 ps
CPU time 70 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:55 PM PDT 24
Peak memory 257388 kb
Host smart-a3d56420-f14a-4bcd-8e58-937b6fc8ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534802850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1534802850
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2114123143
Short name T993
Test name
Test status
Simulation time 201782732 ps
CPU time 2.77 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:49 PM PDT 24
Peak memory 233484 kb
Host smart-36ecdf62-78ed-4da8-970c-8c6a271c4cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114123143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2114123143
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1513292480
Short name T935
Test name
Test status
Simulation time 7742637321 ps
CPU time 48.28 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:41:28 PM PDT 24
Peak memory 257056 kb
Host smart-6f7c95f0-0d64-45f7-a806-ee1a3eb7ed3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513292480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1513292480
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4067946656
Short name T971
Test name
Test status
Simulation time 3190699155 ps
CPU time 19.03 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 225400 kb
Host smart-313d1c1e-9a4e-4d8e-9871-75b5ffbd36f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067946656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4067946656
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1370983019
Short name T1003
Test name
Test status
Simulation time 111389939517 ps
CPU time 51.79 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:36 PM PDT 24
Peak memory 241756 kb
Host smart-7b800eb1-5de5-42b3-b509-d1e1a9fea8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370983019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1370983019
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4256504820
Short name T542
Test name
Test status
Simulation time 34447580 ps
CPU time 1.09 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:40 PM PDT 24
Peak memory 217356 kb
Host smart-8bdcff6f-230c-4fd1-974f-13fe8cc5555e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256504820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4256504820
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2663890395
Short name T197
Test name
Test status
Simulation time 209981322 ps
CPU time 4.25 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 225376 kb
Host smart-78290fe1-d9d4-47fb-bb4e-c64c71fa6235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663890395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2663890395
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2374199753
Short name T251
Test name
Test status
Simulation time 3897995062 ps
CPU time 11 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:40:50 PM PDT 24
Peak memory 225496 kb
Host smart-a5303506-6c3e-48fc-a31f-bcbf6b330e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374199753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2374199753
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.4020118186
Short name T436
Test name
Test status
Simulation time 550582177 ps
CPU time 4.27 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:46 PM PDT 24
Peak memory 219956 kb
Host smart-a40b9c22-b676-4e17-9c69-a2e3fceb58ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4020118186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.4020118186
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4169473172
Short name T18
Test name
Test status
Simulation time 44630151547 ps
CPU time 385.66 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:47:07 PM PDT 24
Peak memory 254292 kb
Host smart-2cc8157b-7f22-4686-a603-13f4d0a3ac8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169473172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4169473172
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2476543646
Short name T840
Test name
Test status
Simulation time 893924412 ps
CPU time 10.98 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:53 PM PDT 24
Peak memory 217144 kb
Host smart-4bb4b534-80cf-4929-bb40-bfb6caf154ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476543646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2476543646
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1225616648
Short name T905
Test name
Test status
Simulation time 13196683044 ps
CPU time 16.33 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:56 PM PDT 24
Peak memory 217204 kb
Host smart-c4a0caf4-892c-44d9-846d-3c47c8cb80dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225616648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1225616648
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4273731696
Short name T711
Test name
Test status
Simulation time 50930610 ps
CPU time 0.82 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:45 PM PDT 24
Peak memory 207592 kb
Host smart-cf45424e-7112-4303-babd-4c30cdd9899a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273731696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4273731696
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3204508848
Short name T458
Test name
Test status
Simulation time 20696012 ps
CPU time 0.76 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:46 PM PDT 24
Peak memory 206676 kb
Host smart-dcde6bf6-ae77-482d-b39f-eb3c3663b8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204508848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3204508848
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1930537605
Short name T666
Test name
Test status
Simulation time 11256251732 ps
CPU time 9.73 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:55 PM PDT 24
Peak memory 233604 kb
Host smart-c1315a36-44de-4263-a1d0-1c1cfd1c0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930537605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1930537605
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3341200237
Short name T1006
Test name
Test status
Simulation time 158536519 ps
CPU time 0.71 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:40:39 PM PDT 24
Peak memory 205412 kb
Host smart-07652ee5-d929-472f-8134-99b610ec8c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341200237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
341200237
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3757539530
Short name T567
Test name
Test status
Simulation time 6101910898 ps
CPU time 15.25 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:55 PM PDT 24
Peak memory 233528 kb
Host smart-43f5c59b-0a4b-4521-811e-0e57106a0838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757539530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3757539530
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.940238571
Short name T332
Test name
Test status
Simulation time 54467473 ps
CPU time 0.79 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 207132 kb
Host smart-28c250c0-c38b-495e-b1de-30f96fb53cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940238571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.940238571
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2797873498
Short name T199
Test name
Test status
Simulation time 90194923314 ps
CPU time 147.13 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:43:13 PM PDT 24
Peak memory 239504 kb
Host smart-b729c65f-0af5-44f3-8b89-27c0d4b5d187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797873498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2797873498
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.724544334
Short name T736
Test name
Test status
Simulation time 4403317714 ps
CPU time 27.54 seconds
Started Jul 23 04:40:42 PM PDT 24
Finished Jul 23 04:41:14 PM PDT 24
Peak memory 241332 kb
Host smart-5a9a28cd-9f2a-4dcc-b42c-77138ba4d3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724544334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
724544334
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3182371902
Short name T897
Test name
Test status
Simulation time 2545172250 ps
CPU time 26.22 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:41:04 PM PDT 24
Peak memory 241844 kb
Host smart-ccd7547f-3707-4d3e-92f3-e6b544ba28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182371902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3182371902
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2544355730
Short name T964
Test name
Test status
Simulation time 8888459548 ps
CPU time 17.65 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:02 PM PDT 24
Peak memory 225444 kb
Host smart-97d6175f-b7e1-4e77-9b43-a7d35c871486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544355730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2544355730
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1150623251
Short name T510
Test name
Test status
Simulation time 25683900537 ps
CPU time 46.77 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:41:29 PM PDT 24
Peak memory 249980 kb
Host smart-0e81a59e-4a73-48b3-a7f1-3eb3fb7e78c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150623251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1150623251
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1089710363
Short name T990
Test name
Test status
Simulation time 54511302 ps
CPU time 1.24 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 217328 kb
Host smart-5877fa48-6e36-4132-a705-b252deda4941
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089710363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1089710363
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1499562870
Short name T762
Test name
Test status
Simulation time 1599953874 ps
CPU time 9.15 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:51 PM PDT 24
Peak memory 233568 kb
Host smart-42a58762-9ab0-4cd9-b654-c921b6a62a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499562870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1499562870
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1409058511
Short name T475
Test name
Test status
Simulation time 572246275 ps
CPU time 2.86 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:48 PM PDT 24
Peak memory 225312 kb
Host smart-47ac3dbe-fc15-4c58-be30-7f985d50a1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409058511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1409058511
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2264834837
Short name T772
Test name
Test status
Simulation time 4284738221 ps
CPU time 9.96 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 220212 kb
Host smart-c1ba2dbc-5ab0-4cad-ae3e-fa465f6292e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2264834837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2264834837
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3357073574
Short name T254
Test name
Test status
Simulation time 16254216711 ps
CPU time 117.68 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:42:42 PM PDT 24
Peak memory 266648 kb
Host smart-a9356f71-0bc5-4660-8b77-a3c350a26c9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357073574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3357073574
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2213661691
Short name T47
Test name
Test status
Simulation time 5006241070 ps
CPU time 14.46 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:57 PM PDT 24
Peak memory 217148 kb
Host smart-3b499e01-31f1-48c3-81fe-a20a09092fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213661691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2213661691
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3147512475
Short name T657
Test name
Test status
Simulation time 28150779869 ps
CPU time 17.14 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:41:03 PM PDT 24
Peak memory 218344 kb
Host smart-3caa5721-0a12-4e38-950c-e8000e208646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147512475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3147512475
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3078384225
Short name T645
Test name
Test status
Simulation time 81159781 ps
CPU time 0.81 seconds
Started Jul 23 04:40:35 PM PDT 24
Finished Jul 23 04:40:36 PM PDT 24
Peak memory 206640 kb
Host smart-677c34a3-1964-44fc-94a1-bff14c623c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078384225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3078384225
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1155525324
Short name T624
Test name
Test status
Simulation time 98242804 ps
CPU time 0.8 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 206664 kb
Host smart-e36e8b26-d719-4a09-b197-7cabd95c90a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155525324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1155525324
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.251567570
Short name T833
Test name
Test status
Simulation time 8580262174 ps
CPU time 9.22 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:54 PM PDT 24
Peak memory 225460 kb
Host smart-53e9003d-42f3-4d0c-9e74-376f808cca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251567570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.251567570
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4018282430
Short name T547
Test name
Test status
Simulation time 50790560 ps
CPU time 0.73 seconds
Started Jul 23 04:40:46 PM PDT 24
Finished Jul 23 04:40:49 PM PDT 24
Peak memory 205880 kb
Host smart-903551c2-0426-4d84-a276-525de09a9d15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018282430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
018282430
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.868092573
Short name T165
Test name
Test status
Simulation time 3844913380 ps
CPU time 15.65 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:00 PM PDT 24
Peak memory 225180 kb
Host smart-da6db843-7266-436d-85bf-8993026b7c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868092573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.868092573
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4246405765
Short name T365
Test name
Test status
Simulation time 42466682 ps
CPU time 0.82 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:45 PM PDT 24
Peak memory 206164 kb
Host smart-736412f1-b89d-45db-9b34-6481634ce165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246405765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4246405765
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4154459437
Short name T317
Test name
Test status
Simulation time 10050774650 ps
CPU time 68.32 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:41:52 PM PDT 24
Peak memory 257784 kb
Host smart-f4b4af9c-a3e9-4f5f-b3fe-6a6b625fb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154459437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4154459437
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3436373397
Short name T52
Test name
Test status
Simulation time 23600251810 ps
CPU time 93.42 seconds
Started Jul 23 04:40:46 PM PDT 24
Finished Jul 23 04:42:21 PM PDT 24
Peak memory 256596 kb
Host smart-bf132db9-d418-468b-92d6-e080aa3964c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436373397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3436373397
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1751305832
Short name T462
Test name
Test status
Simulation time 1120612746 ps
CPU time 12.68 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:58 PM PDT 24
Peak memory 250036 kb
Host smart-7dd86e98-eb6d-4f0d-82c9-57b4fdef71c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751305832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1751305832
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.679920417
Short name T873
Test name
Test status
Simulation time 355666852 ps
CPU time 8.98 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:55 PM PDT 24
Peak memory 235744 kb
Host smart-51dd408e-0e50-4107-93f8-351a868eee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679920417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
679920417
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3252135403
Short name T177
Test name
Test status
Simulation time 1247021042 ps
CPU time 16.04 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:58 PM PDT 24
Peak memory 225360 kb
Host smart-e8d8ba2c-8c18-40c0-a6e2-4f8ec945d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252135403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3252135403
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.688926051
Short name T627
Test name
Test status
Simulation time 153303722 ps
CPU time 3.91 seconds
Started Jul 23 04:40:41 PM PDT 24
Finished Jul 23 04:40:50 PM PDT 24
Peak memory 233496 kb
Host smart-0239ed1c-56e4-45d5-9432-e6b1dc653c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688926051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.688926051
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3086514246
Short name T30
Test name
Test status
Simulation time 87282090 ps
CPU time 1.06 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:40:46 PM PDT 24
Peak memory 217388 kb
Host smart-d475a14d-c869-4005-ac11-96a73eae0f7c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086514246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3086514246
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.457172631
Short name T55
Test name
Test status
Simulation time 1787062812 ps
CPU time 6.66 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 225348 kb
Host smart-45a1f626-1d97-484a-a6ba-3960750bf3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457172631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
457172631
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1657093330
Short name T900
Test name
Test status
Simulation time 33572992791 ps
CPU time 25.76 seconds
Started Jul 23 04:40:42 PM PDT 24
Finished Jul 23 04:41:12 PM PDT 24
Peak memory 241840 kb
Host smart-c618a14a-7e85-4d0e-be83-1428ba15ea54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657093330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1657093330
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3469390361
Short name T784
Test name
Test status
Simulation time 144298314 ps
CPU time 3.88 seconds
Started Jul 23 04:40:37 PM PDT 24
Finished Jul 23 04:40:42 PM PDT 24
Peak memory 223808 kb
Host smart-c6e2c829-d97d-4935-a1dc-67f039fc0cef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3469390361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3469390361
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4182153876
Short name T776
Test name
Test status
Simulation time 10214467432 ps
CPU time 57.87 seconds
Started Jul 23 04:40:40 PM PDT 24
Finished Jul 23 04:41:42 PM PDT 24
Peak memory 258192 kb
Host smart-608bd25a-b644-47fe-935e-1c14a4ddbad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182153876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4182153876
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3182113609
Short name T417
Test name
Test status
Simulation time 17951760 ps
CPU time 0.77 seconds
Started Jul 23 04:40:39 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 206396 kb
Host smart-9ab713ad-53ed-43ab-bfa2-606c6c21ef4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182113609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3182113609
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2386573229
Short name T753
Test name
Test status
Simulation time 110775658235 ps
CPU time 19.11 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:41:01 PM PDT 24
Peak memory 217160 kb
Host smart-ec10eee1-bae9-46e4-9c62-0a1a4cd18fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386573229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2386573229
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.253640618
Short name T1027
Test name
Test status
Simulation time 40315700 ps
CPU time 1.43 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:41 PM PDT 24
Peak memory 217076 kb
Host smart-606fd92f-0fa1-4f65-a5d4-56fce69fa202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253640618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.253640618
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3455578078
Short name T800
Test name
Test status
Simulation time 141916770 ps
CPU time 0.88 seconds
Started Jul 23 04:40:42 PM PDT 24
Finished Jul 23 04:40:47 PM PDT 24
Peak memory 207240 kb
Host smart-bcfad294-1959-4494-8b68-2430dcc4f63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455578078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3455578078
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1831943612
Short name T693
Test name
Test status
Simulation time 124959655 ps
CPU time 2.2 seconds
Started Jul 23 04:40:38 PM PDT 24
Finished Jul 23 04:40:43 PM PDT 24
Peak memory 224892 kb
Host smart-69ff941a-125c-4f38-9396-feedfc75a626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831943612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1831943612
Directory /workspace/9.spi_device_upload/latest
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