Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[1]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[2]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[3]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[4]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[5]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[6]	2990870	1			T1	2576		T2	1386		T3	3591
all_values[7]	2990870	1			T1	2576		T2	1386		T3	3591

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22502669

1

T1

20608

T2

11088

T3

28728

auto[1]

1424291

1

T13

99

T15

138

T16

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23901212

1

T1

20608

T2

11088

T3

28702

auto[1]

25748

1

T3

26

T8

103

T13

75

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2854766	1			T1	2576		T2	1386		T3	3565
all_values[0]	auto[0]	auto[1]	12400	1			T3	26		T8	57		T13	3
all_values[0]	auto[1]	auto[0]	123166	1			T13	4		T15	5		T16	1
all_values[0]	auto[1]	auto[1]	538	1			T13	7		T15	13		T16	3
all_values[1]	auto[0]	auto[0]	2733388	1			T1	2576		T2	1386		T3	3591
all_values[1]	auto[0]	auto[1]	7538	1			T8	46		T13	5		T33	60
all_values[1]	auto[1]	auto[0]	249357	1			T13	5		T15	8		T16	1
all_values[1]	auto[1]	auto[1]	587	1			T13	9		T15	7		T16	2
all_values[2]	auto[0]	auto[0]	2782902	1			T1	2576		T2	1386		T3	3591
all_values[2]	auto[0]	auto[1]	2384	1			T13	6		T33	19		T43	116
all_values[2]	auto[1]	auto[0]	205289	1			T13	11		T15	9		T16	2
all_values[2]	auto[1]	auto[1]	295	1			T13	3		T15	13		T16	2
all_values[3]	auto[0]	auto[0]	2919501	1			T1	2576		T2	1386		T3	3591
all_values[3]	auto[0]	auto[1]	202	1			T13	7		T15	8		T19	1
all_values[3]	auto[1]	auto[0]	70955	1			T13	9		T15	10		T16	2
all_values[3]	auto[1]	auto[1]	212	1			T13	5		T15	9		T16	2
all_values[4]	auto[0]	auto[0]	2735075	1			T1	2576		T2	1386		T3	3591
all_values[4]	auto[0]	auto[1]	196	1			T13	5		T15	6		T21	3
all_values[4]	auto[1]	auto[0]	255399	1			T13	6		T15	16		T16	3
all_values[4]	auto[1]	auto[1]	200	1			T13	2		T15	8		T16	2
all_values[5]	auto[0]	auto[0]	2887423	1			T1	2576		T2	1386		T3	3591
all_values[5]	auto[0]	auto[1]	204	1			T13	3		T15	8		T18	2
all_values[5]	auto[1]	auto[0]	103073	1			T13	6		T15	4		T18	1
all_values[5]	auto[1]	auto[1]	170	1			T13	4		T15	4		T16	1
all_values[6]	auto[0]	auto[0]	2810197	1			T1	2576		T2	1386		T3	3591
all_values[6]	auto[0]	auto[1]	213	1			T13	3		T15	6		T18	1
all_values[6]	auto[1]	auto[0]	180258	1			T13	11		T15	14		T16	1
all_values[6]	auto[1]	auto[1]	202	1			T13	1		T15	4		T20	1
all_values[7]	auto[0]	auto[0]	2756050	1			T1	2576		T2	1386		T3	3591
all_values[7]	auto[0]	auto[1]	230	1			T13	2		T15	9		T16	1
all_values[7]	auto[1]	auto[0]	234413	1			T13	6		T15	10		T16	3
all_values[7]	auto[1]	auto[1]	177	1			T13	10		T15	4		T18	1