Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33803	1			T1	140		T2	10		T3	36
auto[SpiFlashAddrCfg]	7497	1			T1	26		T3	11		T6	4
auto[SpiFlashAddr3b]	9092	1			T1	29		T2	2		T3	3
auto[SpiFlashAddr4b]	7498	1			T1	18		T2	2		T3	5

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32275

1

T1

73

T2

14

T3

24

auto[1]

25615

1

T1

140

T3

31

T8

113

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32157

1

T1

66

T2

12

T3

15

auto[1]

25733

1

T1

147

T2

2

T3

40

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38608	1			T1	155		T2	6		T3	35
values[1]	1129	1			T1	2		T3	2		T8	5
values[2]	1458	1			T1	7		T3	3		T8	5
values[3]	1457	1			T2	4		T3	1		T6	2
values[4]	1471	1			T1	6		T3	1		T6	4
values[5]	1500	1			T1	2		T3	2		T8	5
values[6]	1301	1			T1	5		T3	2		T6	4
values[7]	1365	1			T1	4		T6	4		T8	3
values[8]	9601	1			T1	32		T2	4		T3	9

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29282

1

T1

213

T2

14

T6

14

auto[1]

28608

1

T3

55

T7

1

T8

452

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54629

1

T1

204

T2

14

T3

55

write

3261

1

T1

9

T8

24

T10

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18753

1

T1

60

T2

2

T3

19

valids[0x1]

39137

1

T1

153

T2

12

T3

36

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1520	1			T1	8		T2	4		T3	2
internal_process_ops[0x5a]	1672	1			T1	2		T3	2		T8	13
internal_process_ops[0x05]	20221	1			T1	96		T2	2		T3	15
internal_process_ops[0x35]	1545	1			T1	6		T3	4		T8	10
internal_process_ops[0x15]	1562	1			T1	3		T3	2		T8	7
internal_process_ops[0x03]	999	1			T1	7		T2	2		T8	4
internal_process_ops[0x0b]	1014	1			T1	4		T6	2		T8	1
internal_process_ops[0x3b]	1006	1			T1	4		T6	4		T8	2
internal_process_ops[0x6b]	1030	1			T1	5		T3	1		T6	4
internal_process_ops[0xbb]	1036	1			T1	2		T3	4		T8	2
internal_process_ops[0xeb]	966	1			T1	7		T3	1		T6	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56263

1

T1

210

T2

14

T3

55

auto[1]

1627

1

T1

3

T8

9

T13

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55513

1

T1

204

T2

14

T3

51

auto[1]

2377

1

T1

9

T3

4

T8

20

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9677

1

T1

25

T2

10

T10

56

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6328

1

T1

115

T23

4

T41

68

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1966

1

T1

15

T6

4

T9

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1777

1

T1

8

T23

9

T41

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2370

1

T1

16

T2

2

T6

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1990

1

T1

8

T23

11

T41

31

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1889

1

T1

10

T2

2

T9

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1742

1

T1

7

T23

5

T41

16

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

99

1

T41

1

T33

1

T46

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T33

1

T96

1

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

78

1

T23

1

T39

1

T33

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

80

1

T41

1

T39

2

T45

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

139

1

T1

2

T39

1

T96

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

69

1

T1

1

T23

2

T39

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T33

4

T47

3

T36

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

117

1

T23

1

T33

4

T43

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

103

1

T1

2

T10

2

T23

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

78

1

T1

2

T23

1

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

82

1

T1

1

T23

2

T39

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T23

1

T41

2

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

119

1

T39

2

T33

4

T96

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

94

1

T33

2

T43

1

T48

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

101

1

T1

1

T41

1

T33

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

102

1

T39

2

T33

1

T43

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9900

1

T3

15

T8

288

T13

11

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7135

1

T3

21

T8

39

T13

5

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1435

1

T3

5

T7

1

T8

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1482

1

T3

6

T8

18

T13

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1910

1

T3

1

T8

23

T82

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2029

1

T3

2

T8

25

T13

4

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1498

1

T3

3

T8

9

T13

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1501

1

T3

2

T8

17

T13

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T82

3

T165

1

T16

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

109

1

T8

1

T166

1

T165

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

103

1

T8

3

T54

2

T93

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T8

1

T82

1

T93

9

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T82

1

T93

1

T166

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

123

1

T8

4

T93

1

T53

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T8

5

T13

1

T54

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

106

1

T8

2

T54

1

T82

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

93

1

T8

1

T93

2

T53

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

118

1

T82

2

T93

1

T53

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

120

1

T8

1

T82

2

T166

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

109

1

T82

1

T166

1

T165

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T8

3

T82

4

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T8

1

T13

2

T82

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

125

1

T8

2

T82

1

T93

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

123

1

T82

5

T53

1

T165

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3599	1			T1	25		T10	2		T23	18
auto[0]	values[0]	valids[0x1]	15221	1			T1	130		T2	6		T10	56
auto[0]	values[1]	valids[0x1]	582	1			T1	2		T23	2		T41	2
auto[0]	values[2]	valids[0x0]	528	1			T1	4		T23	2		T41	5
auto[0]	values[2]	valids[0x1]	257	1			T1	3		T23	1		T41	1
auto[0]	values[3]	valids[0x0]	487	1			T23	1		T41	6		T67	4
auto[0]	values[3]	valids[0x1]	297	1			T2	4		T6	2		T23	1
auto[0]	values[4]	valids[0x0]	501	1			T1	6		T6	4		T23	1
auto[0]	values[4]	valids[0x1]	306	1			T23	4		T41	9		T39	2
auto[0]	values[5]	valids[0x0]	574	1			T1	1		T23	4		T41	8
auto[0]	values[5]	valids[0x1]	268	1			T1	1		T23	4		T39	2
auto[0]	values[6]	valids[0x0]	490	1			T1	3		T6	4		T23	2
auto[0]	values[6]	valids[0x1]	216	1			T1	2		T41	4		T39	3
auto[0]	values[7]	valids[0x0]	450	1			T1	2		T6	4		T23	6
auto[0]	values[7]	valids[0x1]	301	1			T1	2		T23	2		T41	6
auto[0]	values[8]	valids[0x0]	3274	1			T1	19		T2	2		T9	12
auto[0]	values[8]	valids[0x1]	1931	1			T1	13		T2	2		T23	4
auto[1]	values[0]	valids[0x0]	4034	1			T3	10		T8	51		T13	5
auto[1]	values[0]	valids[0x1]	15754	1			T3	25		T8	319		T13	23
auto[1]	values[1]	valids[0x1]	547	1			T3	2		T8	5		T13	1
auto[1]	values[2]	valids[0x0]	414	1			T3	3		T54	1		T82	3
auto[1]	values[2]	valids[0x1]	259	1			T8	5		T82	2		T93	4
auto[1]	values[3]	valids[0x0]	369	1			T7	1		T8	2		T82	3
auto[1]	values[3]	valids[0x1]	304	1			T3	1		T8	1		T82	8
auto[1]	values[4]	valids[0x0]	386	1			T8	1		T54	1		T82	3
auto[1]	values[4]	valids[0x1]	278	1			T3	1		T8	5		T13	1
auto[1]	values[5]	valids[0x0]	370	1			T3	1		T8	4		T13	1
auto[1]	values[5]	valids[0x1]	288	1			T3	1		T8	1		T54	2
auto[1]	values[6]	valids[0x0]	364	1			T8	4		T54	2		T82	3
auto[1]	values[6]	valids[0x1]	231	1			T3	2		T8	2		T13	1
auto[1]	values[7]	valids[0x0]	338	1			T8	3		T13	1		T82	10
auto[1]	values[7]	valids[0x1]	276	1			T13	1		T82	5		T53	1
auto[1]	values[8]	valids[0x0]	2575	1			T3	5		T8	31		T13	6
auto[1]	values[8]	valids[0x1]	1821	1			T3	4		T8	18		T13	1