Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3131163

1

T1

10251

T2

5581

T3

3828

auto[1]

27151

1

T1

94

T3

15

T8

252

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

830655

1

T1

46

T2

1

T3

14

auto[1]

2327659

1

T1

10299

T2

5580

T3

3829

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	598320	1			T1	416		T2	5581		T3	526
auto[524288:1048575]	365771	1			T1	1		T6	294		T8	1284
auto[1048576:1572863]	383855	1			T1	2		T6	272		T8	276
auto[1572864:2097151]	342092	1			T1	3428		T6	153		T8	2747
auto[2097152:2621439]	403524	1			T1	3074		T3	129		T6	24
auto[2621440:3145727]	355512	1			T3	10		T6	2		T8	1260
auto[3145728:3670015]	387246	1			T1	257		T3	3000		T6	340
auto[3670016:4194303]	321994	1			T1	3167		T3	178		T6	357

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2360453

1

T1

10337

T2

5581

T3

3843

auto[1]

797861

1

T1

8

T6

1458

T8

23

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2716874

1

T1

9219

T2

5581

T3

321

auto[1]

441440

1

T1

1126

T3

3522

T8

1572

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	168285	1			T1	3		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	344228	1			T1	129		T2	5580		T8	2861
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	91521	1			T1	1		T6	294		T8	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	235154	1			T8	1281		T13	256		T23	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95715	1			T1	2		T6	272		T8	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	230948	1			T8	257		T13	544		T23	513
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	88410	1			T1	14		T6	153		T8	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	193116	1			T1	3361		T8	2743		T41	384
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	108323	1			T1	3		T6	24		T8	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	230266	1			T1	2212		T8	7		T23	512
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	70676	1			T3	1		T6	2		T8	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	230834	1			T3	1		T8	1		T13	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	104741	1			T1	1		T3	2		T6	340
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	225927	1			T1	256		T3	129		T8	512
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	91588	1			T1	5		T6	357		T8	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	185721	1			T1	3149		T3	178		T13	1278
auto[0]	auto[1]	auto[0:524287]	auto[0]	1151	1			T3	5		T41	3		T39	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	80756	1			T1	256		T3	514		T41	2818
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1213	1			T41	6		T39	3		T82	20
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	34621	1			T41	2		T39	1		T82	384
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	800	1			T39	3		T33	3		T82	9
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53907	1			T39	2017		T33	120		T46	3646
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	718	1			T1	3		T23	8		T41	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	56558	1			T1	1		T41	5		T39	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	962	1			T1	1		T3	1		T8	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60672	1			T1	850		T3	128		T8	259
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1566	1			T8	12		T41	2		T82	19
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49668	1			T8	1128		T41	503		T82	312
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	648	1			T8	9		T41	2		T33	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	51878	1			T3	2868		T8	4		T47	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	489	1			T1	3		T41	1		T82	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40103	1			T1	1		T41	3		T39	384
auto[1]	auto[0]	auto[0:524287]	auto[0]	513	1			T1	1		T8	2		T10	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2652	1			T1	27		T8	23		T10	44
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	322	1			T8	1		T23	9		T33	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1964	1			T33	38		T53	2		T216	74
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	322	1			T8	1		T23	8		T33	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1368	1			T8	15		T33	106		T82	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	393	1			T1	5		T8	1		T39	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2348	1			T1	42		T39	79		T33	124
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	403	1			T1	2		T8	4		T23	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2054	1			T1	6		T8	47		T41	16
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	329	1			T3	1		T23	6		T39	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1914	1			T3	7		T39	15		T33	132
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	382	1			T3	1		T13	1		T23	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2895	1			T23	107		T93	14		T47	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	366	1			T33	5		T82	8		T96	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3196	1			T33	36		T216	12		T47	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	103	1			T3	2		T41	1		T82	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	632	1			T3	4		T41	8		T82	43
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	112	1			T41	2		T39	1		T82	11
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	864	1			T41	58		T39	14		T47	36
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	99	1			T33	1		T47	1		T166	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	696	1			T33	76		T47	2		T166	128
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	104	1			T1	1		T39	2		T82	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	445	1			T1	1		T39	23		T187	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	95	1			T8	1		T39	1		T96	6
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	749	1			T8	8		T39	58		T96	215
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	111	1			T8	6		T166	20		T165	7
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	414	1			T8	104		T36	4		T179	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	120	1			T8	4		T82	3		T47	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	655	1			T8	35		T47	5		T166	256
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	75	1			T1	1		T93	3		T178	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	456	1			T1	8		T178	56		T16	6

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1900469	1			T1	9135		T2	5581		T3	312
auto[0]	auto[0]	auto[1]	794984	1			T1	1		T6	1458		T8	2
auto[0]	auto[1]	auto[0]	433522	1			T1	1114		T3	3516		T8	1404
auto[0]	auto[1]	auto[1]	2188	1			T1	1		T8	10		T39	3
auto[1]	auto[0]	auto[0]	20882	1			T1	79		T3	9		T8	90
auto[1]	auto[0]	auto[1]	539	1			T1	4		T8	4		T10	2
auto[1]	auto[1]	auto[0]	5580	1			T1	9		T3	6		T8	151
auto[1]	auto[1]	auto[1]	150	1			T1	2		T8	7		T82	4