Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[1]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[2]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[3]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[4]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[5]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[6]	2990870	1			T1	2576		T2	1386		T3	3591
all_pins[7]	2990870	1			T1	2576		T2	1386		T3	3591

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23744033	1			T1	20608		T2	11088		T3	28728
values[0x1]	182927	1			T13	41		T15	62		T16	12
transitions[0x0=>0x1]	182261	1			T13	30		T15	46		T16	4
transitions[0x1=>0x0]	182269	1			T13	30		T15	46		T16	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2990274	1			T1	2576		T2	1386		T3	3591
all_pins[0]	values[0x1]	596	1			T13	7		T15	13		T16	3
all_pins[0]	transitions[0x0=>0x1]	351	1			T13	5		T15	11		T16	1
all_pins[0]	transitions[0x1=>0x0]	394	1			T13	7		T15	5		T20	24
all_pins[1]	values[0x0]	2990231	1			T1	2576		T2	1386		T3	3591
all_pins[1]	values[0x1]	639	1			T13	9		T15	7		T16	2
all_pins[1]	transitions[0x0=>0x1]	489	1			T13	8		T15	1		T20	23
all_pins[1]	transitions[0x1=>0x0]	165	1			T13	2		T15	7		T19	2
all_pins[2]	values[0x0]	2990555	1			T1	2576		T2	1386		T3	3591
all_pins[2]	values[0x1]	315	1			T13	3		T15	13		T16	2
all_pins[2]	transitions[0x0=>0x1]	260	1			T13	3		T15	9		T19	2
all_pins[2]	transitions[0x1=>0x0]	157	1			T13	5		T15	5		T19	1
all_pins[3]	values[0x0]	2990658	1			T1	2576		T2	1386		T3	3591
all_pins[3]	values[0x1]	212	1			T13	5		T15	9		T16	2
all_pins[3]	transitions[0x0=>0x1]	163	1			T13	4		T15	6		T19	1
all_pins[3]	transitions[0x1=>0x0]	151	1			T13	1		T15	5		T18	1
all_pins[4]	values[0x0]	2990670	1			T1	2576		T2	1386		T3	3591
all_pins[4]	values[0x1]	200	1			T13	2		T15	8		T16	2
all_pins[4]	transitions[0x0=>0x1]	159	1			T13	2		T15	8		T16	2
all_pins[4]	transitions[0x1=>0x0]	1003	1			T13	4		T15	4		T16	1
all_pins[5]	values[0x0]	2989826	1			T1	2576		T2	1386		T3	3591
all_pins[5]	values[0x1]	1044	1			T13	4		T15	4		T16	1
all_pins[5]	transitions[0x0=>0x1]	1008	1			T13	3		T15	4		T16	1
all_pins[5]	transitions[0x1=>0x0]	179708	1			T15	4		T20	17100		T21	1
all_pins[6]	values[0x0]	2811126	1			T1	2576		T2	1386		T3	3591
all_pins[6]	values[0x1]	179744	1			T13	1		T15	4		T20	17100
all_pins[6]	transitions[0x0=>0x1]	179697	1			T15	4		T20	17100		T21	1
all_pins[6]	transitions[0x1=>0x0]	130	1			T13	9		T15	4		T18	1
all_pins[7]	values[0x0]	2990693	1			T1	2576		T2	1386		T3	3591
all_pins[7]	values[0x1]	177	1			T13	10		T15	4		T18	1
all_pins[7]	transitions[0x0=>0x1]	134	1			T13	5		T15	3		T20	2
all_pins[7]	transitions[0x1=>0x0]	561	1			T13	2		T15	12		T16	3