Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16701

1

T1

73

T2

14

T6

14

auto[1]

12581

1

T1

140

T23

34

T41

133

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4049	1			T1	32		T50	4		T39	119
values[1]	4505	1			T23	20		T39	20		T33	128
values[2]	3637	1			T1	61		T6	14		T23	20
values[3]	3483	1			T1	29		T23	40		T41	57
values[4]	3158	1			T23	20		T33	91		T97	6
values[5]	3690	1			T1	71		T9	12		T41	155
values[6]	3372	1			T2	14		T10	62		T49	12
values[7]	3388	1			T1	20		T41	20		T51	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3285	1			T1	52		T23	40		T41	20
values[1]	4023	1			T1	80		T23	20		T41	20
values[2]	4053	1			T41	60		T50	4		T39	79
values[3]	3470	1			T23	20		T41	92		T39	81
values[4]	3382	1			T1	61		T41	65		T51	6
values[5]	4188	1			T1	20		T6	14		T10	62
values[6]	3216	1			T41	20		T52	2		T33	249
values[7]	3665	1			T2	14		T9	12		T23	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	323	1			T1	13		T39	15		T187	16
auto[0]	values[0]	values[1]	440	1			T194	116		T63	9		T237	2
auto[0]	values[0]	values[2]	158	1			T39	10		T185	8		T238	12
auto[0]	values[0]	values[3]	329	1			T43	14		T83	62		T84	17
auto[0]	values[0]	values[4]	273	1			T48	68		T213	61		T188	16
auto[0]	values[0]	values[5]	211	1			T39	9		T186	12		T22	13
auto[0]	values[0]	values[6]	307	1			T33	9		T205	16		T187	12
auto[0]	values[0]	values[7]	255	1			T96	9		T186	14		T22	8
auto[0]	values[1]	values[0]	267	1			T23	17		T36	12		T187	6
auto[0]	values[1]	values[1]	239	1			T187	10		T22	16		T83	15
auto[0]	values[1]	values[2]	386	1			T47	89		T206	14		T194	81
auto[0]	values[1]	values[3]	297	1			T233	8		T239	2		T213	8
auto[0]	values[1]	values[4]	468	1			T39	14		T78	24		T16	15
auto[0]	values[1]	values[5]	273	1			T96	15		T43	33		T16	8
auto[0]	values[1]	values[6]	255	1			T84	28		T228	12		T188	11
auto[0]	values[1]	values[7]	325	1			T33	117		T48	11		T16	9
auto[0]	values[2]	values[0]	190	1			T94	18		T240	8		T83	47
auto[0]	values[2]	values[1]	296	1			T48	28		T36	22		T187	7
auto[0]	values[2]	values[2]	264	1			T96	12		T81	14		T241	2
auto[0]	values[2]	values[3]	289	1			T39	8		T95	16		T96	12
auto[0]	values[2]	values[4]	320	1			T1	15		T41	14		T33	41
auto[0]	values[2]	values[5]	156	1			T6	14		T216	12		T187	23
auto[0]	values[2]	values[6]	193	1			T187	12		T194	10		T181	15
auto[0]	values[2]	values[7]	295	1			T23	9		T96	11		T16	26
auto[0]	values[3]	values[0]	206	1			T39	37		T190	18		T242	39
auto[0]	values[3]	values[1]	169	1			T1	9		T23	10		T39	10
auto[0]	values[3]	values[2]	190	1			T187	16		T194	45		T158	11
auto[0]	values[3]	values[3]	299	1			T23	14		T41	26		T39	14
auto[0]	values[3]	values[4]	167	1			T46	10		T213	28		T227	20
auto[0]	values[3]	values[5]	461	1			T33	28		T186	15		T196	3
auto[0]	values[3]	values[6]	243	1			T41	11		T33	11		T47	16
auto[0]	values[3]	values[7]	340	1			T243	4		T196	8		T83	11
auto[0]	values[4]	values[0]	176	1			T23	16		T181	16		T244	14
auto[0]	values[4]	values[1]	189	1			T213	37		T206	14		T245	4
auto[0]	values[4]	values[2]	183	1			T79	6		T246	14		T186	11
auto[0]	values[4]	values[3]	321	1			T33	10		T47	13		T36	17
auto[0]	values[4]	values[4]	109	1			T188	6		T247	13		T159	16
auto[0]	values[4]	values[5]	210	1			T33	19		T216	16		T185	17
auto[0]	values[4]	values[6]	199	1			T248	10		T249	2		T250	6
auto[0]	values[4]	values[7]	372	1			T47	8		T48	10		T211	13
auto[0]	values[5]	values[0]	248	1			T1	12		T41	13		T96	16
auto[0]	values[5]	values[1]	271	1			T1	12		T41	10		T43	15
auto[0]	values[5]	values[2]	387	1			T41	32		T183	8		T47	45
auto[0]	values[5]	values[3]	188	1			T41	9		T200	16		T197	14
auto[0]	values[5]	values[4]	198	1			T41	13		T43	11		T16	5
auto[0]	values[5]	values[5]	201	1			T43	13		T47	29		T200	11
auto[0]	values[5]	values[6]	178	1			T46	12		T36	12		T251	8
auto[0]	values[5]	values[7]	291	1			T9	12		T33	13		T252	12
auto[0]	values[6]	values[0]	171	1			T253	2		T44	12		T254	2
auto[0]	values[6]	values[1]	376	1			T49	12		T223	10		T47	15
auto[0]	values[6]	values[2]	244	1			T33	7		T96	14		T255	8
auto[0]	values[6]	values[3]	289	1			T46	9		T21	12		T84	53
auto[0]	values[6]	values[4]	239	1			T67	12		T184	8		T84	39
auto[0]	values[6]	values[5]	266	1			T10	62		T201	13		T22	19
auto[0]	values[6]	values[6]	355	1			T33	201		T98	8		T42	18
auto[0]	values[6]	values[7]	141	1			T2	14		T96	11		T75	10
auto[0]	values[7]	values[0]	302	1			T96	15		T46	9		T48	7
auto[0]	values[7]	values[1]	326	1			T43	33		T36	12		T186	9
auto[0]	values[7]	values[2]	305	1			T41	16		T33	34		T47	9
auto[0]	values[7]	values[3]	207	1			T46	12		T84	28		T206	12
auto[0]	values[7]	values[4]	184	1			T51	6		T256	4		T188	15
auto[0]	values[7]	values[5]	347	1			T1	12		T230	2		T231	10
auto[0]	values[7]	values[6]	141	1			T48	16		T22	16		T84	18
auto[0]	values[7]	values[7]	203	1			T96	5		T185	28		T186	11
auto[1]	values[0]	values[0]	261	1			T1	19		T39	5		T187	7
auto[1]	values[0]	values[1]	155	1			T194	6		T63	15		T257	9
auto[1]	values[0]	values[2]	310	1			T50	4		T39	69		T185	12
auto[1]	values[0]	values[3]	154	1			T43	9		T83	6		T84	9
auto[1]	values[0]	values[4]	193	1			T48	7		T213	21		T188	5
auto[1]	values[0]	values[5]	295	1			T39	11		T186	8		T258	2
auto[1]	values[0]	values[6]	188	1			T33	11		T259	10		T187	8
auto[1]	values[0]	values[7]	197	1			T96	11		T186	6		T22	23
auto[1]	values[1]	values[0]	184	1			T23	3		T36	8		T187	24
auto[1]	values[1]	values[1]	292	1			T187	11		T22	4		T83	152
auto[1]	values[1]	values[2]	223	1			T47	24		T206	26		T194	9
auto[1]	values[1]	values[3]	143	1			T213	12		T228	21		T188	5
auto[1]	values[1]	values[4]	157	1			T39	6		T16	8		T187	5
auto[1]	values[1]	values[5]	429	1			T96	5		T43	7		T16	12
auto[1]	values[1]	values[6]	414	1			T84	10		T228	30		T188	55
auto[1]	values[1]	values[7]	153	1			T33	11		T48	9		T16	11
auto[1]	values[2]	values[0]	157	1			T83	8		T84	23		T194	10
auto[1]	values[2]	values[1]	221	1			T48	6		T36	14		T187	13
auto[1]	values[2]	values[2]	335	1			T96	8		T260	7		T206	7
auto[1]	values[2]	values[3]	199	1			T39	37		T96	8		T185	8
auto[1]	values[2]	values[4]	215	1			T1	46		T41	31		T33	5
auto[1]	values[2]	values[5]	188	1			T216	8		T187	18		T201	11
auto[1]	values[2]	values[6]	180	1			T187	8		T194	18		T181	5
auto[1]	values[2]	values[7]	139	1			T23	11		T96	9		T16	19
auto[1]	values[3]	values[0]	111	1			T39	9		T196	6		T83	18
auto[1]	values[3]	values[1]	342	1			T1	20		T23	10		T39	91
auto[1]	values[3]	values[2]	132	1			T187	6		T194	9		T158	9
auto[1]	values[3]	values[3]	178	1			T23	6		T41	11		T39	22
auto[1]	values[3]	values[4]	132	1			T46	10		T213	6		T58	10
auto[1]	values[3]	values[5]	176	1			T33	7		T186	5		T196	22
auto[1]	values[3]	values[6]	80	1			T41	9		T33	9		T47	4
auto[1]	values[3]	values[7]	257	1			T196	12		T83	11		T188	13
auto[1]	values[4]	values[0]	122	1			T23	4		T181	4		T244	6
auto[1]	values[4]	values[1]	114	1			T97	6		T213	8		T206	29
auto[1]	values[4]	values[2]	86	1			T186	9		T22	9		T261	4
auto[1]	values[4]	values[3]	195	1			T33	18		T47	7		T36	3
auto[1]	values[4]	values[4]	254	1			T188	16		T247	7		T159	4
auto[1]	values[4]	values[5]	369	1			T33	44		T216	92		T185	3
auto[1]	values[4]	values[6]	91	1			T194	8		T181	9		T247	14
auto[1]	values[4]	values[7]	168	1			T47	15		T48	38		T211	9
auto[1]	values[5]	values[0]	263	1			T1	8		T41	7		T96	4
auto[1]	values[5]	values[1]	228	1			T1	39		T41	10		T43	9
auto[1]	values[5]	values[2]	332	1			T41	8		T45	14		T47	12
auto[1]	values[5]	values[3]	146	1			T41	46		T200	8		T197	6
auto[1]	values[5]	values[4]	212	1			T41	7		T43	10		T16	17
auto[1]	values[5]	values[5]	243	1			T43	7		T47	9		T200	9
auto[1]	values[5]	values[6]	157	1			T46	8		T36	8		T194	6
auto[1]	values[5]	values[7]	147	1			T33	7		T47	5		T194	24
auto[1]	values[6]	values[0]	130	1			T260	6		T197	7		T247	15
auto[1]	values[6]	values[1]	207	1			T212	10		T47	9		T206	6
auto[1]	values[6]	values[2]	351	1			T33	88		T96	6		T255	14
auto[1]	values[6]	values[3]	100	1			T46	11		T21	11		T84	9
auto[1]	values[6]	values[4]	151	1			T84	11		T206	10		T188	9
auto[1]	values[6]	values[5]	83	1			T201	7		T22	6		T213	3
auto[1]	values[6]	values[6]	110	1			T52	2		T33	8		T47	9
auto[1]	values[6]	values[7]	159	1			T96	9		T43	23		T193	18
auto[1]	values[7]	values[0]	174	1			T96	5		T46	11		T48	48
auto[1]	values[7]	values[1]	158	1			T43	5		T36	21		T186	11
auto[1]	values[7]	values[2]	167	1			T41	4		T33	2		T47	11
auto[1]	values[7]	values[3]	136	1			T46	8		T84	18		T206	8
auto[1]	values[7]	values[4]	110	1			T262	2		T229	20		T207	6
auto[1]	values[7]	values[5]	280	1			T1	8		T36	18		T84	5
auto[1]	values[7]	values[6]	125	1			T48	40		T22	14		T84	3
auto[1]	values[7]	values[7]	223	1			T96	15		T185	6		T186	9