Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	399	1			T6	4		T9	2		T23	6
auto[ReadAddrCrossIntoMailbox]	292	1			T23	4		T39	4		T33	5
auto[ReadAddrCrossOutOfMailbox]	302	1			T1	1		T6	4		T9	2
auto[ReadAddrCrossAllMailbox]	226	1			T1	2		T6	2		T9	2
auto[ReadAddrOutsideMailbox]	3200	1			T1	26		T2	2		T6	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2271

1

T1

18

T2

1

T6

7

auto[1]

2148

1

T1

11

T2

1

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	722	1			T1	7		T2	2		T23	3
read_ops[0x0b]	712	1			T1	4		T6	2		T23	4
read_ops[0x3b]	761	1			T1	4		T6	4		T9	6
read_ops[0x6b]	743	1			T1	5		T6	4		T9	6
read_ops[0xbb]	765	1			T1	2		T23	5		T41	4
read_ops[0xeb]	716	1			T1	7		T6	4		T23	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T33	1		T186	1		T21	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T23	1		T39	1		T47	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T23	1		T33	1		T185	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T43	1		T47	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T1	1		T41	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T47	1		T236	1		T247	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T1	1		T33	1		T47	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T41	1		T33	1		T46	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T1	2		T2	1		T23	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T1	3		T2	1		T41	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T23	1		T33	1		T96	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T23	1		T96	1		T42	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T33	1		T231	1		T47	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T39	1		T231	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T41	1		T47	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T33	1		T43	1		T185	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T6	1		T231	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T6	1		T231	1		T186	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T1	3		T23	2		T41	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	266	1			T1	1		T41	4		T39	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T6	1		T33	2		T96	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T6	1		T33	1		T96	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T39	1		T33	1		T36	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T23	1		T39	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T96	1		T186	1		T206	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T23	3		T46	1		T83	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T48	1		T256	1		T255	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T33	1		T96	1		T256	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T1	3		T6	1		T9	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T1	1		T6	1		T9	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T9	1		T39	1		T33	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T9	1		T23	1		T41	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T47	1		T187	1		T243	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T33	1		T186	1		T243	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T6	2		T9	1		T33	3
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T6	2		T9	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T9	1		T46	1		T187	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T1	1		T9	1		T23	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T1	1		T41	1		T39	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T1	3		T23	3		T41	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T39	2		T96	1		T231	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T23	2		T33	1		T96	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T39	1		T33	1		T46	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T96	2		T47	1		T21	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T96	1		T46	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T23	1		T33	1		T16	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	28	1			T230	1		T83	1		T84	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T23	1		T230	1		T96	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T1	2		T41	2		T67	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T23	1		T41	2		T67	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T6	1		T33	1		T47	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T6	1		T96	2		T47	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T23	1		T47	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T23	1		T96	1		T36	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T33	1		T43	1		T16	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T213	2		T206	1		T188	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T16	1		T185	1		T187	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T46	1		T234	1		T22	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T1	5		T6	1		T41	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	263	1			T1	2		T6	1		T41	3