Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3421	1			T41	20		T39	45		T33	128
values[1]	3347	1			T1	51		T23	20		T67	12
values[2]	4242	1			T1	20		T23	20		T41	82
values[3]	3989	1			T1	32		T6	14		T23	20
values[4]	3547	1			T1	61		T10	62		T39	20
values[5]	3711	1			T1	20		T9	12		T23	20
values[6]	3741	1			T2	14		T41	60		T52	2
values[7]	3284	1			T1	29		T23	20		T41	40

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3387	1			T10	62		T23	20		T50	4
values[1]	2709	1			T6	14		T41	37		T33	40
values[2]	3584	1			T41	20		T39	121		T33	434
values[3]	3759	1			T1	161		T2	14		T41	45
values[4]	4616	1			T1	32		T23	40		T39	56
values[5]	3926	1			T1	20		T9	12		T23	20
values[6]	3661	1			T41	20		T52	2		T33	95
values[7]	3640	1			T23	20		T39	91		T94	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28554

1

T1

210

T2

14

T6

14

auto[1]

728

1

T1

3

T23

5

T41

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	338	1			T240	8		T180	6		T228	18
auto[0]	values[0]	values[1]	403	1			T249	2		T21	25		T83	92
auto[0]	values[0]	values[2]	506	1			T33	127		T263	20		T264	30
auto[0]	values[0]	values[3]	395	1			T96	20		T186	20		T22	20
auto[0]	values[0]	values[4]	279	1			T259	10		T48	74		T200	20
auto[0]	values[0]	values[5]	710	1			T41	20		T43	21		T194	120
auto[0]	values[0]	values[6]	265	1			T192	6		T188	20		T214	33
auto[0]	values[0]	values[7]	432	1			T39	45		T43	38		T47	21
auto[0]	values[1]	values[0]	402	1			T67	12		T33	48		T96	19
auto[0]	values[1]	values[1]	210	1			T47	22		T265	20		T247	20
auto[0]	values[1]	values[2]	296	1			T200	20		T186	20		T22	25
auto[0]	values[1]	values[3]	410	1			T1	51		T48	47		T83	23
auto[0]	values[1]	values[4]	722	1			T33	46		T222	12		T201	20
auto[0]	values[1]	values[5]	345	1			T97	6		T223	10		T213	37
auto[0]	values[1]	values[6]	426	1			T252	12		T47	27		T213	90
auto[0]	values[1]	values[7]	453	1			T23	20		T39	45		T46	20
auto[0]	values[2]	values[0]	405	1			T50	4		T216	107		T186	20
auto[0]	values[2]	values[1]	432	1			T41	35		T187	20		T186	20
auto[0]	values[2]	values[2]	613	1			T39	100		T186	20		T184	8
auto[0]	values[2]	values[3]	584	1			T1	20		T41	45		T196	20
auto[0]	values[2]	values[4]	670	1			T23	18		T47	20		T186	19
auto[0]	values[2]	values[5]	314	1			T96	40		T193	18		T194	28
auto[0]	values[2]	values[6]	642	1			T248	10		T185	27		T187	46
auto[0]	values[2]	values[7]	445	1			T213	96		T236	49		T181	20
auto[0]	values[3]	values[0]	503	1			T79	6		T216	20		T187	19
auto[0]	values[3]	values[1]	420	1			T6	14		T96	20		T75	10
auto[0]	values[3]	values[2]	601	1			T41	20		T33	206		T47	20
auto[0]	values[3]	values[3]	454	1			T36	19		T202	14		T226	20
auto[0]	values[3]	values[4]	572	1			T1	30		T39	34		T205	16
auto[0]	values[3]	values[5]	375	1			T23	20		T41	55		T96	20
auto[0]	values[3]	values[6]	556	1			T36	55		T234	14		T266	8
auto[0]	values[3]	values[7]	413	1			T96	20		T47	49		T48	20
auto[0]	values[4]	values[0]	419	1			T10	62		T39	20		T98	8
auto[0]	values[4]	values[1]	266	1			T33	40		T84	20		T267	12
auto[0]	values[4]	values[2]	337	1			T33	96		T46	20		T63	37
auto[0]	values[4]	values[3]	594	1			T1	60		T33	20		T96	20
auto[0]	values[4]	values[4]	498	1			T246	14		T185	33		T187	21
auto[0]	values[4]	values[5]	388	1			T33	34		T219	6		T36	24
auto[0]	values[4]	values[6]	471	1			T33	92		T45	10		T78	24
auto[0]	values[4]	values[7]	497	1			T43	19		T47	38		T268	16
auto[0]	values[5]	values[0]	496	1			T42	18		T185	19		T186	16
auto[0]	values[5]	values[1]	319	1			T239	2		T201	47		T228	20
auto[0]	values[5]	values[2]	229	1			T47	24		T186	17		T228	18
auto[0]	values[5]	values[3]	430	1			T95	16		T236	71		T158	20
auto[0]	values[5]	values[4]	390	1			T23	18		T43	38		T262	2
auto[0]	values[5]	values[5]	593	1			T1	20		T9	12		T49	12
auto[0]	values[5]	values[6]	606	1			T81	14		T269	18		T187	23
auto[0]	values[5]	values[7]	558	1			T230	2		T43	22		T46	39
auto[0]	values[6]	values[0]	428	1			T43	38		T213	22		T260	20
auto[0]	values[6]	values[1]	256	1			T47	20		T229	20		T16	19
auto[0]	values[6]	values[2]	724	1			T48	57		T233	8		T187	42
auto[0]	values[6]	values[3]	489	1			T2	14		T253	2		T208	20
auto[0]	values[6]	values[4]	627	1			T39	19		T176	8		T47	84
auto[0]	values[6]	values[5]	453	1			T41	40		T33	41		T16	23
auto[0]	values[6]	values[6]	329	1			T41	20		T52	2		T46	20
auto[0]	values[6]	values[7]	361	1			T94	18		T36	18		T22	30
auto[0]	values[7]	values[0]	311	1			T23	19		T231	10		T16	21
auto[0]	values[7]	values[1]	342	1			T96	20		T258	2		T254	2
auto[0]	values[7]	values[2]	189	1			T39	19		T185	20		T21	21
auto[0]	values[7]	values[3]	336	1			T1	29		T201	20		T22	31
auto[0]	values[7]	values[4]	736	1			T33	32		T46	19		T47	56
auto[0]	values[7]	values[5]	658	1			T41	39		T51	6		T36	20
auto[0]	values[7]	values[6]	261	1			T183	8		T196	19		T84	47
auto[0]	values[7]	values[7]	372	1			T44	12		T22	23		T84	25
auto[1]	values[0]	values[0]	11	1			T228	2		T194	1		T188	3
auto[1]	values[0]	values[1]	15	1			T83	3		T58	1		T265	2
auto[1]	values[0]	values[2]	10	1			T33	1		T264	2		T163	2
auto[1]	values[0]	values[3]	5	1			T215	1		T270	1		T271	1
auto[1]	values[0]	values[4]	6	1			T48	1		T63	2		T161	2
auto[1]	values[0]	values[5]	22	1			T194	4		T188	1		T195	1
auto[1]	values[0]	values[6]	11	1			T214	1		T159	3		T271	3
auto[1]	values[0]	values[7]	13	1			T43	2		T187	1		T198	1
auto[1]	values[1]	values[0]	6	1			T96	1		T272	1		T182	2
auto[1]	values[1]	values[1]	7	1			T47	1		T273	2		T274	1
auto[1]	values[1]	values[2]	8	1			T200	4		T83	1		T58	1
auto[1]	values[1]	values[3]	8	1			T48	1		T83	4		T161	3
auto[1]	values[1]	values[4]	13	1			T22	1		T275	1		T264	1
auto[1]	values[1]	values[5]	12	1			T214	1		T159	2		T209	1
auto[1]	values[1]	values[6]	15	1			T47	2		T213	5		T63	1
auto[1]	values[1]	values[7]	14	1			T39	1		T48	1		T185	2
auto[1]	values[2]	values[0]	8	1			T216	1		T264	1		T276	1
auto[1]	values[2]	values[1]	9	1			T41	2		T211	2		T265	2
auto[1]	values[2]	values[2]	12	1			T39	1		T83	3		T58	1
auto[1]	values[2]	values[3]	13	1			T228	3		T194	2		T188	1
auto[1]	values[2]	values[4]	32	1			T23	2		T186	1		T58	2
auto[1]	values[2]	values[5]	12	1			T194	2		T158	1		T277	1
auto[1]	values[2]	values[6]	25	1			T185	1		T187	3		T196	1
auto[1]	values[2]	values[7]	26	1			T213	3		T158	3		T278	2
auto[1]	values[3]	values[0]	21	1			T187	1		T213	1		T194	1
auto[1]	values[3]	values[1]	4	1			T48	1		T279	1		T280	1
auto[1]	values[3]	values[2]	9	1			T33	3		T194	1		T198	2
auto[1]	values[3]	values[3]	8	1			T36	1		T201	2		T159	1
auto[1]	values[3]	values[4]	23	1			T1	2		T39	2		T47	2
auto[1]	values[3]	values[5]	7	1			T281	1		T282	2		T283	2
auto[1]	values[3]	values[6]	12	1			T36	1		T209	3		T264	1
auto[1]	values[3]	values[7]	11	1			T206	2		T194	1		T188	2
auto[1]	values[4]	values[0]	9	1			T260	1		T63	2		T199	2
auto[1]	values[4]	values[1]	5	1			T84	1		T284	4		-	-
auto[1]	values[4]	values[2]	11	1			T33	1		T63	2		T257	3
auto[1]	values[4]	values[3]	13	1			T1	1		T21	2		T188	1
auto[1]	values[4]	values[4]	11	1			T185	1		T213	1		T265	1
auto[1]	values[4]	values[5]	5	1			T33	2		T36	1		T63	1
auto[1]	values[4]	values[6]	10	1			T33	3		T45	4		T285	1
auto[1]	values[4]	values[7]	13	1			T43	1		T213	2		T158	2
auto[1]	values[5]	values[0]	12	1			T185	1		T186	4		T83	1
auto[1]	values[5]	values[1]	2	1			T199	1		T270	1		-	-
auto[1]	values[5]	values[2]	11	1			T186	3		T228	2		T261	2
auto[1]	values[5]	values[3]	13	1			T236	4		T286	5		T261	2
auto[1]	values[5]	values[4]	11	1			T23	2		T158	2		T214	2
auto[1]	values[5]	values[5]	16	1			T39	2		T185	2		T186	1
auto[1]	values[5]	values[6]	13	1			T84	3		T161	1		T278	1
auto[1]	values[5]	values[7]	12	1			T43	2		T46	1		T21	1
auto[1]	values[6]	values[0]	5	1			T265	1		T159	1		T161	2
auto[1]	values[6]	values[1]	10	1			T16	1		T186	1		T261	1
auto[1]	values[6]	values[2]	15	1			T48	2		T187	2		T247	3
auto[1]	values[6]	values[3]	3	1			T213	1		T181	1		T261	1
auto[1]	values[6]	values[4]	7	1			T39	1		T84	1		T281	1
auto[1]	values[6]	values[5]	8	1			T33	2		T16	2		T188	2
auto[1]	values[6]	values[6]	13	1			T188	1		T287	1		T209	3
auto[1]	values[6]	values[7]	13	1			T36	2		T207	2		T288	2
auto[1]	values[7]	values[0]	13	1			T23	1		T16	2		T63	2
auto[1]	values[7]	values[1]	9	1			T159	1		T271	1		T289	5
auto[1]	values[7]	values[2]	13	1			T39	1		T21	2		T181	4
auto[1]	values[7]	values[3]	4	1			T290	2		T291	2		-	-
auto[1]	values[7]	values[4]	19	1			T33	3		T46	1		T47	1
auto[1]	values[7]	values[5]	8	1			T41	1		T16	2		T84	2
auto[1]	values[7]	values[6]	6	1			T196	1		T84	3		T292	2
auto[1]	values[7]	values[7]	7	1			T84	1		T293	4		T294	2