Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	874	1			T13	20		T15	31		T16	4
all_values[1]	874	1			T13	20		T15	31		T16	4
all_values[2]	874	1			T13	20		T15	31		T16	4
all_values[3]	874	1			T13	20		T15	31		T16	4
all_values[4]	874	1			T13	20		T15	31		T16	4
all_values[5]	874	1			T13	20		T15	31		T16	4
all_values[6]	874	1			T13	20		T15	31		T16	4
all_values[7]	874	1			T13	20		T15	31		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3767

1

T13

95

T15

136

T16

14

auto[1]

3225

1

T13

65

T15

112

T16

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2813

1

T13

61

T15

98

T16

15

auto[1]

4179

1

T13

99

T15

150

T16

17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4019

1

T13

91

T15

139

T16

23

auto[1]

2973

1

T13

69

T15

109

T16

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	182	1			T13	5		T15	7		T16	1
all_values[0]	auto[0]	auto[0]	auto[1]	80	1			T13	1		T15	3		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	142	1			T15	1		T21	1		T22	4
all_values[0]	auto[0]	auto[1]	auto[1]	104	1			T13	5		T15	4		T16	2
all_values[0]	auto[1]	auto[0]	auto[1]	202	1			T13	7		T15	7		T18	1
all_values[0]	auto[1]	auto[1]	auto[1]	164	1			T13	2		T15	9		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	175	1			T13	5		T15	7		T19	4
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T13	2		T15	5		T16	2
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T15	5		T20	1		T21	4
all_values[1]	auto[0]	auto[1]	auto[1]	97	1			T13	5		T15	3		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	209	1			T13	4		T15	6		T16	1
all_values[1]	auto[1]	auto[1]	auto[1]	166	1			T13	4		T15	5		T18	1
all_values[2]	auto[0]	auto[0]	auto[0]	171	1			T13	3		T15	2		T16	1
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T13	3		T15	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	164	1			T13	5		T15	4		T16	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T15	3		T16	1		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	215	1			T13	5		T15	10		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	177	1			T13	4		T15	11		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T13	1		T15	5		T16	1
all_values[3]	auto[0]	auto[0]	auto[1]	97	1			T13	4		T15	4		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	169	1			T13	3		T15	7		T16	1
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T13	1		T15	4		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	197	1			T13	8		T15	7		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	176	1			T13	3		T15	4		T16	1
all_values[4]	auto[0]	auto[0]	auto[0]	175	1			T13	5		T15	3		T18	1
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T13	2		T15	3		T21	1
all_values[4]	auto[0]	auto[1]	auto[0]	172	1			T13	4		T15	8		T16	2
all_values[4]	auto[0]	auto[1]	auto[1]	88	1			T15	2		T16	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	192	1			T13	7		T15	10		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	160	1			T13	2		T15	5		T16	1
all_values[5]	auto[0]	auto[0]	auto[0]	284	1			T13	7		T15	13		T16	2
all_values[5]	auto[0]	auto[1]	auto[0]	216	1			T13	6		T15	6		T16	1
all_values[5]	auto[1]	auto[0]	auto[1]	203	1			T13	5		T15	7		T18	1
all_values[5]	auto[1]	auto[1]	auto[1]	171	1			T13	2		T15	5		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	197	1			T13	7		T15	8		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	82	1			T13	2		T15	2		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T13	6		T15	11		T16	1
all_values[6]	auto[0]	auto[1]	auto[1]	80	1			T15	1		T20	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	218	1			T13	4		T15	7		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	156	1			T13	1		T15	2		T16	1
all_values[7]	auto[0]	auto[0]	auto[0]	162	1			T13	4		T15	6		T16	1
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T15	3		T18	1		T19	1
all_values[7]	auto[0]	auto[1]	auto[0]	175	1			T15	5		T16	1		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T13	5		T15	3		T20	1
all_values[7]	auto[1]	auto[0]	auto[1]	224	1			T13	4		T15	10		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	143	1			T13	7		T15	4		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal