Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1754

1

T3

12

T8

5

T13

3

auto[1]

1587

1

T3

6

T8

3

T13

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1858

1

T3

16

T8

8

T13

13

auto[1]

1483

1

T3

2

T27

23

T30

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2653

1

T3

11

T8

5

T13

8

auto[1]

688

1

T3

7

T8

3

T13

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	689	1			T13	3		T25	2		T27	5
valid[1]	663	1			T3	5		T8	4		T13	2
valid[2]	683	1			T3	3		T8	1		T25	6
valid[3]	674	1			T3	5		T8	2		T13	5
valid[4]	632	1			T3	5		T8	1		T13	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	126	1			T13	1		T30	1		T33	1
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T27	3		T31	3		T43	2
auto[0]	auto[0]	valid[1]	auto[0]	112	1			T3	2		T8	2		T25	2
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T27	4		T80	2		T90	3
auto[0]	auto[0]	valid[2]	auto[0]	143	1			T8	1		T25	2		T30	1
auto[0]	auto[0]	valid[2]	auto[1]	163	1			T27	1		T31	3		T80	2
auto[0]	auto[0]	valid[3]	auto[0]	120	1			T3	1		T13	1		T25	1
auto[0]	auto[0]	valid[3]	auto[1]	177	1			T3	1		T27	1		T31	1
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T3	2		T30	1		T91	1
auto[0]	auto[0]	valid[4]	auto[1]	132	1			T3	1		T27	4		T80	1
auto[0]	auto[1]	valid[0]	auto[0]	108	1			T13	1		T25	2		T33	2
auto[0]	auto[1]	valid[0]	auto[1]	147	1			T27	2		T92	1		T19	1
auto[0]	auto[1]	valid[1]	auto[0]	110	1			T3	1		T8	2		T13	2
auto[0]	auto[1]	valid[1]	auto[1]	135	1			T27	2		T31	1		T92	1
auto[0]	auto[1]	valid[2]	auto[0]	101	1			T25	1		T53	2		T91	1
auto[0]	auto[1]	valid[2]	auto[1]	147	1			T27	1		T30	1		T92	1
auto[0]	auto[1]	valid[3]	auto[0]	108	1			T3	1		T13	1		T53	1
auto[0]	auto[1]	valid[3]	auto[1]	125	1			T27	3		T31	1		T92	2
auto[0]	auto[1]	valid[4]	auto[0]	123	1			T3	2		T13	2		T25	1
auto[0]	auto[1]	valid[4]	auto[1]	133	1			T27	2		T80	1		T90	1
auto[1]	auto[0]	valid[0]	auto[0]	72	1			T53	1		T16	1		T18	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T3	1		T25	1		T30	1
auto[1]	auto[0]	valid[2]	auto[0]	56	1			T3	2		T25	2		T30	1
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T3	2		T8	1		T25	1
auto[1]	auto[0]	valid[4]	auto[0]	71	1			T8	1		T13	1		T25	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T13	1		T47	1		T36	1
auto[1]	auto[1]	valid[1]	auto[0]	69	1			T3	1		T25	1		T32	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T3	1		T25	1		T32	1
auto[1]	auto[1]	valid[3]	auto[0]	79	1			T8	1		T13	3		T25	1
auto[1]	auto[1]	valid[4]	auto[0]	54	1			T25	1		T33	2		T43	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal