Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48130

1

T3

457

T4

1

T8

105

auto[1]

14733

1

T3

73

T27

268

T30

37

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45282

1

T3

354

T8

75

T13

255

auto[1]

17581

1

T3

176

T4

1

T8

30

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32285	1			T3	260		T8	60		T13	178
others[1]	5339	1			T3	44		T8	5		T13	44
others[2]	5298	1			T3	36		T8	10		T13	36
others[3]	6135	1			T3	52		T8	8		T13	42
interest[1]	3428	1			T3	36		T4	1		T8	3
interest[4]	21122	1			T3	166		T8	38		T13	120
interest[64]	10378	1			T3	102		T8	19		T13	71

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15683	1			T3	133		T8	45		T13	119
auto[0]	auto[0]	others[1]	2601	1			T3	23		T8	3		T13	26
auto[0]	auto[0]	others[2]	2527	1			T3	22		T8	7		T13	24
auto[0]	auto[0]	others[3]	2988	1			T3	21		T8	6		T13	29
auto[0]	auto[0]	interest[1]	1679	1			T3	23		T8	2		T13	4
auto[0]	auto[0]	interest[4]	10216	1			T3	84		T8	25		T13	83
auto[0]	auto[0]	interest[64]	5071	1			T3	59		T8	12		T13	53
auto[0]	auto[1]	others[0]	7655	1			T3	36		T27	144		T30	18
auto[0]	auto[1]	others[1]	1244	1			T3	6		T27	23		T30	2
auto[0]	auto[1]	others[2]	1275	1			T3	3		T27	25		T30	5
auto[0]	auto[1]	others[3]	1417	1			T3	13		T27	27		T30	4
auto[0]	auto[1]	interest[1]	777	1			T3	3		T27	12		T30	2
auto[0]	auto[1]	interest[4]	5118	1			T3	23		T27	108		T30	13
auto[0]	auto[1]	interest[64]	2365	1			T3	12		T27	37		T30	6
auto[1]	auto[0]	others[0]	8947	1			T3	91		T8	15		T13	59
auto[1]	auto[0]	others[1]	1494	1			T3	15		T8	2		T13	18
auto[1]	auto[0]	others[2]	1496	1			T3	11		T8	3		T13	12
auto[1]	auto[0]	others[3]	1730	1			T3	18		T8	2		T13	13
auto[1]	auto[0]	interest[1]	972	1			T3	10		T4	1		T8	1
auto[1]	auto[0]	interest[4]	5788	1			T3	59		T8	13		T13	37
auto[1]	auto[0]	interest[64]	2942	1			T3	31		T8	7		T13	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal