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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1151
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T1041 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2249882739 Jul 24 04:59:44 PM PDT 24 Jul 24 04:59:45 PM PDT 24 34462215 ps
T121 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.392159089 Jul 24 05:00:02 PM PDT 24 Jul 24 05:00:19 PM PDT 24 99823092 ps
T113 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2668968477 Jul 24 05:01:29 PM PDT 24 Jul 24 05:01:32 PM PDT 24 878553100 ps
T122 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3740893052 Jul 24 05:00:08 PM PDT 24 Jul 24 05:00:17 PM PDT 24 154826740 ps
T1042 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1235561424 Jul 24 05:00:13 PM PDT 24 Jul 24 05:00:17 PM PDT 24 18828226 ps
T105 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1456578467 Jul 24 04:59:44 PM PDT 24 Jul 24 04:59:49 PM PDT 24 385002013 ps
T106 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1953495187 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:20 PM PDT 24 70233658 ps
T1043 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1677279536 Jul 24 05:00:14 PM PDT 24 Jul 24 05:00:17 PM PDT 24 26847453 ps
T123 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4018176690 Jul 24 05:00:00 PM PDT 24 Jul 24 05:00:03 PM PDT 24 193559059 ps
T124 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3110161275 Jul 24 04:59:38 PM PDT 24 Jul 24 04:59:40 PM PDT 24 359830805 ps
T115 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4211136363 Jul 24 05:00:02 PM PDT 24 Jul 24 05:00:19 PM PDT 24 152795327 ps
T125 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.68684653 Jul 24 04:59:57 PM PDT 24 Jul 24 04:59:59 PM PDT 24 30941117 ps
T1044 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3633715270 Jul 24 05:00:00 PM PDT 24 Jul 24 05:00:00 PM PDT 24 11983386 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3054238868 Jul 24 04:59:49 PM PDT 24 Jul 24 04:59:53 PM PDT 24 417588062 ps
T103 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2616121015 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:59 PM PDT 24 829814040 ps
T116 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3541313584 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:53 PM PDT 24 65791285 ps
T1046 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.805930958 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:17 PM PDT 24 231149433 ps
T104 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2574728478 Jul 24 05:00:20 PM PDT 24 Jul 24 05:00:40 PM PDT 24 1238858487 ps
T170 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3233528876 Jul 24 04:59:57 PM PDT 24 Jul 24 05:00:16 PM PDT 24 1252786713 ps
T1047 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4057283367 Jul 24 04:59:47 PM PDT 24 Jul 24 04:59:48 PM PDT 24 16575049 ps
T126 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3427885650 Jul 24 04:59:43 PM PDT 24 Jul 24 04:59:46 PM PDT 24 74781531 ps
T168 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1046019043 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:35 PM PDT 24 306046844 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.800673621 Jul 24 04:59:44 PM PDT 24 Jul 24 04:59:45 PM PDT 24 10954960 ps
T1049 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.313020610 Jul 24 04:59:53 PM PDT 24 Jul 24 04:59:59 PM PDT 24 48377728 ps
T173 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2789218622 Jul 24 04:59:58 PM PDT 24 Jul 24 05:00:10 PM PDT 24 770760634 ps
T155 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2098524012 Jul 24 04:59:52 PM PDT 24 Jul 24 04:59:56 PM PDT 24 685733925 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4196592398 Jul 24 04:59:47 PM PDT 24 Jul 24 04:59:48 PM PDT 24 30674962 ps
T156 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3235226982 Jul 24 04:59:46 PM PDT 24 Jul 24 04:59:50 PM PDT 24 593700153 ps
T157 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2569956831 Jul 24 04:59:47 PM PDT 24 Jul 24 04:59:50 PM PDT 24 949553559 ps
T1051 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2710986669 Jul 24 04:59:53 PM PDT 24 Jul 24 04:59:54 PM PDT 24 53024707 ps
T87 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2977120117 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:50 PM PDT 24 38925230 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2856753014 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:49 PM PDT 24 47139707 ps
T127 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.798827421 Jul 24 04:59:47 PM PDT 24 Jul 24 05:00:03 PM PDT 24 698130596 ps
T1052 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2919861337 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:18 PM PDT 24 378845783 ps
T164 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.858254301 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:55 PM PDT 24 677105500 ps
T114 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.595074316 Jul 24 04:59:57 PM PDT 24 Jul 24 04:59:58 PM PDT 24 210502347 ps
T107 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2791061200 Jul 24 05:00:13 PM PDT 24 Jul 24 05:00:19 PM PDT 24 81703011 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3493711833 Jul 24 04:59:46 PM PDT 24 Jul 24 04:59:59 PM PDT 24 116356338 ps
T108 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2723485243 Jul 24 05:00:14 PM PDT 24 Jul 24 05:00:19 PM PDT 24 69799681 ps
T1053 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1360361491 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:22 PM PDT 24 15909218 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1134661666 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:19 PM PDT 24 243411310 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.536238588 Jul 24 04:59:53 PM PDT 24 Jul 24 04:59:57 PM PDT 24 55697997 ps
T174 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.31540520 Jul 24 04:59:49 PM PDT 24 Jul 24 04:59:57 PM PDT 24 1079081552 ps
T1056 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3028604228 Jul 24 04:59:43 PM PDT 24 Jul 24 04:59:46 PM PDT 24 132143239 ps
T128 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3626301296 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:52 PM PDT 24 73224419 ps
T175 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1345592056 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:58 PM PDT 24 1680110882 ps
T131 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3136549740 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:59 PM PDT 24 110121143 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.69153566 Jul 24 04:59:58 PM PDT 24 Jul 24 05:00:02 PM PDT 24 186803422 ps
T1058 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2665979799 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:19 PM PDT 24 18064906 ps
T129 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.961919142 Jul 24 04:59:57 PM PDT 24 Jul 24 05:00:16 PM PDT 24 339883404 ps
T169 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.577310439 Jul 24 04:59:39 PM PDT 24 Jul 24 04:59:47 PM PDT 24 289355275 ps
T1059 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.297306770 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:24 PM PDT 24 171313427 ps
T110 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3696989570 Jul 24 05:00:16 PM PDT 24 Jul 24 05:00:20 PM PDT 24 1655042289 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3475280631 Jul 24 04:59:50 PM PDT 24 Jul 24 05:00:05 PM PDT 24 2508716779 ps
T1061 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2366659104 Jul 24 04:59:47 PM PDT 24 Jul 24 04:59:52 PM PDT 24 29102986 ps
T111 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.509254624 Jul 24 05:00:16 PM PDT 24 Jul 24 05:00:21 PM PDT 24 289241671 ps
T1062 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1444550599 Jul 24 05:00:11 PM PDT 24 Jul 24 05:00:17 PM PDT 24 53634977 ps
T1063 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1050627556 Jul 24 05:00:17 PM PDT 24 Jul 24 05:00:18 PM PDT 24 19767633 ps
T1064 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2421293349 Jul 24 04:59:57 PM PDT 24 Jul 24 05:00:00 PM PDT 24 128298937 ps
T1065 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3569649318 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:19 PM PDT 24 141746266 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4013157777 Jul 24 05:01:26 PM PDT 24 Jul 24 05:01:29 PM PDT 24 53003693 ps
T1067 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3754239912 Jul 24 05:00:22 PM PDT 24 Jul 24 05:00:24 PM PDT 24 52698881 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1478639073 Jul 24 04:59:46 PM PDT 24 Jul 24 04:59:51 PM PDT 24 221725570 ps
T1068 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3139142660 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:16 PM PDT 24 15523226 ps
T1069 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.65477553 Jul 24 05:01:47 PM PDT 24 Jul 24 05:01:50 PM PDT 24 572851919 ps
T1070 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.83358993 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:26 PM PDT 24 826796263 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.326541346 Jul 24 04:59:45 PM PDT 24 Jul 24 05:00:07 PM PDT 24 566280391 ps
T1072 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1897508825 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:49 PM PDT 24 22064857 ps
T1073 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1118848017 Jul 24 04:59:52 PM PDT 24 Jul 24 04:59:53 PM PDT 24 45724979 ps
T1074 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.626273902 Jul 24 05:00:16 PM PDT 24 Jul 24 05:00:31 PM PDT 24 638414158 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3527684996 Jul 24 04:59:49 PM PDT 24 Jul 24 04:59:51 PM PDT 24 25791314 ps
T171 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3448767942 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:24 PM PDT 24 287432529 ps
T1076 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2426004609 Jul 24 04:59:48 PM PDT 24 Jul 24 05:00:03 PM PDT 24 712444310 ps
T1077 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1945479622 Jul 24 05:00:02 PM PDT 24 Jul 24 05:00:17 PM PDT 24 48454514 ps
T1078 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.455972269 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:54 PM PDT 24 64237592 ps
T1079 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3043426566 Jul 24 04:59:44 PM PDT 24 Jul 24 04:59:46 PM PDT 24 104253577 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1425495816 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:49 PM PDT 24 257324642 ps
T1080 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1071712675 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:17 PM PDT 24 12377688 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3864579025 Jul 24 04:59:57 PM PDT 24 Jul 24 04:59:58 PM PDT 24 25135320 ps
T1082 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1777940682 Jul 24 04:59:42 PM PDT 24 Jul 24 04:59:43 PM PDT 24 37378090 ps
T1083 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.887721609 Jul 24 05:00:00 PM PDT 24 Jul 24 05:00:02 PM PDT 24 53891553 ps
T1084 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3312511378 Jul 24 05:00:00 PM PDT 24 Jul 24 05:00:09 PM PDT 24 1371108252 ps
T1085 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2728295568 Jul 24 04:59:49 PM PDT 24 Jul 24 04:59:53 PM PDT 24 613770523 ps
T1086 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.518559311 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:17 PM PDT 24 16351790 ps
T1087 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.317353051 Jul 24 05:00:25 PM PDT 24 Jul 24 05:00:27 PM PDT 24 292453007 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3750917227 Jul 24 04:59:57 PM PDT 24 Jul 24 05:00:10 PM PDT 24 208358052 ps
T1089 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1344293518 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:18 PM PDT 24 53994706 ps
T1090 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1291441693 Jul 24 04:59:42 PM PDT 24 Jul 24 04:59:45 PM PDT 24 725583135 ps
T1091 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2338250752 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:20 PM PDT 24 888918601 ps
T167 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.356384239 Jul 24 04:59:46 PM PDT 24 Jul 24 04:59:50 PM PDT 24 323953793 ps
T172 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.380806717 Jul 24 04:59:55 PM PDT 24 Jul 24 05:00:19 PM PDT 24 1125685506 ps
T1092 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1020863690 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:38 PM PDT 24 369825970 ps
T1093 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1920031617 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:23 PM PDT 24 549849014 ps
T1094 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.391920653 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:17 PM PDT 24 28519987 ps
T1095 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4205063504 Jul 24 05:00:08 PM PDT 24 Jul 24 05:00:24 PM PDT 24 1497369167 ps
T1096 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2134185811 Jul 24 04:59:58 PM PDT 24 Jul 24 05:00:00 PM PDT 24 146454161 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4109643988 Jul 24 04:59:44 PM PDT 24 Jul 24 04:59:46 PM PDT 24 115453916 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3905195895 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:19 PM PDT 24 103201151 ps
T1099 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1123045397 Jul 24 05:00:23 PM PDT 24 Jul 24 05:00:24 PM PDT 24 126678144 ps
T1100 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3723421519 Jul 24 05:00:10 PM PDT 24 Jul 24 05:00:17 PM PDT 24 33319351 ps
T1101 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1464123065 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:49 PM PDT 24 13884304 ps
T1102 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2777292342 Jul 24 04:59:40 PM PDT 24 Jul 24 04:59:42 PM PDT 24 1172753731 ps
T1103 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3555503703 Jul 24 04:59:54 PM PDT 24 Jul 24 04:59:55 PM PDT 24 122236565 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3931176826 Jul 24 04:59:48 PM PDT 24 Jul 24 04:59:49 PM PDT 24 113460168 ps
T1105 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.21610026 Jul 24 05:00:10 PM PDT 24 Jul 24 05:00:17 PM PDT 24 36342929 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1725489470 Jul 24 05:00:13 PM PDT 24 Jul 24 05:00:20 PM PDT 24 64178037 ps
T1107 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3996747922 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:17 PM PDT 24 11310564 ps
T1108 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4158200117 Jul 24 05:00:07 PM PDT 24 Jul 24 05:00:17 PM PDT 24 18508830 ps
T1109 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3277148246 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:17 PM PDT 24 13420680 ps
T1110 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.55421832 Jul 24 05:00:00 PM PDT 24 Jul 24 05:00:01 PM PDT 24 43894311 ps
T1111 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3839202933 Jul 24 05:00:21 PM PDT 24 Jul 24 05:00:22 PM PDT 24 55834186 ps
T1112 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3921505556 Jul 24 04:59:57 PM PDT 24 Jul 24 04:59:58 PM PDT 24 15669274 ps
T1113 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.870186146 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:17 PM PDT 24 21970554 ps
T1114 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3941226003 Jul 24 04:59:53 PM PDT 24 Jul 24 04:59:56 PM PDT 24 473262402 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3584882857 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:54 PM PDT 24 367287949 ps
T1116 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1026926395 Jul 24 04:59:49 PM PDT 24 Jul 24 04:59:53 PM PDT 24 58874633 ps
T1117 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2715944825 Jul 24 05:00:18 PM PDT 24 Jul 24 05:00:25 PM PDT 24 204130675 ps
T1118 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2520285270 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:20 PM PDT 24 191384574 ps
T1119 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.110661228 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:17 PM PDT 24 27602827 ps
T1120 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1417766464 Jul 24 04:59:59 PM PDT 24 Jul 24 05:00:02 PM PDT 24 50869075 ps
T1121 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1224883219 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:59 PM PDT 24 525701268 ps
T1122 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1651568383 Jul 24 04:59:55 PM PDT 24 Jul 24 04:59:59 PM PDT 24 43725589 ps
T1123 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2994117829 Jul 24 04:59:43 PM PDT 24 Jul 24 04:59:46 PM PDT 24 328540893 ps
T1124 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3685345235 Jul 24 04:59:53 PM PDT 24 Jul 24 04:59:55 PM PDT 24 35904386 ps
T1125 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2259601853 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:52 PM PDT 24 19885392 ps
T1126 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1766302192 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:18 PM PDT 24 14063557 ps
T1127 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3784200961 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:20 PM PDT 24 203036210 ps
T1128 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.418139987 Jul 24 04:59:52 PM PDT 24 Jul 24 04:59:54 PM PDT 24 137359190 ps
T1129 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2902516856 Jul 24 04:59:40 PM PDT 24 Jul 24 04:59:41 PM PDT 24 22866235 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2010897071 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:18 PM PDT 24 52924729 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3384003207 Jul 24 04:59:57 PM PDT 24 Jul 24 05:00:11 PM PDT 24 2546799114 ps
T1132 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2469502676 Jul 24 05:00:15 PM PDT 24 Jul 24 05:00:18 PM PDT 24 16107590 ps
T1133 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.996853393 Jul 24 05:00:09 PM PDT 24 Jul 24 05:00:17 PM PDT 24 22720632 ps
T1134 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.840133486 Jul 24 04:59:56 PM PDT 24 Jul 24 04:59:57 PM PDT 24 196663446 ps
T1135 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.395996908 Jul 24 04:59:50 PM PDT 24 Jul 24 05:00:07 PM PDT 24 1564032157 ps
T1136 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.185109018 Jul 24 04:59:50 PM PDT 24 Jul 24 04:59:51 PM PDT 24 116500439 ps
T1137 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.927050392 Jul 24 04:59:56 PM PDT 24 Jul 24 04:59:59 PM PDT 24 144329866 ps
T1138 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2052650791 Jul 24 05:00:19 PM PDT 24 Jul 24 05:00:20 PM PDT 24 22181611 ps
T1139 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.312717617 Jul 24 04:59:58 PM PDT 24 Jul 24 05:00:01 PM PDT 24 84870941 ps
T1140 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1381941491 Jul 24 05:00:26 PM PDT 24 Jul 24 05:00:27 PM PDT 24 47898430 ps
T1141 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1312765500 Jul 24 04:59:47 PM PDT 24 Jul 24 04:59:51 PM PDT 24 256481351 ps
T1142 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2593601157 Jul 24 04:59:55 PM PDT 24 Jul 24 04:59:58 PM PDT 24 121576704 ps
T1143 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3229607781 Jul 24 05:00:08 PM PDT 24 Jul 24 05:00:17 PM PDT 24 27333399 ps
T1144 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.679835510 Jul 24 04:59:48 PM PDT 24 Jul 24 05:00:22 PM PDT 24 1840201451 ps
T1145 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4277343001 Jul 24 04:59:58 PM PDT 24 Jul 24 05:00:00 PM PDT 24 34862293 ps
T1146 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2838624269 Jul 24 04:59:59 PM PDT 24 Jul 24 05:00:07 PM PDT 24 672750506 ps
T1147 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3012796774 Jul 24 04:59:51 PM PDT 24 Jul 24 04:59:54 PM PDT 24 98966291 ps
T1148 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3141621567 Jul 24 05:00:04 PM PDT 24 Jul 24 05:00:18 PM PDT 24 88620415 ps
T1149 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1901914024 Jul 24 05:00:05 PM PDT 24 Jul 24 05:00:19 PM PDT 24 1895348581 ps
T1150 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2165232207 Jul 24 05:00:03 PM PDT 24 Jul 24 05:00:17 PM PDT 24 13753725 ps
T1151 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2688224567 Jul 24 05:00:12 PM PDT 24 Jul 24 05:00:22 PM PDT 24 152948206 ps

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2439329603
Short name T8
Test name
Test status
Simulation time 16581952373 ps
CPU time 147.6 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 251628 kb
Host smart-d2b61bb0-4160-48ef-bcdc-2a12e105d9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439329603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2439329603
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3571528831
Short name T41
Test name
Test status
Simulation time 38226088759 ps
CPU time 164.37 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:09:25 PM PDT 24
Peak memory 250376 kb
Host smart-b0f8fdb4-72c7-4cc7-89db-18bf5a27a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571528831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3571528831
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.266700015
Short name T19
Test name
Test status
Simulation time 7917557503 ps
CPU time 140.46 seconds
Started Jul 24 05:05:56 PM PDT 24
Finished Jul 24 05:08:16 PM PDT 24
Peak memory 274488 kb
Host smart-334be18a-9f5a-44ad-bd68-c93ee797c351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266700015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.266700015
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.270598490
Short name T43
Test name
Test status
Simulation time 13646540559 ps
CPU time 110.11 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:07:42 PM PDT 24
Peak memory 258372 kb
Host smart-fb9ec326-291f-4a04-adef-c2192ce0ef64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270598490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.270598490
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2616121015
Short name T103
Test name
Test status
Simulation time 829814040 ps
CPU time 7.73 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 216064 kb
Host smart-8559d566-cdbf-4f91-a7f8-f921fb4f10ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616121015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2616121015
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2138031531
Short name T22
Test name
Test status
Simulation time 46133373838 ps
CPU time 375.2 seconds
Started Jul 24 05:06:22 PM PDT 24
Finished Jul 24 05:12:37 PM PDT 24
Peak memory 253464 kb
Host smart-75fd0551-6b43-4b17-902a-e3219955caa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138031531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2138031531
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4077537313
Short name T33
Test name
Test status
Simulation time 10302593001 ps
CPU time 121 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 274556 kb
Host smart-7a5a8f04-f354-43a2-8c60-c9050e669552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077537313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4077537313
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2449336293
Short name T70
Test name
Test status
Simulation time 14889199 ps
CPU time 0.74 seconds
Started Jul 24 05:04:38 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 216784 kb
Host smart-0c186ad7-2fdd-425b-9144-d924a370c7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449336293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2449336293
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.630594311
Short name T188
Test name
Test status
Simulation time 112404475522 ps
CPU time 871.16 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:19:48 PM PDT 24
Peak memory 286516 kb
Host smart-f64b8eb6-caa8-4da4-bba8-70a6db77a558
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630594311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.630594311
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1953495187
Short name T106
Test name
Test status
Simulation time 70233658 ps
CPU time 4 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 216188 kb
Host smart-8fb043a6-cc4a-4dc7-bd7a-ea6dbbeff2c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953495187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
953495187
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2741011103
Short name T187
Test name
Test status
Simulation time 335003889496 ps
CPU time 501.29 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:13:14 PM PDT 24
Peak memory 257780 kb
Host smart-f6fb8e54-7fab-40f3-a685-38a848c54b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741011103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2741011103
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4080292086
Short name T158
Test name
Test status
Simulation time 63087256289 ps
CPU time 576.52 seconds
Started Jul 24 05:06:26 PM PDT 24
Finished Jul 24 05:16:03 PM PDT 24
Peak memory 272648 kb
Host smart-ee95f75a-6c1b-449c-a020-62341275d32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080292086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4080292086
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3945487807
Short name T14
Test name
Test status
Simulation time 331867055 ps
CPU time 1.19 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 237420 kb
Host smart-2156dd50-3264-43f2-8527-a2f2360cb24e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945487807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3945487807
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.935530704
Short name T159
Test name
Test status
Simulation time 130154694542 ps
CPU time 1124.88 seconds
Started Jul 24 05:06:19 PM PDT 24
Finished Jul 24 05:25:05 PM PDT 24
Peak memory 274664 kb
Host smart-54cea96f-1233-4c13-8bc0-a6eda02d24ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935530704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.935530704
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3354642666
Short name T150
Test name
Test status
Simulation time 5149477543 ps
CPU time 23.04 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 234460 kb
Host smart-18519ae5-8dc0-4710-b8f7-e86f97ec0c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354642666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3354642666
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2935880449
Short name T16
Test name
Test status
Simulation time 119660162382 ps
CPU time 519.59 seconds
Started Jul 24 05:05:30 PM PDT 24
Finished Jul 24 05:14:10 PM PDT 24
Peak memory 273416 kb
Host smart-67cb2a4b-87a6-483a-9959-39eaa3d9f0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935880449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2935880449
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.179219709
Short name T181
Test name
Test status
Simulation time 106550560424 ps
CPU time 408.09 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:12:52 PM PDT 24
Peak memory 270196 kb
Host smart-7a3920f3-326c-49f9-935a-e64f7a83ad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179219709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.179219709
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3901087847
Short name T117
Test name
Test status
Simulation time 148677519 ps
CPU time 1.23 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 215876 kb
Host smart-8da8d544-dd5d-47c3-b44e-c44100da18cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901087847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3901087847
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.384846462
Short name T83
Test name
Test status
Simulation time 7965681012 ps
CPU time 55.59 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 241944 kb
Host smart-b0d8b40a-df01-483e-8697-29be1c69238a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384846462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.384846462
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1291150197
Short name T24
Test name
Test status
Simulation time 420978856 ps
CPU time 1.05 seconds
Started Jul 24 05:04:23 PM PDT 24
Finished Jul 24 05:04:24 PM PDT 24
Peak memory 217368 kb
Host smart-04c09067-3934-4a38-be88-8929f8b4a9e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291150197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1291150197
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.367118848
Short name T47
Test name
Test status
Simulation time 57966121646 ps
CPU time 212.56 seconds
Started Jul 24 05:06:21 PM PDT 24
Finished Jul 24 05:09:54 PM PDT 24
Peak memory 266492 kb
Host smart-eb1298c6-f3db-4969-ab48-357a4b0277fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367118848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.367118848
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3334363500
Short name T84
Test name
Test status
Simulation time 103377266212 ps
CPU time 402.24 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:13:25 PM PDT 24
Peak memory 272052 kb
Host smart-b8dc7e57-b915-4457-9cae-5c53c845bd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334363500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3334363500
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1324630693
Short name T48
Test name
Test status
Simulation time 40900866856 ps
CPU time 108.31 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 250124 kb
Host smart-858b0135-ff8f-42e5-8c92-0ee8ca32f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324630693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1324630693
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3233528876
Short name T170
Test name
Test status
Simulation time 1252786713 ps
CPU time 18.35 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 224064 kb
Host smart-45ca0bff-472c-4bcd-a6c6-868f06933bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233528876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3233528876
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.989994683
Short name T53
Test name
Test status
Simulation time 109666717125 ps
CPU time 227.83 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:09:49 PM PDT 24
Peak memory 251632 kb
Host smart-ad524647-1734-4d40-975e-08ce82d3d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989994683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.989994683
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.412220111
Short name T63
Test name
Test status
Simulation time 37091896696 ps
CPU time 195.39 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:08:01 PM PDT 24
Peak memory 265628 kb
Host smart-76f50d9a-623d-4093-8971-624ea4bb2432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412220111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.412220111
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1871794673
Short name T55
Test name
Test status
Simulation time 13364428762 ps
CPU time 126.42 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 274496 kb
Host smart-059ebccb-1448-48c2-a21e-08b3a2409a64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871794673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1871794673
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.435536726
Short name T69
Test name
Test status
Simulation time 12401641 ps
CPU time 0.74 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:30 PM PDT 24
Peak memory 205440 kb
Host smart-ece81357-e4b3-4d5c-ba6f-4ba14f85377d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435536726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.435536726
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3119011677
Short name T281
Test name
Test status
Simulation time 115510162949 ps
CPU time 1033.77 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:23:28 PM PDT 24
Peak memory 291036 kb
Host smart-328f8b42-cada-4d51-984d-54f6e1f4397c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119011677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3119011677
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2965168542
Short name T96
Test name
Test status
Simulation time 28390743232 ps
CPU time 102.98 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 257988 kb
Host smart-2007238e-a677-4f19-b179-8dc730074d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965168542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2965168542
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.577310439
Short name T169
Test name
Test status
Simulation time 289355275 ps
CPU time 7.63 seconds
Started Jul 24 04:59:39 PM PDT 24
Finished Jul 24 04:59:47 PM PDT 24
Peak memory 216156 kb
Host smart-1841d7ce-c16c-487f-9566-27f87151fb4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577310439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.577310439
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1441341710
Short name T195
Test name
Test status
Simulation time 60826989076 ps
CPU time 534.19 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:13:44 PM PDT 24
Peak memory 257848 kb
Host smart-553dcadc-0e44-40a1-905a-5b03d487d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441341710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1441341710
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.18390903
Short name T359
Test name
Test status
Simulation time 44297611 ps
CPU time 0.78 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 206532 kb
Host smart-4ed410ee-4160-419c-a229-adeb49b69fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18390903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.18390903
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.520795648
Short name T261
Test name
Test status
Simulation time 58981958774 ps
CPU time 148.9 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:08:36 PM PDT 24
Peak memory 258020 kb
Host smart-3f7166c5-3886-4e96-9f81-c7b1c9f3dfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520795648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.520795648
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.4202362205
Short name T900
Test name
Test status
Simulation time 109319771294 ps
CPU time 403 seconds
Started Jul 24 05:06:15 PM PDT 24
Finished Jul 24 05:12:58 PM PDT 24
Peak memory 270760 kb
Host smart-9a4d31d6-4d06-4383-885f-736c0a45eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202362205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.4202362205
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3589436063
Short name T298
Test name
Test status
Simulation time 634818624 ps
CPU time 12.71 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 241868 kb
Host smart-a5a7c381-51a8-4875-90fa-687fd24783ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589436063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3589436063
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1478639073
Short name T112
Test name
Test status
Simulation time 221725570 ps
CPU time 4.97 seconds
Started Jul 24 04:59:46 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 216296 kb
Host smart-223f4ae6-1006-4455-80e8-e278ab2c3136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478639073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
478639073
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2305419174
Short name T270
Test name
Test status
Simulation time 186436885056 ps
CPU time 477.7 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:13:39 PM PDT 24
Peak memory 261352 kb
Host smart-d5b2e6fe-5878-4f36-b9af-947c4b0075a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305419174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2305419174
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1900645228
Short name T142
Test name
Test status
Simulation time 10523059320 ps
CPU time 158.27 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:08:44 PM PDT 24
Peak memory 266560 kb
Host smart-d9f26fa0-6aee-445f-a11d-93f8ec9e11e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900645228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1900645228
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1687517528
Short name T152
Test name
Test status
Simulation time 461055149 ps
CPU time 11.67 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 241724 kb
Host smart-479ee17b-8ca7-4430-bf0d-03d955c4d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687517528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1687517528
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4148732668
Short name T209
Test name
Test status
Simulation time 20416966411 ps
CPU time 159.88 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:07:50 PM PDT 24
Peak memory 271208 kb
Host smart-0767b62c-1e80-430c-bbbc-11f701525858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148732668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4148732668
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1304429743
Short name T180
Test name
Test status
Simulation time 1567094302 ps
CPU time 4.29 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 225404 kb
Host smart-abf1717d-7cc6-4852-98dc-60200faf08f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304429743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1304429743
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2618198293
Short name T290
Test name
Test status
Simulation time 22367023965 ps
CPU time 100.63 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 274592 kb
Host smart-022d3fdb-f74e-47a2-b5e4-7db55c1251a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618198293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2618198293
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1618915364
Short name T28
Test name
Test status
Simulation time 38288504 ps
CPU time 0.81 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:35 PM PDT 24
Peak memory 207564 kb
Host smart-56de45f6-3831-48e3-8488-ccc179c54512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618915364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1618915364
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1362915353
Short name T98
Test name
Test status
Simulation time 6730112740 ps
CPU time 18.68 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:31 PM PDT 24
Peak memory 225452 kb
Host smart-69103969-b913-42b8-a618-7778e3d2d966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362915353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1362915353
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3120442766
Short name T86
Test name
Test status
Simulation time 38947815 ps
CPU time 0.98 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 207588 kb
Host smart-cb6fe0bf-ff63-4d08-bb98-017c14583636
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120442766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3120442766
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2728295568
Short name T1085
Test name
Test status
Simulation time 613770523 ps
CPU time 4.6 seconds
Started Jul 24 04:59:49 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 216236 kb
Host smart-125b09b3-f1c9-488f-baac-80d5dc4d028c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728295568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2728295568
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3136549740
Short name T131
Test name
Test status
Simulation time 110121143 ps
CPU time 7.76 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 207836 kb
Host smart-b4f6dd15-a9be-4235-8050-74d38d9ec353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136549740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3136549740
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.326541346
Short name T1071
Test name
Test status
Simulation time 566280391 ps
CPU time 21.49 seconds
Started Jul 24 04:59:45 PM PDT 24
Finished Jul 24 05:00:07 PM PDT 24
Peak memory 207864 kb
Host smart-e8e3b009-2b07-41fd-84b8-398a55aac25d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326541346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.326541346
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1425495816
Short name T88
Test name
Test status
Simulation time 257324642 ps
CPU time 1.15 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 207864 kb
Host smart-85d7569a-9189-41fc-b223-b891e981c162
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425495816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1425495816
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3584882857
Short name T1115
Test name
Test status
Simulation time 367287949 ps
CPU time 2.81 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:54 PM PDT 24
Peak memory 217444 kb
Host smart-69b07c68-98b7-4e22-b41d-64588afab6f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584882857 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3584882857
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2450368433
Short name T120
Test name
Test status
Simulation time 69392605 ps
CPU time 1.31 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 216048 kb
Host smart-0acd4b4d-fe3c-43f5-9253-9f37fbd46d24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450368433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
450368433
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1464123065
Short name T1101
Test name
Test status
Simulation time 13884304 ps
CPU time 0.72 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 204724 kb
Host smart-2408e7d2-3bc0-40c2-934e-14660b75756e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464123065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
464123065
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3043426566
Short name T1079
Test name
Test status
Simulation time 104253577 ps
CPU time 1.91 seconds
Started Jul 24 04:59:44 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 215980 kb
Host smart-4eb9f3eb-2013-4e55-99cc-5674ed523b5d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043426566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3043426566
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2259601853
Short name T1125
Test name
Test status
Simulation time 19885392 ps
CPU time 0.66 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:52 PM PDT 24
Peak memory 204372 kb
Host smart-d47c2ea6-15f5-4749-82f7-69e6a59913a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259601853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2259601853
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1026926395
Short name T1116
Test name
Test status
Simulation time 58874633 ps
CPU time 3.74 seconds
Started Jul 24 04:59:49 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 216032 kb
Host smart-292faa10-dbff-4dd7-b069-81cd25f06433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026926395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1026926395
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1456578467
Short name T105
Test name
Test status
Simulation time 385002013 ps
CPU time 4.99 seconds
Started Jul 24 04:59:44 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 217164 kb
Host smart-77872e67-0d24-4bec-86dd-1b0df393e789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456578467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
456578467
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3750917227
Short name T1088
Test name
Test status
Simulation time 208358052 ps
CPU time 13.38 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 05:00:10 PM PDT 24
Peak memory 216064 kb
Host smart-b070d13c-af06-4041-8aa6-b1dac2508632
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750917227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3750917227
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3493711833
Short name T130
Test name
Test status
Simulation time 116356338 ps
CPU time 7.89 seconds
Started Jul 24 04:59:46 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 207764 kb
Host smart-800a4eac-4ad0-4e79-9d71-f5399736608f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493711833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3493711833
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.679835510
Short name T1144
Test name
Test status
Simulation time 1840201451 ps
CPU time 33.9 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 207820 kb
Host smart-f025dc9a-1694-43f9-8e8a-70f993609722
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679835510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.679835510
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3541313584
Short name T116
Test name
Test status
Simulation time 65791285 ps
CPU time 1.84 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 216044 kb
Host smart-bed75048-3252-4c12-ac4a-f99b85e6c87d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541313584 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3541313584
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.68684653
Short name T125
Test name
Test status
Simulation time 30941117 ps
CPU time 1.95 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 215980 kb
Host smart-22d5e726-dcec-4217-b5c8-39c869e9b139
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68684653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.68684653
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3864579025
Short name T1081
Test name
Test status
Simulation time 25135320 ps
CPU time 0.75 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 204408 kb
Host smart-8d49d47e-5f5b-4c75-adf9-b8b883d5aa30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864579025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
864579025
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2777292342
Short name T1102
Test name
Test status
Simulation time 1172753731 ps
CPU time 1.98 seconds
Started Jul 24 04:59:40 PM PDT 24
Finished Jul 24 04:59:42 PM PDT 24
Peak memory 216064 kb
Host smart-186c7fc2-b866-403e-8378-dbe7d6a39185
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777292342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2777292342
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2249882739
Short name T1041
Test name
Test status
Simulation time 34462215 ps
CPU time 0.67 seconds
Started Jul 24 04:59:44 PM PDT 24
Finished Jul 24 04:59:45 PM PDT 24
Peak memory 204388 kb
Host smart-1b5371e0-bbf2-4549-8a55-df57d9579794
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249882739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2249882739
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1312765500
Short name T1141
Test name
Test status
Simulation time 256481351 ps
CPU time 3.59 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 215960 kb
Host smart-282a1b4d-8ac2-4851-b314-87aa9f8bdc21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312765500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1312765500
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.356384239
Short name T167
Test name
Test status
Simulation time 323953793 ps
CPU time 3.88 seconds
Started Jul 24 04:59:46 PM PDT 24
Finished Jul 24 04:59:50 PM PDT 24
Peak memory 216304 kb
Host smart-fe6a516f-cabf-4848-b62c-c4b42624265c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356384239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.356384239
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.31540520
Short name T174
Test name
Test status
Simulation time 1079081552 ps
CPU time 7.66 seconds
Started Jul 24 04:59:49 PM PDT 24
Finished Jul 24 04:59:57 PM PDT 24
Peak memory 215984 kb
Host smart-982bb787-53e5-4989-9b92-d86760b4d62b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31540520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_t
l_intg_err.31540520
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2919861337
Short name T1052
Test name
Test status
Simulation time 378845783 ps
CPU time 2.76 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 218140 kb
Host smart-e3370e51-6443-4fc5-af5c-d7698598365b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919861337 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2919861337
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2994117829
Short name T1123
Test name
Test status
Simulation time 328540893 ps
CPU time 2.51 seconds
Started Jul 24 04:59:43 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 207748 kb
Host smart-3f9ebb16-820d-4910-87bb-84f9fac59e7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994117829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2994117829
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4196592398
Short name T1050
Test name
Test status
Simulation time 30674962 ps
CPU time 0.72 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:48 PM PDT 24
Peak memory 204320 kb
Host smart-3aadbc3c-d697-45ff-8051-166c8abe2d1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196592398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4196592398
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.805930958
Short name T1046
Test name
Test status
Simulation time 231149433 ps
CPU time 1.82 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 216012 kb
Host smart-ab47a8d5-e5d8-478b-a797-afa4da780c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805930958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.805930958
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.429068875
Short name T101
Test name
Test status
Simulation time 616742052 ps
CPU time 3.89 seconds
Started Jul 24 05:01:13 PM PDT 24
Finished Jul 24 05:01:17 PM PDT 24
Peak memory 215272 kb
Host smart-4bb529dd-24fd-427b-8f51-2704be090401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429068875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.429068875
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4205063504
Short name T1095
Test name
Test status
Simulation time 1497369167 ps
CPU time 7.72 seconds
Started Jul 24 05:00:08 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 215560 kb
Host smart-e0f348f9-ec29-4927-bafc-d14846e44c2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205063504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4205063504
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4013157777
Short name T1066
Test name
Test status
Simulation time 53003693 ps
CPU time 3.16 seconds
Started Jul 24 05:01:26 PM PDT 24
Finished Jul 24 05:01:29 PM PDT 24
Peak memory 217792 kb
Host smart-3074f20c-719d-4c0f-8363-97035e34196e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013157777 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4013157777
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2902516856
Short name T1129
Test name
Test status
Simulation time 22866235 ps
CPU time 0.68 seconds
Started Jul 24 04:59:40 PM PDT 24
Finished Jul 24 04:59:41 PM PDT 24
Peak memory 204516 kb
Host smart-adea40ad-b39e-4031-9f8b-154ba672c683
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902516856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2902516856
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2134185811
Short name T1096
Test name
Test status
Simulation time 146454161 ps
CPU time 1.85 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:00 PM PDT 24
Peak memory 215932 kb
Host smart-1ff0f33b-604e-49e9-8d23-a565e8da056c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134185811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2134185811
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3258585481
Short name T109
Test name
Test status
Simulation time 291105823 ps
CPU time 1.98 seconds
Started Jul 24 04:59:46 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 217188 kb
Host smart-c83f6e4b-7eda-4a86-9489-79465345a2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258585481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3258585481
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2789218622
Short name T173
Test name
Test status
Simulation time 770760634 ps
CPU time 11.36 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:10 PM PDT 24
Peak memory 215940 kb
Host smart-989b38f9-8b59-4d3b-8705-927acd2d1e8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789218622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2789218622
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1134661666
Short name T1054
Test name
Test status
Simulation time 243411310 ps
CPU time 3.55 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 218668 kb
Host smart-c6e75fd4-67c5-459e-90f2-bce5dd227d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134661666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1134661666
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.927050392
Short name T1137
Test name
Test status
Simulation time 144329866 ps
CPU time 2.49 seconds
Started Jul 24 04:59:56 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 216036 kb
Host smart-407c842f-7477-4fe9-b2bb-6f20d67e029c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927050392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.927050392
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1677279536
Short name T1043
Test name
Test status
Simulation time 26847453 ps
CPU time 0.75 seconds
Started Jul 24 05:00:14 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204744 kb
Host smart-05eafa59-5eaf-4f51-b789-ce905e696a6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677279536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1677279536
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.455972269
Short name T1078
Test name
Test status
Simulation time 64237592 ps
CPU time 1.87 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:54 PM PDT 24
Peak memory 215896 kb
Host smart-8a84a0d7-3e18-48f0-b70c-6149c4beeaa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455972269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.455972269
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.380806717
Short name T172
Test name
Test status
Simulation time 1125685506 ps
CPU time 18.15 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 216584 kb
Host smart-689d923d-4cd7-4d49-a60e-d57a06eae5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380806717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.380806717
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2791061200
Short name T107
Test name
Test status
Simulation time 81703011 ps
CPU time 2.44 seconds
Started Jul 24 05:00:13 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 217172 kb
Host smart-9ad1307b-a24a-45db-bb7c-acda88700d7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791061200 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2791061200
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1490028233
Short name T119
Test name
Test status
Simulation time 211127979 ps
CPU time 2.63 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:23 PM PDT 24
Peak memory 207708 kb
Host smart-3e73e097-1736-412e-a1d1-c070a5fadcaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490028233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1490028233
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1071712675
Short name T1080
Test name
Test status
Simulation time 12377688 ps
CPU time 0.71 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204544 kb
Host smart-f0cc5676-f7ae-49be-ac42-5dcb37921cc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071712675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1071712675
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3784200961
Short name T1127
Test name
Test status
Simulation time 203036210 ps
CPU time 4.19 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 215972 kb
Host smart-f03a282d-1c6e-4fe0-809c-6bafb2d3a353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784200961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3784200961
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3905195895
Short name T1098
Test name
Test status
Simulation time 103201151 ps
CPU time 3.39 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 216232 kb
Host smart-f761f617-95c6-4810-a134-84183c56c85d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905195895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3905195895
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2574728478
Short name T104
Test name
Test status
Simulation time 1238858487 ps
CPU time 19.58 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:40 PM PDT 24
Peak memory 216572 kb
Host smart-4fddc78e-7841-4409-be3d-9fb551775616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574728478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2574728478
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3569649318
Short name T1065
Test name
Test status
Simulation time 141746266 ps
CPU time 3.14 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 217384 kb
Host smart-8f69f45e-4ba1-4123-a6cf-4be331879401
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569649318 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3569649318
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2366659104
Short name T1061
Test name
Test status
Simulation time 29102986 ps
CPU time 1.83 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:52 PM PDT 24
Peak memory 216056 kb
Host smart-dde85606-cac1-4053-a3f1-6c96d1050738
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366659104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2366659104
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1123045397
Short name T1099
Test name
Test status
Simulation time 126678144 ps
CPU time 0.73 seconds
Started Jul 24 05:00:23 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 204832 kb
Host smart-3b7219bc-e7eb-46b5-9c35-300715eadd0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123045397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1123045397
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2688224567
Short name T1151
Test name
Test status
Simulation time 152948206 ps
CPU time 1.67 seconds
Started Jul 24 05:00:12 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 207832 kb
Host smart-8a0bb21c-0514-4ed0-a0c8-66813f6819ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688224567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2688224567
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2723485243
Short name T108
Test name
Test status
Simulation time 69799681 ps
CPU time 2.22 seconds
Started Jul 24 05:00:14 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 216420 kb
Host smart-902a5b84-ee1f-4ec2-b98f-c9e0b7aba77f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723485243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2723485243
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2715944825
Short name T1117
Test name
Test status
Simulation time 204130675 ps
CPU time 6.31 seconds
Started Jul 24 05:00:18 PM PDT 24
Finished Jul 24 05:00:25 PM PDT 24
Peak memory 215984 kb
Host smart-e6053544-afdc-4e93-8fc1-eb0006c12bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715944825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2715944825
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4211136363
Short name T115
Test name
Test status
Simulation time 152795327 ps
CPU time 2.68 seconds
Started Jul 24 05:00:02 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 217396 kb
Host smart-b2eaa22d-109b-45a7-a906-f1f5b57685f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211136363 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4211136363
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.297306770
Short name T1059
Test name
Test status
Simulation time 171313427 ps
CPU time 2.12 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 215964 kb
Host smart-e0a80a25-9795-4d2d-b874-bb6ddbbb922d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297306770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.297306770
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1235561424
Short name T1042
Test name
Test status
Simulation time 18828226 ps
CPU time 0.81 seconds
Started Jul 24 05:00:13 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204684 kb
Host smart-838e659a-457e-4a79-9a00-d1b5db2fddc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235561424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1235561424
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1920031617
Short name T1093
Test name
Test status
Simulation time 549849014 ps
CPU time 3.01 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:23 PM PDT 24
Peak memory 215912 kb
Host smart-ac0d73ff-62af-4fc8-809e-84fea8048ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920031617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1920031617
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.887721609
Short name T1083
Test name
Test status
Simulation time 53891553 ps
CPU time 1.86 seconds
Started Jul 24 05:00:00 PM PDT 24
Finished Jul 24 05:00:02 PM PDT 24
Peak memory 216172 kb
Host smart-a035a278-5360-42a3-8316-a5bcfe62a228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887721609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.887721609
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3312511378
Short name T1084
Test name
Test status
Simulation time 1371108252 ps
CPU time 8.06 seconds
Started Jul 24 05:00:00 PM PDT 24
Finished Jul 24 05:00:09 PM PDT 24
Peak memory 215948 kb
Host smart-61294c02-5fb1-448c-9a47-f17887a0f55b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312511378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3312511378
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.595074316
Short name T114
Test name
Test status
Simulation time 210502347 ps
CPU time 1.63 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 216032 kb
Host smart-d8b4eca9-c644-4be1-a3bd-ed8da11c0b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595074316 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.595074316
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.392159089
Short name T121
Test name
Test status
Simulation time 99823092 ps
CPU time 2.42 seconds
Started Jul 24 05:00:02 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 216080 kb
Host smart-a62eaad9-e283-4071-ac69-8bb7b38b433f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392159089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.392159089
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.701648698
Short name T1031
Test name
Test status
Simulation time 23223977 ps
CPU time 0.76 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 204412 kb
Host smart-c63122e5-d1e8-43ee-afde-f5e0337cb1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701648698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.701648698
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.391920653
Short name T1094
Test name
Test status
Simulation time 28519987 ps
CPU time 1.73 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 207840 kb
Host smart-74cf786f-eb15-4f70-9878-f0eb9c4e2a82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391920653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.391920653
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.83358993
Short name T1070
Test name
Test status
Simulation time 826796263 ps
CPU time 4.47 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:26 PM PDT 24
Peak memory 216148 kb
Host smart-9f54da59-2fa1-4bd4-8bd6-240096e31deb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83358993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.83358993
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.626273902
Short name T1074
Test name
Test status
Simulation time 638414158 ps
CPU time 13.9 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:00:31 PM PDT 24
Peak memory 215996 kb
Host smart-273e1133-5920-490e-a670-fefa169b38af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626273902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.626273902
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1417766464
Short name T1120
Test name
Test status
Simulation time 50869075 ps
CPU time 2.87 seconds
Started Jul 24 04:59:59 PM PDT 24
Finished Jul 24 05:00:02 PM PDT 24
Peak memory 218464 kb
Host smart-5e525e6a-b01e-4cb3-a842-c84539eb5b28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417766464 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1417766464
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3685345235
Short name T1124
Test name
Test status
Simulation time 35904386 ps
CPU time 1.27 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 04:59:55 PM PDT 24
Peak memory 207788 kb
Host smart-d2499c90-edb4-4d4a-8446-44e26fa4aaa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685345235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3685345235
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.110661228
Short name T1119
Test name
Test status
Simulation time 27602827 ps
CPU time 0.78 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204512 kb
Host smart-022ed3f1-025b-478a-a68e-55394bb5a738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110661228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.110661228
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2338250752
Short name T1091
Test name
Test status
Simulation time 888918601 ps
CPU time 4.03 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 215900 kb
Host smart-ee966498-3ba9-449c-a558-a3fd583ff6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338250752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2338250752
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3696989570
Short name T110
Test name
Test status
Simulation time 1655042289 ps
CPU time 2.77 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 216188 kb
Host smart-4a432b53-ed8f-489e-be0f-37cfaa6aefcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696989570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3696989570
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2838624269
Short name T1146
Test name
Test status
Simulation time 672750506 ps
CPU time 7.68 seconds
Started Jul 24 04:59:59 PM PDT 24
Finished Jul 24 05:00:07 PM PDT 24
Peak memory 216152 kb
Host smart-2a87ff92-e90d-42d7-a8d7-95349e3c7693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838624269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2838624269
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1725489470
Short name T1106
Test name
Test status
Simulation time 64178037 ps
CPU time 3.31 seconds
Started Jul 24 05:00:13 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 218768 kb
Host smart-26354cec-1fdc-42f7-8f43-a87bb25a519a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725489470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1725489470
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3740893052
Short name T122
Test name
Test status
Simulation time 154826740 ps
CPU time 1.4 seconds
Started Jul 24 05:00:08 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 215920 kb
Host smart-1ae41fe4-4fe0-4a91-bfe4-b8c1cf1a6a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740893052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3740893052
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.518559311
Short name T1086
Test name
Test status
Simulation time 16351790 ps
CPU time 0.75 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204392 kb
Host smart-e390e4f3-428b-46cf-84ed-5a2380e637c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518559311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.518559311
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.317353051
Short name T1087
Test name
Test status
Simulation time 292453007 ps
CPU time 1.74 seconds
Started Jul 24 05:00:25 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 207752 kb
Host smart-8119dca6-7618-46be-a842-109e3a3eba1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317353051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.317353051
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.509254624
Short name T111
Test name
Test status
Simulation time 289241671 ps
CPU time 4.11 seconds
Started Jul 24 05:00:16 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 216284 kb
Host smart-27d7eed5-c138-4a55-a283-2f0b2d498996
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509254624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.509254624
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1679027635
Short name T102
Test name
Test status
Simulation time 573458995 ps
CPU time 14.39 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:30 PM PDT 24
Peak memory 218264 kb
Host smart-51b73d3e-b8c6-461a-b944-1d33a1f21404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679027635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1679027635
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.312717617
Short name T1139
Test name
Test status
Simulation time 84870941 ps
CPU time 2.55 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:01 PM PDT 24
Peak memory 217132 kb
Host smart-9a598e9e-b0e7-4710-ae98-8bb86239bc98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312717617 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.312717617
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4277343001
Short name T1145
Test name
Test status
Simulation time 34862293 ps
CPU time 1.11 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:00 PM PDT 24
Peak memory 207712 kb
Host smart-e41b5b9f-efc9-4bf7-9c46-02ec7f2261c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277343001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4277343001
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2052650791
Short name T1138
Test name
Test status
Simulation time 22181611 ps
CPU time 0.75 seconds
Started Jul 24 05:00:19 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 204496 kb
Host smart-069f907b-0f2d-4c51-98ee-a758baab8521
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052650791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2052650791
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4204228252
Short name T145
Test name
Test status
Simulation time 44502517 ps
CPU time 2.65 seconds
Started Jul 24 05:00:02 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 215988 kb
Host smart-4bed59a0-b1b5-4684-ac0d-5a10eda95e72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204228252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4204228252
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3754239912
Short name T1067
Test name
Test status
Simulation time 52698881 ps
CPU time 1.73 seconds
Started Jul 24 05:00:22 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 217344 kb
Host smart-31d317e1-3b59-4465-9624-ab3e15999eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754239912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3754239912
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3448767942
Short name T171
Test name
Test status
Simulation time 287432529 ps
CPU time 6.97 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:24 PM PDT 24
Peak memory 215888 kb
Host smart-023378ff-9062-45b2-9c5d-fe1f871af77c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448767942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3448767942
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.798827421
Short name T127
Test name
Test status
Simulation time 698130596 ps
CPU time 15.44 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 05:00:03 PM PDT 24
Peak memory 216036 kb
Host smart-e63d0352-d33f-4219-8859-b6e76db37a95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798827421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.798827421
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1693277441
Short name T118
Test name
Test status
Simulation time 1612153002 ps
CPU time 11.04 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 05:00:09 PM PDT 24
Peak memory 207752 kb
Host smart-a861b496-a3eb-416c-b067-2fa4de49ac8a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693277441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1693277441
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.543519466
Short name T85
Test name
Test status
Simulation time 106057891 ps
CPU time 0.95 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 207484 kb
Host smart-12f0dafa-4260-4d33-a9ad-07f047abfba7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543519466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.543519466
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3141621567
Short name T1148
Test name
Test status
Simulation time 88620415 ps
CPU time 1.56 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 215972 kb
Host smart-81c4710b-c4cb-4c4a-9bda-ddedc798ae77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141621567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3141621567
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2593601157
Short name T1142
Test name
Test status
Simulation time 121576704 ps
CPU time 2.75 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 216072 kb
Host smart-fbe35220-f5fd-4e05-b2fd-153e21526763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593601157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
593601157
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.185109018
Short name T1136
Test name
Test status
Simulation time 116500439 ps
CPU time 0.69 seconds
Started Jul 24 04:59:50 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 204748 kb
Host smart-1bc2be6d-6044-4d97-952e-0faab6155aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185109018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.185109018
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.961919142
Short name T129
Test name
Test status
Simulation time 339883404 ps
CPU time 1.33 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 215960 kb
Host smart-8ad44506-2277-4bb5-b5bb-1d401fbd9993
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961919142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.961919142
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1777940682
Short name T1082
Test name
Test status
Simulation time 37378090 ps
CPU time 0.66 seconds
Started Jul 24 04:59:42 PM PDT 24
Finished Jul 24 04:59:43 PM PDT 24
Peak memory 204620 kb
Host smart-14f657c6-63c3-459b-afed-00da0cb42c97
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777940682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1777940682
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1901914024
Short name T1149
Test name
Test status
Simulation time 1895348581 ps
CPU time 3.86 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 215932 kb
Host smart-2cf4dbf9-4ac6-4d38-8551-a04d48b1af58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901914024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1901914024
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.858254301
Short name T164
Test name
Test status
Simulation time 677105500 ps
CPU time 7.53 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:55 PM PDT 24
Peak memory 216084 kb
Host smart-c053b705-afc5-4e0c-acb4-35cb62f56352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858254301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.858254301
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1444550599
Short name T1062
Test name
Test status
Simulation time 53634977 ps
CPU time 0.76 seconds
Started Jul 24 05:00:11 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204836 kb
Host smart-c1e5dc06-be76-4261-a3e8-fd4818abb680
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444550599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1444550599
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3942860508
Short name T1037
Test name
Test status
Simulation time 11705240 ps
CPU time 0.77 seconds
Started Jul 24 05:00:06 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 204776 kb
Host smart-de5b8475-61e3-4f71-a7f5-770f022b57ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942860508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3942860508
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3723421519
Short name T1100
Test name
Test status
Simulation time 33319351 ps
CPU time 0.67 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204424 kb
Host smart-77c42217-1fea-4e71-9b94-f57b7acd5393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723421519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3723421519
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.313020610
Short name T1049
Test name
Test status
Simulation time 48377728 ps
CPU time 0.74 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 204344 kb
Host smart-e41601d4-6658-47cf-8c69-f2722cdefb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313020610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.313020610
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.7453190
Short name T1040
Test name
Test status
Simulation time 14774872 ps
CPU time 0.78 seconds
Started Jul 24 05:00:20 PM PDT 24
Finished Jul 24 05:00:21 PM PDT 24
Peak memory 204492 kb
Host smart-669e0e92-501d-4f97-8db0-89f1472fc213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7453190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.7453190
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1945479622
Short name T1077
Test name
Test status
Simulation time 48454514 ps
CPU time 0.75 seconds
Started Jul 24 05:00:02 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204508 kb
Host smart-504ee74f-abeb-43d4-897e-afe00e513712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945479622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1945479622
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.870186146
Short name T1113
Test name
Test status
Simulation time 21970554 ps
CPU time 0.75 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204752 kb
Host smart-1ce40fd6-56d8-4b3d-b0d7-5e7aabb218db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870186146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.870186146
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2266359291
Short name T1039
Test name
Test status
Simulation time 14253198 ps
CPU time 0.71 seconds
Started Jul 24 05:00:18 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 204504 kb
Host smart-0e9fb5c5-893f-40a2-b270-47a5915dd362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266359291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2266359291
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2665979799
Short name T1058
Test name
Test status
Simulation time 18064906 ps
CPU time 0.77 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 204412 kb
Host smart-6e3b3001-8e5f-4655-b83a-a6a56c04eed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665979799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2665979799
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2710986669
Short name T1051
Test name
Test status
Simulation time 53024707 ps
CPU time 0.75 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 04:59:54 PM PDT 24
Peak memory 204756 kb
Host smart-d5a34b82-2817-4505-be24-dc665f44fb78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710986669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2710986669
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3475280631
Short name T1060
Test name
Test status
Simulation time 2508716779 ps
CPU time 15.09 seconds
Started Jul 24 04:59:50 PM PDT 24
Finished Jul 24 05:00:05 PM PDT 24
Peak memory 207816 kb
Host smart-cf2ba1ed-cdea-4dd2-a16b-fd9e3d78a794
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475280631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3475280631
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3384003207
Short name T1131
Test name
Test status
Simulation time 2546799114 ps
CPU time 12.9 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 05:00:11 PM PDT 24
Peak memory 208036 kb
Host smart-c870230b-aaea-4932-8746-6838fda3a0de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384003207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3384003207
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2856753014
Short name T89
Test name
Test status
Simulation time 47139707 ps
CPU time 1.43 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 216968 kb
Host smart-47bc31d4-07d4-4cf9-9a15-a038ac71b7b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856753014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2856753014
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2569956831
Short name T157
Test name
Test status
Simulation time 949553559 ps
CPU time 2.85 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:50 PM PDT 24
Peak memory 217868 kb
Host smart-f5acabf9-e045-45fd-b50f-595782059312
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569956831 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2569956831
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3110161275
Short name T124
Test name
Test status
Simulation time 359830805 ps
CPU time 1.75 seconds
Started Jul 24 04:59:38 PM PDT 24
Finished Jul 24 04:59:40 PM PDT 24
Peak memory 215876 kb
Host smart-8ea66629-4491-446f-835c-9fcc6f3ba301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110161275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
110161275
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.37562855
Short name T1033
Test name
Test status
Simulation time 89535639 ps
CPU time 0.75 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 204784 kb
Host smart-bd3ac550-2b05-4e90-961d-06d0db89acbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37562855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.37562855
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2010897071
Short name T1130
Test name
Test status
Simulation time 52924729 ps
CPU time 2.14 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 215932 kb
Host smart-0667d784-aef5-4809-a553-f879efb13c6c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010897071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2010897071
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1651568383
Short name T1122
Test name
Test status
Simulation time 43725589 ps
CPU time 0.65 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 204232 kb
Host smart-c4916ae1-3fd8-4c81-a0dc-c0b6cbb6d525
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651568383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1651568383
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1344293518
Short name T1089
Test name
Test status
Simulation time 53994706 ps
CPU time 1.65 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 216440 kb
Host smart-a85f3c23-44d9-415f-9a12-db0547f4f83c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344293518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1344293518
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3941226003
Short name T1114
Test name
Test status
Simulation time 473262402 ps
CPU time 2.25 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 04:59:56 PM PDT 24
Peak memory 216472 kb
Host smart-7b81e1cb-448c-4caf-9a07-cfbb12c79e16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941226003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
941226003
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3614765812
Short name T1032
Test name
Test status
Simulation time 17620167 ps
CPU time 0.78 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:19 PM PDT 24
Peak memory 204300 kb
Host smart-f446d57e-e486-4e3a-85db-27e7b61e8a50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614765812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3614765812
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.771184387
Short name T1038
Test name
Test status
Simulation time 29541788 ps
CPU time 0.72 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204428 kb
Host smart-e1c0b3e1-544f-4369-a518-7415f2ff00be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771184387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.771184387
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.4057283367
Short name T1047
Test name
Test status
Simulation time 16575049 ps
CPU time 0.72 seconds
Started Jul 24 04:59:47 PM PDT 24
Finished Jul 24 04:59:48 PM PDT 24
Peak memory 204508 kb
Host smart-d352d7a8-f97c-4759-a434-fe5a1c7c5ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057283367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
4057283367
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4158200117
Short name T1108
Test name
Test status
Simulation time 18508830 ps
CPU time 0.73 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204772 kb
Host smart-d4f9cbb8-8b76-43b7-a370-9d1ce8d53213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158200117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4158200117
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3277148246
Short name T1109
Test name
Test status
Simulation time 13420680 ps
CPU time 0.76 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204800 kb
Host smart-9047411a-ffe7-4492-9d24-d9c47845ba24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277148246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3277148246
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3921505556
Short name T1112
Test name
Test status
Simulation time 15669274 ps
CPU time 0.7 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 204696 kb
Host smart-ba2e8212-0567-4362-b2d3-e4cd0ca68b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921505556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3921505556
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1360361491
Short name T1053
Test name
Test status
Simulation time 15909218 ps
CPU time 0.74 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 204308 kb
Host smart-44122d07-73c6-4e01-be23-f37d76b76d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360361491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1360361491
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.3839202933
Short name T1111
Test name
Test status
Simulation time 55834186 ps
CPU time 0.74 seconds
Started Jul 24 05:00:21 PM PDT 24
Finished Jul 24 05:00:22 PM PDT 24
Peak memory 204532 kb
Host smart-96d48629-e2a1-4316-bdbe-1624bd27a973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839202933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
3839202933
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3633715270
Short name T1044
Test name
Test status
Simulation time 11983386 ps
CPU time 0.67 seconds
Started Jul 24 05:00:00 PM PDT 24
Finished Jul 24 05:00:00 PM PDT 24
Peak memory 204756 kb
Host smart-71a9812f-e07e-4c22-a84a-3a841e81f774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633715270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3633715270
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2165232207
Short name T1150
Test name
Test status
Simulation time 13753725 ps
CPU time 0.76 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204736 kb
Host smart-e470ff18-af03-41cb-aa03-7a777ce81c67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165232207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2165232207
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.395996908
Short name T1135
Test name
Test status
Simulation time 1564032157 ps
CPU time 16.42 seconds
Started Jul 24 04:59:50 PM PDT 24
Finished Jul 24 05:00:07 PM PDT 24
Peak memory 207756 kb
Host smart-4fb27876-19a7-4447-a39e-99add9886168
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395996908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.395996908
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1020863690
Short name T1092
Test name
Test status
Simulation time 369825970 ps
CPU time 22.99 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:38 PM PDT 24
Peak memory 215940 kb
Host smart-774a728e-86b6-4c36-91eb-b014491ca441
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020863690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1020863690
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2977120117
Short name T87
Test name
Test status
Simulation time 38925230 ps
CPU time 1.19 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:50 PM PDT 24
Peak memory 207504 kb
Host smart-1a89c8ef-5ae1-4d35-af46-401349c30bcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977120117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2977120117
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3527684996
Short name T1075
Test name
Test status
Simulation time 25791314 ps
CPU time 1.62 seconds
Started Jul 24 04:59:49 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 216024 kb
Host smart-5df8000a-0fa5-43a5-9e42-be1eba442f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527684996 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3527684996
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3377532351
Short name T144
Test name
Test status
Simulation time 423967029 ps
CPU time 1.29 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:00 PM PDT 24
Peak memory 207796 kb
Host smart-7cc3f550-5571-4b33-8043-11231d1ea867
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377532351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
377532351
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.800673621
Short name T1048
Test name
Test status
Simulation time 10954960 ps
CPU time 0.71 seconds
Started Jul 24 04:59:44 PM PDT 24
Finished Jul 24 04:59:45 PM PDT 24
Peak memory 204512 kb
Host smart-4b28aaf4-4a27-4884-810e-68f5b1ddc30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800673621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.800673621
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.840133486
Short name T1134
Test name
Test status
Simulation time 196663446 ps
CPU time 1.66 seconds
Started Jul 24 04:59:56 PM PDT 24
Finished Jul 24 04:59:57 PM PDT 24
Peak memory 216068 kb
Host smart-f280fa93-7687-41f9-ba48-5bf77c4a2634
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840133486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.840133486
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4263953941
Short name T1035
Test name
Test status
Simulation time 87953670 ps
CPU time 0.67 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 204380 kb
Host smart-855c94c8-d9e6-4e04-8a0a-605b17618c14
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263953941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4263953941
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3235226982
Short name T156
Test name
Test status
Simulation time 593700153 ps
CPU time 3.14 seconds
Started Jul 24 04:59:46 PM PDT 24
Finished Jul 24 04:59:50 PM PDT 24
Peak memory 216020 kb
Host smart-56a689a3-8eb9-4473-8b16-18174aa6c576
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235226982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3235226982
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1291441693
Short name T1090
Test name
Test status
Simulation time 725583135 ps
CPU time 3.25 seconds
Started Jul 24 04:59:42 PM PDT 24
Finished Jul 24 04:59:45 PM PDT 24
Peak memory 216096 kb
Host smart-1098fa74-fed2-4377-8c68-12e421853720
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291441693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
291441693
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.996853393
Short name T1133
Test name
Test status
Simulation time 22720632 ps
CPU time 0.72 seconds
Started Jul 24 05:00:09 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204368 kb
Host smart-9601cc37-8ca4-4451-98ad-24d91b2b10be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996853393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.996853393
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3827534827
Short name T1036
Test name
Test status
Simulation time 49394688 ps
CPU time 0.71 seconds
Started Jul 24 04:59:55 PM PDT 24
Finished Jul 24 04:59:55 PM PDT 24
Peak memory 204724 kb
Host smart-18fb9b0b-f05c-4653-9c9c-77a5fd00a5fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827534827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3827534827
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3996747922
Short name T1107
Test name
Test status
Simulation time 11310564 ps
CPU time 0.71 seconds
Started Jul 24 05:00:03 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204416 kb
Host smart-53174084-16be-462d-a077-4e23dedcc9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996747922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3996747922
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.55421832
Short name T1110
Test name
Test status
Simulation time 43894311 ps
CPU time 0.75 seconds
Started Jul 24 05:00:00 PM PDT 24
Finished Jul 24 05:00:01 PM PDT 24
Peak memory 204364 kb
Host smart-a42c0d0a-1ecf-4be3-b9f5-b1330a7e3f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55421832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.55421832
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2469502676
Short name T1132
Test name
Test status
Simulation time 16107590 ps
CPU time 0.79 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204500 kb
Host smart-52ae8d8e-0cee-4627-b860-a3199a91182f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469502676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2469502676
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3229607781
Short name T1143
Test name
Test status
Simulation time 27333399 ps
CPU time 0.75 seconds
Started Jul 24 05:00:08 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 204500 kb
Host smart-9cc5a0f4-6c37-4ce0-91b9-1676f22be850
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229607781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3229607781
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3139142660
Short name T1068
Test name
Test status
Simulation time 15523226 ps
CPU time 0.72 seconds
Started Jul 24 05:00:05 PM PDT 24
Finished Jul 24 05:00:16 PM PDT 24
Peak memory 204768 kb
Host smart-b2021e82-98e9-4b6a-9715-6434b221ae16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139142660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3139142660
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1766302192
Short name T1126
Test name
Test status
Simulation time 14063557 ps
CPU time 0.72 seconds
Started Jul 24 05:00:15 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204376 kb
Host smart-f40da04b-505e-4471-9daf-38f94de5aab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766302192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1766302192
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1381941491
Short name T1140
Test name
Test status
Simulation time 47898430 ps
CPU time 0.78 seconds
Started Jul 24 05:00:26 PM PDT 24
Finished Jul 24 05:00:27 PM PDT 24
Peak memory 204692 kb
Host smart-55fbe89e-eecd-4813-a15b-97ef9b9053aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381941491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1381941491
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1050627556
Short name T1063
Test name
Test status
Simulation time 19767633 ps
CPU time 0.71 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:18 PM PDT 24
Peak memory 204692 kb
Host smart-5c2b7f9d-da3d-4e95-bc3c-3992d46462e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050627556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1050627556
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2668968477
Short name T113
Test name
Test status
Simulation time 878553100 ps
CPU time 2.94 seconds
Started Jul 24 05:01:29 PM PDT 24
Finished Jul 24 05:01:32 PM PDT 24
Peak memory 218340 kb
Host smart-2b35cca9-0c74-433e-835f-a37ddad84acb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668968477 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2668968477
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1897508825
Short name T1072
Test name
Test status
Simulation time 22064857 ps
CPU time 1.23 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 207796 kb
Host smart-0c592095-482b-419f-b381-7971220b39d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897508825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
897508825
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2662751665
Short name T1034
Test name
Test status
Simulation time 19344107 ps
CPU time 0.75 seconds
Started Jul 24 04:59:50 PM PDT 24
Finished Jul 24 04:59:51 PM PDT 24
Peak memory 204508 kb
Host smart-ddeedd01-8d1f-48fe-bedc-c7369977c820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662751665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
662751665
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3054238868
Short name T1045
Test name
Test status
Simulation time 417588062 ps
CPU time 3.48 seconds
Started Jul 24 04:59:49 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 215928 kb
Host smart-b155cc9b-4c62-4f38-8a4b-1908c1bf65b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054238868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3054238868
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2726305817
Short name T99
Test name
Test status
Simulation time 178508172 ps
CPU time 2.03 seconds
Started Jul 24 05:00:17 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 216296 kb
Host smart-a2514c30-651c-45aa-8685-0e964f61d50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726305817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
726305817
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1345592056
Short name T175
Test name
Test status
Simulation time 1680110882 ps
CPU time 6.61 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:58 PM PDT 24
Peak memory 215988 kb
Host smart-2608ce37-c1ec-4a8c-a0a3-d5dc622682a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345592056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1345592056
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.65477553
Short name T1069
Test name
Test status
Simulation time 572851919 ps
CPU time 3.61 seconds
Started Jul 24 05:01:47 PM PDT 24
Finished Jul 24 05:01:50 PM PDT 24
Peak memory 217912 kb
Host smart-dc5a10b5-55f9-4f00-b8b0-e13520dce42a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65477553 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.65477553
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3427885650
Short name T126
Test name
Test status
Simulation time 74781531 ps
CPU time 2.5 seconds
Started Jul 24 04:59:43 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 215932 kb
Host smart-b75d3610-ef21-424e-93ea-fdf48d7fc3ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427885650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
427885650
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1118848017
Short name T1073
Test name
Test status
Simulation time 45724979 ps
CPU time 0.71 seconds
Started Jul 24 04:59:52 PM PDT 24
Finished Jul 24 04:59:53 PM PDT 24
Peak memory 204508 kb
Host smart-a1e8b455-9347-402c-9b5e-d1e5a4a5607c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118848017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
118848017
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1555942286
Short name T143
Test name
Test status
Simulation time 368844914 ps
CPU time 4.06 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:55 PM PDT 24
Peak memory 215904 kb
Host smart-f2759cb1-40ec-4258-8b52-a9d6281881e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555942286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1555942286
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4109643988
Short name T1097
Test name
Test status
Simulation time 115453916 ps
CPU time 1.71 seconds
Started Jul 24 04:59:44 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 216160 kb
Host smart-fc278fcb-3738-4b5b-9e80-2c48371b415d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109643988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
109643988
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1046019043
Short name T168
Test name
Test status
Simulation time 306046844 ps
CPU time 19.94 seconds
Started Jul 24 05:00:07 PM PDT 24
Finished Jul 24 05:00:35 PM PDT 24
Peak memory 216068 kb
Host smart-5dc882fb-9a4c-4774-a754-eff7bf45361a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046019043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1046019043
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.536238588
Short name T1055
Test name
Test status
Simulation time 55697997 ps
CPU time 3.64 seconds
Started Jul 24 04:59:53 PM PDT 24
Finished Jul 24 04:59:57 PM PDT 24
Peak memory 218568 kb
Host smart-4a13e94b-20ab-498f-a8e9-569804d4f1fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536238588 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.536238588
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.418139987
Short name T1128
Test name
Test status
Simulation time 137359190 ps
CPU time 1.78 seconds
Started Jul 24 04:59:52 PM PDT 24
Finished Jul 24 04:59:54 PM PDT 24
Peak memory 215996 kb
Host smart-b50d97ef-0dae-4ab2-8e39-b7c780970c0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418139987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.418139987
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3931176826
Short name T1104
Test name
Test status
Simulation time 113460168 ps
CPU time 0.72 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 04:59:49 PM PDT 24
Peak memory 204388 kb
Host smart-60ab7dfb-3f5f-4dda-99c7-f45354c1be16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931176826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
931176826
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2421293349
Short name T1064
Test name
Test status
Simulation time 128298937 ps
CPU time 3.04 seconds
Started Jul 24 04:59:57 PM PDT 24
Finished Jul 24 05:00:00 PM PDT 24
Peak memory 215980 kb
Host smart-0669916d-9c3f-48af-b394-6ef954c602bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421293349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2421293349
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2426004609
Short name T1076
Test name
Test status
Simulation time 712444310 ps
CPU time 14.31 seconds
Started Jul 24 04:59:48 PM PDT 24
Finished Jul 24 05:00:03 PM PDT 24
Peak memory 217412 kb
Host smart-221ddc05-c619-429f-a1b9-a986dd9c3fbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426004609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2426004609
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2098524012
Short name T155
Test name
Test status
Simulation time 685733925 ps
CPU time 3.95 seconds
Started Jul 24 04:59:52 PM PDT 24
Finished Jul 24 04:59:56 PM PDT 24
Peak memory 218152 kb
Host smart-b48a5a2c-c42f-4024-a407-ef3454ec8806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098524012 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2098524012
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4018176690
Short name T123
Test name
Test status
Simulation time 193559059 ps
CPU time 2.52 seconds
Started Jul 24 05:00:00 PM PDT 24
Finished Jul 24 05:00:03 PM PDT 24
Peak memory 216008 kb
Host smart-acbf3629-d280-4069-8c10-bc4a04affb84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018176690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
018176690
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.21610026
Short name T1105
Test name
Test status
Simulation time 36342929 ps
CPU time 0.74 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:00:17 PM PDT 24
Peak memory 203988 kb
Host smart-9caedbab-b03d-4415-a5b0-7b75119ecc69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21610026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.21610026
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3028604228
Short name T1056
Test name
Test status
Simulation time 132143239 ps
CPU time 1.74 seconds
Started Jul 24 04:59:43 PM PDT 24
Finished Jul 24 04:59:46 PM PDT 24
Peak memory 216024 kb
Host smart-06718dc9-487a-41a1-bca0-8ffa074b3ea0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028604228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3028604228
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3012796774
Short name T1147
Test name
Test status
Simulation time 98966291 ps
CPU time 2.82 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:54 PM PDT 24
Peak memory 219948 kb
Host smart-fa692b4d-29ea-4adc-a8b0-710918d0052d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012796774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
012796774
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1224883219
Short name T1121
Test name
Test status
Simulation time 525701268 ps
CPU time 7.37 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:59 PM PDT 24
Peak memory 217168 kb
Host smart-ea919ab9-e9d7-4c75-8bcd-b325aeeb2025
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224883219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1224883219
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.69153566
Short name T1057
Test name
Test status
Simulation time 186803422 ps
CPU time 3.56 seconds
Started Jul 24 04:59:58 PM PDT 24
Finished Jul 24 05:00:02 PM PDT 24
Peak memory 217696 kb
Host smart-f6c08991-16d8-4919-90af-0a2ef2dd1aba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69153566 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.69153566
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3626301296
Short name T128
Test name
Test status
Simulation time 73224419 ps
CPU time 1.24 seconds
Started Jul 24 04:59:51 PM PDT 24
Finished Jul 24 04:59:52 PM PDT 24
Peak memory 215972 kb
Host smart-11a600c0-18c5-4725-a61f-e15c611c37fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626301296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
626301296
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3555503703
Short name T1103
Test name
Test status
Simulation time 122236565 ps
CPU time 0.67 seconds
Started Jul 24 04:59:54 PM PDT 24
Finished Jul 24 04:59:55 PM PDT 24
Peak memory 204428 kb
Host smart-71c37b28-7102-4c23-b23d-588b80c24252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555503703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
555503703
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2520285270
Short name T1118
Test name
Test status
Simulation time 191384574 ps
CPU time 4.21 seconds
Started Jul 24 05:00:04 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 215880 kb
Host smart-01c2085b-681c-42f9-aaa7-84563df0380e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520285270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2520285270
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2736534531
Short name T100
Test name
Test status
Simulation time 76773645 ps
CPU time 3.7 seconds
Started Jul 24 05:00:10 PM PDT 24
Finished Jul 24 05:00:20 PM PDT 24
Peak memory 216164 kb
Host smart-c9131419-8160-4817-b85a-3b1183b32432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736534531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
736534531
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2151709121
Short name T391
Test name
Test status
Simulation time 5007664100 ps
CPU time 5.28 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 225468 kb
Host smart-15c031b9-f20f-4504-9a20-642c8b4d1aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151709121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2151709121
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1434903323
Short name T228
Test name
Test status
Simulation time 51984888065 ps
CPU time 328.89 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:10:06 PM PDT 24
Peak memory 266408 kb
Host smart-dd422ab7-858a-4b87-8d13-2198c6f6ed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434903323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1434903323
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3219380964
Short name T211
Test name
Test status
Simulation time 38006954427 ps
CPU time 191.18 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:07:44 PM PDT 24
Peak memory 257448 kb
Host smart-f0a64d97-e35c-424d-a387-f3d5f94e88b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219380964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3219380964
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3961534428
Short name T197
Test name
Test status
Simulation time 5961873251 ps
CPU time 126.05 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 262088 kb
Host smart-72c31ab5-755b-4efc-a4c6-77e1b9c91672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961534428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3961534428
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2146898795
Short name T300
Test name
Test status
Simulation time 258736536 ps
CPU time 7.97 seconds
Started Jul 24 05:04:32 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 241100 kb
Host smart-3cbe418d-152d-4a08-b5f3-2327c6b3822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146898795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2146898795
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3723656774
Short name T165
Test name
Test status
Simulation time 3235719332 ps
CPU time 56.42 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 251720 kb
Host smart-827fb2b6-59b6-40f0-b557-b41230d8eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723656774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3723656774
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.823916306
Short name T976
Test name
Test status
Simulation time 422088023 ps
CPU time 4.98 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:04:51 PM PDT 24
Peak memory 233620 kb
Host smart-23e5e9a3-c1dc-41e8-a170-6a9d533a7d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823916306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.823916306
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1462513044
Short name T608
Test name
Test status
Simulation time 4453141731 ps
CPU time 12.68 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 225456 kb
Host smart-7df40695-fd70-4879-bd23-45864fa3e1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462513044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1462513044
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4293118736
Short name T827
Test name
Test status
Simulation time 77813500 ps
CPU time 0.99 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 218684 kb
Host smart-f899a9ee-60ab-4bcc-9bcb-280dac5662d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293118736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4293118736
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3828738645
Short name T393
Test name
Test status
Simulation time 4247426568 ps
CPU time 14.49 seconds
Started Jul 24 05:04:39 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 233556 kb
Host smart-2e5dc490-4e14-4210-ab85-58631fc64b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828738645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3828738645
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.105232997
Short name T956
Test name
Test status
Simulation time 45769258941 ps
CPU time 19.02 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 241672 kb
Host smart-b0e0cf8b-7381-4b66-8d86-2f7cb4e54cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105232997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.105232997
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.369960496
Short name T503
Test name
Test status
Simulation time 99333421 ps
CPU time 3.94 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 223352 kb
Host smart-ae21b970-f5c9-488a-b04a-85cb26d78f62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=369960496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.369960496
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2105963829
Short name T71
Test name
Test status
Simulation time 60947082 ps
CPU time 1.05 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 235972 kb
Host smart-bed2fac5-73cf-4c96-b37d-ca355cf4459a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105963829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2105963829
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.109369056
Short name T691
Test name
Test status
Simulation time 19482769380 ps
CPU time 169.56 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:07:32 PM PDT 24
Peak memory 249172 kb
Host smart-c074951c-f961-4c99-80a4-125669988646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109369056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.109369056
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1657530160
Short name T475
Test name
Test status
Simulation time 1156994878 ps
CPU time 10.68 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 217216 kb
Host smart-e7231048-c8f0-4451-8f9e-153fe0ffbbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657530160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1657530160
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4074314885
Short name T355
Test name
Test status
Simulation time 4452814219 ps
CPU time 4.56 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 217108 kb
Host smart-5b41ebc0-5f45-4af4-90d6-674baa2fb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074314885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4074314885
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4001632214
Short name T374
Test name
Test status
Simulation time 487836133 ps
CPU time 2.05 seconds
Started Jul 24 05:04:36 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 217188 kb
Host smart-5a87a61f-727d-4716-87f2-3d7e767b89f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001632214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4001632214
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.135735096
Short name T840
Test name
Test status
Simulation time 406276408 ps
CPU time 0.98 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 206752 kb
Host smart-da9186c1-e9e4-41f3-83ca-388f7d0d821b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135735096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.135735096
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2971568881
Short name T865
Test name
Test status
Simulation time 402069516 ps
CPU time 5.39 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:56 PM PDT 24
Peak memory 234644 kb
Host smart-6f0894a0-72a5-4f12-83f1-c3f4b454c567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971568881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2971568881
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3271635213
Short name T5
Test name
Test status
Simulation time 13445826 ps
CPU time 0.68 seconds
Started Jul 24 05:04:28 PM PDT 24
Finished Jul 24 05:04:29 PM PDT 24
Peak memory 205532 kb
Host smart-4bb401d1-689b-4b72-82b1-39cdd4d36b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271635213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
271635213
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2788149240
Short name T842
Test name
Test status
Simulation time 636174521 ps
CPU time 3.21 seconds
Started Jul 24 05:04:39 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 225464 kb
Host smart-38e30b44-5899-403f-900a-81b3348a3e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788149240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2788149240
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1057256026
Short name T583
Test name
Test status
Simulation time 16860020 ps
CPU time 0.77 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:25 PM PDT 24
Peak memory 207296 kb
Host smart-bd4f72e4-c182-447d-9086-a3469cbf3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057256026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1057256026
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2568218509
Short name T686
Test name
Test status
Simulation time 958735660 ps
CPU time 7.21 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:04:37 PM PDT 24
Peak memory 241788 kb
Host smart-b0aad330-2240-424c-98df-2ab436a73c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568218509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2568218509
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2402797934
Short name T141
Test name
Test status
Simulation time 8046174454 ps
CPU time 120.16 seconds
Started Jul 24 05:04:29 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 266556 kb
Host smart-6a72c961-6dcd-457b-bd55-80e35243865a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402797934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2402797934
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1707875377
Short name T404
Test name
Test status
Simulation time 2084649733 ps
CPU time 49.44 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 256928 kb
Host smart-0852bdb1-a34e-410d-8d00-055a9c87ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707875377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1707875377
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2246503635
Short name T658
Test name
Test status
Simulation time 654973372 ps
CPU time 4.78 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 225456 kb
Host smart-ba5afaec-4ebc-469c-8d1d-342fb433a88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246503635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2246503635
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1238349390
Short name T577
Test name
Test status
Simulation time 388638409 ps
CPU time 2.07 seconds
Started Jul 24 05:04:37 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 233336 kb
Host smart-f1022c5f-e8ae-4fe4-8625-c595b32d7e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238349390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1238349390
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.492210173
Short name T516
Test name
Test status
Simulation time 47991996 ps
CPU time 1.06 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 217396 kb
Host smart-0c85c49d-1337-4e49-ad99-05b8ef8e0df6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492210173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.492210173
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.551502210
Short name T878
Test name
Test status
Simulation time 1647539548 ps
CPU time 8.36 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:50 PM PDT 24
Peak memory 233632 kb
Host smart-dfedebc9-5b23-4241-83a8-7db2413a982b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551502210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
551502210
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.301640956
Short name T443
Test name
Test status
Simulation time 11977563338 ps
CPU time 9.6 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 233604 kb
Host smart-963239ca-1875-4f0d-9a10-7d08f63c2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301640956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.301640956
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1255864224
Short name T12
Test name
Test status
Simulation time 2546372727 ps
CPU time 20.77 seconds
Started Jul 24 05:04:40 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 222348 kb
Host smart-05ceb56e-8b0a-4c7e-8248-f4eda99cb390
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1255864224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1255864224
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3550007475
Short name T73
Test name
Test status
Simulation time 100574058 ps
CPU time 1.03 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 235844 kb
Host smart-145a7e37-6172-4162-9af5-6cf84e43a51c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550007475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3550007475
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2651850905
Short name T715
Test name
Test status
Simulation time 45324219 ps
CPU time 0.96 seconds
Started Jul 24 05:04:40 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 207396 kb
Host smart-7d14d0c8-0dfc-4b28-803f-b300fe540fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651850905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2651850905
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4011420411
Short name T689
Test name
Test status
Simulation time 1312584826 ps
CPU time 4.91 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:04:46 PM PDT 24
Peak memory 217240 kb
Host smart-7f65c23b-ba41-4f6f-80e7-b0c0e644c9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011420411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4011420411
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1322349602
Short name T379
Test name
Test status
Simulation time 14735917162 ps
CPU time 6.6 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 217156 kb
Host smart-9653004a-5edd-4f87-b9a9-cb00775e2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322349602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1322349602
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1221329073
Short name T837
Test name
Test status
Simulation time 110448537 ps
CPU time 0.67 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 206188 kb
Host smart-4b04157e-b03d-4321-be63-45033aaf2e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221329073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1221329073
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3166227270
Short name T924
Test name
Test status
Simulation time 94766368 ps
CPU time 0.96 seconds
Started Jul 24 05:04:39 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 206796 kb
Host smart-c143adba-7f67-496f-ba45-bd40ff91a0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166227270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3166227270
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1332492714
Short name T441
Test name
Test status
Simulation time 411301079 ps
CPU time 7.28 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 233628 kb
Host smart-1893e5e4-3646-4018-be1f-e22b85e17004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332492714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1332492714
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1196445828
Short name T68
Test name
Test status
Simulation time 11580380 ps
CPU time 0.71 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 206104 kb
Host smart-e7b99504-defd-474c-8cdf-a0377ad1334a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196445828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1196445828
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4234422285
Short name T791
Test name
Test status
Simulation time 345816770 ps
CPU time 2.48 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 225416 kb
Host smart-6ff4511d-a50f-4282-8d7d-abf503a4dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234422285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4234422285
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2600643139
Short name T513
Test name
Test status
Simulation time 50304502 ps
CPU time 0.71 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 207452 kb
Host smart-28551ff0-3ef7-4c34-be55-105aed8a4702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600643139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2600643139
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3534528646
Short name T477
Test name
Test status
Simulation time 3110003645 ps
CPU time 36.67 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 225548 kb
Host smart-52d0cd36-2c98-4a0e-92de-eb6d5dae9325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534528646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3534528646
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.682959696
Short name T547
Test name
Test status
Simulation time 6652955682 ps
CPU time 76.48 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 255984 kb
Host smart-85f267d0-cc6f-4d93-a948-3df0c6637969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682959696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.682959696
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3629504923
Short name T802
Test name
Test status
Simulation time 131670433 ps
CPU time 4.67 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 225512 kb
Host smart-d37f4a32-ccd7-4487-99c3-1fa0d1c7b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629504923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3629504923
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.763545100
Short name T319
Test name
Test status
Simulation time 38619436 ps
CPU time 0.78 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:08 PM PDT 24
Peak memory 216604 kb
Host smart-cc4c5b06-ea75-47e2-a6bd-d0db97989df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763545100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.763545100
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4096514986
Short name T522
Test name
Test status
Simulation time 10500007365 ps
CPU time 13.97 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 225424 kb
Host smart-0b856b76-e226-4526-9385-3adf7f22430d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096514986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4096514986
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1364343685
Short name T94
Test name
Test status
Simulation time 2804504460 ps
CPU time 16.16 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 225440 kb
Host smart-458e8b23-4693-4236-867f-2a4b4caf935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364343685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1364343685
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1085827972
Short name T135
Test name
Test status
Simulation time 91059792 ps
CPU time 1 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:48 PM PDT 24
Peak memory 218544 kb
Host smart-9f648a22-508c-4eea-b181-02ee09d3530d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085827972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1085827972
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4259994872
Short name T619
Test name
Test status
Simulation time 1818839058 ps
CPU time 5.75 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 233668 kb
Host smart-d849165b-9a37-4db8-93d4-abc1f867a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259994872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4259994872
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2420844525
Short name T219
Test name
Test status
Simulation time 266056076 ps
CPU time 4.66 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 225464 kb
Host smart-cbe94674-2c5e-4629-af61-cee508cc3813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420844525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2420844525
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3395887106
Short name T743
Test name
Test status
Simulation time 1510401980 ps
CPU time 18.67 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 221460 kb
Host smart-5a18c8b8-f280-44db-806a-dd3eb4647e14
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3395887106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3395887106
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1134683450
Short name T1030
Test name
Test status
Simulation time 5422133739 ps
CPU time 9.08 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 217216 kb
Host smart-0cf174ce-28ef-4776-adcc-807b810a3ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134683450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1134683450
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3164801045
Short name T968
Test name
Test status
Simulation time 3054930095 ps
CPU time 11.68 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 217264 kb
Host smart-bd9ced7a-8e4c-48b9-88a6-70c15f36164f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164801045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3164801045
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3056627269
Short name T892
Test name
Test status
Simulation time 72247972 ps
CPU time 2.04 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 217088 kb
Host smart-a1122364-253e-4c52-862a-aa50e39d991e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056627269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3056627269
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.78711463
Short name T614
Test name
Test status
Simulation time 23102288 ps
CPU time 0.81 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 206760 kb
Host smart-188dc366-676c-4e71-90c0-d1137788e5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78711463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.78711463
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3379605181
Short name T524
Test name
Test status
Simulation time 1077672107 ps
CPU time 8.29 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 240180 kb
Host smart-af19e3f7-f4b6-4403-b821-55ff0656119c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379605181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3379605181
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2323917644
Short name T318
Test name
Test status
Simulation time 15730300 ps
CPU time 0.73 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 206372 kb
Host smart-badd8277-63c5-45e0-b096-f4ccad10d678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323917644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2323917644
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.174036460
Short name T890
Test name
Test status
Simulation time 1654888033 ps
CPU time 3.99 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 233592 kb
Host smart-45973e0a-a197-457e-b321-fa44682c9336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174036460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.174036460
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1022069473
Short name T328
Test name
Test status
Simulation time 17952015 ps
CPU time 0.77 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 207328 kb
Host smart-b605dbf2-cc2a-4e36-a31f-9e000543c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022069473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1022069473
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1188669865
Short name T893
Test name
Test status
Simulation time 5838258677 ps
CPU time 30.87 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 252376 kb
Host smart-dcf65489-7468-427e-bbed-b47d4d1b9287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188669865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1188669865
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4178568346
Short name T912
Test name
Test status
Simulation time 221353836310 ps
CPU time 449.72 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:12:44 PM PDT 24
Peak memory 269916 kb
Host smart-71c7dd5c-51af-48e8-803a-a9d10bbd88ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178568346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4178568346
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.585505388
Short name T935
Test name
Test status
Simulation time 17350096079 ps
CPU time 190.81 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:08:21 PM PDT 24
Peak memory 257292 kb
Host smart-dc340cc5-687c-4c14-8ec7-baf7bb11eb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585505388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.585505388
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3242934559
Short name T724
Test name
Test status
Simulation time 15380803326 ps
CPU time 38.31 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 233584 kb
Host smart-8b947e93-0272-4dea-9e9f-0630bee191e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242934559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3242934559
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2644737693
Short name T581
Test name
Test status
Simulation time 48353073205 ps
CPU time 82.03 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 250048 kb
Host smart-31ceb199-0beb-423a-b863-d696a775911c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644737693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2644737693
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3939819126
Short name T945
Test name
Test status
Simulation time 111334158 ps
CPU time 3.62 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:56 PM PDT 24
Peak memory 233696 kb
Host smart-8ede510b-0c65-46f9-96a3-e6eb85232f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939819126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3939819126
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3026551679
Short name T230
Test name
Test status
Simulation time 5319077517 ps
CPU time 19.14 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 233692 kb
Host smart-7fa27019-e3db-4e7d-a029-b1ccb1329891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026551679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3026551679
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.594256826
Short name T38
Test name
Test status
Simulation time 52439587 ps
CPU time 1.03 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 217408 kb
Host smart-6c3eb0c6-44bc-4af3-a3dc-5de24d9db988
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594256826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.594256826
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3419494161
Short name T585
Test name
Test status
Simulation time 63924369356 ps
CPU time 15.09 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:37 PM PDT 24
Peak memory 233504 kb
Host smart-36420c54-80f1-4ddc-9285-a601c5b409a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419494161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3419494161
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2023252175
Short name T78
Test name
Test status
Simulation time 19569871851 ps
CPU time 18.02 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 233660 kb
Host smart-95b5aa5a-581a-4024-ab73-ba5744e34123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023252175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2023252175
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.49285603
Short name T1026
Test name
Test status
Simulation time 706663771 ps
CPU time 3.92 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 221260 kb
Host smart-3d152ae0-d911-488a-934c-fc2e51e936f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49285603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direc
t.49285603
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4090779949
Short name T13
Test name
Test status
Simulation time 11857317368 ps
CPU time 55.9 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 249936 kb
Host smart-5496a2e4-dd4f-4ca5-ae13-7b36a03e74b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090779949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4090779949
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.331163206
Short name T568
Test name
Test status
Simulation time 5878204181 ps
CPU time 6.38 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:14 PM PDT 24
Peak memory 217320 kb
Host smart-2b25cff4-3ac8-40d6-abbe-3e597f043ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331163206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.331163206
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3262099434
Short name T324
Test name
Test status
Simulation time 83452446 ps
CPU time 0.67 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 206408 kb
Host smart-0d83206a-2719-4d79-9752-580c4540cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262099434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3262099434
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1053873182
Short name T589
Test name
Test status
Simulation time 14087755 ps
CPU time 0.68 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:04:57 PM PDT 24
Peak memory 206260 kb
Host smart-baced140-9394-4762-a28b-b77a669ae94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053873182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1053873182
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3175496845
Short name T701
Test name
Test status
Simulation time 134358848 ps
CPU time 0.83 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 206808 kb
Host smart-4139ed79-8485-45ba-b973-ecd79852d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175496845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3175496845
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2699617585
Short name T813
Test name
Test status
Simulation time 4768356743 ps
CPU time 9.67 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:14 PM PDT 24
Peak memory 225424 kb
Host smart-19593792-f170-4f82-bd73-f0e318ba420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699617585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2699617585
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4291465663
Short name T1011
Test name
Test status
Simulation time 33472570 ps
CPU time 0.74 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 206072 kb
Host smart-f22e3607-5b46-45a7-9180-005a68762979
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291465663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4291465663
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2639305489
Short name T680
Test name
Test status
Simulation time 334450285 ps
CPU time 4.98 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 225416 kb
Host smart-1438bc35-ca67-46b7-ab68-bafc774aa11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639305489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2639305489
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3375509603
Short name T776
Test name
Test status
Simulation time 16031718 ps
CPU time 0.79 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 207272 kb
Host smart-80e79076-2d83-44ce-b6e4-210682d5ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375509603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3375509603
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1074837520
Short name T203
Test name
Test status
Simulation time 27231962345 ps
CPU time 226.02 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:08:56 PM PDT 24
Peak memory 254596 kb
Host smart-146a3ec3-541f-485f-a28d-9e65ee84369a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074837520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1074837520
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2463952795
Short name T992
Test name
Test status
Simulation time 5919107424 ps
CPU time 6.49 seconds
Started Jul 24 05:05:13 PM PDT 24
Finished Jul 24 05:05:20 PM PDT 24
Peak memory 218516 kb
Host smart-1bd13270-073e-4c0b-bf46-912f947fe863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463952795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2463952795
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3619969136
Short name T398
Test name
Test status
Simulation time 579596979 ps
CPU time 2.87 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 225436 kb
Host smart-2af324a9-6ee5-4c0d-8585-53478f7ab833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619969136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3619969136
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3974672364
Short name T805
Test name
Test status
Simulation time 11251373772 ps
CPU time 53.02 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 233716 kb
Host smart-9c70cb73-a69a-4501-890d-0dea9041bc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974672364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3974672364
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4156730699
Short name T241
Test name
Test status
Simulation time 324948664 ps
CPU time 3.14 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 225288 kb
Host smart-ed8fa892-ccff-42fe-b719-40e1af7f186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156730699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4156730699
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2352344654
Short name T140
Test name
Test status
Simulation time 690936922 ps
CPU time 5.37 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:08 PM PDT 24
Peak memory 225420 kb
Host smart-15a2a8a1-be76-438b-828a-be5cf1031516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352344654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2352344654
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.486738466
Short name T424
Test name
Test status
Simulation time 35975942 ps
CPU time 1.08 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 217300 kb
Host smart-fc879ab7-1e55-4985-9b00-a42ff31a96cb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486738466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.486738466
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2163703720
Short name T907
Test name
Test status
Simulation time 393997729 ps
CPU time 3.54 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 233576 kb
Host smart-af753690-b645-4c6c-9120-1e85d709f17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163703720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2163703720
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1979185817
Short name T394
Test name
Test status
Simulation time 5238434460 ps
CPU time 8.71 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 225416 kb
Host smart-ff4de747-5f1b-449e-bf29-04bfa0f17a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979185817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1979185817
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2225462193
Short name T460
Test name
Test status
Simulation time 801220527 ps
CPU time 11.47 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:15 PM PDT 24
Peak memory 221244 kb
Host smart-1fc736d1-519a-4d50-822f-844ce5ef0ad2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225462193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2225462193
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3158827666
Short name T792
Test name
Test status
Simulation time 173987177075 ps
CPU time 378.88 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:11:16 PM PDT 24
Peak memory 266492 kb
Host smart-5a7bd5bf-da95-4a58-815a-24f465f14606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158827666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3158827666
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.37825532
Short name T133
Test name
Test status
Simulation time 18433693187 ps
CPU time 7.2 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 220440 kb
Host smart-0e273dd2-36d2-42ca-9aa3-fff787add416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37825532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.37825532
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.162767421
Short name T351
Test name
Test status
Simulation time 15619723996 ps
CPU time 9.79 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 218428 kb
Host smart-bf632302-0200-4c98-8cb5-6a7b768cb669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162767421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.162767421
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.66885665
Short name T832
Test name
Test status
Simulation time 181255267 ps
CPU time 1.3 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 217096 kb
Host smart-d4613667-0ec8-40b3-93a3-cd0e0f50a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66885665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.66885665
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3760411711
Short name T995
Test name
Test status
Simulation time 57291233 ps
CPU time 0.84 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 206796 kb
Host smart-3f5a25e6-1979-4bbf-8f4b-b9c3c4d8589b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760411711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3760411711
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2122229438
Short name T609
Test name
Test status
Simulation time 5560454295 ps
CPU time 18.07 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 241652 kb
Host smart-36635b3b-c3fc-4a5d-b4d6-b64534b45778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122229438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2122229438
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4173294351
Short name T462
Test name
Test status
Simulation time 14213247 ps
CPU time 0.69 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 206016 kb
Host smart-17af4699-091b-4513-a40a-ae7f86c3d721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173294351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4173294351
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.536486805
Short name T49
Test name
Test status
Simulation time 116423989 ps
CPU time 2.83 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 225432 kb
Host smart-80c2c33a-5eb6-4f5f-83db-04fdd5ea713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536486805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.536486805
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2864941870
Short name T647
Test name
Test status
Simulation time 47764910 ps
CPU time 0.77 seconds
Started Jul 24 05:05:23 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 207584 kb
Host smart-cc4d1c8b-7962-4810-aa9a-18eff7e4d9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864941870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2864941870
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4274993538
Short name T576
Test name
Test status
Simulation time 6857644009 ps
CPU time 50.67 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 250276 kb
Host smart-c6ebf0eb-09be-4c23-8172-3d65546ddaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274993538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4274993538
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1254292068
Short name T661
Test name
Test status
Simulation time 190486513866 ps
CPU time 149.52 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:07:49 PM PDT 24
Peak memory 241884 kb
Host smart-f9433830-8f6c-491c-a2c4-48d1685238e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254292068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1254292068
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4236361755
Short name T646
Test name
Test status
Simulation time 94020298890 ps
CPU time 200.18 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:08:31 PM PDT 24
Peak memory 250196 kb
Host smart-fb767be3-91e9-4c0b-b5e3-5f2fefdc4314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236361755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4236361755
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2767750213
Short name T769
Test name
Test status
Simulation time 346815862 ps
CPU time 3.39 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 233656 kb
Host smart-16240446-447c-43c0-8e9d-f86289ef2f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767750213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2767750213
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4033473046
Short name T657
Test name
Test status
Simulation time 20406409 ps
CPU time 0.77 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 216552 kb
Host smart-b1e67f7a-23e5-470c-8286-1e8515188934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033473046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4033473046
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2208037776
Short name T496
Test name
Test status
Simulation time 74595364 ps
CPU time 2.82 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 233636 kb
Host smart-2778e9b5-d26b-4371-a881-003e577236db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208037776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2208037776
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2885080688
Short name T786
Test name
Test status
Simulation time 16022042023 ps
CPU time 23.8 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:36 PM PDT 24
Peak memory 235288 kb
Host smart-b07ee4c3-6f27-436a-aa31-bc22038dd2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885080688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2885080688
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1006198494
Short name T35
Test name
Test status
Simulation time 44334334 ps
CPU time 0.98 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 218692 kb
Host smart-a376dbe0-5573-4079-9db3-25aebfe055a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006198494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1006198494
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2157970950
Short name T565
Test name
Test status
Simulation time 9559674324 ps
CPU time 19.87 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 241620 kb
Host smart-b1987d0a-f92c-4072-a3ca-c46df19eae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157970950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2157970950
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2199707590
Short name T574
Test name
Test status
Simulation time 1346290396 ps
CPU time 5.58 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:05:14 PM PDT 24
Peak memory 233616 kb
Host smart-dfc179c4-fa2c-4481-9740-0f8a19c98541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199707590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2199707590
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2417942999
Short name T11
Test name
Test status
Simulation time 658010837 ps
CPU time 4.41 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 221528 kb
Host smart-03bd052d-592e-491c-8a84-e57218b2bba1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417942999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2417942999
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.422847292
Short name T1002
Test name
Test status
Simulation time 2016592920 ps
CPU time 13.85 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 217288 kb
Host smart-d4b4ed71-5817-4c52-a8a6-10780a4d1765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422847292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.422847292
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3924074992
Short name T385
Test name
Test status
Simulation time 1929520065 ps
CPU time 2.54 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 216924 kb
Host smart-9d44c8a0-9e00-46eb-86d2-3d56e8b367c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924074992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3924074992
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2675378116
Short name T573
Test name
Test status
Simulation time 276720563 ps
CPU time 1.72 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 217044 kb
Host smart-ddbaf250-e644-466d-9941-8b20d98c59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675378116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2675378116
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3163471178
Short name T906
Test name
Test status
Simulation time 94053398 ps
CPU time 0.78 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 206700 kb
Host smart-02dc3e91-30e1-40f7-8c04-fcc1b53b8282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163471178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3163471178
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1201798630
Short name T238
Test name
Test status
Simulation time 859566011 ps
CPU time 7.39 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 241684 kb
Host smart-85539844-7c17-49d9-9cb0-fc3f2147db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201798630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1201798630
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3150083830
Short name T426
Test name
Test status
Simulation time 20263687 ps
CPU time 0.7 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 206048 kb
Host smart-3f87b607-7cee-4d38-9e2b-a541677c9700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150083830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3150083830
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2879788344
Short name T560
Test name
Test status
Simulation time 1011546687 ps
CPU time 12.5 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 233604 kb
Host smart-76826769-7a1f-4096-aa35-4f3b3fa28678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879788344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2879788344
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.692890083
Short name T486
Test name
Test status
Simulation time 47238377 ps
CPU time 0.81 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:08 PM PDT 24
Peak memory 207160 kb
Host smart-917f94d5-d100-4239-9237-aaa6f1463f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692890083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.692890083
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1610959768
Short name T644
Test name
Test status
Simulation time 74547220870 ps
CPU time 98.24 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 250148 kb
Host smart-13199084-11de-4ff0-b42c-7436b0d56790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610959768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1610959768
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2056026684
Short name T309
Test name
Test status
Simulation time 6114233699 ps
CPU time 15.95 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 218548 kb
Host smart-66e52b17-6c75-4ea8-a128-93237a16f477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056026684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2056026684
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3188231612
Short name T1001
Test name
Test status
Simulation time 46913408391 ps
CPU time 325.2 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:10:42 PM PDT 24
Peak memory 262552 kb
Host smart-58821f16-b023-46c7-879d-23c3b2967ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188231612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3188231612
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3707327591
Short name T629
Test name
Test status
Simulation time 1195131184 ps
CPU time 12.8 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 225396 kb
Host smart-aa041d9c-8287-4d04-9fd9-65130042e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707327591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3707327591
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1297405359
Short name T845
Test name
Test status
Simulation time 44444337897 ps
CPU time 137.04 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:07:20 PM PDT 24
Peak memory 250304 kb
Host smart-2b46010d-cfee-46db-b890-20dac0ad47bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297405359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1297405359
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.261309999
Short name T384
Test name
Test status
Simulation time 61034817000 ps
CPU time 34.29 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:28 PM PDT 24
Peak memory 233668 kb
Host smart-99398e66-cbdf-4d8a-b2fc-ed4517acfdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261309999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.261309999
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1972213686
Short name T231
Test name
Test status
Simulation time 8585196312 ps
CPU time 74.19 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 249920 kb
Host smart-45252510-ebf2-4dff-9d2c-9b4104da0bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972213686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1972213686
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.200749926
Short name T1022
Test name
Test status
Simulation time 95671383 ps
CPU time 1.04 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 217464 kb
Host smart-b7b6f2bb-0f4e-434e-ad6c-d5eb22cb7a4f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200749926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.200749926
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2461652411
Short name T481
Test name
Test status
Simulation time 6166877806 ps
CPU time 11.95 seconds
Started Jul 24 05:05:25 PM PDT 24
Finished Jul 24 05:05:37 PM PDT 24
Peak memory 225580 kb
Host smart-412ec4d9-f439-44ec-8365-95964c95c1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461652411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2461652411
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4170084029
Short name T889
Test name
Test status
Simulation time 2268776717 ps
CPU time 9.16 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:33 PM PDT 24
Peak memory 225520 kb
Host smart-940cccca-eb6c-4978-bbfe-cd7c08c8a038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170084029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4170084029
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4204055043
Short name T579
Test name
Test status
Simulation time 268777756 ps
CPU time 4.04 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 220576 kb
Host smart-fe93606c-fb3b-4489-97c2-50d81aa93faf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4204055043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4204055043
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3226346143
Short name T17
Test name
Test status
Simulation time 302044912 ps
CPU time 4.05 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 217420 kb
Host smart-c8be1e54-ec23-425e-9861-797994e4dc29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226346143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3226346143
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.107576778
Short name T636
Test name
Test status
Simulation time 783399607 ps
CPU time 7.32 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 217220 kb
Host smart-24173377-a151-4639-b9da-f915d3cf1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107576778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.107576778
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4132268426
Short name T471
Test name
Test status
Simulation time 2579477446 ps
CPU time 6.09 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 217080 kb
Host smart-9dd3f8ad-e55c-4d66-8fee-0eccb89cd270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132268426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4132268426
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1688259890
Short name T692
Test name
Test status
Simulation time 141357298 ps
CPU time 2.73 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 217188 kb
Host smart-2c31515b-3f04-4a9a-848a-36c8d9529486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688259890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1688259890
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.414014224
Short name T710
Test name
Test status
Simulation time 11089880 ps
CPU time 0.69 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 206296 kb
Host smart-70df1adc-96ed-4742-8085-7e09422ea8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414014224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.414014224
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2252526944
Short name T552
Test name
Test status
Simulation time 7293377770 ps
CPU time 26.53 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 249928 kb
Host smart-b78b39e2-393d-4616-8ea4-e266784e2d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252526944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2252526944
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.331844912
Short name T820
Test name
Test status
Simulation time 55971062 ps
CPU time 0.71 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 206012 kb
Host smart-1a257ce5-de64-48b2-ac16-c7e5a71ad849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331844912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.331844912
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3133765034
Short name T561
Test name
Test status
Simulation time 37674473 ps
CPU time 0.72 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 206184 kb
Host smart-3633319b-3322-42ff-ac84-c6554b517de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133765034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3133765034
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3020912038
Short name T628
Test name
Test status
Simulation time 15272350118 ps
CPU time 38.64 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:06:08 PM PDT 24
Peak memory 250632 kb
Host smart-b7a19b7b-33e0-447d-99e1-fec0f2bfddfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020912038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3020912038
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.458208552
Short name T919
Test name
Test status
Simulation time 3335488266 ps
CPU time 38.66 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 250144 kb
Host smart-227b3887-10b3-4450-b8e5-f0e8fa998970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458208552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.458208552
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2736460024
Short name T601
Test name
Test status
Simulation time 322364210 ps
CPU time 4.97 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 220768 kb
Host smart-3136990d-3c81-4cc6-9606-90b65f88d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736460024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2736460024
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.929133355
Short name T702
Test name
Test status
Simulation time 177812239 ps
CPU time 8.35 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 236712 kb
Host smart-07238af5-1173-4a8a-8936-b46278d11a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929133355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.929133355
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1155957581
Short name T582
Test name
Test status
Simulation time 580353569 ps
CPU time 8.65 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 225464 kb
Host smart-bace4003-9828-476a-8406-232319375c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155957581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1155957581
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1067625010
Short name T991
Test name
Test status
Simulation time 29792970 ps
CPU time 2.01 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 225072 kb
Host smart-7cfc4cc3-1cc4-4733-9212-8cb36970db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067625010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1067625010
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2989872980
Short name T921
Test name
Test status
Simulation time 111274002 ps
CPU time 1.03 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 217464 kb
Host smart-edcbb4ad-ecec-43d1-9e2e-38fcd1feefce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989872980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2989872980
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.546191198
Short name T633
Test name
Test status
Simulation time 33556294738 ps
CPU time 22.08 seconds
Started Jul 24 05:05:23 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 233644 kb
Host smart-76952c97-a039-4a01-aa5a-87b74883512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546191198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.546191198
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2402208067
Short name T717
Test name
Test status
Simulation time 6110073751 ps
CPU time 9.51 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:31 PM PDT 24
Peak memory 233620 kb
Host smart-9a318712-957f-4bda-a6a3-59388f2cb36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402208067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2402208067
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1224451496
Short name T500
Test name
Test status
Simulation time 650939790 ps
CPU time 8.4 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:23 PM PDT 24
Peak memory 219992 kb
Host smart-52f850c6-2779-43ff-a809-b6e24410422a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1224451496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1224451496
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.112127491
Short name T817
Test name
Test status
Simulation time 42576681 ps
CPU time 0.87 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 206536 kb
Host smart-55c4df42-3d0f-4167-904d-7dee661f3153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112127491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.112127491
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2824143018
Short name T498
Test name
Test status
Simulation time 6556854955 ps
CPU time 13.27 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 217208 kb
Host smart-decb9941-3bcd-47d4-b7bd-169cb606f47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824143018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2824143018
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.612879635
Short name T445
Test name
Test status
Simulation time 3322561261 ps
CPU time 10.66 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 217200 kb
Host smart-29ec5532-ec9e-4ed1-85fb-b0ae93ad96c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612879635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.612879635
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.133224573
Short name T432
Test name
Test status
Simulation time 138759646 ps
CPU time 1.93 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 208936 kb
Host smart-d2c5c83a-c2cf-4e46-9a29-ec42d25fd09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133224573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.133224573
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.512566981
Short name T456
Test name
Test status
Simulation time 52334946 ps
CPU time 0.84 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 206872 kb
Host smart-647772b8-1232-4975-aeb3-00ac8c6ccd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512566981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.512566981
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3118928161
Short name T495
Test name
Test status
Simulation time 29526140000 ps
CPU time 11.26 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 222728 kb
Host smart-d2a34739-926d-4828-810c-3f95cb044b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118928161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3118928161
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2719255076
Short name T373
Test name
Test status
Simulation time 39090119 ps
CPU time 0.7 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 205496 kb
Host smart-24507ecf-c755-4b38-9ab8-362d1b0bfe15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719255076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2719255076
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.158848656
Short name T652
Test name
Test status
Simulation time 689895915 ps
CPU time 3.6 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:15 PM PDT 24
Peak memory 233688 kb
Host smart-66ee3900-231e-4217-a6f8-03a2df727e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158848656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.158848656
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.985682461
Short name T474
Test name
Test status
Simulation time 38157966 ps
CPU time 0.8 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:05:38 PM PDT 24
Peak memory 207316 kb
Host smart-b628b186-da94-492e-9242-197a52551efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985682461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.985682461
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.686195516
Short name T225
Test name
Test status
Simulation time 1693744705 ps
CPU time 22.7 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:33 PM PDT 24
Peak memory 237700 kb
Host smart-d29f69f9-7495-4206-bce0-92ca76a14bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686195516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.686195516
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2570771482
Short name T1027
Test name
Test status
Simulation time 16118762739 ps
CPU time 77.76 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 256308 kb
Host smart-57377f45-71dd-4c71-9e82-74f936dc7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570771482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2570771482
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2788295568
Short name T611
Test name
Test status
Simulation time 3217933916 ps
CPU time 45.83 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 241956 kb
Host smart-b3f8ae6a-1b67-4669-84d4-8a0784d06d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788295568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2788295568
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3220871048
Short name T958
Test name
Test status
Simulation time 614481571 ps
CPU time 8.82 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 233672 kb
Host smart-b55d381d-c7aa-46bc-a119-58649c04ec4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220871048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3220871048
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2779247530
Short name T448
Test name
Test status
Simulation time 3735641582 ps
CPU time 41.3 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 257080 kb
Host smart-3427cd7e-3231-467a-b49d-c399d2091fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779247530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2779247530
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.315688001
Short name T401
Test name
Test status
Simulation time 391537677 ps
CPU time 5.17 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:37 PM PDT 24
Peak memory 219720 kb
Host smart-e5ec0af1-f0d1-4c8a-beae-f7963e0a61f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315688001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.315688001
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2516176191
Short name T846
Test name
Test status
Simulation time 7432133830 ps
CPU time 15.85 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 225412 kb
Host smart-dd2ddbaf-0fcb-441c-9531-242c9c8d3b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516176191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2516176191
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1798129335
Short name T548
Test name
Test status
Simulation time 89531142 ps
CPU time 1.05 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 217320 kb
Host smart-79eb934f-827b-445f-9834-f4a6f3881c3f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798129335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1798129335
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2620267211
Short name T824
Test name
Test status
Simulation time 642393523 ps
CPU time 5.87 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 225376 kb
Host smart-d7e8c89f-d603-4c91-87e9-a9eaed9bfdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620267211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2620267211
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.494202715
Short name T249
Test name
Test status
Simulation time 457137145 ps
CPU time 2.47 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 225424 kb
Host smart-fbbea464-345e-48ac-889d-c8424560f67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494202715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.494202715
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3060437026
Short name T349
Test name
Test status
Simulation time 117818336 ps
CPU time 4.22 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 220632 kb
Host smart-4b1ff5b6-5016-4234-b7cc-fd6439858e92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3060437026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3060437026
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2189029692
Short name T285
Test name
Test status
Simulation time 2874274707 ps
CPU time 62.75 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 235884 kb
Host smart-76fa917e-7525-45e5-81d8-1271c7c7d2e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189029692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2189029692
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3991179033
Short name T997
Test name
Test status
Simulation time 2049866316 ps
CPU time 6.51 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 217192 kb
Host smart-f2d4e66d-b1ce-4f3d-899d-4c9df3277b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991179033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3991179033
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2189753784
Short name T908
Test name
Test status
Simulation time 2385575413 ps
CPU time 3.71 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 217040 kb
Host smart-258cde47-29e8-4e75-91ce-c609ea581809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189753784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2189753784
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.848666085
Short name T1015
Test name
Test status
Simulation time 166167715 ps
CPU time 7.73 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:30 PM PDT 24
Peak memory 217100 kb
Host smart-0219edca-4fbe-4464-8c57-9f0b3027ffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848666085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.848666085
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2615664843
Short name T399
Test name
Test status
Simulation time 48488869 ps
CPU time 0.86 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:05:20 PM PDT 24
Peak memory 206940 kb
Host smart-06678683-b9d3-43c2-b235-fb7972dd617f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615664843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2615664843
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3368293285
Short name T75
Test name
Test status
Simulation time 23004148804 ps
CPU time 34.03 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 233700 kb
Host smart-71a86158-a448-4658-94b4-12a5abeeeddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368293285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3368293285
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.730893049
Short name T888
Test name
Test status
Simulation time 14520519 ps
CPU time 0.69 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 205496 kb
Host smart-470a0964-1acd-4fdd-b435-86ba14b50b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730893049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.730893049
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3095031169
Short name T553
Test name
Test status
Simulation time 71162549 ps
CPU time 2.95 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 225356 kb
Host smart-5f212f3a-1637-47a3-b2b8-544a507f375c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095031169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3095031169
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1856300969
Short name T796
Test name
Test status
Simulation time 61083793 ps
CPU time 0.78 seconds
Started Jul 24 05:05:28 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 207192 kb
Host smart-4bc0ce00-80ca-4592-9145-608f54f037cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856300969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1856300969
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2975500676
Short name T416
Test name
Test status
Simulation time 30473499452 ps
CPU time 37.59 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 241172 kb
Host smart-41e807c3-4c64-4b0f-b327-8e48ef9bdbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975500676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2975500676
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3276250526
Short name T509
Test name
Test status
Simulation time 835137406 ps
CPU time 8.42 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 218380 kb
Host smart-c576a6f5-0a59-4abd-8279-2d9ff587cd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276250526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3276250526
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.688198736
Short name T806
Test name
Test status
Simulation time 63349275961 ps
CPU time 66.69 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 239200 kb
Host smart-c93189ce-5e15-477b-a31a-9a1d86f77aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688198736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.688198736
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.4102311847
Short name T864
Test name
Test status
Simulation time 14594717979 ps
CPU time 43.5 seconds
Started Jul 24 05:05:23 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 233752 kb
Host smart-f9b40b63-944b-4861-87e4-0020683f6e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102311847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.4102311847
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1813945494
Short name T478
Test name
Test status
Simulation time 27916670 ps
CPU time 0.75 seconds
Started Jul 24 05:05:25 PM PDT 24
Finished Jul 24 05:05:30 PM PDT 24
Peak memory 216636 kb
Host smart-db2a9465-4c52-4047-bebb-d89f769235ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813945494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1813945494
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.583015735
Short name T815
Test name
Test status
Simulation time 579741375 ps
CPU time 5.13 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 225396 kb
Host smart-4dab26cb-4de7-4cb6-be5a-1062e153ab3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583015735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.583015735
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1990458925
Short name T497
Test name
Test status
Simulation time 29753490872 ps
CPU time 19.16 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:30 PM PDT 24
Peak memory 225432 kb
Host smart-14024b52-6f06-4ea9-8fb3-a8c60b8f898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990458925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1990458925
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3225778470
Short name T672
Test name
Test status
Simulation time 16214007 ps
CPU time 1.01 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 217388 kb
Host smart-0c8f0a7c-9662-4b5d-9eb6-c802076c9d3a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225778470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3225778470
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2299990113
Short name T612
Test name
Test status
Simulation time 8457110026 ps
CPU time 25.72 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 249924 kb
Host smart-cb71967a-6cce-48d8-866d-7064686b1968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299990113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2299990113
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1365755423
Short name T183
Test name
Test status
Simulation time 18505143191 ps
CPU time 16.34 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 233704 kb
Host smart-0914ec6d-6f28-4bd7-8c39-a7f2a87bfb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365755423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1365755423
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2041927563
Short name T427
Test name
Test status
Simulation time 2389730912 ps
CPU time 12.02 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 222828 kb
Host smart-625b624c-3078-4e3c-ad34-b201b47b9a43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2041927563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2041927563
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2403782479
Short name T20
Test name
Test status
Simulation time 37534621391 ps
CPU time 169.9 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:08:04 PM PDT 24
Peak memory 250028 kb
Host smart-e7f3375e-a4fc-459f-acb7-d463aceb580e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403782479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2403782479
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1724255406
Short name T415
Test name
Test status
Simulation time 5839280270 ps
CPU time 27.13 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:05:36 PM PDT 24
Peak memory 217588 kb
Host smart-78966720-08fe-453c-87b7-ee436887e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724255406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1724255406
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1882406185
Short name T599
Test name
Test status
Simulation time 6405838227 ps
CPU time 18.77 seconds
Started Jul 24 05:05:36 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 217184 kb
Host smart-0a1a5cad-71b0-4bff-9c6f-a7ad5574339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882406185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1882406185
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1156768473
Short name T395
Test name
Test status
Simulation time 37337298 ps
CPU time 0.73 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 206296 kb
Host smart-64ab1406-b73a-41c4-b044-2e6821d708e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156768473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1156768473
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1980240035
Short name T678
Test name
Test status
Simulation time 88962159 ps
CPU time 0.77 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 206720 kb
Host smart-90922548-8a35-40e4-af4c-402c4931e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980240035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1980240035
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.205836144
Short name T597
Test name
Test status
Simulation time 2304025027 ps
CPU time 6.47 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:12 PM PDT 24
Peak memory 233684 kb
Host smart-06a344be-0514-47ed-b35f-faf1ee0c21b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205836144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.205836144
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.358620977
Short name T389
Test name
Test status
Simulation time 32286771 ps
CPU time 0.73 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:05:20 PM PDT 24
Peak memory 205524 kb
Host smart-64186d08-cbd3-4d83-92c4-f941b6fc3d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358620977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.358620977
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.161932921
Short name T252
Test name
Test status
Simulation time 524465962 ps
CPU time 4.41 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 233600 kb
Host smart-6692fdc2-853a-4585-8fd0-991757d800a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161932921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.161932921
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2647080313
Short name T984
Test name
Test status
Simulation time 30052489 ps
CPU time 0.73 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 207520 kb
Host smart-4ce303dc-bd81-4b36-b168-80d5f39c7a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647080313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2647080313
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.789725877
Short name T235
Test name
Test status
Simulation time 206212205987 ps
CPU time 153.43 seconds
Started Jul 24 05:05:25 PM PDT 24
Finished Jul 24 05:07:59 PM PDT 24
Peak memory 250468 kb
Host smart-484748b8-9666-407a-8015-d3608944716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789725877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.789725877
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.189374084
Short name T224
Test name
Test status
Simulation time 38410944401 ps
CPU time 275.47 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:10:00 PM PDT 24
Peak memory 257264 kb
Host smart-14ce8fac-3484-4515-9be6-05d0ced3f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189374084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.189374084
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.644288066
Short name T305
Test name
Test status
Simulation time 4981671024 ps
CPU time 35.36 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 225528 kb
Host smart-a1d05649-956a-440d-abe5-56b6cd6a6ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644288066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.644288066
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3698232922
Short name T829
Test name
Test status
Simulation time 1041578487 ps
CPU time 2.53 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 225432 kb
Host smart-189306ee-1727-4be3-826a-43eb7c7cdddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698232922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3698232922
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.765769935
Short name T182
Test name
Test status
Simulation time 451356837669 ps
CPU time 345.24 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:11:19 PM PDT 24
Peak memory 272264 kb
Host smart-000aae35-f7a8-4218-ace0-53ebbd0741ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765769935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.765769935
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1392372913
Short name T65
Test name
Test status
Simulation time 53424350736 ps
CPU time 48.18 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 238424 kb
Host smart-7c0bfb94-cb3c-42e8-94d4-b2c4f652ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392372913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1392372913
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.744748331
Short name T748
Test name
Test status
Simulation time 27872558 ps
CPU time 1.03 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 217396 kb
Host smart-a82e6f3c-1ca2-44cc-b6ee-a6898d821254
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744748331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.744748331
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1905849078
Short name T50
Test name
Test status
Simulation time 494283761 ps
CPU time 3.11 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 225436 kb
Host smart-ad0c537e-c9cd-42b9-b1bc-8f3650d328c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905849078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1905849078
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2917000741
Short name T202
Test name
Test status
Simulation time 320753625 ps
CPU time 6.42 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 241412 kb
Host smart-20f4a3be-1d04-4491-97f9-132795b13325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917000741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2917000741
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2521063118
Short name T942
Test name
Test status
Simulation time 916283663 ps
CPU time 3.64 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 223456 kb
Host smart-464b09a1-4926-4986-a256-36507efd998f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521063118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2521063118
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1731811870
Short name T487
Test name
Test status
Simulation time 2174823829 ps
CPU time 46.92 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 254280 kb
Host smart-ecb1fd2c-87c6-45f2-8bb0-db6d8c34d3c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731811870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1731811870
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1585376055
Short name T310
Test name
Test status
Simulation time 20152656609 ps
CPU time 30.45 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:06:16 PM PDT 24
Peak memory 217240 kb
Host smart-16063b55-b9e8-4429-bebf-106d39bbc5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585376055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1585376055
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3093869865
Short name T854
Test name
Test status
Simulation time 3327487141 ps
CPU time 5.55 seconds
Started Jul 24 05:05:13 PM PDT 24
Finished Jul 24 05:05:19 PM PDT 24
Peak memory 217256 kb
Host smart-d35ea267-4f26-48d7-aa09-9bb69f4469ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093869865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3093869865
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2640356757
Short name T938
Test name
Test status
Simulation time 573437904 ps
CPU time 1.85 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 216980 kb
Host smart-d012a9b7-df2d-4fc9-a811-7a54234c2c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640356757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2640356757
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.477829836
Short name T681
Test name
Test status
Simulation time 178199976 ps
CPU time 0.86 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 206720 kb
Host smart-55d78973-8bf6-451d-a80d-789bff911ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477829836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.477829836
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1812053908
Short name T10
Test name
Test status
Simulation time 3958174426 ps
CPU time 12 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 233552 kb
Host smart-3a814073-3997-411b-9797-25e32688f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812053908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1812053908
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1467283089
Short name T735
Test name
Test status
Simulation time 33885314 ps
CPU time 0.72 seconds
Started Jul 24 05:05:22 PM PDT 24
Finished Jul 24 05:05:23 PM PDT 24
Peak memory 206416 kb
Host smart-1188a898-eed7-447f-a824-c8ce0151bba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467283089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1467283089
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3509894572
Short name T465
Test name
Test status
Simulation time 30473205 ps
CPU time 1.95 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 225364 kb
Host smart-714d85d6-315f-447f-a011-f208dc211ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509894572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3509894572
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2248390239
Short name T719
Test name
Test status
Simulation time 165354461 ps
CPU time 0.74 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 207128 kb
Host smart-bf96064a-dee3-4f06-aa17-22da19e36074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248390239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2248390239
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1108058091
Short name T895
Test name
Test status
Simulation time 14773190448 ps
CPU time 113.8 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 250268 kb
Host smart-4bcccd0d-a4a8-4ade-aca4-dcef11921d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108058091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1108058091
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3905363709
Short name T869
Test name
Test status
Simulation time 2464500492 ps
CPU time 36.53 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 250172 kb
Host smart-3bf05953-958d-4f01-b948-8dcbd259ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905363709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3905363709
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.268591163
Short name T767
Test name
Test status
Simulation time 8114672208 ps
CPU time 78.86 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 254292 kb
Host smart-4d91c1f4-fa86-4d26-a583-3118c4f54a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268591163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.268591163
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2436869840
Short name T665
Test name
Test status
Simulation time 1312431481 ps
CPU time 21.49 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:05:54 PM PDT 24
Peak memory 241756 kb
Host smart-213d183a-98ca-4c86-b524-34a79cace300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436869840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2436869840
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3175241008
Short name T1003
Test name
Test status
Simulation time 2645004959 ps
CPU time 54.03 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 251484 kb
Host smart-63343e14-6bbd-4cfc-8813-108bcfdb1100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175241008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3175241008
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2689665355
Short name T339
Test name
Test status
Simulation time 102473341 ps
CPU time 2.06 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:14 PM PDT 24
Peak memory 223748 kb
Host smart-6db65dc5-63e9-4bc7-a1ec-a13196732d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689665355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2689665355
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2465871709
Short name T375
Test name
Test status
Simulation time 195110296 ps
CPU time 4.13 seconds
Started Jul 24 05:05:22 PM PDT 24
Finished Jul 24 05:05:27 PM PDT 24
Peak memory 233492 kb
Host smart-a838e4a8-f828-4517-bbc8-9631daedd85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465871709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2465871709
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3797301352
Short name T463
Test name
Test status
Simulation time 44298091 ps
CPU time 1.04 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:15 PM PDT 24
Peak memory 217308 kb
Host smart-e1860fed-d8f5-4f55-bb7d-85af57040303
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797301352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3797301352
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3238600722
Short name T799
Test name
Test status
Simulation time 2629213401 ps
CPU time 6.53 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 241832 kb
Host smart-caaadbd1-2002-47a6-b25b-72b9e8c8a198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238600722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3238600722
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2526499499
Short name T512
Test name
Test status
Simulation time 10042457852 ps
CPU time 7.33 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 225528 kb
Host smart-79e9bead-f61d-4b92-8578-fe7f0a2ba727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526499499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2526499499
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2667755883
Short name T637
Test name
Test status
Simulation time 164064973 ps
CPU time 3.72 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 223900 kb
Host smart-7c958063-50d5-4e1f-bcf7-8670aa9da8da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2667755883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2667755883
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1190435999
Short name T162
Test name
Test status
Simulation time 1965151290 ps
CPU time 22.86 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 232524 kb
Host smart-c68565a6-ea54-43a4-b71b-36953a1fd784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190435999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1190435999
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1857907644
Short name T380
Test name
Test status
Simulation time 17404480536 ps
CPU time 23.64 seconds
Started Jul 24 05:05:25 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 217276 kb
Host smart-e3ae7d0d-655b-4a3e-aff3-8426419fdfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857907644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1857907644
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1584525982
Short name T746
Test name
Test status
Simulation time 48081626 ps
CPU time 0.7 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 206368 kb
Host smart-ad1c5cca-8a57-464d-8fde-7c34cabff4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584525982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1584525982
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3471043812
Short name T1029
Test name
Test status
Simulation time 112947126 ps
CPU time 1.26 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 217196 kb
Host smart-c3c1521c-1b2c-4d9f-aba1-3f7b856b8386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471043812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3471043812
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2204168895
Short name T468
Test name
Test status
Simulation time 11710161 ps
CPU time 0.68 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:05:30 PM PDT 24
Peak memory 206320 kb
Host smart-298ce893-eb7a-44f4-8491-a08bb7189097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204168895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2204168895
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1039728075
Short name T51
Test name
Test status
Simulation time 8025863808 ps
CPU time 16.04 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 233676 kb
Host smart-1375aded-9378-4817-9180-21cecb984e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039728075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1039728075
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.929791176
Short name T871
Test name
Test status
Simulation time 25118465 ps
CPU time 0.73 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:04:55 PM PDT 24
Peak memory 206008 kb
Host smart-258524ec-4829-452f-a124-0a42d8893b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929791176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.929791176
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2397778786
Short name T623
Test name
Test status
Simulation time 700467378 ps
CPU time 3.09 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 225332 kb
Host smart-ff5b9f13-6f06-44e4-8717-fb96756a54b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397778786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2397778786
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1357073640
Short name T521
Test name
Test status
Simulation time 37604660 ps
CPU time 0.83 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:46 PM PDT 24
Peak memory 207212 kb
Host smart-cdf03e34-4d19-4b72-861f-994164673548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357073640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1357073640
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.737269615
Short name T54
Test name
Test status
Simulation time 5568281423 ps
CPU time 20.45 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 225568 kb
Host smart-81ae1d01-2887-44cb-9eff-7fb99e27f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737269615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.737269615
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4291712743
Short name T214
Test name
Test status
Simulation time 2829912770 ps
CPU time 65.38 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 257876 kb
Host smart-e27ce3c6-46e8-430d-a96d-5ee38915995e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291712743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4291712743
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.415742766
Short name T138
Test name
Test status
Simulation time 31216010 ps
CPU time 2.59 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 233716 kb
Host smart-91cd6c57-7f22-4248-b466-aedc9b428fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415742766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.415742766
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1423205236
Short name T879
Test name
Test status
Simulation time 23240796069 ps
CPU time 16.27 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 250044 kb
Host smart-10732509-e312-4114-a474-e2773225c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423205236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1423205236
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1410828694
Short name T534
Test name
Test status
Simulation time 1208378897 ps
CPU time 4.71 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:44 PM PDT 24
Peak memory 233516 kb
Host smart-6c671b16-138e-4eba-926a-f9ff2deaabd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410828694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1410828694
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2443924053
Short name T234
Test name
Test status
Simulation time 5956739826 ps
CPU time 12.24 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 225528 kb
Host smart-8f4100ca-42eb-434f-8bdf-a7bf5a7a8c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443924053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2443924053
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3661899058
Short name T697
Test name
Test status
Simulation time 14158276 ps
CPU time 1.04 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 217436 kb
Host smart-a3a428a7-cfc0-430e-9781-672293724d31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661899058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3661899058
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2504354506
Short name T1006
Test name
Test status
Simulation time 1489043688 ps
CPU time 6.89 seconds
Started Jul 24 05:04:34 PM PDT 24
Finished Jul 24 05:04:41 PM PDT 24
Peak memory 233484 kb
Host smart-74e5622d-7b70-4b5a-a6c1-7021722cac92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504354506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2504354506
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3178488502
Short name T967
Test name
Test status
Simulation time 5396651304 ps
CPU time 6.24 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 233604 kb
Host smart-4136c28b-7b69-429c-96f0-db61e3a8787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178488502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3178488502
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2136736002
Short name T542
Test name
Test status
Simulation time 513812407 ps
CPU time 3.86 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 224064 kb
Host smart-d6b3629d-bef2-4b57-9dc8-79509ab3dc49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2136736002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2136736002
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.4289380539
Short name T283
Test name
Test status
Simulation time 12839562488 ps
CPU time 182 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:07:54 PM PDT 24
Peak memory 263328 kb
Host smart-ee0eb2e4-3bc5-45d6-ad3b-d357c5331f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289380539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.4289380539
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.511953085
Short name T795
Test name
Test status
Simulation time 2651043713 ps
CPU time 23.76 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:05:14 PM PDT 24
Peak memory 221548 kb
Host smart-43241654-6280-4e14-a9d5-62ac20072ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511953085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.511953085
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3266198501
Short name T894
Test name
Test status
Simulation time 3206678366 ps
CPU time 9.47 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:43 PM PDT 24
Peak memory 217224 kb
Host smart-2b04cf1c-7d2d-416e-9fc6-6daf71b7ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266198501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3266198501
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.74208775
Short name T875
Test name
Test status
Simulation time 79305291 ps
CPU time 1.08 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 208952 kb
Host smart-8ff232a0-5535-4016-b7d2-fa3192825f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74208775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.74208775
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3132609722
Short name T616
Test name
Test status
Simulation time 61516190 ps
CPU time 0.73 seconds
Started Jul 24 05:04:30 PM PDT 24
Finished Jul 24 05:04:31 PM PDT 24
Peak memory 206660 kb
Host smart-ef70e295-d7bf-4083-a6bc-9aa624209325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132609722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3132609722
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3886989681
Short name T918
Test name
Test status
Simulation time 4425971040 ps
CPU time 6.48 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 225392 kb
Host smart-c2bed82f-bfd7-4246-856e-a2b0dd159a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886989681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3886989681
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3697582932
Short name T1023
Test name
Test status
Simulation time 14978829 ps
CPU time 0.71 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 205492 kb
Host smart-1e0ac2e5-95a4-47ce-bf30-18155df10e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697582932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3697582932
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2131295521
Short name T1016
Test name
Test status
Simulation time 39521352 ps
CPU time 2.13 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 225412 kb
Host smart-23e30d0b-ab97-4456-aaa9-c8fa4a4eb606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131295521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2131295521
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2183188642
Short name T662
Test name
Test status
Simulation time 58841547 ps
CPU time 0.75 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 206152 kb
Host smart-ae98b4ac-410c-4868-9c82-58554a049e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183188642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2183188642
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2871382723
Short name T406
Test name
Test status
Simulation time 24023278191 ps
CPU time 114.71 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 251208 kb
Host smart-4d9706c0-cbf5-4348-af2b-473ef1022bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871382723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2871382723
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.4283132958
Short name T220
Test name
Test status
Simulation time 143548907575 ps
CPU time 350.97 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:11:23 PM PDT 24
Peak memory 257280 kb
Host smart-871ef27c-9e46-44a8-b998-da86b7d9ee94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283132958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.4283132958
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1184788299
Short name T881
Test name
Test status
Simulation time 284140030 ps
CPU time 9.88 seconds
Started Jul 24 05:05:19 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 250720 kb
Host smart-914775e1-fd4a-4d5a-9b0d-f4c7af8f67b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184788299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1184788299
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2466282098
Short name T272
Test name
Test status
Simulation time 6798467977 ps
CPU time 64.92 seconds
Started Jul 24 05:05:28 PM PDT 24
Finished Jul 24 05:06:33 PM PDT 24
Peak memory 256200 kb
Host smart-d378dfd7-7831-46f0-b4d9-b1fe1a228932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466282098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2466282098
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3917793890
Short name T557
Test name
Test status
Simulation time 1071899054 ps
CPU time 6.13 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 233596 kb
Host smart-e28e834e-ce86-4222-8445-2a124b259d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917793890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3917793890
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4108029083
Short name T420
Test name
Test status
Simulation time 58648662 ps
CPU time 2.13 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 225432 kb
Host smart-6888941f-6cdb-451d-81e3-20b4c4b828e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108029083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4108029083
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3212833630
Short name T193
Test name
Test status
Simulation time 39397719671 ps
CPU time 21.83 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:38 PM PDT 24
Peak memory 233596 kb
Host smart-5d971777-1185-4b27-95fc-00bd26c0277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212833630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3212833630
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1855140944
Short name T541
Test name
Test status
Simulation time 72855199 ps
CPU time 2.2 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 224844 kb
Host smart-85b8b031-4c12-47b5-9a0e-b4a63a1987af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855140944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1855140944
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3740355982
Short name T149
Test name
Test status
Simulation time 1626686332 ps
CPU time 9.25 seconds
Started Jul 24 05:05:15 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 223884 kb
Host smart-d4819d0a-35ff-451f-88f4-d33848c33103
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3740355982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3740355982
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.873838462
Short name T742
Test name
Test status
Simulation time 133375661265 ps
CPU time 402.76 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:12:15 PM PDT 24
Peak memory 267456 kb
Host smart-f191fa3d-e4ad-40b2-83c6-c6e972872e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873838462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.873838462
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3921993907
Short name T538
Test name
Test status
Simulation time 15377933 ps
CPU time 0.72 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 206332 kb
Host smart-2845a730-42ae-447b-b73f-e36e89f4d09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921993907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3921993907
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.534787184
Short name T725
Test name
Test status
Simulation time 3167155806 ps
CPU time 4.18 seconds
Started Jul 24 05:05:16 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 217288 kb
Host smart-2108a8db-20ea-4040-ac76-de37585e2a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534787184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.534787184
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2984167848
Short name T642
Test name
Test status
Simulation time 180153745 ps
CPU time 1.19 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 208648 kb
Host smart-cfa24839-8091-466e-991c-2c05ac8e0690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984167848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2984167848
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.498099113
Short name T1014
Test name
Test status
Simulation time 143692603 ps
CPU time 0.85 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:30 PM PDT 24
Peak memory 207752 kb
Host smart-9c57e9d8-c025-41d2-a480-6f880a640b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498099113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.498099113
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2352362840
Short name T708
Test name
Test status
Simulation time 1193880969 ps
CPU time 5.09 seconds
Started Jul 24 05:05:35 PM PDT 24
Finished Jul 24 05:05:40 PM PDT 24
Peak memory 225404 kb
Host smart-1b1dd01e-999c-4cbd-8d9a-72a70dfbc0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352362840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2352362840
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3321045987
Short name T369
Test name
Test status
Simulation time 24942142 ps
CPU time 0.71 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:28 PM PDT 24
Peak memory 205360 kb
Host smart-c6f00964-abc2-4fca-b30d-d66d9cba58b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321045987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3321045987
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1281541588
Short name T370
Test name
Test status
Simulation time 512391193 ps
CPU time 5.48 seconds
Started Jul 24 05:05:26 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 225448 kb
Host smart-f69c3600-1a93-42ab-b9ee-357e59da578d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281541588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1281541588
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4142981595
Short name T66
Test name
Test status
Simulation time 33115355 ps
CPU time 0.74 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 206116 kb
Host smart-e2a60f3a-06c2-4217-bf93-3081748f252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142981595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4142981595
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1040395740
Short name T282
Test name
Test status
Simulation time 122334728251 ps
CPU time 256.39 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:09:55 PM PDT 24
Peak memory 258248 kb
Host smart-7103df16-cc5b-46df-bf90-676b03a2edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040395740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1040395740
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1633149428
Short name T797
Test name
Test status
Simulation time 217983034528 ps
CPU time 239.95 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:09:40 PM PDT 24
Peak memory 257336 kb
Host smart-dad88eb3-a996-45b8-bc1f-ea888c87602a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633149428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1633149428
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1443259472
Short name T571
Test name
Test status
Simulation time 204085127 ps
CPU time 5.52 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 225364 kb
Host smart-e41068a5-5a6d-4aed-96d0-b3c88185877e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443259472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1443259472
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1123820657
Short name T82
Test name
Test status
Simulation time 29054179819 ps
CPU time 192.67 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:08:50 PM PDT 24
Peak memory 249712 kb
Host smart-859afd07-c6f4-4589-bf32-bb0272d1c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123820657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1123820657
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.963764050
Short name T703
Test name
Test status
Simulation time 200894683 ps
CPU time 3.08 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:38 PM PDT 24
Peak memory 233552 kb
Host smart-0e921f1d-dad9-4126-93c8-158bb2eb84a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963764050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.963764050
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1527686568
Short name T755
Test name
Test status
Simulation time 10605839855 ps
CPU time 40.11 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 233716 kb
Host smart-d8db1c60-ab17-4c64-aac7-fde12c550cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527686568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1527686568
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1031775337
Short name T923
Test name
Test status
Simulation time 25309865642 ps
CPU time 32.79 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 233756 kb
Host smart-d3da7627-7a8c-46d7-bd67-4f6e6f82a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031775337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1031775337
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.315518112
Short name T886
Test name
Test status
Simulation time 1982243964 ps
CPU time 7.39 seconds
Started Jul 24 05:05:36 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 233488 kb
Host smart-95df5d8e-5a46-4982-b20d-23976ac3d5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315518112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.315518112
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1126581551
Short name T880
Test name
Test status
Simulation time 3039879515 ps
CPU time 10.98 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 219784 kb
Host smart-618bdeaa-26ac-418f-b098-677324f92d59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1126581551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1126581551
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3727635693
Short name T808
Test name
Test status
Simulation time 24699509667 ps
CPU time 39.89 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:06:25 PM PDT 24
Peak memory 217140 kb
Host smart-c947eb9a-5516-443b-be37-d6cce6a571c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727635693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3727635693
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3441303345
Short name T341
Test name
Test status
Simulation time 10766962 ps
CPU time 0.76 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 206292 kb
Host smart-3c64ab23-c82c-4758-b8c1-777a1dd8482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441303345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3441303345
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2158072192
Short name T930
Test name
Test status
Simulation time 147419164 ps
CPU time 1.46 seconds
Started Jul 24 05:05:11 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 217136 kb
Host smart-7796cdc2-50e6-4b0c-b432-6498f1550c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158072192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2158072192
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1811515694
Short name T411
Test name
Test status
Simulation time 59893558 ps
CPU time 0.9 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:05:19 PM PDT 24
Peak memory 206676 kb
Host smart-aa25f50c-6029-4372-9f8a-919cf2a722cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811515694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1811515694
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3604249208
Short name T843
Test name
Test status
Simulation time 1816249038 ps
CPU time 8.55 seconds
Started Jul 24 05:05:27 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 233628 kb
Host smart-6ba125c3-a76b-4257-965c-e7adaa8f4e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604249208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3604249208
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.676209347
Short name T336
Test name
Test status
Simulation time 51544349 ps
CPU time 0.75 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 206424 kb
Host smart-24ff1291-8785-4129-a630-68bcba57c077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676209347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.676209347
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.508814518
Short name T388
Test name
Test status
Simulation time 746621209 ps
CPU time 9.25 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 233620 kb
Host smart-6b5158ce-3835-44b4-b963-e29ee39ac3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508814518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.508814518
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1143511829
Short name T532
Test name
Test status
Simulation time 22088430 ps
CPU time 0.84 seconds
Started Jul 24 05:05:34 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 207580 kb
Host smart-4f1da721-bbc0-400e-aa1e-dae6994b9c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143511829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1143511829
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3754724032
Short name T315
Test name
Test status
Simulation time 70045192 ps
CPU time 0.81 seconds
Started Jul 24 05:05:26 PM PDT 24
Finished Jul 24 05:05:27 PM PDT 24
Peak memory 216664 kb
Host smart-5d527570-afac-404f-8981-c95f6a40712f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754724032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3754724032
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1799471997
Short name T3
Test name
Test status
Simulation time 7934606493 ps
CPU time 45.53 seconds
Started Jul 24 05:05:28 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 239204 kb
Host smart-8c9c59c3-aa5f-4f3a-afcf-aa3abcb0b749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799471997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1799471997
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.1692886469
Short name T660
Test name
Test status
Simulation time 42820036917 ps
CPU time 80.85 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 250060 kb
Host smart-d7a45f75-7747-4043-b320-182f95ce6542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692886469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.1692886469
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2134874070
Short name T685
Test name
Test status
Simulation time 82940055 ps
CPU time 3.45 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 225448 kb
Host smart-53b5b735-558d-4f12-b438-96a520e342b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134874070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2134874070
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2886388171
Short name T567
Test name
Test status
Simulation time 34596172986 ps
CPU time 80.41 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 241884 kb
Host smart-e3e9312b-1f0a-4173-a6a0-e41b7f93726c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886388171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2886388171
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2321603696
Short name T362
Test name
Test status
Simulation time 7427646747 ps
CPU time 9.48 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 238052 kb
Host smart-81396754-779b-44a5-bc3d-7d95207d721e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321603696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2321603696
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3548482280
Short name T948
Test name
Test status
Simulation time 8249040301 ps
CPU time 9.42 seconds
Started Jul 24 05:05:30 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 233540 kb
Host smart-e4ad9d91-92c1-4a1b-b7c3-09efaec92e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548482280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3548482280
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1423059996
Short name T403
Test name
Test status
Simulation time 3412831694 ps
CPU time 10.14 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 223228 kb
Host smart-a5d34c21-ee05-4077-a04a-1f4425485e3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423059996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1423059996
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1027814681
Short name T826
Test name
Test status
Simulation time 57317555 ps
CPU time 1.16 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 207952 kb
Host smart-f2a33127-e485-4b3b-a072-ddb6cb726dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027814681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1027814681
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3073032578
Short name T621
Test name
Test status
Simulation time 13021987643 ps
CPU time 20.97 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 217184 kb
Host smart-5f5543d4-6a45-4864-a1f3-0a1eb20d372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073032578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3073032578
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3186924051
Short name T687
Test name
Test status
Simulation time 3649615411 ps
CPU time 10.19 seconds
Started Jul 24 05:05:35 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 217140 kb
Host smart-760592a5-5040-42a7-a830-b7d3e9b4151c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186924051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3186924051
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3635673656
Short name T624
Test name
Test status
Simulation time 370591628 ps
CPU time 0.99 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 208080 kb
Host smart-145431ea-fd83-4da2-89c2-f6cb7c3ee42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635673656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3635673656
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3971525096
Short name T489
Test name
Test status
Simulation time 49082174 ps
CPU time 0.76 seconds
Started Jul 24 05:05:30 PM PDT 24
Finished Jul 24 05:05:31 PM PDT 24
Peak memory 206760 kb
Host smart-0db5dd83-361a-48d3-9f23-3117ef887fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971525096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3971525096
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.141763875
Short name T493
Test name
Test status
Simulation time 2668476042 ps
CPU time 4.44 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 233704 kb
Host smart-06021c6f-dde1-4c2a-bf7d-947a5d9b3ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141763875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.141763875
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4289475453
Short name T62
Test name
Test status
Simulation time 12364059 ps
CPU time 0.72 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 205476 kb
Host smart-4f8a5a0e-560a-41fd-ac5f-d2fd69f63f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289475453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4289475453
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.39989004
Short name T177
Test name
Test status
Simulation time 46167244 ps
CPU time 2.23 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 225456 kb
Host smart-3f338456-c383-4da5-9a28-5aae4884c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39989004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.39989004
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3630623052
Short name T333
Test name
Test status
Simulation time 18026788 ps
CPU time 0.76 seconds
Started Jul 24 05:05:18 PM PDT 24
Finished Jul 24 05:05:19 PM PDT 24
Peak memory 207156 kb
Host smart-c1e93144-2fd8-4c2c-94a3-2933e7484cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630623052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3630623052
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2252043179
Short name T947
Test name
Test status
Simulation time 5882503657 ps
CPU time 21.57 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 250108 kb
Host smart-ef23cc2d-0daf-4e0d-b206-1c4a948cb366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252043179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2252043179
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.1772588398
Short name T57
Test name
Test status
Simulation time 71453055124 ps
CPU time 196.68 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:08:55 PM PDT 24
Peak memory 253264 kb
Host smart-71a18f47-e40f-4e4c-aece-c228e7dcd7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772588398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.1772588398
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.374772398
Short name T838
Test name
Test status
Simulation time 105280182 ps
CPU time 3.05 seconds
Started Jul 24 05:05:54 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 233508 kb
Host smart-28e7f52d-8b46-4aab-abec-97a68eaa4178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374772398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.374772398
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.925358547
Short name T166
Test name
Test status
Simulation time 4915088891 ps
CPU time 57.63 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 255032 kb
Host smart-8d0447eb-792f-46b3-9fbd-2191485dd5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925358547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.925358547
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3180213341
Short name T909
Test name
Test status
Simulation time 2660916140 ps
CPU time 8.16 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 233684 kb
Host smart-c7852703-4345-453e-8a61-e4872d7762c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180213341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3180213341
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3757458828
Short name T409
Test name
Test status
Simulation time 4098978144 ps
CPU time 30.31 seconds
Started Jul 24 05:05:26 PM PDT 24
Finished Jul 24 05:05:56 PM PDT 24
Peak memory 225528 kb
Host smart-57f858c9-713d-4949-a5a9-9f1bbfc7fdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757458828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3757458828
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1652706301
Short name T556
Test name
Test status
Simulation time 491676405 ps
CPU time 2.11 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 225016 kb
Host smart-4aa1a16f-443a-4e6f-8afb-2a9a5f18e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652706301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1652706301
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.901413261
Short name T600
Test name
Test status
Simulation time 1744615988 ps
CPU time 8.85 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 241352 kb
Host smart-43e2feb0-00f3-4d7b-8dba-7ff4795b9e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901413261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.901413261
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1357522922
Short name T356
Test name
Test status
Simulation time 5312516855 ps
CPU time 13.65 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 220220 kb
Host smart-2ce69421-603b-4b61-9a0b-1905d7884293
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1357522922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1357522922
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3161453821
Short name T400
Test name
Test status
Simulation time 224411895 ps
CPU time 1.11 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 207644 kb
Host smart-541e141a-a110-4b28-ad34-00eb777edadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161453821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3161453821
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3263873349
Short name T818
Test name
Test status
Simulation time 42963377015 ps
CPU time 22.34 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:54 PM PDT 24
Peak memory 217236 kb
Host smart-43741fbb-4ec1-4c36-8283-8fa511c24e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263873349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3263873349
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3257516712
Short name T729
Test name
Test status
Simulation time 777370725 ps
CPU time 3.7 seconds
Started Jul 24 05:05:22 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 217184 kb
Host smart-878e376d-a1a6-4a1a-a8e8-9b1cb3097d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257516712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3257516712
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4276359685
Short name T378
Test name
Test status
Simulation time 2913300735 ps
CPU time 5.52 seconds
Started Jul 24 05:05:33 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 217260 kb
Host smart-3047b2a1-67a7-4b62-bb95-8ab635ff65e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276359685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4276359685
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_upload.3927858020
Short name T807
Test name
Test status
Simulation time 195716016 ps
CPU time 2.05 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 224968 kb
Host smart-8544922d-1bf7-4550-a2b3-8f32af35519a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927858020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3927858020
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.141509715
Short name T367
Test name
Test status
Simulation time 23400977 ps
CPU time 0.68 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 205520 kb
Host smart-77eec5a5-a5b2-45c7-817d-4022eac6ab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141509715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.141509715
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2841966706
Short name T431
Test name
Test status
Simulation time 98910550 ps
CPU time 3.08 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 225316 kb
Host smart-77671baa-fc0f-4bb0-9064-07613a976815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841966706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2841966706
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2183519913
Short name T467
Test name
Test status
Simulation time 15883662 ps
CPU time 0.75 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 207284 kb
Host smart-070d0ab5-49b3-4632-a2b7-61c54e03629f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183519913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2183519913
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2378965043
Short name T1020
Test name
Test status
Simulation time 11573837012 ps
CPU time 46.51 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 241928 kb
Host smart-4bb50fbc-a4fb-49e1-8e62-a14286feb9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378965043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2378965043
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2484670041
Short name T196
Test name
Test status
Simulation time 79315367976 ps
CPU time 160.77 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:08:05 PM PDT 24
Peak memory 252056 kb
Host smart-1838fed5-d498-4b4d-9c04-66303edd9154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484670041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2484670041
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3100633022
Short name T617
Test name
Test status
Simulation time 55774895425 ps
CPU time 194.57 seconds
Started Jul 24 05:05:59 PM PDT 24
Finished Jul 24 05:09:14 PM PDT 24
Peak memory 274052 kb
Host smart-aeaf60bb-8d85-4ed6-8dff-48d5092f1c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100633022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3100633022
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1840100395
Short name T482
Test name
Test status
Simulation time 97084239 ps
CPU time 2.43 seconds
Started Jul 24 05:05:24 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 225424 kb
Host smart-ba1a113f-0db3-4d06-9071-5a6aec9fae28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840100395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1840100395
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1795648364
Short name T198
Test name
Test status
Simulation time 15666073372 ps
CPU time 107.26 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 267664 kb
Host smart-969d17e8-984a-4602-92aa-272d0e3c29ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795648364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1795648364
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2871356499
Short name T59
Test name
Test status
Simulation time 4642065348 ps
CPU time 13.03 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:54 PM PDT 24
Peak memory 225508 kb
Host smart-95658060-b59f-4117-87de-99f0ac89c1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871356499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2871356499
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.291251383
Short name T783
Test name
Test status
Simulation time 10932328384 ps
CPU time 19.52 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 233652 kb
Host smart-6f452f1a-d819-4683-85c2-1c197eb06841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291251383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.291251383
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2410446088
Short name T321
Test name
Test status
Simulation time 769260371 ps
CPU time 2.15 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:40 PM PDT 24
Peak memory 224984 kb
Host smart-dc3a96f9-fc28-4688-920d-2a6484fbf032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410446088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2410446088
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2644609593
Short name T483
Test name
Test status
Simulation time 70275985 ps
CPU time 2.37 seconds
Started Jul 24 05:05:36 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 233364 kb
Host smart-53704c5c-adc6-43d6-9133-4f043efd293c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644609593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2644609593
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.4122798036
Short name T793
Test name
Test status
Simulation time 1929416190 ps
CPU time 14.8 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:06:02 PM PDT 24
Peak memory 219776 kb
Host smart-f432f44c-312e-4f3d-be68-3b04554441e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4122798036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.4122798036
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1498811932
Short name T758
Test name
Test status
Simulation time 22554408775 ps
CPU time 82.41 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:07:26 PM PDT 24
Peak memory 242012 kb
Host smart-708f69b6-49a8-4e83-bd96-0b4f4b051442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498811932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1498811932
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3976802433
Short name T396
Test name
Test status
Simulation time 474467314 ps
CPU time 4.18 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 217152 kb
Host smart-b3301cb2-62f7-4373-ba0a-a509d4747555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976802433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3976802433
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.179883173
Short name T885
Test name
Test status
Simulation time 643377157 ps
CPU time 1.89 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 207860 kb
Host smart-b1206762-f1e5-45cc-9592-47a12e8b0d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179883173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.179883173
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2300766788
Short name T986
Test name
Test status
Simulation time 57349582 ps
CPU time 0.73 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 206244 kb
Host smart-213339ec-5eca-4384-bcf1-aa6fa40010d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300766788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2300766788
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4175480636
Short name T572
Test name
Test status
Simulation time 16390117 ps
CPU time 0.72 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 206816 kb
Host smart-a45ea1b6-6098-4562-bead-05724a4cb084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175480636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4175480636
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4121172201
Short name T765
Test name
Test status
Simulation time 3482166083 ps
CPU time 8.03 seconds
Started Jul 24 05:05:22 PM PDT 24
Finished Jul 24 05:05:35 PM PDT 24
Peak memory 233564 kb
Host smart-2bc58349-a1cb-4b4e-82e5-42791df10005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121172201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4121172201
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2030451965
Short name T383
Test name
Test status
Simulation time 20880555 ps
CPU time 0.69 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 206352 kb
Host smart-193aa475-b8af-4763-82c5-dea965b020e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030451965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2030451965
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2526030280
Short name T254
Test name
Test status
Simulation time 6176488364 ps
CPU time 11.1 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 233520 kb
Host smart-bf21d5bb-865a-4ed0-aff5-15e9d219aeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526030280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2526030280
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1209443670
Short name T963
Test name
Test status
Simulation time 20355420 ps
CPU time 0.79 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:40 PM PDT 24
Peak memory 207536 kb
Host smart-a1b41c19-a735-4063-b8c2-373b179d60c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209443670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1209443670
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1287227689
Short name T344
Test name
Test status
Simulation time 49956772505 ps
CPU time 99.89 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 258184 kb
Host smart-63a6dd67-1655-41ba-b7b4-f175266f0e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287227689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1287227689
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3108442842
Short name T210
Test name
Test status
Simulation time 4894232060 ps
CPU time 69.19 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 250152 kb
Host smart-39184dcf-e801-4fcb-bdd0-c10f1e0e45c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108442842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3108442842
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.277457869
Short name T803
Test name
Test status
Simulation time 89679703272 ps
CPU time 208.34 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:09:33 PM PDT 24
Peak memory 250120 kb
Host smart-e5821c79-6ea7-4cd5-9bba-bb3d464198ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277457869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.277457869
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.287781778
Short name T618
Test name
Test status
Simulation time 49913872 ps
CPU time 3.12 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 233680 kb
Host smart-d81343fd-5d95-4726-a2ca-631b989a9091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287781778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.287781778
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2773479847
Short name T929
Test name
Test status
Simulation time 29093047989 ps
CPU time 115.82 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:07:34 PM PDT 24
Peak memory 254536 kb
Host smart-f22a3c1d-5aa3-456b-8ed1-aa0b9599e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773479847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2773479847
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.977285506
Short name T830
Test name
Test status
Simulation time 6340582792 ps
CPU time 10.95 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 233604 kb
Host smart-83f13404-b9f7-4fd4-9ef6-4dbcc397721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977285506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.977285506
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3620115379
Short name T771
Test name
Test status
Simulation time 224313826 ps
CPU time 4.77 seconds
Started Jul 24 05:05:21 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 225436 kb
Host smart-8c80f86d-a386-4a18-9c34-fa6fa427e25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620115379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3620115379
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1444529196
Short name T293
Test name
Test status
Simulation time 15686580663 ps
CPU time 12.21 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 233796 kb
Host smart-1c64234e-4ba4-4c00-8be2-c10fcd81f156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444529196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1444529196
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2503267554
Short name T246
Test name
Test status
Simulation time 12488888581 ps
CPU time 15.21 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 225572 kb
Host smart-6fd2bed7-095d-4e74-aede-8ba052569d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503267554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2503267554
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.633833007
Short name T768
Test name
Test status
Simulation time 359472535 ps
CPU time 3.34 seconds
Started Jul 24 05:05:28 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 223576 kb
Host smart-75425e49-8fd3-4e00-aa0e-8f02e47dfa54
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=633833007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.633833007
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1479979715
Short name T1013
Test name
Test status
Simulation time 345862308874 ps
CPU time 926.61 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:21:08 PM PDT 24
Peak memory 299532 kb
Host smart-608131c3-fe64-4186-b381-d696b5c2b3f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479979715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1479979715
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2263260687
Short name T537
Test name
Test status
Simulation time 1615769293 ps
CPU time 19.51 seconds
Started Jul 24 05:05:29 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 217436 kb
Host smart-29d39056-7523-40d2-8cb5-ec54a871d0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263260687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2263260687
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.838387345
Short name T544
Test name
Test status
Simulation time 1324172002 ps
CPU time 4.4 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 217172 kb
Host smart-943d6e27-312a-4708-a345-6febded9ed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838387345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.838387345
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2127559460
Short name T377
Test name
Test status
Simulation time 136290565 ps
CPU time 1.43 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 217152 kb
Host smart-e5d553be-9f75-4a93-9d81-9daa80bcd580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127559460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2127559460
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.30589672
Short name T823
Test name
Test status
Simulation time 126433102 ps
CPU time 0.77 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:32 PM PDT 24
Peak memory 206772 kb
Host smart-66532ec8-cf2a-4e50-9640-107fa2dc5897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30589672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.30589672
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.4246220582
Short name T479
Test name
Test status
Simulation time 172631246 ps
CPU time 3.94 seconds
Started Jul 24 05:05:17 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 233472 kb
Host smart-e9efddd0-3999-4c1e-a015-f1bc33238b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246220582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4246220582
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.950295093
Short name T979
Test name
Test status
Simulation time 33507795 ps
CPU time 0.74 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 206060 kb
Host smart-e9c7ad2f-b74c-4a08-afdd-81233eae25f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950295093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.950295093
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.364656819
Short name T764
Test name
Test status
Simulation time 51223498 ps
CPU time 2.82 seconds
Started Jul 24 05:05:30 PM PDT 24
Finished Jul 24 05:05:33 PM PDT 24
Peak memory 233652 kb
Host smart-f9967973-d1b6-42b5-bc44-8cd3da16cae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364656819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.364656819
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.967369646
Short name T850
Test name
Test status
Simulation time 26823044 ps
CPU time 0.82 seconds
Started Jul 24 05:05:22 PM PDT 24
Finished Jul 24 05:05:23 PM PDT 24
Peak memory 207144 kb
Host smart-2efe3bf8-f3e7-4352-af1e-94f43c54002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967369646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.967369646
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3044013350
Short name T353
Test name
Test status
Simulation time 13166952 ps
CPU time 0.73 seconds
Started Jul 24 05:05:38 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 216556 kb
Host smart-1ab9c278-c11d-4fd8-88e7-c31bd4aa04bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044013350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3044013350
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4220655485
Short name T635
Test name
Test status
Simulation time 206116997831 ps
CPU time 74.33 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 242328 kb
Host smart-848c668e-aed9-4cd5-9c8c-ff086dd96ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220655485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4220655485
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2453410850
Short name T897
Test name
Test status
Simulation time 21146498157 ps
CPU time 39.31 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 225400 kb
Host smart-cdda4a2d-3d59-4307-8129-0d4666dc4fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453410850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2453410850
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1075148311
Short name T418
Test name
Test status
Simulation time 70123736 ps
CPU time 3.32 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 233620 kb
Host smart-cb18bac3-b177-4803-bc41-fda3e723d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075148311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1075148311
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2202437912
Short name T287
Test name
Test status
Simulation time 300372029759 ps
CPU time 196.48 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:09:00 PM PDT 24
Peak memory 250032 kb
Host smart-7e1dbfa2-cea7-4df2-96f5-e0286b2f00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202437912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2202437912
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1697475287
Short name T1019
Test name
Test status
Simulation time 2251576843 ps
CPU time 8.06 seconds
Started Jul 24 05:05:30 PM PDT 24
Finished Jul 24 05:05:39 PM PDT 24
Peak memory 233676 kb
Host smart-dc260671-8846-4f09-a167-fb8fdc9d797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697475287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1697475287
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.160749578
Short name T518
Test name
Test status
Simulation time 17229668073 ps
CPU time 20.2 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 241892 kb
Host smart-f94a6cfb-8c96-46c0-95c8-e73d04807f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160749578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.160749578
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.202841807
Short name T711
Test name
Test status
Simulation time 31819578638 ps
CPU time 40.58 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 233748 kb
Host smart-c0dbf445-fe5b-443f-a2e2-b57793746af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202841807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.202841807
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4077965446
Short name T876
Test name
Test status
Simulation time 707676962 ps
CPU time 6.94 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 241396 kb
Host smart-4fd4caa0-b911-4198-bf03-0092ed588798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077965446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4077965446
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3154742303
Short name T40
Test name
Test status
Simulation time 556861873 ps
CPU time 5.09 seconds
Started Jul 24 05:05:35 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 219892 kb
Host smart-bcf4d913-51ad-4ec1-8005-b5cd22de9c87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3154742303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3154742303
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2711613846
Short name T677
Test name
Test status
Simulation time 378981879760 ps
CPU time 356.57 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:11:44 PM PDT 24
Peak memory 284532 kb
Host smart-8cbd6d42-0b55-4673-b688-25138d8f1f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711613846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2711613846
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4168329125
Short name T546
Test name
Test status
Simulation time 3458371179 ps
CPU time 11.36 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 217136 kb
Host smart-182d6f21-774f-4a40-9f15-f5e32453fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168329125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4168329125
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3624203643
Short name T640
Test name
Test status
Simulation time 13363704915 ps
CPU time 10.78 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 217316 kb
Host smart-cb56c239-cc38-4433-9470-af81560ad546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624203643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3624203643
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3278475689
Short name T966
Test name
Test status
Simulation time 101935240 ps
CPU time 1.28 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 217180 kb
Host smart-9fb13f59-f362-45ed-874c-878406b8dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278475689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3278475689
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2807482156
Short name T580
Test name
Test status
Simulation time 203292417 ps
CPU time 0.86 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 206808 kb
Host smart-734ca5a0-3bf7-4325-b23c-79b57c2b6c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807482156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2807482156
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1358780025
Short name T741
Test name
Test status
Simulation time 1136668004 ps
CPU time 2.78 seconds
Started Jul 24 05:05:26 PM PDT 24
Finished Jul 24 05:05:29 PM PDT 24
Peak memory 225512 kb
Host smart-60e14046-2e8a-43ad-8ee2-97eb5197c4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358780025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1358780025
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.236194222
Short name T343
Test name
Test status
Simulation time 59847456 ps
CPU time 0.69 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 206396 kb
Host smart-444ba4ac-ec90-4363-8cc5-d0f69aff4314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236194222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.236194222
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.569276761
Short name T386
Test name
Test status
Simulation time 330221513 ps
CPU time 2.58 seconds
Started Jul 24 05:05:35 PM PDT 24
Finished Jul 24 05:05:38 PM PDT 24
Peak memory 233484 kb
Host smart-69ebc3ac-3505-44f6-a722-7ddd9b371eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569276761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.569276761
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1500346372
Short name T433
Test name
Test status
Simulation time 58074251 ps
CPU time 0.78 seconds
Started Jul 24 05:05:56 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 207204 kb
Host smart-d3e1c4f2-0c44-4d1c-9840-558b2771c991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500346372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1500346372
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3373482073
Short name T206
Test name
Test status
Simulation time 6105768996 ps
CPU time 87.32 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 264336 kb
Host smart-d48d0483-695c-4385-8e9b-bb5b7ff70f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373482073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3373482073
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.962692177
Short name T294
Test name
Test status
Simulation time 63137233443 ps
CPU time 626.51 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:16:11 PM PDT 24
Peak memory 253544 kb
Host smart-ad5df1ff-bbbc-4267-964f-835636a0bd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962692177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.962692177
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1124938634
Short name T306
Test name
Test status
Simulation time 16848203910 ps
CPU time 167.09 seconds
Started Jul 24 05:05:37 PM PDT 24
Finished Jul 24 05:08:24 PM PDT 24
Peak memory 256200 kb
Host smart-2e65ca64-97d2-46a9-808d-9e59655e42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124938634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1124938634
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4073139283
Short name T877
Test name
Test status
Simulation time 409742002 ps
CPU time 2.87 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 225336 kb
Host smart-aa8f22c5-fb5e-474f-91aa-b61dfae2032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073139283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4073139283
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1551050710
Short name T531
Test name
Test status
Simulation time 32491080395 ps
CPU time 224.16 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:09:27 PM PDT 24
Peak memory 258456 kb
Host smart-61c4b4fd-1988-447b-acce-22a2efc9a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551050710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1551050710
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4253065167
Short name T825
Test name
Test status
Simulation time 30765871 ps
CPU time 2.55 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 228932 kb
Host smart-88c4eb52-c458-4857-b7b7-f06bf9aac55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253065167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4253065167
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.736401795
Short name T959
Test name
Test status
Simulation time 21768888059 ps
CPU time 47.13 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 241776 kb
Host smart-7df886e0-6a43-43f1-9ef2-cb190d633db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736401795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.736401795
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.995632317
Short name T1005
Test name
Test status
Simulation time 449315633 ps
CPU time 8.73 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 240640 kb
Host smart-cfdcbd7f-a4b3-4086-bd48-87f70f6f345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995632317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.995632317
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3016950423
Short name T267
Test name
Test status
Simulation time 1067007757 ps
CPU time 7.44 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 241564 kb
Host smart-bec0ddae-fa4e-4db8-bc17-cd0566cf3d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016950423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3016950423
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2717906150
Short name T1004
Test name
Test status
Simulation time 1556160695 ps
CPU time 10.85 seconds
Started Jul 24 05:05:35 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 220524 kb
Host smart-9cc9ae04-836f-43a5-aa54-7f237fcb25b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717906150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2717906150
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.942977341
Short name T861
Test name
Test status
Simulation time 2357556304 ps
CPU time 22.9 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:06:18 PM PDT 24
Peak memory 217480 kb
Host smart-d7f89928-4ccb-44fe-beba-3cbc477c5704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942977341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.942977341
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3922118851
Short name T688
Test name
Test status
Simulation time 4780419085 ps
CPU time 7.71 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 217164 kb
Host smart-c6ed465e-03a5-4c84-90a9-3b5fad7050ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922118851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3922118851
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.612623544
Short name T34
Test name
Test status
Simulation time 63528331 ps
CPU time 1.33 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:05:42 PM PDT 24
Peak memory 217240 kb
Host smart-569ff344-7cd0-4cfc-b4e4-93c212ffa5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612623544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.612623544
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3340660259
Short name T882
Test name
Test status
Simulation time 238795218 ps
CPU time 0.8 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 206772 kb
Host smart-95521e25-d971-4e94-867d-fa33b543db36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340660259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3340660259
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2790068460
Short name T480
Test name
Test status
Simulation time 126519771 ps
CPU time 2.19 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 225372 kb
Host smart-3ecab131-4d1f-424c-82e3-34af21e6e587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790068460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2790068460
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1314585430
Short name T666
Test name
Test status
Simulation time 12613924 ps
CPU time 0.7 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 206096 kb
Host smart-44b69037-6b1f-4366-aadd-f431bd3a5292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314585430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1314585430
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2487537236
Short name T505
Test name
Test status
Simulation time 833229250 ps
CPU time 6.71 seconds
Started Jul 24 05:05:31 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 233588 kb
Host smart-be8f6d25-20bc-49d4-a0df-4c03af4bebb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487537236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2487537236
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2928599134
Short name T436
Test name
Test status
Simulation time 16068186 ps
CPU time 0.82 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 206176 kb
Host smart-984525fd-53ee-462e-953a-caabbb8f520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928599134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2928599134
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2069699534
Short name T630
Test name
Test status
Simulation time 10825055 ps
CPU time 0.74 seconds
Started Jul 24 05:05:56 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 216580 kb
Host smart-1ab41bf1-2af6-42d6-b1f7-093ac1a32ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069699534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2069699534
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1669640681
Short name T304
Test name
Test status
Simulation time 5617398658 ps
CPU time 24.23 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 241928 kb
Host smart-a840bf1e-48f5-488a-8012-139fceb14965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669640681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1669640681
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2377808955
Short name T472
Test name
Test status
Simulation time 25233388977 ps
CPU time 35.47 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:06:25 PM PDT 24
Peak memory 225452 kb
Host smart-b2bd1d14-4240-4e9a-8108-bfe5b8bcbcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377808955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2377808955
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.932377475
Short name T713
Test name
Test status
Simulation time 198915585 ps
CPU time 2.63 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 225312 kb
Host smart-23941fe8-4b1c-412a-a7a2-1186f06f334e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932377475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.932377475
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2440592820
Short name T720
Test name
Test status
Simulation time 17078409946 ps
CPU time 27.04 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 225688 kb
Host smart-615cc650-deb6-4522-b8a9-9564a60ac938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440592820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2440592820
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.899013517
Short name T932
Test name
Test status
Simulation time 247378081 ps
CPU time 2.97 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 233608 kb
Host smart-e56321cc-452f-484b-847c-2c4f9a1fe81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899013517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.899013517
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3447024936
Short name T928
Test name
Test status
Simulation time 110788941 ps
CPU time 2.48 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 233316 kb
Host smart-fa8f4378-a01f-45de-8eb9-c6a919ac0bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447024936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3447024936
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3864066086
Short name T97
Test name
Test status
Simulation time 50631339 ps
CPU time 2.37 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 225388 kb
Host smart-25650c47-9ea0-4459-b1f1-e97ee9cd0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864066086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3864066086
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1748056840
Short name T669
Test name
Test status
Simulation time 246382352 ps
CPU time 3.44 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 233504 kb
Host smart-f17cafd8-a402-4758-b3e7-29bf4640fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748056840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1748056840
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2604754652
Short name T435
Test name
Test status
Simulation time 1539922368 ps
CPU time 8.73 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 220100 kb
Host smart-35b6bc06-5cc7-4733-87b7-79453a394be1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2604754652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2604754652
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2888566888
Short name T527
Test name
Test status
Simulation time 120673017 ps
CPU time 0.97 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:05:46 PM PDT 24
Peak memory 207320 kb
Host smart-bfc769c5-07d7-4056-be17-97a568da9cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888566888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2888566888
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.47560194
Short name T533
Test name
Test status
Simulation time 5423460746 ps
CPU time 15.38 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 217308 kb
Host smart-085a6604-b99e-4749-9cec-b10b23c80941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47560194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.47560194
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3775683591
Short name T962
Test name
Test status
Simulation time 1267673412 ps
CPU time 4.66 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:54 PM PDT 24
Peak memory 217124 kb
Host smart-3e35d26b-653f-49f2-a080-882e5808e6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775683591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3775683591
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1058552069
Short name T590
Test name
Test status
Simulation time 53894157 ps
CPU time 1.67 seconds
Started Jul 24 05:05:41 PM PDT 24
Finished Jul 24 05:05:43 PM PDT 24
Peak memory 217188 kb
Host smart-a2a3179f-6d6c-47b7-b4f4-4a8a40399a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058552069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1058552069
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.4066282251
Short name T450
Test name
Test status
Simulation time 43999511 ps
CPU time 0.82 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 206692 kb
Host smart-e2ef1f0f-3393-4a28-8556-cb4695e0c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066282251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.4066282251
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1966139524
Short name T223
Test name
Test status
Simulation time 3325486753 ps
CPU time 10.64 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:06:02 PM PDT 24
Peak memory 225424 kb
Host smart-75f99fc5-5e70-4fb8-8b13-5d67284d065a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966139524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1966139524
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1159005392
Short name T667
Test name
Test status
Simulation time 35319154 ps
CPU time 0.7 seconds
Started Jul 24 05:05:43 PM PDT 24
Finished Jul 24 05:05:44 PM PDT 24
Peak memory 206296 kb
Host smart-7f79e48e-ae63-4bb8-bd22-a0c92dc0f904
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159005392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1159005392
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2277944341
Short name T457
Test name
Test status
Simulation time 2493093550 ps
CPU time 6.34 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 225612 kb
Host smart-9ffb4934-4d98-4dd0-a581-abac9b5f0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277944341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2277944341
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.462628739
Short name T397
Test name
Test status
Simulation time 22158174 ps
CPU time 0.75 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 207160 kb
Host smart-da9b3fbf-c70c-406b-9f5e-57a15effb2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462628739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.462628739
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2387016565
Short name T236
Test name
Test status
Simulation time 12626297594 ps
CPU time 98.91 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:07:43 PM PDT 24
Peak memory 233640 kb
Host smart-dd8c48d9-036e-4e49-abd2-01e55a096585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387016565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2387016565
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2389425247
Short name T185
Test name
Test status
Simulation time 10753555105 ps
CPU time 87.09 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:07:09 PM PDT 24
Peak memory 256576 kb
Host smart-31890f82-1b13-4d0b-8474-e356d6fbf035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389425247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2389425247
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.58003095
Short name T201
Test name
Test status
Simulation time 120649167026 ps
CPU time 541.77 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:14:48 PM PDT 24
Peak memory 258020 kb
Host smart-c96a583d-e537-43b4-ac86-96d0f4249612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58003095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.58003095
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3160305894
Short name T954
Test name
Test status
Simulation time 194507471 ps
CPU time 4.89 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 233676 kb
Host smart-3ff23074-458b-43b5-b522-946dbfc2309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160305894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3160305894
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3530541340
Short name T332
Test name
Test status
Simulation time 57930496 ps
CPU time 0.75 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:48 PM PDT 24
Peak memory 216552 kb
Host smart-2d02a4f9-0516-4932-ab4a-35299f612c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530541340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3530541340
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1364252644
Short name T732
Test name
Test status
Simulation time 1062664227 ps
CPU time 10.58 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 233532 kb
Host smart-8b50062e-e1d5-4c64-bc14-f6cdcf630f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364252644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1364252644
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1377266664
Short name T191
Test name
Test status
Simulation time 5875009326 ps
CPU time 19.78 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 225468 kb
Host smart-c5505ffd-e17e-4ae6-b65f-a9664a591d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377266664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1377266664
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3596545160
Short name T988
Test name
Test status
Simulation time 8027574439 ps
CPU time 5.56 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 233672 kb
Host smart-bd4d75ad-5ea3-45bd-a4fa-808d05bbde61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596545160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3596545160
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1216017075
Short name T587
Test name
Test status
Simulation time 221453886 ps
CPU time 2.69 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 233504 kb
Host smart-42ec2ceb-317e-4b35-a4b8-1d5e6f23404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216017075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1216017075
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2341035308
Short name T643
Test name
Test status
Simulation time 995332459 ps
CPU time 5.63 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 224016 kb
Host smart-3e2bef5a-aaf3-4471-b107-212cbd2975f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2341035308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2341035308
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1286249053
Short name T451
Test name
Test status
Simulation time 170415992210 ps
CPU time 353.59 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:11:41 PM PDT 24
Peak memory 265328 kb
Host smart-d63d3afd-b48d-43cd-94e7-7776225163a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286249053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1286249053
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.429761193
Short name T30
Test name
Test status
Simulation time 2746903863 ps
CPU time 14.33 seconds
Started Jul 24 05:05:32 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 217228 kb
Host smart-ba15dc55-cac6-4db4-bc24-0574cfc607ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429761193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.429761193
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1804286577
Short name T936
Test name
Test status
Simulation time 423780344 ps
CPU time 3.29 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 217196 kb
Host smart-281b4eac-d70f-4773-a244-15e6ea7a5ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804286577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1804286577
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2585037291
Short name T447
Test name
Test status
Simulation time 39370262 ps
CPU time 1.11 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 208412 kb
Host smart-909b4d4e-defa-4790-8fb0-64d44362ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585037291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2585037291
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2483560696
Short name T364
Test name
Test status
Simulation time 161315258 ps
CPU time 0.87 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 206624 kb
Host smart-a7b00da2-c9cb-4788-837e-6574c6aa4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483560696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2483560696
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2793411566
Short name T64
Test name
Test status
Simulation time 13827831325 ps
CPU time 12.31 seconds
Started Jul 24 05:05:45 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 225324 kb
Host smart-be278e64-2105-4b16-8b80-03a6fa383c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793411566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2793411566
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3516363488
Short name T502
Test name
Test status
Simulation time 52647634 ps
CPU time 0.67 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:04:56 PM PDT 24
Peak memory 205400 kb
Host smart-8628993c-a208-484a-aaad-1d1bbb821846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516363488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
516363488
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3210498013
Short name T814
Test name
Test status
Simulation time 74884304 ps
CPU time 3.21 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:55 PM PDT 24
Peak memory 225392 kb
Host smart-26e00185-2d07-474c-a009-66678d7c24db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210498013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3210498013
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3812189708
Short name T29
Test name
Test status
Simulation time 133624123 ps
CPU time 0.74 seconds
Started Jul 24 05:04:25 PM PDT 24
Finished Jul 24 05:04:26 PM PDT 24
Peak memory 206424 kb
Host smart-d3304663-98b4-4a14-85db-72abedff0d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812189708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3812189708
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3523986032
Short name T452
Test name
Test status
Simulation time 6368787455 ps
CPU time 23.86 seconds
Started Jul 24 05:04:37 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 221444 kb
Host smart-51d81290-84e1-467a-8d8e-44b451962370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523986032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3523986032
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2042518362
Short name T884
Test name
Test status
Simulation time 38963423613 ps
CPU time 164.62 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:07:34 PM PDT 24
Peak memory 251184 kb
Host smart-72babce4-ef32-4843-9691-2a31e22c30bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042518362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2042518362
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3227749767
Short name T296
Test name
Test status
Simulation time 4624159858 ps
CPU time 20.77 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 225432 kb
Host smart-1073539d-1e65-4c3e-890a-6371f21ea341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227749767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3227749767
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2255531312
Short name T833
Test name
Test status
Simulation time 6092755613 ps
CPU time 26.77 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 225448 kb
Host smart-f14c1b0f-72ae-417b-a1e4-5e624830e3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255531312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2255531312
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2918939614
Short name T42
Test name
Test status
Simulation time 4958163068 ps
CPU time 27.22 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 225436 kb
Host smart-125ea552-6d1d-412f-b873-9adc4dca0138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918939614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2918939614
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2280410919
Short name T699
Test name
Test status
Simulation time 18769145874 ps
CPU time 80.88 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 240172 kb
Host smart-3df9d31c-3827-4eb9-946e-d15be12bc0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280410919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2280410919
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1279572532
Short name T841
Test name
Test status
Simulation time 6953384932 ps
CPU time 24.66 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 233648 kb
Host smart-3b111526-3115-487b-bcce-03e42fe69211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279572532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1279572532
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1525941178
Short name T693
Test name
Test status
Simulation time 11911915663 ps
CPU time 13.51 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 240120 kb
Host smart-82ff7859-cf52-4133-8732-7df875799d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525941178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1525941178
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2615271930
Short name T510
Test name
Test status
Simulation time 955994202 ps
CPU time 8.89 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:04:51 PM PDT 24
Peak memory 223216 kb
Host smart-93e07a5c-81aa-4593-acd8-d6a62570a431
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2615271930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2615271930
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.204942709
Short name T72
Test name
Test status
Simulation time 60947179 ps
CPU time 1.07 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 235976 kb
Host smart-8bcbc5e5-9b49-46ae-bda1-a45179e07157
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204942709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.204942709
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3940216106
Short name T788
Test name
Test status
Simulation time 3989936108 ps
CPU time 99.68 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 269236 kb
Host smart-ab32c979-2ae8-4e0e-a426-b2827345e076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940216106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3940216106
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1196186160
Short name T983
Test name
Test status
Simulation time 788904834 ps
CPU time 6.13 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 220028 kb
Host smart-9bbce452-6050-404c-b397-1735053f7fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196186160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1196186160
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3485551035
Short name T352
Test name
Test status
Simulation time 20907738515 ps
CPU time 26.65 seconds
Started Jul 24 05:04:36 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 217228 kb
Host smart-f39a4ea2-9d42-4cac-a708-7b75fda68637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485551035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3485551035
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3709952399
Short name T562
Test name
Test status
Simulation time 1050866604 ps
CPU time 9.38 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 217188 kb
Host smart-3f0e4f89-0290-4e13-bd04-d3da68a429d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709952399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3709952399
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3467133358
Short name T996
Test name
Test status
Simulation time 248238230 ps
CPU time 0.84 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 206716 kb
Host smart-ed41b9b3-f86c-407a-8b6a-c0dd3bf17120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467133358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3467133358
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3586907139
Short name T981
Test name
Test status
Simulation time 12545362636 ps
CPU time 14.6 seconds
Started Jul 24 05:04:24 PM PDT 24
Finished Jul 24 05:04:39 PM PDT 24
Peak memory 241932 kb
Host smart-a5ad2a1e-c8b9-40c1-b5cf-9b0f5705c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586907139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3586907139
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3723490233
Short name T770
Test name
Test status
Simulation time 34813742 ps
CPU time 0.72 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 206092 kb
Host smart-7e82da79-6c9a-4863-a914-c96bf902f063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723490233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3723490233
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1298267884
Short name T519
Test name
Test status
Simulation time 106991050 ps
CPU time 2.33 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 225484 kb
Host smart-397cb468-3f7c-4c75-a3a8-e55ac1086391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298267884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1298267884
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3386179215
Short name T317
Test name
Test status
Simulation time 147198529 ps
CPU time 0.81 seconds
Started Jul 24 05:05:50 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 206504 kb
Host smart-cd9eabf9-54ed-42fa-9af9-1cea4c7b8c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386179215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3386179215
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1214543991
Short name T926
Test name
Test status
Simulation time 10857349606 ps
CPU time 134.13 seconds
Started Jul 24 05:05:39 PM PDT 24
Finished Jul 24 05:07:53 PM PDT 24
Peak memory 258348 kb
Host smart-dbfa2029-50cc-4605-98f4-22ef849907c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214543991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1214543991
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1091165297
Short name T638
Test name
Test status
Simulation time 13630333843 ps
CPU time 47.34 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 241784 kb
Host smart-ed2cd158-b140-4dad-b61e-8e4a81edad6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091165297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1091165297
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1937681970
Short name T454
Test name
Test status
Simulation time 9133829747 ps
CPU time 50.81 seconds
Started Jul 24 05:05:57 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 250092 kb
Host smart-9d913a74-fef6-4a4e-8653-0b2b98652072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937681970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1937681970
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2142420596
Short name T189
Test name
Test status
Simulation time 679811825 ps
CPU time 7.27 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 230356 kb
Host smart-dfa31267-4892-4e96-b8d2-9747ab87441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142420596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2142420596
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.225585903
Short name T559
Test name
Test status
Simulation time 46416940873 ps
CPU time 101.97 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 234704 kb
Host smart-cb36a520-c64c-4dab-96d4-8f3325ae7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225585903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.225585903
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3811390915
Short name T45
Test name
Test status
Simulation time 1860683006 ps
CPU time 5.19 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 225428 kb
Host smart-2a778a99-becc-44d8-bab6-f000081d71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811390915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3811390915
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2784712694
Short name T794
Test name
Test status
Simulation time 2282401742 ps
CPU time 5.41 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 225432 kb
Host smart-26c268c0-5172-426f-b46f-6a26354da92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784712694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2784712694
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1039454468
Short name T151
Test name
Test status
Simulation time 5339703958 ps
CPU time 13.43 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 219840 kb
Host smart-acda401c-3fa7-4776-bb69-c6558b4b172e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1039454468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1039454468
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3303059173
Short name T790
Test name
Test status
Simulation time 35117951768 ps
CPU time 90.46 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:07:22 PM PDT 24
Peak memory 241976 kb
Host smart-599e1925-c3ab-425e-8acd-50f9d12326d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303059173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3303059173
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2577849575
Short name T543
Test name
Test status
Simulation time 18676896815 ps
CPU time 14.64 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 217124 kb
Host smart-36a1c35d-31c8-41ce-878f-077bce1d7644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577849575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2577849575
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1980113694
Short name T92
Test name
Test status
Simulation time 3347143614 ps
CPU time 3.46 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:05:56 PM PDT 24
Peak memory 217132 kb
Host smart-b9232218-e1d8-4876-988d-103db8ad3610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980113694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1980113694
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2892030938
Short name T867
Test name
Test status
Simulation time 17233208 ps
CPU time 0.76 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 206784 kb
Host smart-954709ac-0a2a-4e7a-b045-e6988dd9193d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892030938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2892030938
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2228383836
Short name T366
Test name
Test status
Simulation time 26261445 ps
CPU time 0.81 seconds
Started Jul 24 05:05:48 PM PDT 24
Finished Jul 24 05:05:49 PM PDT 24
Peak memory 206752 kb
Host smart-cad9e37f-cb5a-4d96-9575-8a0296c7ac85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228383836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2228383836
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1727680012
Short name T507
Test name
Test status
Simulation time 606282231 ps
CPU time 4.32 seconds
Started Jul 24 05:05:42 PM PDT 24
Finished Jul 24 05:05:47 PM PDT 24
Peak memory 225428 kb
Host smart-800bd75c-ff6d-497f-8a98-12cb32d91772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727680012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1727680012
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3976400376
Short name T639
Test name
Test status
Simulation time 30993095 ps
CPU time 0.71 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:05:56 PM PDT 24
Peak memory 206064 kb
Host smart-d81b230b-3378-422c-a310-aca5537fadf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976400376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3976400376
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.440586476
Short name T95
Test name
Test status
Simulation time 492438593 ps
CPU time 6.03 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:57 PM PDT 24
Peak memory 233504 kb
Host smart-ddfe384e-f893-4e4e-801c-9222daa2a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440586476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.440586476
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2799375271
Short name T973
Test name
Test status
Simulation time 40621862 ps
CPU time 0.79 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 207260 kb
Host smart-aad5b12a-9fed-46f5-bacc-de2ed2791329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799375271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2799375271
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1609003295
Short name T887
Test name
Test status
Simulation time 34731296 ps
CPU time 0.81 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 216668 kb
Host smart-bf73ad4e-6165-447c-b6bb-1261d2da80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609003295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1609003295
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4239336194
Short name T762
Test name
Test status
Simulation time 33187491138 ps
CPU time 314.89 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:11:07 PM PDT 24
Peak memory 260420 kb
Host smart-bcc933b8-f866-4aa1-baa4-91bf5b320a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239336194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4239336194
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2670236389
Short name T37
Test name
Test status
Simulation time 45454214907 ps
CPU time 72.46 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 263292 kb
Host smart-57e61d7a-0cb5-4da5-aa98-f5c4c5a603dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670236389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2670236389
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.390891533
Short name T588
Test name
Test status
Simulation time 300494762 ps
CPU time 7.22 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:01 PM PDT 24
Peak memory 225456 kb
Host smart-d4fc5bfa-0571-4339-9cc0-d691241ffce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390891533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.390891533
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2973795460
Short name T836
Test name
Test status
Simulation time 24566439402 ps
CPU time 52.05 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 257956 kb
Host smart-b2ba4be3-92ef-4281-9aee-c90104601b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973795460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2973795460
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3998474803
Short name T1008
Test name
Test status
Simulation time 645703358 ps
CPU time 5.83 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:56 PM PDT 24
Peak memory 225452 kb
Host smart-8e3454d9-b6bf-4c81-b504-19d879e9f765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998474803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3998474803
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2852079276
Short name T566
Test name
Test status
Simulation time 4114354800 ps
CPU time 17 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 241200 kb
Host smart-c71e3e73-bff2-4a8e-a99b-de13400281df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852079276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2852079276
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1157589990
Short name T863
Test name
Test status
Simulation time 10051199695 ps
CPU time 7.51 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:06:02 PM PDT 24
Peak memory 233676 kb
Host smart-9e5e575e-7c8c-4533-b6d2-c13925a4431d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157589990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1157589990
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1648485267
Short name T453
Test name
Test status
Simulation time 218348969 ps
CPU time 5.04 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:11 PM PDT 24
Peak memory 233524 kb
Host smart-5b603d97-984b-406d-9419-7925f89328d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648485267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1648485267
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4256376280
Short name T999
Test name
Test status
Simulation time 960417043 ps
CPU time 9.82 seconds
Started Jul 24 05:05:59 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 221140 kb
Host smart-cc180669-8880-4167-96f1-a66a22741d7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4256376280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4256376280
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4248979908
Short name T425
Test name
Test status
Simulation time 32173481685 ps
CPU time 71.55 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 255588 kb
Host smart-36fb7ffe-f863-4dae-bbc1-ae04a473addd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248979908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4248979908
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3906709767
Short name T302
Test name
Test status
Simulation time 657677090 ps
CPU time 6.23 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:06:01 PM PDT 24
Peak memory 217172 kb
Host smart-d3a49e12-3950-4598-afe6-811f11f10b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906709767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3906709767
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2114109550
Short name T737
Test name
Test status
Simulation time 7509215904 ps
CPU time 21.52 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 217148 kb
Host smart-9c5ea298-7e7d-47a8-8d7f-a29186ea2701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114109550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2114109550
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.251960195
Short name T312
Test name
Test status
Simulation time 974020554 ps
CPU time 2.57 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:51 PM PDT 24
Peak memory 217216 kb
Host smart-5dd5de6b-9d0d-46dd-8909-6aa28d1eeb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251960195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.251960195
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1980425686
Short name T989
Test name
Test status
Simulation time 96686583 ps
CPU time 0.81 seconds
Started Jul 24 05:05:44 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 206648 kb
Host smart-5523ce98-4f31-4819-bde2-42d23232bef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980425686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1980425686
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3164719294
Short name T977
Test name
Test status
Simulation time 15595896192 ps
CPU time 8.36 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:11 PM PDT 24
Peak memory 233676 kb
Host smart-c453816c-2d57-40c7-a8ef-27b9420da6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164719294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3164719294
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2560520895
Short name T326
Test name
Test status
Simulation time 20717273 ps
CPU time 0.7 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:02 PM PDT 24
Peak memory 206000 kb
Host smart-bb814755-4d31-4b25-b9e0-38da726380ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560520895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2560520895
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2833541857
Short name T700
Test name
Test status
Simulation time 2494636509 ps
CPU time 3.89 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 233680 kb
Host smart-a87d6acb-6d23-48a0-ae7e-086c2ce0ac2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833541857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2833541857
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1871971957
Short name T970
Test name
Test status
Simulation time 16191218 ps
CPU time 0.78 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 207488 kb
Host smart-2fdd095c-0eaf-42ce-907b-99fea32e7623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871971957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1871971957
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1366156308
Short name T953
Test name
Test status
Simulation time 585511601248 ps
CPU time 294.22 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:10:46 PM PDT 24
Peak memory 257716 kb
Host smart-066524b4-dd29-4a76-b54c-93de2720afc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366156308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1366156308
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3047262859
Short name T523
Test name
Test status
Simulation time 513291390 ps
CPU time 7.03 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 218428 kb
Host smart-b2358d22-69d6-401f-a9d8-71ca81b66359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047262859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3047262859
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3149556475
Short name T839
Test name
Test status
Simulation time 6198548569 ps
CPU time 21.03 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 249956 kb
Host smart-b87a7972-ccf5-4000-b725-ef119609f17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149556475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3149556475
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2840418714
Short name T295
Test name
Test status
Simulation time 13310630049 ps
CPU time 86.55 seconds
Started Jul 24 05:05:47 PM PDT 24
Finished Jul 24 05:07:14 PM PDT 24
Peak memory 241920 kb
Host smart-71c0ae89-d579-4bf2-ac59-78d59728121f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840418714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2840418714
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4147356656
Short name T605
Test name
Test status
Simulation time 7034942816 ps
CPU time 26.99 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:25 PM PDT 24
Peak memory 236032 kb
Host smart-c5da9f32-7f92-4fa3-ba37-b135a76b1fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147356656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4147356656
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2925559469
Short name T736
Test name
Test status
Simulation time 1842259623 ps
CPU time 11.84 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 225444 kb
Host smart-b1efcd35-2424-4149-a962-930343cfdc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925559469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2925559469
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1483506016
Short name T205
Test name
Test status
Simulation time 1091774122 ps
CPU time 12.83 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 236984 kb
Host smart-08b6da52-8df4-4213-89eb-7985837b4b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483506016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1483506016
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1422727613
Short name T940
Test name
Test status
Simulation time 3768654219 ps
CPU time 8.85 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:06:23 PM PDT 24
Peak memory 235836 kb
Host smart-200b7661-a418-4027-a0d6-63ad174a5b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422727613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1422727613
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4120823805
Short name T674
Test name
Test status
Simulation time 16698619227 ps
CPU time 15.14 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 238392 kb
Host smart-924e1e3b-3a8e-430c-a6d8-e1096bce567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120823805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4120823805
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2081987806
Short name T856
Test name
Test status
Simulation time 640759504 ps
CPU time 3.52 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 223212 kb
Host smart-8997abed-1088-4c55-8fcc-ee2fffcde627
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2081987806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2081987806
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3327458374
Short name T778
Test name
Test status
Simulation time 72766400 ps
CPU time 1.1 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 208504 kb
Host smart-904b980c-b077-4d0b-980d-fc6bc01362fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327458374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3327458374
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2114784339
Short name T673
Test name
Test status
Simulation time 15605897951 ps
CPU time 37.74 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 217228 kb
Host smart-a2446786-013e-448f-ac29-d759234677fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114784339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2114784339
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3532661687
Short name T363
Test name
Test status
Simulation time 6950937054 ps
CPU time 18.74 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 217140 kb
Host smart-53633ac9-9239-4a71-898c-48d10dd62e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532661687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3532661687
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.849599929
Short name T429
Test name
Test status
Simulation time 14976883 ps
CPU time 0.84 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 207372 kb
Host smart-d811e44c-e115-4bce-a34e-e303b4865503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849599929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.849599929
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.269206540
Short name T501
Test name
Test status
Simulation time 49898385 ps
CPU time 0.83 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:05:50 PM PDT 24
Peak memory 206668 kb
Host smart-811673c8-dc76-4d05-b863-3d02ef75317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269206540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.269206540
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3022749867
Short name T766
Test name
Test status
Simulation time 189528321 ps
CPU time 2.96 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 233520 kb
Host smart-694791c6-552a-4077-9602-e2c8f54349d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022749867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3022749867
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2424920312
Short name T323
Test name
Test status
Simulation time 26132951 ps
CPU time 0.74 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 206428 kb
Host smart-3e15c974-f572-421c-a253-407da7678b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424920312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2424920312
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1362296901
Short name T591
Test name
Test status
Simulation time 241494450 ps
CPU time 2.85 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 233672 kb
Host smart-713e89c0-6401-4341-af44-21940b607f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362296901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1362296901
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1103047792
Short name T625
Test name
Test status
Simulation time 17724862 ps
CPU time 0.76 seconds
Started Jul 24 05:06:16 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 207584 kb
Host smart-5d81cd0e-3360-481b-b69e-9120715e22b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103047792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1103047792
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3949729285
Short name T964
Test name
Test status
Simulation time 25725848406 ps
CPU time 20.09 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 239664 kb
Host smart-1ec32aa0-e562-42d0-ad5b-6af03fe6e8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949729285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3949729285
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1090870011
Short name T257
Test name
Test status
Simulation time 74983569428 ps
CPU time 378.45 seconds
Started Jul 24 05:05:49 PM PDT 24
Finished Jul 24 05:12:13 PM PDT 24
Peak memory 256924 kb
Host smart-f322876b-a134-4b6f-bc12-22371b64495d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090870011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1090870011
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1502555578
Short name T314
Test name
Test status
Simulation time 16626715286 ps
CPU time 70.21 seconds
Started Jul 24 05:06:12 PM PDT 24
Finished Jul 24 05:07:22 PM PDT 24
Peak memory 240948 kb
Host smart-b70ca40f-ded5-458c-9f7d-3c9f94c03b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502555578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1502555578
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.830248178
Short name T987
Test name
Test status
Simulation time 1182892371 ps
CPU time 19.21 seconds
Started Jul 24 05:05:52 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 241796 kb
Host smart-bc7fa1fd-9482-4592-a893-89d69b6475e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830248178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.830248178
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1444718208
Short name T752
Test name
Test status
Simulation time 14680145263 ps
CPU time 119.6 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:08:22 PM PDT 24
Peak memory 253564 kb
Host smart-8c1fb62d-04e4-4d29-bdf9-019d738b389c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444718208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1444718208
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3288036654
Short name T569
Test name
Test status
Simulation time 887806674 ps
CPU time 6.76 seconds
Started Jul 24 05:05:57 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 233684 kb
Host smart-81dc4169-ab38-4323-8394-da75162a1a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288036654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3288036654
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.98061824
Short name T980
Test name
Test status
Simulation time 8105612863 ps
CPU time 22.6 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 233732 kb
Host smart-de99cdc4-5abb-45e8-8483-551d4e59b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98061824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.98061824
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1341500032
Short name T610
Test name
Test status
Simulation time 1461869368 ps
CPU time 6.65 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 233640 kb
Host smart-04ffa56f-9480-4a39-a296-4cc11ca74eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341500032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1341500032
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.893063346
Short name T227
Test name
Test status
Simulation time 78933089777 ps
CPU time 22.13 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 234656 kb
Host smart-25664e68-c768-4212-8d61-43ec99cab543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893063346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.893063346
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.708301399
Short name T659
Test name
Test status
Simulation time 204302239 ps
CPU time 4.13 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 223964 kb
Host smart-6ffdb3cd-9120-4828-9e04-b998f3ba4385
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=708301399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.708301399
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4067007978
Short name T313
Test name
Test status
Simulation time 41818954368 ps
CPU time 18.26 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 217200 kb
Host smart-728c70fd-46b2-4687-8013-bea33f3f016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067007978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4067007978
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.859197364
Short name T756
Test name
Test status
Simulation time 8300598182 ps
CPU time 6.81 seconds
Started Jul 24 05:05:51 PM PDT 24
Finished Jul 24 05:05:58 PM PDT 24
Peak memory 217328 kb
Host smart-3151d38c-c16c-4c27-bc9d-813ad41b5bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859197364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.859197364
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1569256027
Short name T1012
Test name
Test status
Simulation time 89742447 ps
CPU time 1.26 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 209168 kb
Host smart-72a01ef2-6f83-4e4a-851f-94d13f09c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569256027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1569256027
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2854930173
Short name T1000
Test name
Test status
Simulation time 12677677 ps
CPU time 0.69 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 206192 kb
Host smart-86820a74-aedd-4bf0-8c06-ae23dd9533ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854930173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2854930173
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3157244320
Short name T800
Test name
Test status
Simulation time 50384810 ps
CPU time 2.16 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 225436 kb
Host smart-5d19717d-a5d4-4c82-88e1-608abdb866cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157244320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3157244320
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.111855131
Short name T134
Test name
Test status
Simulation time 13943490 ps
CPU time 0.72 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:02 PM PDT 24
Peak memory 206084 kb
Host smart-4eb29589-21da-4de5-a978-a846387e6f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111855131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.111855131
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2011450596
Short name T240
Test name
Test status
Simulation time 306151329 ps
CPU time 2.12 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:05 PM PDT 24
Peak memory 225496 kb
Host smart-c755a0b3-1a99-4e0e-ab58-cfdd0a0e1317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011450596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2011450596
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2192879996
Short name T949
Test name
Test status
Simulation time 62833855 ps
CPU time 0.72 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:08 PM PDT 24
Peak memory 206232 kb
Host smart-581ec625-9eac-480c-a741-8e54064db165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192879996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2192879996
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.756034204
Short name T280
Test name
Test status
Simulation time 12975566900 ps
CPU time 53.42 seconds
Started Jul 24 05:06:16 PM PDT 24
Finished Jul 24 05:07:10 PM PDT 24
Peak memory 249184 kb
Host smart-b334e065-86dc-4b2f-872f-08174d7225d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756034204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.756034204
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3067148406
Short name T707
Test name
Test status
Simulation time 9957674627 ps
CPU time 23.65 seconds
Started Jul 24 05:05:57 PM PDT 24
Finished Jul 24 05:06:21 PM PDT 24
Peak memory 233692 kb
Host smart-8fd1f5a7-6c05-4b04-acb2-2f0d7d5cc7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067148406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3067148406
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.926880872
Short name T200
Test name
Test status
Simulation time 22854982180 ps
CPU time 200.25 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 258192 kb
Host smart-8b303f84-3d81-4854-a211-67bb470d2ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926880872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.926880872
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4028926012
Short name T412
Test name
Test status
Simulation time 1770914693 ps
CPU time 23.45 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:21 PM PDT 24
Peak memory 230012 kb
Host smart-645dc52e-83c9-44a5-bdce-641cd7fe6173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028926012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4028926012
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.950651725
Short name T265
Test name
Test status
Simulation time 43760746240 ps
CPU time 197.17 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 256672 kb
Host smart-8a013466-7cab-445a-a10b-0cfa07ce236a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950651725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.950651725
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1177264293
Short name T266
Test name
Test status
Simulation time 15844912712 ps
CPU time 28.77 seconds
Started Jul 24 05:05:46 PM PDT 24
Finished Jul 24 05:06:16 PM PDT 24
Peak memory 233656 kb
Host smart-aeabb237-e728-4e69-b0dc-bc8ea2c7e302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177264293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1177264293
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3860075429
Short name T1024
Test name
Test status
Simulation time 7604294354 ps
CPU time 27.99 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 225552 kb
Host smart-2ad5b85c-9d88-4a3e-8bb6-97e17458b90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860075429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3860075429
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.546588539
Short name T402
Test name
Test status
Simulation time 16547814824 ps
CPU time 18.56 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 241328 kb
Host smart-d372c900-292d-425d-b214-2d7a88e03bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546588539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.546588539
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4120842255
Short name T994
Test name
Test status
Simulation time 9268495122 ps
CPU time 12.42 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 233624 kb
Host smart-2f1c102c-1959-4c74-9046-1920790424d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120842255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4120842255
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.389727849
Short name T348
Test name
Test status
Simulation time 845977106 ps
CPU time 4.4 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:05 PM PDT 24
Peak memory 219656 kb
Host smart-ec177391-35bc-42d1-a090-8191b2770e6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=389727849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.389727849
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1993516301
Short name T199
Test name
Test status
Simulation time 77059361449 ps
CPU time 700.87 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:17:54 PM PDT 24
Peak memory 258140 kb
Host smart-3cfe6c92-bebe-4b26-833d-19fe5a24b7d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993516301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1993516301
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2873851403
Short name T414
Test name
Test status
Simulation time 38062366110 ps
CPU time 24.15 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 217212 kb
Host smart-d10497fb-a7c0-437f-b7b4-3b3729eba49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873851403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2873851403
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4236690530
Short name T744
Test name
Test status
Simulation time 482487070 ps
CPU time 2.73 seconds
Started Jul 24 05:06:23 PM PDT 24
Finished Jul 24 05:06:26 PM PDT 24
Peak memory 217216 kb
Host smart-699c0714-429a-49b2-af0c-dd8b9611add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236690530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4236690530
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3601371195
Short name T598
Test name
Test status
Simulation time 138302446 ps
CPU time 5.55 seconds
Started Jul 24 05:05:54 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 217108 kb
Host smart-a71526c6-cf4e-4a26-8cd7-085619a48bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601371195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3601371195
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.906902545
Short name T922
Test name
Test status
Simulation time 91943674 ps
CPU time 0.84 seconds
Started Jul 24 05:06:23 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 206744 kb
Host smart-172ea143-c59c-4fb0-8bb2-20e8a784a733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906902545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.906902545
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2090732781
Short name T774
Test name
Test status
Simulation time 2166418882 ps
CPU time 4 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 241884 kb
Host smart-740ffb9f-4af1-4f18-85e1-8ecb2db4d9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090732781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2090732781
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3615423120
Short name T777
Test name
Test status
Simulation time 11912760 ps
CPU time 0.7 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 205380 kb
Host smart-243950f7-1006-4eda-a193-00402e0c7995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615423120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3615423120
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3532313158
Short name T517
Test name
Test status
Simulation time 368565370 ps
CPU time 4.74 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 225472 kb
Host smart-04643fb1-061e-4900-a8bf-82ca8c82076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532313158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3532313158
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1531897697
Short name T325
Test name
Test status
Simulation time 20536866 ps
CPU time 0.76 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 206156 kb
Host smart-cd2fef1d-f7cb-4bea-8e75-7fe3f121ef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531897697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1531897697
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3893317772
Short name T946
Test name
Test status
Simulation time 11199011601 ps
CPU time 107.11 seconds
Started Jul 24 05:06:15 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 262080 kb
Host smart-03053c31-94ba-4430-8599-9b827bc2c631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893317772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3893317772
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.4038577318
Short name T292
Test name
Test status
Simulation time 355133417456 ps
CPU time 424.25 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:13:08 PM PDT 24
Peak memory 253172 kb
Host smart-8916b85a-80c7-46da-a63b-2bc89dd095f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038577318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.4038577318
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2474196651
Short name T148
Test name
Test status
Simulation time 342172972 ps
CPU time 8.53 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 225256 kb
Host smart-274711ba-3798-48c6-bd43-26d948cb809a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474196651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2474196651
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3716992187
Short name T274
Test name
Test status
Simulation time 113936812168 ps
CPU time 229.56 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:09:54 PM PDT 24
Peak memory 250120 kb
Host smart-8c49f607-ffc6-4652-a0f7-a62cf22e594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716992187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3716992187
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.89078870
Short name T250
Test name
Test status
Simulation time 6840636490 ps
CPU time 12.91 seconds
Started Jul 24 05:05:59 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 233684 kb
Host smart-b01e36e7-d67a-44f3-90d9-0df71f66cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89078870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.89078870
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1345055651
Short name T733
Test name
Test status
Simulation time 3947468856 ps
CPU time 32.16 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:33 PM PDT 24
Peak memory 233684 kb
Host smart-0acdb182-4804-4192-8dfd-cfe62929f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345055651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1345055651
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4172552152
Short name T207
Test name
Test status
Simulation time 1218136824 ps
CPU time 2.86 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 225436 kb
Host smart-ce090f82-ec80-426d-9cc8-d18dbbb1833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172552152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4172552152
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4221288117
Short name T536
Test name
Test status
Simulation time 7283027216 ps
CPU time 7.23 seconds
Started Jul 24 05:05:53 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 233600 kb
Host smart-4dc5c909-40d7-433f-bbbf-451baff2c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221288117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4221288117
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.775021293
Short name T971
Test name
Test status
Simulation time 1100877166 ps
CPU time 8.43 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 222668 kb
Host smart-46f02d44-74e1-4e61-a62c-3de989b0d2d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=775021293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.775021293
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2980552596
Short name T160
Test name
Test status
Simulation time 5835573798 ps
CPU time 35.15 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 241768 kb
Host smart-4ff02123-b1fa-42f2-b27c-f04001f6fe7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980552596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2980552596
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3498910177
Short name T1007
Test name
Test status
Simulation time 6873430950 ps
CPU time 34.06 seconds
Started Jul 24 05:05:56 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 217132 kb
Host smart-3e4f3790-9950-43ea-b433-066a1722f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498910177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3498910177
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1682945968
Short name T368
Test name
Test status
Simulation time 10967276164 ps
CPU time 21.5 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 217308 kb
Host smart-a104c7c5-5a78-459a-b9d8-5b1f3f045b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682945968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1682945968
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3396553128
Short name T745
Test name
Test status
Simulation time 74374284 ps
CPU time 1.6 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 217188 kb
Host smart-d624602b-0f3e-4e92-a957-ccd300d51fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396553128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3396553128
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2461107247
Short name T694
Test name
Test status
Simulation time 109524387 ps
CPU time 1.02 seconds
Started Jul 24 05:05:58 PM PDT 24
Finished Jul 24 05:06:00 PM PDT 24
Peak memory 207760 kb
Host smart-407df6c5-ce3a-4269-9d97-ebc0eb4e675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461107247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2461107247
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3100446444
Short name T682
Test name
Test status
Simulation time 548109962 ps
CPU time 8.69 seconds
Started Jul 24 05:05:55 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 249956 kb
Host smart-aaf774d6-8fe5-4e64-9a16-0d3ff5c0576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100446444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3100446444
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3151504772
Short name T520
Test name
Test status
Simulation time 46261350 ps
CPU time 0.73 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 206080 kb
Host smart-a0cac47e-2d89-4bf3-9d8a-e687a2449d53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151504772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3151504772
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2257045932
Short name T849
Test name
Test status
Simulation time 484551100 ps
CPU time 2.62 seconds
Started Jul 24 05:06:11 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 225512 kb
Host smart-1f3bfb9a-3759-48d8-9e48-7c7bffa0a79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257045932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2257045932
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3507140414
Short name T490
Test name
Test status
Simulation time 28315520 ps
CPU time 0.72 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:01 PM PDT 24
Peak memory 207280 kb
Host smart-22a889cd-2b08-4902-8a3a-ba3ee6b64da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507140414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3507140414
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1626860088
Short name T277
Test name
Test status
Simulation time 2881759276 ps
CPU time 66.55 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 267592 kb
Host smart-bfde5feb-84c6-4acb-bdc0-983339c18025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626860088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1626860088
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3106591497
Short name T132
Test name
Test status
Simulation time 34675303237 ps
CPU time 132.88 seconds
Started Jul 24 05:06:15 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 252732 kb
Host smart-739e4180-5cc0-41f5-9476-7da0a5c61e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106591497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3106591497
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3646116619
Short name T870
Test name
Test status
Simulation time 613852507 ps
CPU time 9.16 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:06:23 PM PDT 24
Peak memory 250048 kb
Host smart-ed8b0782-49cc-48ef-b63b-39556e106922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646116619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3646116619
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3240830425
Short name T939
Test name
Test status
Simulation time 2871789412 ps
CPU time 20.02 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:28 PM PDT 24
Peak memory 251112 kb
Host smart-078a6ab0-ac76-49de-a148-73418c08b469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240830425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3240830425
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1427438426
Short name T622
Test name
Test status
Simulation time 747059437 ps
CPU time 6.41 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 233600 kb
Host smart-1e39a9f4-db2b-4a1c-8a6b-866ae6cd6cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427438426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1427438426
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2825616121
Short name T243
Test name
Test status
Simulation time 2637197856 ps
CPU time 25.25 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 231136 kb
Host smart-fabdfb26-2db2-48bd-b821-715bc4af072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825616121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2825616121
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1999068044
Short name T212
Test name
Test status
Simulation time 2488275345 ps
CPU time 6.64 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 237776 kb
Host smart-f425709b-af6a-4511-916a-d86933ca14bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999068044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1999068044
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.908682940
Short name T504
Test name
Test status
Simulation time 227608547 ps
CPU time 3.5 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 233628 kb
Host smart-4d798832-ca39-444c-8f47-13914d71fe4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908682940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.908682940
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4045427157
Short name T60
Test name
Test status
Simulation time 881266011 ps
CPU time 4.75 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:05 PM PDT 24
Peak memory 220168 kb
Host smart-178cbd2a-bc4f-43c0-be6a-6cb3c4215ac8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045427157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4045427157
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1286988370
Short name T679
Test name
Test status
Simulation time 7842665540 ps
CPU time 12.98 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 217388 kb
Host smart-54804b54-fd2a-4659-ac6b-db6fef3fb416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286988370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1286988370
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3741152385
Short name T831
Test name
Test status
Simulation time 9848732762 ps
CPU time 13.43 seconds
Started Jul 24 05:05:59 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 217308 kb
Host smart-6b9871b3-d72f-4b0a-80f7-cc15b3680262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741152385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3741152385
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2704338901
Short name T750
Test name
Test status
Simulation time 22839888 ps
CPU time 0.67 seconds
Started Jul 24 05:06:26 PM PDT 24
Finished Jul 24 05:06:26 PM PDT 24
Peak memory 206228 kb
Host smart-578f6d2f-ed51-4c20-86bc-493fa3f7f267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704338901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2704338901
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.218932294
Short name T844
Test name
Test status
Simulation time 63526117 ps
CPU time 0.67 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:04 PM PDT 24
Peak memory 206648 kb
Host smart-ed17cd07-22a7-49b4-9ddd-02d7430ec9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218932294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.218932294
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1177026471
Short name T902
Test name
Test status
Simulation time 2260502859 ps
CPU time 7.37 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 233744 kb
Host smart-e919feb1-3ae9-40f5-9320-8c396c22ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177026471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1177026471
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2828291854
Short name T442
Test name
Test status
Simulation time 66139645 ps
CPU time 0.72 seconds
Started Jul 24 05:06:02 PM PDT 24
Finished Jul 24 05:06:03 PM PDT 24
Peak memory 205496 kb
Host smart-47d962b8-35d8-49b8-bea1-c737cd06ac83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828291854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2828291854
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1199403197
Short name T593
Test name
Test status
Simulation time 455260015 ps
CPU time 7.01 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 225336 kb
Host smart-c78b9f7f-31dd-4ef1-88f2-8452290f8149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199403197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1199403197
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.278404286
Short name T340
Test name
Test status
Simulation time 21725252 ps
CPU time 0.8 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:18 PM PDT 24
Peak memory 207168 kb
Host smart-6b9dabf9-4dc6-4daa-b539-6830c3279414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278404286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.278404286
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3813379819
Short name T213
Test name
Test status
Simulation time 40065635601 ps
CPU time 332.8 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:11:42 PM PDT 24
Peak memory 265936 kb
Host smart-57cfad81-d2ad-405d-9de4-0180b308ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813379819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3813379819
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1035111913
Short name T215
Test name
Test status
Simulation time 4581648116 ps
CPU time 66.2 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:07:12 PM PDT 24
Peak memory 233688 kb
Host smart-d262b8ca-a9f7-4516-a6b5-36d2314656ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035111913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1035111913
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1690008040
Short name T423
Test name
Test status
Simulation time 25384695495 ps
CPU time 158.55 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:08:48 PM PDT 24
Peak memory 252200 kb
Host smart-0f212a1f-15eb-4194-9f84-7bab58eecad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690008040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1690008040
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.539075566
Short name T299
Test name
Test status
Simulation time 1433942222 ps
CPU time 10.34 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 240988 kb
Host smart-d02eb6a7-fcbd-4df6-afc0-b2b7d78c96fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539075566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.539075566
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3466188661
Short name T260
Test name
Test status
Simulation time 3787345663 ps
CPU time 22.82 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 250260 kb
Host smart-8f282dbb-a9e6-4ae3-a339-549a51778c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466188661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3466188661
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1823517645
Short name T221
Test name
Test status
Simulation time 8404827091 ps
CPU time 15.73 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 225488 kb
Host smart-f5445cf6-c7f1-4701-ae4b-322628145911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823517645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1823517645
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2633897880
Short name T239
Test name
Test status
Simulation time 4363265531 ps
CPU time 15.03 seconds
Started Jul 24 05:06:20 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 240184 kb
Host smart-087c194a-de2f-4921-b0f5-09fb76963510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633897880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2633897880
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.145172399
Short name T709
Test name
Test status
Simulation time 680521689 ps
CPU time 3.32 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 225388 kb
Host smart-825b7d77-3823-4727-ba53-d44cdda48d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145172399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.145172399
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3547391124
Short name T190
Test name
Test status
Simulation time 2399879095 ps
CPU time 7.93 seconds
Started Jul 24 05:06:15 PM PDT 24
Finished Jul 24 05:06:23 PM PDT 24
Peak memory 233628 kb
Host smart-a82383a5-c4d8-4c26-8e9f-5e2550344962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547391124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3547391124
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.25431505
Short name T941
Test name
Test status
Simulation time 631955787 ps
CPU time 5.67 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:06:19 PM PDT 24
Peak memory 223672 kb
Host smart-a7afbf1f-0c78-42e3-9a11-1471995be35f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25431505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direc
t.25431505
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2981829240
Short name T161
Test name
Test status
Simulation time 46945656308 ps
CPU time 169.43 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:09:03 PM PDT 24
Peak memory 274160 kb
Host smart-dd0f27c7-2c43-42c2-bc58-4c047ddbc245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981829240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2981829240
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1316600523
Short name T1017
Test name
Test status
Simulation time 3930478646 ps
CPU time 17.43 seconds
Started Jul 24 05:06:11 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 217284 kb
Host smart-1133bdd1-aeb3-43b5-ab5d-2028e4346d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316600523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1316600523
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2085179218
Short name T350
Test name
Test status
Simulation time 1592690375 ps
CPU time 3.07 seconds
Started Jul 24 05:05:56 PM PDT 24
Finished Jul 24 05:05:59 PM PDT 24
Peak memory 217124 kb
Host smart-67d8e1e6-d3ce-4194-8e8c-0ddd6214cda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085179218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2085179218
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.908304292
Short name T1018
Test name
Test status
Simulation time 162355882 ps
CPU time 2.77 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 217100 kb
Host smart-f5ed5d3d-a277-4ef2-97a1-49c80058f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908304292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.908304292
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1655768829
Short name T866
Test name
Test status
Simulation time 112532904 ps
CPU time 0.81 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:06:05 PM PDT 24
Peak memory 206780 kb
Host smart-d8487ec4-7d9b-4e70-b5a3-3d43afcec6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655768829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1655768829
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.209359231
Short name T439
Test name
Test status
Simulation time 1645674922 ps
CPU time 2.94 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 233484 kb
Host smart-2ca3c460-94b6-409e-b4be-eac9ce5e07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209359231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.209359231
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3522270592
Short name T626
Test name
Test status
Simulation time 12082361 ps
CPU time 0.72 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:06 PM PDT 24
Peak memory 205524 kb
Host smart-81324ce9-8f21-4b6c-b53f-d792ffeed61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522270592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3522270592
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3346233627
Short name T649
Test name
Test status
Simulation time 128259395 ps
CPU time 3.27 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:11 PM PDT 24
Peak memory 233496 kb
Host smart-334c5e67-0b77-423c-a9d1-f5d90b78e111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346233627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3346233627
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1454424397
Short name T354
Test name
Test status
Simulation time 34641000 ps
CPU time 0.8 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 207240 kb
Host smart-c02ba56c-2323-4866-b2d6-8bc1e71e2f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454424397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1454424397
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.847193627
Short name T216
Test name
Test status
Simulation time 1623180441 ps
CPU time 11.33 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:16 PM PDT 24
Peak memory 237024 kb
Host smart-492d9ba5-a471-4fdf-b312-7bea7520affe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847193627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.847193627
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1688089943
Short name T194
Test name
Test status
Simulation time 198468366282 ps
CPU time 174.81 seconds
Started Jul 24 05:06:11 PM PDT 24
Finished Jul 24 05:09:06 PM PDT 24
Peak memory 269224 kb
Host smart-fae26ded-5d72-444c-916b-136e980803a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688089943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1688089943
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.722577180
Short name T911
Test name
Test status
Simulation time 172906136 ps
CPU time 3.14 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 225440 kb
Host smart-38805da3-a701-49d2-bf83-4354e583c85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722577180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.722577180
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.630011640
Short name T186
Test name
Test status
Simulation time 116911547420 ps
CPU time 240.25 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:10:14 PM PDT 24
Peak memory 266436 kb
Host smart-670d5f20-1e11-4219-8dc4-7b1b058a5b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630011640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.630011640
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1080343182
Short name T690
Test name
Test status
Simulation time 580313343 ps
CPU time 7.37 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 225400 kb
Host smart-8711b1a8-f135-4890-b23d-127a80ca7581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080343182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1080343182
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.514350494
Short name T251
Test name
Test status
Simulation time 9705504445 ps
CPU time 8.34 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 233700 kb
Host smart-86e493c5-9fbe-40eb-a203-5ba2c053715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514350494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.514350494
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3024805656
Short name T726
Test name
Test status
Simulation time 127925333 ps
CPU time 2.13 seconds
Started Jul 24 05:06:11 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 233256 kb
Host smart-f323b062-a62a-4677-b2d8-182cb2e43296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024805656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3024805656
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3654701442
Short name T810
Test name
Test status
Simulation time 3696345439 ps
CPU time 11.26 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 233632 kb
Host smart-213ccad2-306d-47eb-855f-26e9ad0185ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654701442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3654701442
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1791146420
Short name T154
Test name
Test status
Simulation time 4883510126 ps
CPU time 8.53 seconds
Started Jul 24 05:06:00 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 223976 kb
Host smart-6aacf06b-0c43-4777-8a4e-cc9861d6924f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1791146420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1791146420
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2254363577
Short name T284
Test name
Test status
Simulation time 18989261618 ps
CPU time 66.02 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 256496 kb
Host smart-56e3cb4e-06aa-4ad4-8bc5-42f85405b079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254363577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2254363577
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1664980571
Short name T361
Test name
Test status
Simulation time 2986847055 ps
CPU time 19.81 seconds
Started Jul 24 05:06:21 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 217344 kb
Host smart-f3f57934-8e45-40a2-8aaa-eae0a92c5bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664980571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1664980571
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3229019831
Short name T428
Test name
Test status
Simulation time 563669610 ps
CPU time 2.01 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:06:11 PM PDT 24
Peak memory 208736 kb
Host smart-2d8eedaf-64f9-473c-8d5a-6588fca1f80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229019831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3229019831
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1798115085
Short name T822
Test name
Test status
Simulation time 727895608 ps
CPU time 6.62 seconds
Started Jul 24 05:06:16 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 217124 kb
Host smart-a99de4f0-b3d8-43f0-bd4f-e4cab1d10410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798115085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1798115085
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2967173675
Short name T704
Test name
Test status
Simulation time 190839830 ps
CPU time 1.04 seconds
Started Jul 24 05:06:21 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 207024 kb
Host smart-28e7ba97-a496-43ff-a667-9dc554252514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967173675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2967173675
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2909524392
Short name T564
Test name
Test status
Simulation time 1766370057 ps
CPU time 4.1 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 233488 kb
Host smart-c4a1a883-6144-4bad-9705-81eb4eb47971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909524392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2909524392
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2630486610
Short name T862
Test name
Test status
Simulation time 37372447 ps
CPU time 0.73 seconds
Started Jul 24 05:06:22 PM PDT 24
Finished Jul 24 05:06:23 PM PDT 24
Peak memory 205504 kb
Host smart-6d6477b2-eff1-4dec-a9cf-31a9f7fa2de2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630486610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2630486610
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1710948793
Short name T668
Test name
Test status
Simulation time 1448473092 ps
CPU time 5.45 seconds
Started Jul 24 05:06:25 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 233568 kb
Host smart-21d93ac4-d07d-40ca-af1f-fae3322b1fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710948793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1710948793
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3502440213
Short name T931
Test name
Test status
Simulation time 181723226 ps
CPU time 0.75 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 206584 kb
Host smart-89e844bd-0c85-4a8e-8533-cab3055e0301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502440213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3502440213
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2088124495
Short name T476
Test name
Test status
Simulation time 117495529197 ps
CPU time 214.02 seconds
Started Jul 24 05:06:12 PM PDT 24
Finished Jul 24 05:09:46 PM PDT 24
Peak memory 250136 kb
Host smart-ffaa354f-7226-44d8-afc9-a8eae7f7005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088124495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2088124495
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3778190065
Short name T279
Test name
Test status
Simulation time 14131800443 ps
CPU time 95.27 seconds
Started Jul 24 05:06:01 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 255428 kb
Host smart-46783f8d-d1db-429a-b49b-45d72c8b1532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778190065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3778190065
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.393304104
Short name T727
Test name
Test status
Simulation time 2210684309 ps
CPU time 38.96 seconds
Started Jul 24 05:06:16 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 258248 kb
Host smart-0dd29538-67bf-4690-b875-660da5e0af30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393304104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.393304104
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.748962952
Short name T899
Test name
Test status
Simulation time 1014463244 ps
CPU time 15.21 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:33 PM PDT 24
Peak memory 234020 kb
Host smart-5f19ef91-3f35-4bfd-9721-9173877bbdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748962952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.748962952
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3723566879
Short name T484
Test name
Test status
Simulation time 90290545 ps
CPU time 2.48 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 233208 kb
Host smart-c4d135d4-a4f4-42ce-8135-b520a02af572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723566879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3723566879
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2249453979
Short name T960
Test name
Test status
Simulation time 9788040803 ps
CPU time 77.05 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:07:35 PM PDT 24
Peak memory 250096 kb
Host smart-f46f7f9d-2b46-4080-92ec-ed527b953e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249453979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2249453979
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1654369523
Short name T222
Test name
Test status
Simulation time 3041940609 ps
CPU time 10.2 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 225484 kb
Host smart-e65e66ea-1e54-4cf4-acc2-62ef30c427ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654369523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1654369523
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3825719126
Short name T896
Test name
Test status
Simulation time 61426697 ps
CPU time 2.37 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 233236 kb
Host smart-86c6191b-2a46-4e82-94fe-b29f016a4dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825719126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3825719126
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3295457625
Short name T645
Test name
Test status
Simulation time 4027943760 ps
CPU time 10.77 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:17 PM PDT 24
Peak memory 221476 kb
Host smart-fe3d9bbc-8e58-44b6-a4f3-fcc3bd73b6a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3295457625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3295457625
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2087149132
Short name T1028
Test name
Test status
Simulation time 49198116 ps
CPU time 0.94 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:09 PM PDT 24
Peak memory 208308 kb
Host smart-cdf50128-037d-41fe-bf84-3d882eabd0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087149132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2087149132
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2541662428
Short name T303
Test name
Test status
Simulation time 1361551240 ps
CPU time 9.5 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 219880 kb
Host smart-63215674-1553-43d3-aca2-f9e147c8183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541662428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2541662428
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3186517288
Short name T80
Test name
Test status
Simulation time 217218810 ps
CPU time 1.71 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 208736 kb
Host smart-41d9ba0f-3197-422d-a2e9-c93f50dfe793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186517288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3186517288
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3649917429
Short name T558
Test name
Test status
Simulation time 61826618 ps
CPU time 0.8 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 206704 kb
Host smart-f9f9fd7b-16a3-4fd1-9fa1-6756c819ad61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649917429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3649917429
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1974005508
Short name T61
Test name
Test status
Simulation time 50258534 ps
CPU time 0.68 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:13 PM PDT 24
Peak memory 206200 kb
Host smart-8fdb4343-2faf-4797-a2ae-3db66ae4e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974005508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1974005508
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1389230994
Short name T208
Test name
Test status
Simulation time 1079718088 ps
CPU time 5.57 seconds
Started Jul 24 05:06:21 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 225500 kb
Host smart-e49234d3-ff90-487a-9b34-f79a0eae11ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389230994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1389230994
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1116815426
Short name T345
Test name
Test status
Simulation time 48441930 ps
CPU time 0.75 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 205972 kb
Host smart-764bdb7b-6f84-475e-869a-38794f738261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116815426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
116815426
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3739166005
Short name T322
Test name
Test status
Simulation time 1424780870 ps
CPU time 19.57 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 225452 kb
Host smart-eb032e4c-e0d5-411f-9d81-d0e492a7c8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739166005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3739166005
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2903163868
Short name T972
Test name
Test status
Simulation time 23123963 ps
CPU time 0.76 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 207308 kb
Host smart-9cd987d5-28ef-42e9-a2ab-434dee72243b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903163868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2903163868
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2671393289
Short name T937
Test name
Test status
Simulation time 8116591310 ps
CPU time 53.04 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:55 PM PDT 24
Peak memory 250100 kb
Host smart-b7b42d4b-781f-4011-a477-93a8cd4a8d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671393289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2671393289
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.86777554
Short name T376
Test name
Test status
Simulation time 59535937339 ps
CPU time 172.76 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:07:57 PM PDT 24
Peak memory 257972 kb
Host smart-e57bd914-bf4c-42a0-a699-8d3f7a21311b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86777554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.86777554
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3552989723
Short name T650
Test name
Test status
Simulation time 13508798356 ps
CPU time 58.94 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:05:45 PM PDT 24
Peak memory 225520 kb
Host smart-c43c65db-e0a0-4c93-8b7a-39173c92f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552989723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3552989723
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1057343726
Short name T357
Test name
Test status
Simulation time 728783116 ps
CPU time 6.31 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 233548 kb
Host smart-34342149-7276-4220-8c92-0aa863e57144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057343726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1057343726
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3405191834
Short name T217
Test name
Test status
Simulation time 1232486437 ps
CPU time 9.32 seconds
Started Jul 24 05:05:12 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 225384 kb
Host smart-cd07d58a-07cf-47b6-91fd-6dfd68f91228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405191834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3405191834
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4121006918
Short name T526
Test name
Test status
Simulation time 1456289818 ps
CPU time 4.26 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 233636 kb
Host smart-c52dd50c-3673-4c4a-8427-0c9c1ac7529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121006918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4121006918
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2305118019
Short name T9
Test name
Test status
Simulation time 5739476148 ps
CPU time 21.85 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 240240 kb
Host smart-a6a3a4bb-2b5b-459a-8b46-d924dfefc7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305118019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2305118019
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4134443883
Short name T855
Test name
Test status
Simulation time 100357356 ps
CPU time 1.02 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 217416 kb
Host smart-61aeba19-f233-47d5-9a21-f74f636d9d4e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134443883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4134443883
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.652946323
Short name T656
Test name
Test status
Simulation time 19402230126 ps
CPU time 17.56 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 240944 kb
Host smart-4763b23f-ec74-40d8-94c4-ddaf3f593e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652946323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
652946323
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2171195310
Short name T44
Test name
Test status
Simulation time 6931181626 ps
CPU time 5.08 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 225408 kb
Host smart-e290a822-beee-4bee-b973-8ecdd063a26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171195310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2171195310
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2397756806
Short name T901
Test name
Test status
Simulation time 2097377906 ps
CPU time 14.27 seconds
Started Jul 24 05:04:43 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 222696 kb
Host smart-8e61ad55-9f6f-447e-ad61-cea7941df2ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397756806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2397756806
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3718486820
Short name T74
Test name
Test status
Simulation time 178409431 ps
CPU time 1.14 seconds
Started Jul 24 05:04:37 PM PDT 24
Finished Jul 24 05:04:38 PM PDT 24
Peak memory 235936 kb
Host smart-95af912c-4c74-40f2-9678-213ec3b5eab5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718486820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3718486820
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.701916221
Short name T784
Test name
Test status
Simulation time 11157405231 ps
CPU time 47.34 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:05:36 PM PDT 24
Peak memory 236624 kb
Host smart-8a2eb32e-162a-40c5-9d8c-ba2edca69a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701916221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.701916221
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.195903777
Short name T32
Test name
Test status
Simulation time 1377485320 ps
CPU time 6.74 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 218496 kb
Host smart-92eb0a93-6b60-40db-b536-c777abcd0262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195903777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.195903777
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2826392997
Short name T90
Test name
Test status
Simulation time 260976392 ps
CPU time 1.36 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:04:36 PM PDT 24
Peak memory 208548 kb
Host smart-fd1afe94-6127-4c45-8f4e-c48144a40b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826392997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2826392997
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2268571465
Short name T26
Test name
Test status
Simulation time 130566373 ps
CPU time 0.68 seconds
Started Jul 24 05:04:21 PM PDT 24
Finished Jul 24 05:04:22 PM PDT 24
Peak memory 206180 kb
Host smart-f7b58d04-4905-4fae-af6e-8ae9a505e1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268571465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2268571465
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4021205691
Short name T969
Test name
Test status
Simulation time 50920659 ps
CPU time 0.81 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:49 PM PDT 24
Peak memory 206688 kb
Host smart-2d061c4a-c2f1-4501-ae92-c43ed444a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021205691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4021205691
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4167588131
Short name T714
Test name
Test status
Simulation time 4367145587 ps
CPU time 7.42 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 238592 kb
Host smart-bdecc54c-f3c8-4d4c-9991-cbd6c5310eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167588131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4167588131
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1493493302
Short name T381
Test name
Test status
Simulation time 30598603 ps
CPU time 0.73 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:06:05 PM PDT 24
Peak memory 205984 kb
Host smart-a2003ff4-f797-40f2-9622-cf66c3d06224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493493302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1493493302
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1432523339
Short name T269
Test name
Test status
Simulation time 2663987953 ps
CPU time 3.63 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:21 PM PDT 24
Peak memory 225384 kb
Host smart-044a2901-d1e0-4627-8f28-1e9ac316ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432523339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1432523339
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2424110249
Short name T407
Test name
Test status
Simulation time 22716880 ps
CPU time 0.77 seconds
Started Jul 24 05:06:09 PM PDT 24
Finished Jul 24 05:06:10 PM PDT 24
Peak memory 207124 kb
Host smart-e25843b0-516a-469f-9726-151e1773dfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424110249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2424110249
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.203721171
Short name T957
Test name
Test status
Simulation time 238195202897 ps
CPU time 281.4 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:11:05 PM PDT 24
Peak memory 254924 kb
Host smart-616ad3e4-4d29-49f1-8762-9014cc83c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203721171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.203721171
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2059277171
Short name T247
Test name
Test status
Simulation time 17104270627 ps
CPU time 217 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:10:21 PM PDT 24
Peak memory 266336 kb
Host smart-3d3b0869-a4a4-4fb3-914f-6a0cc3cde5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059277171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2059277171
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3210395774
Short name T440
Test name
Test status
Simulation time 16187683287 ps
CPU time 68.71 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 253232 kb
Host smart-26b6718d-43d9-47ca-8815-2a87a06f4ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210395774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3210395774
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.847670602
Short name T603
Test name
Test status
Simulation time 750907039 ps
CPU time 4.99 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:06:12 PM PDT 24
Peak memory 225452 kb
Host smart-58347e3a-427e-450b-beae-58e55e45ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847670602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.847670602
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1020395527
Short name T539
Test name
Test status
Simulation time 24859547208 ps
CPU time 186.22 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:09:31 PM PDT 24
Peak memory 253672 kb
Host smart-b243e0e8-deb3-48ed-bd8d-7ae30cb836c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020395527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1020395527
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.4113255589
Short name T917
Test name
Test status
Simulation time 3327425497 ps
CPU time 5.01 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 225504 kb
Host smart-4d54a61f-df3f-4957-81e1-2fe1bb7d0e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113255589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.4113255589
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2601732007
Short name T632
Test name
Test status
Simulation time 1857425455 ps
CPU time 9.17 seconds
Started Jul 24 05:06:12 PM PDT 24
Finished Jul 24 05:06:21 PM PDT 24
Peak memory 225400 kb
Host smart-2cd49e43-597b-4c2e-8efe-fdef0f3c6b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601732007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2601732007
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1662676830
Short name T229
Test name
Test status
Simulation time 908955271 ps
CPU time 7.34 seconds
Started Jul 24 05:06:08 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 233624 kb
Host smart-52029415-3b82-4fc1-8d85-59f22d18f7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662676830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1662676830
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1793078404
Short name T943
Test name
Test status
Simulation time 6730129488 ps
CPU time 10.86 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 225464 kb
Host smart-fc5f93dc-14b5-4e10-a618-ddb9dbf6f12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793078404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1793078404
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.881410826
Short name T811
Test name
Test status
Simulation time 194275625 ps
CPU time 3.96 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 223792 kb
Host smart-7e748ac9-a078-4982-9d30-9b5e314db88d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881410826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.881410826
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.414368667
Short name T653
Test name
Test status
Simulation time 8318459777 ps
CPU time 66.22 seconds
Started Jul 24 05:06:13 PM PDT 24
Finished Jul 24 05:07:19 PM PDT 24
Peak memory 249424 kb
Host smart-535842f5-6206-47ce-a7d8-c1b21354a92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414368667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.414368667
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.484375925
Short name T311
Test name
Test status
Simulation time 6421649853 ps
CPU time 31.16 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 217276 kb
Host smart-57d357be-ce9a-49cc-be6e-c4cab1a980a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484375925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.484375925
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3349851013
Short name T858
Test name
Test status
Simulation time 397793441 ps
CPU time 1.1 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 208488 kb
Host smart-8cc7bf84-8914-4e7f-88c1-38acf658a09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349851013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3349851013
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1074089045
Short name T459
Test name
Test status
Simulation time 318163291 ps
CPU time 1.71 seconds
Started Jul 24 05:06:31 PM PDT 24
Finished Jul 24 05:06:33 PM PDT 24
Peak memory 217124 kb
Host smart-0372ca46-8b49-4f63-8a94-d0c6994faad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074089045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1074089045
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3783569373
Short name T734
Test name
Test status
Simulation time 102566930 ps
CPU time 0.73 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 206728 kb
Host smart-3f35e44f-e67f-48b5-9ca8-4167101f6802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783569373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3783569373
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.488513289
Short name T1010
Test name
Test status
Simulation time 22822759598 ps
CPU time 20.8 seconds
Started Jul 24 05:06:10 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 241444 kb
Host smart-c0f77c0f-0b94-4860-a209-d2a9c0fd56b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488513289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.488513289
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1921911868
Short name T927
Test name
Test status
Simulation time 26733653 ps
CPU time 0.73 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 206088 kb
Host smart-b8a15d70-0968-48b1-9506-e6f689c17684
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921911868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1921911868
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1804334255
Short name T253
Test name
Test status
Simulation time 95374503 ps
CPU time 2.49 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 225464 kb
Host smart-7816c2a3-94f1-4d4c-a776-65cd5f4fc5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804334255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1804334255
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2095293046
Short name T76
Test name
Test status
Simulation time 24015376 ps
CPU time 0.78 seconds
Started Jul 24 05:06:26 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 207604 kb
Host smart-55ff85b3-0339-49fa-9f2f-52f6081cbc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095293046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2095293046
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.1935928160
Short name T178
Test name
Test status
Simulation time 11617002975 ps
CPU time 69.72 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:07:27 PM PDT 24
Peak memory 250124 kb
Host smart-f4811a24-ceaf-4b8f-ab42-b8b15f2cf769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935928160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.1935928160
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.291728552
Short name T990
Test name
Test status
Simulation time 10303648383 ps
CPU time 92.91 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 258220 kb
Host smart-34b3f38b-6ff9-429d-b0f5-b5beec9fd4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291728552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.291728552
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.805510532
Short name T276
Test name
Test status
Simulation time 274293231852 ps
CPU time 375.31 seconds
Started Jul 24 05:06:25 PM PDT 24
Finished Jul 24 05:12:41 PM PDT 24
Peak memory 273900 kb
Host smart-88b7de4f-80a1-46c3-9eee-600354928125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805510532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.805510532
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1782717776
Short name T961
Test name
Test status
Simulation time 645026533 ps
CPU time 5.52 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 233548 kb
Host smart-3312f4e2-8c29-42c2-a8e4-67b1651257c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782717776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1782717776
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3967262184
Short name T950
Test name
Test status
Simulation time 139967268404 ps
CPU time 241.25 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:10:28 PM PDT 24
Peak memory 250132 kb
Host smart-0776f5ef-eabb-49c1-ac3b-226823558633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967262184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3967262184
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.627924039
Short name T535
Test name
Test status
Simulation time 236815450 ps
CPU time 3.27 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 233544 kb
Host smart-5ea84143-41a1-4d2b-9263-927a6e73b397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627924039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.627924039
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1687702179
Short name T506
Test name
Test status
Simulation time 183346521 ps
CPU time 3.45 seconds
Started Jul 24 05:06:15 PM PDT 24
Finished Jul 24 05:06:19 PM PDT 24
Peak memory 225392 kb
Host smart-7c43fffd-5a0d-45f0-bc1e-e9e13a755026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687702179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1687702179
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.987724276
Short name T578
Test name
Test status
Simulation time 74788336 ps
CPU time 2.22 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 223956 kb
Host smart-b56bd75b-cd34-4d8c-a851-398e8dbff053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987724276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.987724276
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3855413663
Short name T916
Test name
Test status
Simulation time 1969913523 ps
CPU time 5.28 seconds
Started Jul 24 05:06:22 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 225424 kb
Host smart-2a649e26-7c5a-438e-8964-02f87630d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855413663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3855413663
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1342833020
Short name T554
Test name
Test status
Simulation time 3637398111 ps
CPU time 20.93 seconds
Started Jul 24 05:06:16 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 221444 kb
Host smart-100e141d-e25c-4c4b-85a8-e768d2469495
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1342833020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1342833020
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3479982847
Short name T18
Test name
Test status
Simulation time 15745300761 ps
CPU time 144.87 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:08:39 PM PDT 24
Peak memory 253048 kb
Host smart-7042672f-29d2-43da-b62c-e12efc5cf5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479982847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3479982847
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.237390275
Short name T905
Test name
Test status
Simulation time 11358648310 ps
CPU time 30.95 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 217588 kb
Host smart-4bae7a85-4771-4b89-b4dd-9f116d0869c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237390275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.237390275
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1677085133
Short name T27
Test name
Test status
Simulation time 30237298293 ps
CPU time 10.03 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 217232 kb
Host smart-0a9056c8-d720-4f37-bd02-890dcca52619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677085133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1677085133
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2970444786
Short name T904
Test name
Test status
Simulation time 30280440 ps
CPU time 1.26 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 217160 kb
Host smart-9d79f322-d58e-48d9-8114-196c4479d05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970444786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2970444786
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2190124167
Short name T706
Test name
Test status
Simulation time 38091429 ps
CPU time 0.78 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 206692 kb
Host smart-cd854be4-6428-4152-957b-f87d2a38bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190124167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2190124167
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2461852539
Short name T874
Test name
Test status
Simulation time 19146579913 ps
CPU time 15.35 seconds
Started Jul 24 05:06:03 PM PDT 24
Finished Jul 24 05:06:19 PM PDT 24
Peak memory 225456 kb
Host smart-5f0ae4da-92f9-4249-8058-5d981415aa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461852539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2461852539
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3500373732
Short name T738
Test name
Test status
Simulation time 120811098 ps
CPU time 0.7 seconds
Started Jul 24 05:06:14 PM PDT 24
Finished Jul 24 05:06:15 PM PDT 24
Peak memory 206440 kb
Host smart-cb09a9ff-b590-45ab-8d94-f7711a120b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500373732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3500373732
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2621342001
Short name T683
Test name
Test status
Simulation time 146475677 ps
CPU time 2.39 seconds
Started Jul 24 05:06:51 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 233192 kb
Host smart-3b87e0e1-e56b-4d7f-9841-c468eeb7c4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621342001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2621342001
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1575827522
Short name T334
Test name
Test status
Simulation time 82755075 ps
CPU time 0.78 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:18 PM PDT 24
Peak memory 207188 kb
Host smart-856f87a7-7000-4851-8013-4809abeb83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575827522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1575827522
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1160569534
Short name T485
Test name
Test status
Simulation time 36147559183 ps
CPU time 157.89 seconds
Started Jul 24 05:06:04 PM PDT 24
Finished Jul 24 05:08:42 PM PDT 24
Peak memory 251012 kb
Host smart-037cfeae-72c0-4064-bec1-b28f1628b9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160569534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1160569534
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3720641729
Short name T759
Test name
Test status
Simulation time 8931414325 ps
CPU time 40.44 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:07:07 PM PDT 24
Peak memory 237204 kb
Host smart-adfe642f-fd54-4906-a551-0d2ada40a879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720641729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3720641729
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.40687050
Short name T883
Test name
Test status
Simulation time 43986630769 ps
CPU time 354.43 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:12:22 PM PDT 24
Peak memory 250056 kb
Host smart-35230ac6-a88d-4447-a2c6-9ed3fce482e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40687050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.40687050
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3463091900
Short name T705
Test name
Test status
Simulation time 1187284342 ps
CPU time 7.94 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 225308 kb
Host smart-2bc2b9ac-d917-414c-a609-1648a4cdf595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463091900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3463091900
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2247129495
Short name T273
Test name
Test status
Simulation time 6511079542 ps
CPU time 85.42 seconds
Started Jul 24 05:06:11 PM PDT 24
Finished Jul 24 05:07:37 PM PDT 24
Peak memory 252180 kb
Host smart-a0200e9c-9c2a-4b4a-8146-ba28006f45fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247129495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2247129495
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2254264508
Short name T237
Test name
Test status
Simulation time 633706615 ps
CPU time 4.6 seconds
Started Jul 24 05:06:22 PM PDT 24
Finished Jul 24 05:06:26 PM PDT 24
Peak memory 219680 kb
Host smart-a407bffb-7308-4f91-90ef-10d303807ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254264508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2254264508
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.108060490
Short name T749
Test name
Test status
Simulation time 7248581856 ps
CPU time 7.53 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:32 PM PDT 24
Peak memory 225504 kb
Host smart-5b504373-6d5a-4239-9970-095dca834b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108060490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.108060490
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1275200334
Short name T262
Test name
Test status
Simulation time 5480735479 ps
CPU time 3.26 seconds
Started Jul 24 05:06:12 PM PDT 24
Finished Jul 24 05:06:16 PM PDT 24
Peak memory 225424 kb
Host smart-0a54298a-6b92-4fcb-999e-f996226050c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275200334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1275200334
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1878541476
Short name T81
Test name
Test status
Simulation time 8327163530 ps
CPU time 10.76 seconds
Started Jul 24 05:06:10 PM PDT 24
Finished Jul 24 05:06:21 PM PDT 24
Peak memory 225328 kb
Host smart-c8ffb35f-27f7-4196-afde-b7666ddcd0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878541476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1878541476
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1659456834
Short name T153
Test name
Test status
Simulation time 349916868 ps
CPU time 3.57 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 220080 kb
Host smart-42d592bb-ed92-4626-b6bf-a02b5377015b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1659456834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1659456834
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2368840550
Short name T789
Test name
Test status
Simulation time 12348619855 ps
CPU time 93.21 seconds
Started Jul 24 05:06:07 PM PDT 24
Finished Jul 24 05:07:40 PM PDT 24
Peak memory 257640 kb
Host smart-8ce312b5-5cd0-4732-8eb0-68c39f1c5101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368840550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2368840550
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.743332039
Short name T91
Test name
Test status
Simulation time 3121770743 ps
CPU time 10.47 seconds
Started Jul 24 05:06:32 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 217272 kb
Host smart-a410b6eb-a882-4dea-8044-a9c415c633a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743332039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.743332039
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.66635569
Short name T514
Test name
Test status
Simulation time 4456131476 ps
CPU time 14.58 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:20 PM PDT 24
Peak memory 217172 kb
Host smart-7e19cb8c-7189-4a85-8c3e-b70ca31847c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66635569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.66635569
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2583968581
Short name T613
Test name
Test status
Simulation time 451001887 ps
CPU time 1.39 seconds
Started Jul 24 05:06:17 PM PDT 24
Finished Jul 24 05:06:18 PM PDT 24
Peak memory 217096 kb
Host smart-02912238-a747-48e2-9c99-e7207f74a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583968581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2583968581
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1947872846
Short name T499
Test name
Test status
Simulation time 74047719 ps
CPU time 0.85 seconds
Started Jul 24 05:06:32 PM PDT 24
Finished Jul 24 05:06:33 PM PDT 24
Peak memory 206716 kb
Host smart-3fc1b9cd-b1da-494c-a098-04cca2860cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947872846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1947872846
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3988977399
Short name T329
Test name
Test status
Simulation time 7942822447 ps
CPU time 26.41 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 225404 kb
Host smart-65b8ca9f-5a2d-4bbb-acea-d6e19e4e0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988977399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3988977399
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.297845103
Short name T978
Test name
Test status
Simulation time 12099922 ps
CPU time 0.71 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 206068 kb
Host smart-a8f08736-cce5-49b3-87a7-24dea08b3f9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297845103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.297845103
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3545956537
Short name T248
Test name
Test status
Simulation time 1251839224 ps
CPU time 6.11 seconds
Started Jul 24 05:06:18 PM PDT 24
Finished Jul 24 05:06:24 PM PDT 24
Peak memory 225372 kb
Host smart-b84657f2-1f11-4c8f-8bbd-ef72e298df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545956537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3545956537
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.423515810
Short name T615
Test name
Test status
Simulation time 110222084 ps
CPU time 0.84 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:29 PM PDT 24
Peak memory 206276 kb
Host smart-b4221b70-8a77-4363-8a8e-31773592610e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423515810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.423515810
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3429970404
Short name T586
Test name
Test status
Simulation time 18013798690 ps
CPU time 62.43 seconds
Started Jul 24 05:06:26 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 253316 kb
Host smart-cca1ca67-97b8-41a1-b9d0-95b3da560aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429970404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3429970404
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3583342170
Short name T56
Test name
Test status
Simulation time 57231793092 ps
CPU time 110.72 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:08:25 PM PDT 24
Peak memory 250172 kb
Host smart-e0ffb122-7356-438d-9754-8a4d7dece675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583342170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3583342170
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3472825432
Short name T264
Test name
Test status
Simulation time 7470073546 ps
CPU time 152.75 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:09:18 PM PDT 24
Peak memory 265728 kb
Host smart-1304ddc7-a1a9-4b6c-8db8-7ee8882718cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472825432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3472825432
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3188045240
Short name T232
Test name
Test status
Simulation time 10875110893 ps
CPU time 34.99 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:07:15 PM PDT 24
Peak memory 225368 kb
Host smart-4f31a7a7-b6de-439e-8707-0b62a0174124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188045240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3188045240
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1729931471
Short name T291
Test name
Test status
Simulation time 3261662570 ps
CPU time 59.19 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:07:33 PM PDT 24
Peak memory 258276 kb
Host smart-9cccf082-85ae-4028-9ff3-301c966bdc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729931471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1729931471
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2246632437
Short name T139
Test name
Test status
Simulation time 2312380600 ps
CPU time 8.39 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 225520 kb
Host smart-93dad368-07e7-465c-a732-d67b62084963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246632437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2246632437
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3894812450
Short name T79
Test name
Test status
Simulation time 3686279869 ps
CPU time 31.34 seconds
Started Jul 24 05:06:25 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 225364 kb
Host smart-5c5b9bda-de34-4972-9483-822ce8483d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894812450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3894812450
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3209380128
Short name T258
Test name
Test status
Simulation time 440478591 ps
CPU time 7.65 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 241420 kb
Host smart-593d6f02-684f-4056-a7b1-8714c6f733ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209380128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3209380128
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2218133425
Short name T137
Test name
Test status
Simulation time 9202531351 ps
CPU time 8.65 seconds
Started Jul 24 05:06:05 PM PDT 24
Finished Jul 24 05:06:14 PM PDT 24
Peak memory 225428 kb
Host smart-62f61731-fbf6-4b70-b411-ca987e8ff2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218133425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2218133425
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.815690718
Short name T147
Test name
Test status
Simulation time 446062298 ps
CPU time 5.8 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 223852 kb
Host smart-f43bdb8b-504e-46d1-9841-de19d21575d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=815690718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.815690718
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3836233792
Short name T494
Test name
Test status
Simulation time 14680293414 ps
CPU time 17.53 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 217224 kb
Host smart-c597334d-3ac7-4ace-b19a-75692b0cc4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836233792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3836233792
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2067768310
Short name T31
Test name
Test status
Simulation time 150374196 ps
CPU time 2.22 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 216980 kb
Host smart-fbd2275f-8b05-4fac-bb4c-6b027b958bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067768310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2067768310
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3193645524
Short name T371
Test name
Test status
Simulation time 1340652547 ps
CPU time 2.6 seconds
Started Jul 24 05:06:32 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 217040 kb
Host smart-6f397cc6-4564-40be-9421-87790542a25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193645524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3193645524
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.680739112
Short name T985
Test name
Test status
Simulation time 68374393 ps
CPU time 0.89 seconds
Started Jul 24 05:06:06 PM PDT 24
Finished Jul 24 05:06:07 PM PDT 24
Peak memory 206772 kb
Host smart-39218eb9-5e63-4268-8b86-c7c1134c1e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680739112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.680739112
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2407181578
Short name T469
Test name
Test status
Simulation time 112300959 ps
CPU time 2.47 seconds
Started Jul 24 05:06:20 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 233440 kb
Host smart-8fc84623-3300-4d78-9d01-bb5123e89713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407181578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2407181578
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.370257764
Short name T491
Test name
Test status
Simulation time 15390001 ps
CPU time 0.69 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:28 PM PDT 24
Peak memory 205436 kb
Host smart-600530ed-9c30-4cd8-bbbb-f5519e1d03d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370257764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.370257764
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1221207650
Short name T488
Test name
Test status
Simulation time 103048668 ps
CPU time 2.77 seconds
Started Jul 24 05:06:19 PM PDT 24
Finished Jul 24 05:06:22 PM PDT 24
Peak memory 233696 kb
Host smart-ab5e0a02-9dc6-420a-83ec-4356d38ee6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221207650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1221207650
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2573292927
Short name T757
Test name
Test status
Simulation time 41737472 ps
CPU time 0.82 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:35 PM PDT 24
Peak memory 207300 kb
Host smart-f0d3d4d4-473d-48b2-9a64-3211e728353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573292927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2573292927
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2262199207
Short name T550
Test name
Test status
Simulation time 166458967 ps
CPU time 0.85 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 216832 kb
Host smart-c675fe9e-912e-402b-97b7-7ab7e8a559a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262199207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2262199207
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3010471015
Short name T288
Test name
Test status
Simulation time 38308900532 ps
CPU time 113.57 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:08:28 PM PDT 24
Peak memory 255496 kb
Host smart-c87021cb-afef-41de-bb9c-ff7127394878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010471015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3010471015
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1451305529
Short name T297
Test name
Test status
Simulation time 5427346618 ps
CPU time 14.89 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 240820 kb
Host smart-36e8c7ad-283b-4c60-bb99-1a3514f8090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451305529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1451305529
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2997314448
Short name T46
Test name
Test status
Simulation time 2286009049 ps
CPU time 48.27 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 244668 kb
Host smart-739e5406-d43d-41b8-b209-71a4b6652a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997314448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2997314448
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.591139153
Short name T1021
Test name
Test status
Simulation time 550794057 ps
CPU time 4.11 seconds
Started Jul 24 05:06:31 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 233596 kb
Host smart-5952df6e-35da-429b-a542-b3468c19e914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591139153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.591139153
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1505047659
Short name T6
Test name
Test status
Simulation time 496420843 ps
CPU time 11.33 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 233592 kb
Host smart-41767a4b-b9a3-4750-afaa-ce8e75d635ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505047659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1505047659
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1991361637
Short name T136
Test name
Test status
Simulation time 187872705 ps
CPU time 2.55 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 225420 kb
Host smart-721d9532-b90b-47d6-9259-a6a3735d4b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991361637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1991361637
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3543391320
Short name T594
Test name
Test status
Simulation time 37159908 ps
CPU time 2.38 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 233244 kb
Host smart-796bbe14-7e68-4d3b-9dd5-e5281e32604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543391320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3543391320
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1538216691
Short name T740
Test name
Test status
Simulation time 1288135211 ps
CPU time 4.39 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 223824 kb
Host smart-eb76efc8-ee20-4f41-bf31-c782d9b43ad0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1538216691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1538216691
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1566146421
Short name T437
Test name
Test status
Simulation time 15341540721 ps
CPU time 38 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:07:18 PM PDT 24
Peak memory 217072 kb
Host smart-fa7b6aad-ecb8-4a46-af89-439feac92c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566146421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1566146421
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2605791623
Short name T872
Test name
Test status
Simulation time 6133748817 ps
CPU time 8.3 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:52 PM PDT 24
Peak memory 217144 kb
Host smart-630dd588-d962-4f23-a3f3-dee9728be4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605791623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2605791623
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1110667707
Short name T320
Test name
Test status
Simulation time 149606187 ps
CPU time 3.14 seconds
Started Jul 24 05:06:24 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 217192 kb
Host smart-ecb15182-1336-41e5-8441-a77e78cd3b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110667707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1110667707
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1153822419
Short name T718
Test name
Test status
Simulation time 97785575 ps
CPU time 0.8 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:06:28 PM PDT 24
Peak memory 206780 kb
Host smart-0cc5ccda-81d0-4045-8bb1-1758f7796641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153822419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1153822419
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3273230931
Short name T860
Test name
Test status
Simulation time 105076252 ps
CPU time 2 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 225060 kb
Host smart-afded5e2-968f-4d95-8349-3be1ac39092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273230931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3273230931
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3612983077
Short name T455
Test name
Test status
Simulation time 10874774 ps
CPU time 0.69 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 206120 kb
Host smart-52a5864c-a520-44b4-b611-51fadf849f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612983077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3612983077
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1866168969
Short name T434
Test name
Test status
Simulation time 123882538 ps
CPU time 2.45 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:32 PM PDT 24
Peak memory 233640 kb
Host smart-e812bee2-627c-401c-bd10-aabec7b02612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866168969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1866168969
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.612048672
Short name T338
Test name
Test status
Simulation time 14712763 ps
CPU time 0.77 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 207612 kb
Host smart-67691a6d-ffb4-4bd0-bf65-b497b817ec9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612048672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.612048672
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1306949833
Short name T570
Test name
Test status
Simulation time 2015316166 ps
CPU time 8.35 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 225436 kb
Host smart-16141012-53f2-428c-922c-bd8e1005e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306949833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1306949833
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3191819013
Short name T925
Test name
Test status
Simulation time 3359042918 ps
CPU time 67.25 seconds
Started Jul 24 05:07:00 PM PDT 24
Finished Jul 24 05:08:07 PM PDT 24
Peak memory 250068 kb
Host smart-8b03e10b-9c7d-4c44-8d24-bf7a8d078d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191819013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3191819013
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2662763463
Short name T1025
Test name
Test status
Simulation time 111547620 ps
CPU time 3 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:32 PM PDT 24
Peak memory 225276 kb
Host smart-09c0dd3b-d42d-440e-b78a-48c98bd5cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662763463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2662763463
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1884932572
Short name T93
Test name
Test status
Simulation time 21315552659 ps
CPU time 155.91 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:09:17 PM PDT 24
Peak memory 252444 kb
Host smart-9cd8583c-cb97-43c1-8ed6-689c4a504c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884932572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1884932572
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3474138144
Short name T417
Test name
Test status
Simulation time 610558651 ps
CPU time 10.46 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 225348 kb
Host smart-1dfdee4c-0873-4da0-a1aa-f5574ffb8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474138144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3474138144
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2061362422
Short name T760
Test name
Test status
Simulation time 14247679547 ps
CPU time 19.41 seconds
Started Jul 24 05:06:25 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 225520 kb
Host smart-1bb3cc1c-9c92-4c45-9d75-281176cc7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061362422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2061362422
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3557646695
Short name T933
Test name
Test status
Simulation time 1759238795 ps
CPU time 7.06 seconds
Started Jul 24 05:06:31 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 240272 kb
Host smart-270e8170-e9e5-4bc0-9705-e8c1c7eb33c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557646695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3557646695
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.888618663
Short name T466
Test name
Test status
Simulation time 36020513266 ps
CPU time 20 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 233704 kb
Host smart-60512fcc-54e7-4894-ad1e-abd10ada31ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888618663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.888618663
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2086338152
Short name T684
Test name
Test status
Simulation time 689142081 ps
CPU time 6.42 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:06:54 PM PDT 24
Peak memory 221320 kb
Host smart-6a5d446f-f4e4-4e20-916c-a70713a1b6df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2086338152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2086338152
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1077143096
Short name T382
Test name
Test status
Simulation time 1060407945 ps
CPU time 1.06 seconds
Started Jul 24 05:06:26 PM PDT 24
Finished Jul 24 05:06:27 PM PDT 24
Peak memory 208580 kb
Host smart-07dc6511-5c32-48a8-bb15-cf173babd2b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077143096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1077143096
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.238754863
Short name T828
Test name
Test status
Simulation time 18049691889 ps
CPU time 22.04 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 217192 kb
Host smart-4e2de4a0-c81b-4e84-93bd-63d107942cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238754863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.238754863
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2795085572
Short name T787
Test name
Test status
Simulation time 674944106 ps
CPU time 3.56 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 217064 kb
Host smart-aaacb3fb-831a-43de-b010-f7061ed87c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795085572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2795085572
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.898406225
Short name T641
Test name
Test status
Simulation time 99665741 ps
CPU time 1.45 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 209008 kb
Host smart-9381f3cc-2d08-43ac-ae91-208cfab4754f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898406225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.898406225
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3925069968
Short name T781
Test name
Test status
Simulation time 47853432 ps
CPU time 0.86 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:31 PM PDT 24
Peak memory 206664 kb
Host smart-1ad97c71-099c-4767-807f-d35a31593de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925069968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3925069968
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.907784696
Short name T596
Test name
Test status
Simulation time 8184817075 ps
CPU time 27.62 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 250284 kb
Host smart-ee749e59-1e21-4a84-a67f-d2fb75b8ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907784696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.907784696
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.17768994
Short name T910
Test name
Test status
Simulation time 23642922 ps
CPU time 0.81 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 206100 kb
Host smart-39d0f003-2780-4af8-bf3b-9cb60faee197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17768994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.17768994
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.301502810
Short name T993
Test name
Test status
Simulation time 544753508 ps
CPU time 5.17 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 233624 kb
Host smart-b6ec80a5-8c9e-4ba2-bc24-c42ed857ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301502810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.301502810
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3562860650
Short name T392
Test name
Test status
Simulation time 20909042 ps
CPU time 0.79 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 207188 kb
Host smart-ada05bb1-ef94-4166-8b61-7e14ab615281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562860650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3562860650
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2728410979
Short name T934
Test name
Test status
Simulation time 2608129458 ps
CPU time 13.6 seconds
Started Jul 24 05:06:47 PM PDT 24
Finished Jul 24 05:07:01 PM PDT 24
Peak memory 237176 kb
Host smart-dfae3861-ba85-425e-befc-e9f6cc3bd35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728410979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2728410979
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3249128065
Short name T255
Test name
Test status
Simulation time 23076639808 ps
CPU time 49.93 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:07:28 PM PDT 24
Peak memory 241648 kb
Host smart-88a7aaee-1294-46b6-8a8f-784aa4e173da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249128065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3249128065
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1867725076
Short name T179
Test name
Test status
Simulation time 4308082799 ps
CPU time 66.96 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:07:35 PM PDT 24
Peak memory 252512 kb
Host smart-a02242a1-cf06-4940-a7a4-bac586a4efe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867725076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1867725076
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4285343103
Short name T446
Test name
Test status
Simulation time 22455251308 ps
CPU time 14.9 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 237104 kb
Host smart-596da834-3469-4dbc-b028-99d698e04c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285343103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4285343103
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2984211978
Short name T346
Test name
Test status
Simulation time 2750578188 ps
CPU time 17.34 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 225544 kb
Host smart-51d6ac75-078a-4da6-b88f-4cfdde78c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984211978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2984211978
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1062934175
Short name T575
Test name
Test status
Simulation time 399775901 ps
CPU time 4.73 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 233648 kb
Host smart-3a1fe299-2521-457e-8d09-b42c3a385472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062934175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1062934175
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1521282756
Short name T753
Test name
Test status
Simulation time 6483766865 ps
CPU time 16.41 seconds
Started Jul 24 05:06:30 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 233636 kb
Host smart-1b796424-92be-4ef4-b95f-3f3ae4e266dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521282756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1521282756
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1161857568
Short name T868
Test name
Test status
Simulation time 1539809166 ps
CPU time 13.36 seconds
Started Jul 24 05:06:32 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 249984 kb
Host smart-3c4ac74c-6330-4164-9e5b-51903547c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161857568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1161857568
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1064241507
Short name T549
Test name
Test status
Simulation time 3646826513 ps
CPU time 16.38 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 249856 kb
Host smart-4f07cc7c-ac98-405a-9ae9-27b324bdd8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064241507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1064241507
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3040841415
Short name T835
Test name
Test status
Simulation time 556406561 ps
CPU time 3.57 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 220164 kb
Host smart-2a8ee6fe-6539-43ac-ad9e-dca988d0108a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040841415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3040841415
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.536102299
Short name T271
Test name
Test status
Simulation time 107666523824 ps
CPU time 541.68 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:15:45 PM PDT 24
Peak memory 270692 kb
Host smart-8d2376f5-e76b-40f4-a206-930d539aed4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536102299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.536102299
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1647403136
Short name T712
Test name
Test status
Simulation time 5247286348 ps
CPU time 16.45 seconds
Started Jul 24 05:06:31 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 217180 kb
Host smart-a6748c80-613c-4d1f-9a91-300424f371e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647403136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1647403136
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4169959038
Short name T342
Test name
Test status
Simulation time 494309438 ps
CPU time 4.2 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 217156 kb
Host smart-b5ce79d9-8526-4e01-b256-9fc1dcb0221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169959038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4169959038
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3255198476
Short name T4
Test name
Test status
Simulation time 13108187 ps
CPU time 0.76 seconds
Started Jul 24 05:06:33 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 206764 kb
Host smart-0eb65f80-a707-4fe6-9054-619c11563d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255198476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3255198476
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3227606941
Short name T458
Test name
Test status
Simulation time 22789766 ps
CPU time 0.74 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 206756 kb
Host smart-43fe628e-65f8-45b9-aeba-b1a19f6a661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227606941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3227606941
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.508456758
Short name T226
Test name
Test status
Simulation time 3019357419 ps
CPU time 8.54 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 241712 kb
Host smart-6a440bda-9c59-4971-91d2-09c193502fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508456758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.508456758
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1060092430
Short name T337
Test name
Test status
Simulation time 45284289 ps
CPU time 0.78 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 206028 kb
Host smart-d647e546-0e70-428d-af2d-58ba9be2fd26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060092430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1060092430
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2673569681
Short name T655
Test name
Test status
Simulation time 677205210 ps
CPU time 2.24 seconds
Started Jul 24 05:06:46 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 224848 kb
Host smart-c01b8941-dd6a-4be0-bb20-f639326b3ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673569681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2673569681
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2723396076
Short name T722
Test name
Test status
Simulation time 14086689 ps
CPU time 0.74 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:51 PM PDT 24
Peak memory 207248 kb
Host smart-6e9afff8-ae0b-4ccd-aa36-4aac9f8232e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723396076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2723396076
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.575217436
Short name T1009
Test name
Test status
Simulation time 5757344661 ps
CPU time 21.63 seconds
Started Jul 24 05:06:38 PM PDT 24
Finished Jul 24 05:07:00 PM PDT 24
Peak memory 241924 kb
Host smart-2eeab20a-6c04-4652-9ead-89a12df6fb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575217436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.575217436
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3016421584
Short name T620
Test name
Test status
Simulation time 159818260790 ps
CPU time 275.07 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:11:25 PM PDT 24
Peak memory 257396 kb
Host smart-cb86684f-da39-45c9-b1a5-0a3126daa396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016421584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3016421584
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2703317611
Short name T244
Test name
Test status
Simulation time 7702810611 ps
CPU time 40.55 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:07:17 PM PDT 24
Peak memory 250220 kb
Host smart-96a5c37b-0285-457f-96b3-e5d03c062dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703317611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2703317611
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1008632386
Short name T721
Test name
Test status
Simulation time 160170377 ps
CPU time 4.91 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 233640 kb
Host smart-f706a8fb-c839-488a-b269-5ef9fdc43466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008632386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1008632386
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.347199079
Short name T421
Test name
Test status
Simulation time 11711828289 ps
CPU time 20.01 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:07:05 PM PDT 24
Peak memory 253104 kb
Host smart-b4ad5093-7ed1-4c83-8340-1c35c0248556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347199079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.347199079
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.143237630
Short name T551
Test name
Test status
Simulation time 10059382964 ps
CPU time 14.29 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:07:04 PM PDT 24
Peak memory 225520 kb
Host smart-b931ba86-3c3a-46d7-8078-326c6a8cb58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143237630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.143237630
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1490878226
Short name T607
Test name
Test status
Simulation time 3549190638 ps
CPU time 28.57 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:07:06 PM PDT 24
Peak memory 225536 kb
Host smart-2d39743a-46ab-4d4f-b14a-a74334a5f49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490878226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1490878226
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1919027093
Short name T259
Test name
Test status
Simulation time 11426683642 ps
CPU time 10.74 seconds
Started Jul 24 05:06:32 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 233708 kb
Host smart-c44c7235-7e7f-451a-9239-c1a5867385cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919027093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1919027093
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2920364266
Short name T857
Test name
Test status
Simulation time 384021541 ps
CPU time 2.39 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 225260 kb
Host smart-5cadfafc-8ff5-4293-a287-4daa65e3327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920364266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2920364266
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.454569288
Short name T955
Test name
Test status
Simulation time 333818923 ps
CPU time 6.41 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 223060 kb
Host smart-455bcbdb-332f-44dd-babb-19d2e58269ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454569288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.454569288
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3624226654
Short name T15
Test name
Test status
Simulation time 298222074 ps
CPU time 1.12 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 216656 kb
Host smart-3984bff4-43f2-47a6-a4e0-4ca177346110
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624226654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3624226654
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.924648528
Short name T852
Test name
Test status
Simulation time 16740644 ps
CPU time 0.73 seconds
Started Jul 24 05:06:46 PM PDT 24
Finished Jul 24 05:06:48 PM PDT 24
Peak memory 206392 kb
Host smart-81530572-aabf-4b60-9d0a-dae5da7b75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924648528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.924648528
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3919482789
Short name T444
Test name
Test status
Simulation time 26255962541 ps
CPU time 17.9 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:59 PM PDT 24
Peak memory 217224 kb
Host smart-c8440756-fa7e-42f4-add9-9d897a218072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919482789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3919482789
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2746089665
Short name T898
Test name
Test status
Simulation time 14900347 ps
CPU time 0.84 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 207796 kb
Host smart-72df9beb-f46d-438a-8fee-06989cc08efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746089665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2746089665
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.937463253
Short name T773
Test name
Test status
Simulation time 24114686 ps
CPU time 0.77 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 206732 kb
Host smart-9169c531-85e5-446e-a012-e91aec723613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937463253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.937463253
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3943588070
Short name T648
Test name
Test status
Simulation time 28712714095 ps
CPU time 23.04 seconds
Started Jul 24 05:06:39 PM PDT 24
Finished Jul 24 05:07:02 PM PDT 24
Peak memory 233676 kb
Host smart-b7bef594-b2bf-481c-95b4-079bbd868b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943588070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3943588070
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2409501599
Short name T347
Test name
Test status
Simulation time 79547306 ps
CPU time 0.72 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 206420 kb
Host smart-15a11f3e-cc38-4065-a18c-02e0e4625e05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409501599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2409501599
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1854697710
Short name T676
Test name
Test status
Simulation time 136965687 ps
CPU time 2.26 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:43 PM PDT 24
Peak memory 224336 kb
Host smart-00521934-bfc8-437f-af7f-43c5a4f39569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854697710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1854697710
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3682633135
Short name T775
Test name
Test status
Simulation time 18230547 ps
CPU time 0.74 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 206212 kb
Host smart-f128d32d-1733-4c88-a6aa-476e44b6bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682633135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3682633135
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2097042528
Short name T812
Test name
Test status
Simulation time 15073610129 ps
CPU time 100.79 seconds
Started Jul 24 05:06:52 PM PDT 24
Finished Jul 24 05:08:32 PM PDT 24
Peak memory 241844 kb
Host smart-f26096f5-005c-46cd-b000-5927401ed4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097042528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2097042528
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.843652911
Short name T664
Test name
Test status
Simulation time 28788859423 ps
CPU time 113.34 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:08:30 PM PDT 24
Peak memory 250180 kb
Host smart-063902eb-1306-4fb5-bf6b-2c2eecc5cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843652911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.843652911
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2204120732
Short name T218
Test name
Test status
Simulation time 98178001738 ps
CPU time 214.01 seconds
Started Jul 24 05:06:22 PM PDT 24
Finished Jul 24 05:09:56 PM PDT 24
Peak memory 254496 kb
Host smart-7cb00ada-ed93-4e74-9c81-99ead1d97b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204120732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2204120732
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1607504655
Short name T327
Test name
Test status
Simulation time 118312182 ps
CPU time 2.48 seconds
Started Jul 24 05:06:34 PM PDT 24
Finished Jul 24 05:06:37 PM PDT 24
Peak memory 233512 kb
Host smart-a52a9783-6726-4eb1-8672-aa9ccdb6ac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607504655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1607504655
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3613501894
Short name T492
Test name
Test status
Simulation time 21027972501 ps
CPU time 173.01 seconds
Started Jul 24 05:06:28 PM PDT 24
Finished Jul 24 05:09:26 PM PDT 24
Peak memory 252780 kb
Host smart-87d7ec6f-ca56-4bbf-a520-50a94eb239dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613501894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3613501894
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2598029271
Short name T67
Test name
Test status
Simulation time 2407473195 ps
CPU time 28.02 seconds
Started Jul 24 05:06:43 PM PDT 24
Finished Jul 24 05:07:12 PM PDT 24
Peak memory 225500 kb
Host smart-400ce7b8-54b0-43ee-bd7f-2c317f6c9bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598029271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2598029271
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3798375043
Short name T782
Test name
Test status
Simulation time 71720463 ps
CPU time 2.54 seconds
Started Jul 24 05:06:35 PM PDT 24
Finished Jul 24 05:06:38 PM PDT 24
Peak memory 233548 kb
Host smart-9c7dd7ac-e15c-4ae3-85ab-54f2aaaf07c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798375043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3798375043
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.124382899
Short name T604
Test name
Test status
Simulation time 736784790 ps
CPU time 4.84 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 233620 kb
Host smart-c2e6d6f4-dca3-479f-b634-4161ceaaf411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124382899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.124382899
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1407702349
Short name T540
Test name
Test status
Simulation time 48725305129 ps
CPU time 18.95 seconds
Started Jul 24 05:07:06 PM PDT 24
Finished Jul 24 05:07:25 PM PDT 24
Peak memory 240252 kb
Host smart-3c184a5d-3742-4624-8ff4-a3fd4289c7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407702349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1407702349
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3959999678
Short name T430
Test name
Test status
Simulation time 1470091811 ps
CPU time 9.89 seconds
Started Jul 24 05:06:46 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 223144 kb
Host smart-0693db57-a736-462e-913d-c734f4585fd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3959999678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3959999678
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2624411973
Short name T278
Test name
Test status
Simulation time 507887789912 ps
CPU time 745.4 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:19:15 PM PDT 24
Peak memory 270432 kb
Host smart-bc89f46d-7ba3-4869-a893-518d730b88fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624411973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2624411973
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1447773683
Short name T913
Test name
Test status
Simulation time 1343727300 ps
CPU time 5.25 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 219248 kb
Host smart-933f93f0-e8ec-4a06-b9ef-44f900b00d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447773683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1447773683
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2672125492
Short name T387
Test name
Test status
Simulation time 20859455290 ps
CPU time 14.23 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:56 PM PDT 24
Peak memory 217280 kb
Host smart-cd1fd248-6987-4efc-82f3-3d9a113f345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672125492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2672125492
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1804195947
Short name T695
Test name
Test status
Simulation time 34483703 ps
CPU time 0.86 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:06:46 PM PDT 24
Peak memory 207608 kb
Host smart-e63f4b29-3dfb-4370-9fa8-55a3829aef4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804195947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1804195947
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1985381037
Short name T914
Test name
Test status
Simulation time 137029980 ps
CPU time 0.83 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 207824 kb
Host smart-fdeb3d04-5523-45a9-9392-83d2b2d9dcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985381037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1985381037
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3435964981
Short name T192
Test name
Test status
Simulation time 344243390 ps
CPU time 3.05 seconds
Started Jul 24 05:06:37 PM PDT 24
Finished Jul 24 05:06:40 PM PDT 24
Peak memory 233700 kb
Host smart-ffa161fc-5ffc-4094-bc1c-a915061cbe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435964981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3435964981
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4034664851
Short name T716
Test name
Test status
Simulation time 44876245 ps
CPU time 0.72 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:30 PM PDT 24
Peak memory 205400 kb
Host smart-95f9c172-896e-4033-b0e4-f2b4da0533fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034664851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4034664851
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.641346120
Short name T410
Test name
Test status
Simulation time 755365852 ps
CPU time 3.55 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:57 PM PDT 24
Peak memory 233696 kb
Host smart-ba198c65-ab34-4e32-916d-671808554024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641346120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.641346120
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1417980078
Short name T780
Test name
Test status
Simulation time 36488317 ps
CPU time 0.79 seconds
Started Jul 24 05:06:42 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 207568 kb
Host smart-9404e302-a8d4-4792-83d3-04144bbcef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417980078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1417980078
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3561482928
Short name T873
Test name
Test status
Simulation time 1425349130 ps
CPU time 4.56 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:49 PM PDT 24
Peak memory 225436 kb
Host smart-28d41683-ee95-4036-823f-d025f3feb658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561482928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3561482928
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1085813831
Short name T286
Test name
Test status
Simulation time 10573517858 ps
CPU time 70.34 seconds
Started Jul 24 05:06:45 PM PDT 24
Finished Jul 24 05:07:56 PM PDT 24
Peak memory 263312 kb
Host smart-771c3ad7-f3cc-458d-9fe7-27196cf92560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085813831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1085813831
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2383031817
Short name T408
Test name
Test status
Simulation time 4755021317 ps
CPU time 66.38 seconds
Started Jul 24 05:06:55 PM PDT 24
Finished Jul 24 05:08:02 PM PDT 24
Peak memory 233544 kb
Host smart-d51b1d38-3ca3-4915-acb3-e381ecbd6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383031817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2383031817
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.81109483
Short name T263
Test name
Test status
Simulation time 458609083 ps
CPU time 13.5 seconds
Started Jul 24 05:06:44 PM PDT 24
Finished Jul 24 05:06:58 PM PDT 24
Peak memory 236356 kb
Host smart-55d257e0-da9d-4ddb-9bb9-a40eff163e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81109483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.81109483
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2417469912
Short name T245
Test name
Test status
Simulation time 9576276320 ps
CPU time 22.77 seconds
Started Jul 24 05:06:19 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 225396 kb
Host smart-eef37138-4f1a-4177-8c88-3d6321099e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417469912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2417469912
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.721560065
Short name T464
Test name
Test status
Simulation time 24334254206 ps
CPU time 53.4 seconds
Started Jul 24 05:06:27 PM PDT 24
Finished Jul 24 05:07:21 PM PDT 24
Peak memory 249816 kb
Host smart-c62d745a-f295-4368-8a67-31a31f501daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721560065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.721560065
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.477613401
Short name T671
Test name
Test status
Simulation time 65416955 ps
CPU time 2.53 seconds
Started Jul 24 05:06:41 PM PDT 24
Finished Jul 24 05:06:44 PM PDT 24
Peak memory 233552 kb
Host smart-f834d08b-4907-4576-8e6c-fea8e9fbb893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477613401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.477613401
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3385417928
Short name T390
Test name
Test status
Simulation time 1447157930 ps
CPU time 6.42 seconds
Started Jul 24 05:06:40 PM PDT 24
Finished Jul 24 05:06:47 PM PDT 24
Peak memory 225408 kb
Host smart-3f23624c-c08f-4564-a28f-86e94222332b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385417928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3385417928
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4088762168
Short name T529
Test name
Test status
Simulation time 3495596436 ps
CPU time 8.59 seconds
Started Jul 24 05:06:36 PM PDT 24
Finished Jul 24 05:06:45 PM PDT 24
Peak memory 221612 kb
Host smart-19047593-ba5d-4587-a66c-c59cce506990
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4088762168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4088762168
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.50926673
Short name T801
Test name
Test status
Simulation time 17224273708 ps
CPU time 33.44 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:07:24 PM PDT 24
Peak memory 233728 kb
Host smart-d7bb4995-2ba3-4e18-9936-f3fc82cafe8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50926673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.50926673
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.141841976
Short name T530
Test name
Test status
Simulation time 1747506737 ps
CPU time 15.93 seconds
Started Jul 24 05:06:39 PM PDT 24
Finished Jul 24 05:06:55 PM PDT 24
Peak memory 217160 kb
Host smart-a444708a-a0d2-45bc-a1e3-1a236af4c8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141841976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.141841976
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2262521308
Short name T891
Test name
Test status
Simulation time 342270723 ps
CPU time 2.15 seconds
Started Jul 24 05:06:39 PM PDT 24
Finished Jul 24 05:06:41 PM PDT 24
Peak memory 217216 kb
Host smart-feebd1f8-9dc0-4b8c-9194-57e4c3d6fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262521308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2262521308
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1264674519
Short name T915
Test name
Test status
Simulation time 401976262 ps
CPU time 2.17 seconds
Started Jul 24 05:06:50 PM PDT 24
Finished Jul 24 05:06:53 PM PDT 24
Peak memory 217140 kb
Host smart-3210cdee-c2eb-466d-83db-30a10165b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264674519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1264674519
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3615830999
Short name T747
Test name
Test status
Simulation time 1221438904 ps
CPU time 0.95 seconds
Started Jul 24 05:06:49 PM PDT 24
Finished Jul 24 05:06:50 PM PDT 24
Peak memory 207864 kb
Host smart-db5b8657-61c8-48df-8460-b1bdb4996084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615830999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3615830999
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2581139983
Short name T242
Test name
Test status
Simulation time 1174597096 ps
CPU time 5.62 seconds
Started Jul 24 05:06:29 PM PDT 24
Finished Jul 24 05:06:34 PM PDT 24
Peak memory 233664 kb
Host smart-9cd0fa90-3228-4619-92f0-68a5f6108491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581139983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2581139983
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1671389737
Short name T982
Test name
Test status
Simulation time 66106915 ps
CPU time 0.69 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 205940 kb
Host smart-949c3821-bf89-4754-8005-8dd37ed72e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671389737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
671389737
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1662274202
Short name T920
Test name
Test status
Simulation time 1152213114 ps
CPU time 4.59 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:08 PM PDT 24
Peak memory 233516 kb
Host smart-1ff02b9c-b63d-4f9c-87e3-bb038661dbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662274202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1662274202
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2563239042
Short name T438
Test name
Test status
Simulation time 17135506 ps
CPU time 0.76 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:46 PM PDT 24
Peak memory 207580 kb
Host smart-2ec40e02-bd28-4007-b12d-1a1de99a032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563239042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2563239042
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.788196447
Short name T39
Test name
Test status
Simulation time 3914140426 ps
CPU time 49.64 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:05:40 PM PDT 24
Peak memory 251376 kb
Host smart-d59fb420-61f6-49e9-85be-c18418f87847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788196447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.788196447
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1152020444
Short name T422
Test name
Test status
Simulation time 822884076139 ps
CPU time 372.78 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:11:07 PM PDT 24
Peak memory 264484 kb
Host smart-7f5cffe2-bad1-45ef-b048-0a4d3f5033be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152020444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1152020444
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.943474602
Short name T275
Test name
Test status
Simulation time 63066526757 ps
CPU time 312.44 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:10:08 PM PDT 24
Peak memory 257736 kb
Host smart-b8ac2c4c-1661-4bd5-85e5-41350974a362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943474602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
943474602
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.810748610
Short name T419
Test name
Test status
Simulation time 4154426972 ps
CPU time 6.9 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:59 PM PDT 24
Peak memory 225372 kb
Host smart-f1e62591-5450-4812-97db-0ef3fba39cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810748610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.810748610
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3855212761
Short name T663
Test name
Test status
Simulation time 103540360325 ps
CPU time 157.42 seconds
Started Jul 24 05:04:35 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 250064 kb
Host smart-a8bd81de-d6e4-49d0-aca7-8c95beb64b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855212761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3855212761
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4289074173
Short name T944
Test name
Test status
Simulation time 792271033 ps
CPU time 3.27 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 225308 kb
Host smart-9a81eeb7-2fc0-4796-872d-90a08ba8d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289074173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4289074173
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2226021615
Short name T847
Test name
Test status
Simulation time 4964785154 ps
CPU time 32.26 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:05:26 PM PDT 24
Peak memory 241908 kb
Host smart-9166c36e-6dca-4bda-a1d8-433720608435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226021615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2226021615
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.531075057
Short name T785
Test name
Test status
Simulation time 26979344 ps
CPU time 1.01 seconds
Started Jul 24 05:04:31 PM PDT 24
Finished Jul 24 05:04:33 PM PDT 24
Peak memory 218712 kb
Host smart-8ed28a1c-10d5-4bb5-ba3f-8b574b003d58
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531075057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.531075057
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1759946209
Short name T52
Test name
Test status
Simulation time 583658332 ps
CPU time 2.72 seconds
Started Jul 24 05:04:33 PM PDT 24
Finished Jul 24 05:04:40 PM PDT 24
Peak memory 225364 kb
Host smart-6d7080c1-b8d6-474c-a7d4-dcc932287f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759946209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1759946209
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2289813433
Short name T360
Test name
Test status
Simulation time 2773058442 ps
CPU time 8.74 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 225412 kb
Host smart-637043fb-ac41-4806-99c8-2012f52bc4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289813433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2289813433
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.964154794
Short name T372
Test name
Test status
Simulation time 2837944390 ps
CPU time 10.58 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:04:57 PM PDT 24
Peak memory 222380 kb
Host smart-3466944d-5b26-4ec4-bed0-e4401a52dffe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=964154794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.964154794
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2476560516
Short name T975
Test name
Test status
Simulation time 142189286 ps
CPU time 0.9 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:04:54 PM PDT 24
Peak memory 206636 kb
Host smart-9238a08e-3ace-4f93-ad5b-3c1a62e8e22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476560516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2476560516
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.258735206
Short name T723
Test name
Test status
Simulation time 1882965414 ps
CPU time 28.98 seconds
Started Jul 24 05:04:42 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 217180 kb
Host smart-23e24a43-c372-444c-ad10-90cda12f3707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258735206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.258735206
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2430657418
Short name T413
Test name
Test status
Simulation time 526071086 ps
CPU time 1.67 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:04:56 PM PDT 24
Peak memory 207740 kb
Host smart-ba35e17b-1572-4149-993d-0fe15e641699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430657418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2430657418
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2327506819
Short name T819
Test name
Test status
Simulation time 48759457 ps
CPU time 1.03 seconds
Started Jul 24 05:04:54 PM PDT 24
Finished Jul 24 05:04:55 PM PDT 24
Peak memory 208508 kb
Host smart-50fe0183-961c-4e9b-9911-f689126d3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327506819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2327506819
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4088094771
Short name T763
Test name
Test status
Simulation time 77708582 ps
CPU time 0.97 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 206816 kb
Host smart-de352ccb-b390-42c4-8106-de65b75c8d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088094771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4088094771
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.843446874
Short name T951
Test name
Test status
Simulation time 1789745139 ps
CPU time 5.19 seconds
Started Jul 24 05:04:45 PM PDT 24
Finished Jul 24 05:04:51 PM PDT 24
Peak memory 237952 kb
Host smart-82fb5122-fbf0-4b44-8661-365b86171900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843446874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.843446874
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2794992818
Short name T772
Test name
Test status
Simulation time 60808211 ps
CPU time 0.69 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 205508 kb
Host smart-465ec488-164a-4eef-ac75-eb54e39dfc26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794992818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
794992818
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2682622809
Short name T176
Test name
Test status
Simulation time 114407584 ps
CPU time 3.26 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:24 PM PDT 24
Peak memory 225476 kb
Host smart-56d2d90f-603d-4d72-8aed-04c707a4a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682622809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2682622809
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3868522759
Short name T365
Test name
Test status
Simulation time 111194219 ps
CPU time 0.73 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 206268 kb
Host smart-da59d793-59da-44ca-8dbe-64ecaeb2547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868522759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3868522759
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2558035356
Short name T1
Test name
Test status
Simulation time 77761383366 ps
CPU time 149.4 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:07:38 PM PDT 24
Peak memory 251788 kb
Host smart-c233c33a-9d48-48d3-aecf-ee9958ef0b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558035356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2558035356
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1131838299
Short name T592
Test name
Test status
Simulation time 2733327476 ps
CPU time 52.61 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:53 PM PDT 24
Peak memory 252480 kb
Host smart-7de6f3a4-fe34-4c92-aad4-79ae0f405e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131838299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1131838299
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3303771838
Short name T563
Test name
Test status
Simulation time 23401663514 ps
CPU time 25.62 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:05:21 PM PDT 24
Peak memory 218344 kb
Host smart-2f5c7681-fd49-4853-9a76-88e3aa5b1a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303771838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3303771838
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.728086262
Short name T634
Test name
Test status
Simulation time 41091564 ps
CPU time 2.36 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:03 PM PDT 24
Peak memory 233576 kb
Host smart-a25a1ddb-3e06-4fb3-835d-5525f9d9c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728086262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.728086262
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1519959451
Short name T821
Test name
Test status
Simulation time 380178733102 ps
CPU time 250.82 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:09:09 PM PDT 24
Peak memory 258152 kb
Host smart-69d832a7-31fe-4ad5-b553-64a7d8aa3798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519959451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1519959451
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3717687264
Short name T834
Test name
Test status
Simulation time 1661882296 ps
CPU time 16.8 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 230332 kb
Host smart-9cba0e0f-2aed-4dae-b516-301189af827b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717687264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3717687264
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1687520350
Short name T555
Test name
Test status
Simulation time 219731218 ps
CPU time 2.34 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 225396 kb
Host smart-c2e6da14-fbfc-41c0-b899-fad3e247dd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687520350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1687520350
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.2660819687
Short name T602
Test name
Test status
Simulation time 131678223 ps
CPU time 1.07 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 217388 kb
Host smart-2dc14147-6a01-45d2-9eb1-10266b942dd8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660819687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.2660819687
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2545534257
Short name T739
Test name
Test status
Simulation time 1854671412 ps
CPU time 8.3 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 225444 kb
Host smart-98c20745-fdcf-454c-b16c-1c57cb995659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545534257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2545534257
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3504909743
Short name T627
Test name
Test status
Simulation time 8460296229 ps
CPU time 14.9 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:05:07 PM PDT 24
Peak memory 241784 kb
Host smart-c907e13d-f581-42aa-9665-e7415c365af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504909743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3504909743
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3338154923
Short name T804
Test name
Test status
Simulation time 172300743 ps
CPU time 4.27 seconds
Started Jul 24 05:05:10 PM PDT 24
Finished Jul 24 05:05:19 PM PDT 24
Peak memory 223012 kb
Host smart-a274cd78-301d-4744-94b3-3fe6cbe6f594
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3338154923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3338154923
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1974828660
Short name T289
Test name
Test status
Simulation time 659832158655 ps
CPU time 401.16 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:11:38 PM PDT 24
Peak memory 270996 kb
Host smart-01ea9d51-89a0-4cc4-a775-1b5038dde62e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974828660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1974828660
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2832512436
Short name T525
Test name
Test status
Simulation time 2205153017 ps
CPU time 19.58 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:18 PM PDT 24
Peak memory 217372 kb
Host smart-1e8b6b29-5bbb-4770-a0c8-b3db08430a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832512436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2832512436
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.463031311
Short name T761
Test name
Test status
Simulation time 1271026062 ps
CPU time 2.49 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 217204 kb
Host smart-24c80538-1954-42cc-922c-bf08f6d22db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463031311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.463031311
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2960749819
Short name T308
Test name
Test status
Simulation time 30183266 ps
CPU time 1.12 seconds
Started Jul 24 05:04:44 PM PDT 24
Finished Jul 24 05:04:45 PM PDT 24
Peak memory 208224 kb
Host smart-922e48d0-389c-4667-a107-515f016f98d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960749819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2960749819
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3818535275
Short name T606
Test name
Test status
Simulation time 20759595 ps
CPU time 0.74 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 206696 kb
Host smart-460d950c-edd5-4264-92bb-f59e857efd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818535275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3818535275
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2388745917
Short name T728
Test name
Test status
Simulation time 250287367 ps
CPU time 2.56 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:01 PM PDT 24
Peak memory 233536 kb
Host smart-2adf34ee-b716-4322-b0d6-788993700cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388745917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2388745917
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1837724316
Short name T851
Test name
Test status
Simulation time 23519807 ps
CPU time 0.71 seconds
Started Jul 24 05:04:47 PM PDT 24
Finished Jul 24 05:04:48 PM PDT 24
Peak memory 205496 kb
Host smart-1775af7a-9fb5-428f-871d-b56a9bcd7240
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837724316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
837724316
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2869003050
Short name T798
Test name
Test status
Simulation time 1128152300 ps
CPU time 2.25 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 225012 kb
Host smart-a8c3bf31-8008-461e-a0eb-304b3b8dbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869003050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2869003050
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.221286949
Short name T974
Test name
Test status
Simulation time 16958481 ps
CPU time 0.76 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 206144 kb
Host smart-096327cd-6a89-4f6c-9bca-ed5a3893fc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221286949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.221286949
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.62760464
Short name T903
Test name
Test status
Simulation time 4578752569 ps
CPU time 41.06 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:34 PM PDT 24
Peak memory 255324 kb
Host smart-8725e76e-a335-429c-8ef2-f626d0efbacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62760464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.62760464
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2243370928
Short name T36
Test name
Test status
Simulation time 5610373259 ps
CPU time 98.5 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:06:36 PM PDT 24
Peak memory 269120 kb
Host smart-d3cbe94e-37d6-4d77-ae69-a71655bfaadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243370928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2243370928
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2189925521
Short name T754
Test name
Test status
Simulation time 13794561145 ps
CPU time 101.8 seconds
Started Jul 24 05:04:41 PM PDT 24
Finished Jul 24 05:06:23 PM PDT 24
Peak memory 233772 kb
Host smart-e7ea38d5-41ad-41b4-bbab-5903337fc408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189925521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2189925521
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2551801491
Short name T23
Test name
Test status
Simulation time 2972923301 ps
CPU time 42.92 seconds
Started Jul 24 05:05:09 PM PDT 24
Finished Jul 24 05:05:52 PM PDT 24
Peak memory 251112 kb
Host smart-ed120f2c-b9c0-4e22-8608-eee5b11eac94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551801491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2551801491
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3470860450
Short name T449
Test name
Test status
Simulation time 24926820756 ps
CPU time 21.75 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:15 PM PDT 24
Peak memory 225416 kb
Host smart-b9c9134d-c3bb-45e6-97c6-e9dfc4034ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470860450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3470860450
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2401126001
Short name T853
Test name
Test status
Simulation time 3931125851 ps
CPU time 43.83 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:38 PM PDT 24
Peak memory 225544 kb
Host smart-2587009d-f4a1-4e1a-b2dd-c8311e9ef0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401126001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2401126001
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2517573947
Short name T545
Test name
Test status
Simulation time 30895822 ps
CPU time 1 seconds
Started Jul 24 05:05:08 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 218520 kb
Host smart-b6a2e3ef-7bef-4985-8119-bff3970ad1a6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517573947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2517573947
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2723079935
Short name T952
Test name
Test status
Simulation time 4649003601 ps
CPU time 14.27 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 241736 kb
Host smart-2e905937-ec46-46c7-8525-523382ea8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723079935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2723079935
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3776541071
Short name T730
Test name
Test status
Simulation time 6922636904 ps
CPU time 16.79 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 233596 kb
Host smart-ab39cb31-d0b7-4171-a756-21f622b08fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776541071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3776541071
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.797985727
Short name T595
Test name
Test status
Simulation time 11011117155 ps
CPU time 9.59 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:10 PM PDT 24
Peak memory 222772 kb
Host smart-817763ab-263a-4f8a-8c2f-3e5b0800adb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=797985727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.797985727
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2305240835
Short name T21
Test name
Test status
Simulation time 76906257263 ps
CPU time 347.12 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:10:40 PM PDT 24
Peak memory 258308 kb
Host smart-60222a21-10c9-4b4a-892f-d698f7e7b053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305240835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2305240835
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1765683647
Short name T307
Test name
Test status
Simulation time 3169680282 ps
CPU time 4.35 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:08 PM PDT 24
Peak memory 217156 kb
Host smart-b339c4e9-c9e5-4709-b2ef-1c244aa365d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765683647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1765683647
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.931008495
Short name T731
Test name
Test status
Simulation time 4903734664 ps
CPU time 6.72 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:04:55 PM PDT 24
Peak memory 217260 kb
Host smart-abbd878b-7126-41f8-846e-2bb324a26901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931008495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.931008495
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1240383941
Short name T584
Test name
Test status
Simulation time 56894320 ps
CPU time 1.56 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 217120 kb
Host smart-5de938b1-5900-4912-8a53-7c40251597c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240383941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1240383941
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1378881083
Short name T779
Test name
Test status
Simulation time 422102326 ps
CPU time 0.75 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 206684 kb
Host smart-82743444-2b86-4d16-a1e7-7f8902490821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378881083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1378881083
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1308085615
Short name T2
Test name
Test status
Simulation time 9391706277 ps
CPU time 27.6 seconds
Started Jul 24 05:04:57 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 233612 kb
Host smart-df9dc9ea-3f09-4413-8860-3c4e59bc70d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308085615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1308085615
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.786541681
Short name T335
Test name
Test status
Simulation time 137630149 ps
CPU time 0.71 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:04 PM PDT 24
Peak memory 205964 kb
Host smart-f5ef3067-de8d-451a-bd13-3ddb854f02f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786541681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.786541681
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2263262859
Short name T316
Test name
Test status
Simulation time 309035309 ps
CPU time 2.26 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:04:56 PM PDT 24
Peak memory 233204 kb
Host smart-c24f98b0-6dba-4bc6-9b36-79dc926dee86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263262859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2263262859
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4125298613
Short name T515
Test name
Test status
Simulation time 30851714 ps
CPU time 0.79 seconds
Started Jul 24 05:04:52 PM PDT 24
Finished Jul 24 05:04:53 PM PDT 24
Peak memory 207176 kb
Host smart-7d13fd5c-9026-4693-8e42-fd1109da1870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125298613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4125298613
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2330682506
Short name T998
Test name
Test status
Simulation time 240542511766 ps
CPU time 156.02 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:07:32 PM PDT 24
Peak memory 251632 kb
Host smart-21573bec-50f5-4652-a487-9ed4100e789d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330682506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2330682506
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.195423597
Short name T204
Test name
Test status
Simulation time 146902538459 ps
CPU time 198.46 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:08:08 PM PDT 24
Peak memory 256220 kb
Host smart-e460446a-742b-415e-ae06-8792f9d27af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195423597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.195423597
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2392903978
Short name T25
Test name
Test status
Simulation time 6397550420 ps
CPU time 39.21 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:05:31 PM PDT 24
Peak memory 225484 kb
Host smart-8a8ab5ac-2701-44cf-8311-8823cae738b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392903978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2392903978
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3781941036
Short name T301
Test name
Test status
Simulation time 104898115 ps
CPU time 4.46 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 233620 kb
Host smart-accfd191-db99-4d09-9cef-32ab166a1b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781941036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3781941036
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3731315520
Short name T58
Test name
Test status
Simulation time 97077396616 ps
CPU time 144.06 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:07:13 PM PDT 24
Peak memory 252672 kb
Host smart-619334bb-a24f-48e8-bc85-c229c33469e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731315520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3731315520
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4095824240
Short name T184
Test name
Test status
Simulation time 4720400959 ps
CPU time 12.59 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:16 PM PDT 24
Peak memory 220736 kb
Host smart-fdb8f1e9-ce98-43a6-ae06-a44c9e883a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095824240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4095824240
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3652300143
Short name T256
Test name
Test status
Simulation time 739023471 ps
CPU time 8.6 seconds
Started Jul 24 05:05:04 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 233652 kb
Host smart-93291aa8-83d7-41ff-86f4-62fad1476ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652300143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3652300143
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2338373749
Short name T670
Test name
Test status
Simulation time 66274011 ps
CPU time 1.05 seconds
Started Jul 24 05:04:49 PM PDT 24
Finished Jul 24 05:04:50 PM PDT 24
Peak memory 218632 kb
Host smart-1946540d-2a8e-42f5-8615-b7974bb9375d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338373749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2338373749
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2500055693
Short name T675
Test name
Test status
Simulation time 11720390195 ps
CPU time 16.97 seconds
Started Jul 24 05:05:05 PM PDT 24
Finished Jul 24 05:05:22 PM PDT 24
Peak memory 225476 kb
Host smart-29aa8cc5-5646-4a62-a8d0-ae482969733a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500055693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2500055693
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3305344206
Short name T405
Test name
Test status
Simulation time 487792090 ps
CPU time 3.47 seconds
Started Jul 24 05:04:51 PM PDT 24
Finished Jul 24 05:04:55 PM PDT 24
Peak memory 233592 kb
Host smart-22edb0c0-5e5d-4646-84c0-1feababa810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305344206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3305344206
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1530610515
Short name T358
Test name
Test status
Simulation time 4136447899 ps
CPU time 10.88 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:13 PM PDT 24
Peak memory 224020 kb
Host smart-2c28d2d0-b0fe-4e01-823e-87b4d88c8b60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530610515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1530610515
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2213302722
Short name T751
Test name
Test status
Simulation time 62894231955 ps
CPU time 314.7 seconds
Started Jul 24 05:04:48 PM PDT 24
Finished Jul 24 05:10:03 PM PDT 24
Peak memory 255576 kb
Host smart-cfdce5d7-46f0-42a6-a7ff-a0b01b6f2de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213302722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2213302722
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1123989350
Short name T816
Test name
Test status
Simulation time 6216553545 ps
CPU time 18.43 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:17 PM PDT 24
Peak memory 217216 kb
Host smart-4acd2503-da98-4d49-a8ed-26f01d18cfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123989350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1123989350
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2207810109
Short name T508
Test name
Test status
Simulation time 2536773743 ps
CPU time 3.86 seconds
Started Jul 24 05:04:55 PM PDT 24
Finished Jul 24 05:04:58 PM PDT 24
Peak memory 217244 kb
Host smart-ee497f57-1808-44b8-bd57-0ba2f9147bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207810109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2207810109
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.243393831
Short name T461
Test name
Test status
Simulation time 427599395 ps
CPU time 2.01 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 217152 kb
Host smart-fe515d88-8170-405a-86c0-dc9f5822c595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243393831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.243393831
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1563454433
Short name T698
Test name
Test status
Simulation time 159227431 ps
CPU time 0.79 seconds
Started Jul 24 05:04:46 PM PDT 24
Finished Jul 24 05:04:47 PM PDT 24
Peak memory 206776 kb
Host smart-64352658-e9f7-4bab-9be4-c14d3b3bf080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563454433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1563454433
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2565781970
Short name T473
Test name
Test status
Simulation time 38872251 ps
CPU time 2.55 seconds
Started Jul 24 05:05:03 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 233644 kb
Host smart-cd065621-d0b0-44d2-8e29-b82a1a4a5e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565781970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2565781970
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3097773632
Short name T651
Test name
Test status
Simulation time 16795871 ps
CPU time 0.7 seconds
Started Jul 24 05:05:40 PM PDT 24
Finished Jul 24 05:05:40 PM PDT 24
Peak memory 205988 kb
Host smart-17524390-7437-4bcc-af70-3d5bd67257c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097773632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
097773632
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.597273344
Short name T631
Test name
Test status
Simulation time 1992261159 ps
CPU time 19.14 seconds
Started Jul 24 05:05:06 PM PDT 24
Finished Jul 24 05:05:25 PM PDT 24
Peak memory 233696 kb
Host smart-36ddf9d2-ce1e-438a-ad43-44c0dd6dd1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597273344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.597273344
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3211622186
Short name T77
Test name
Test status
Simulation time 42552841 ps
CPU time 0.82 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:51 PM PDT 24
Peak memory 207444 kb
Host smart-92dcdc1a-34f8-4127-93f5-f74c55b8f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211622186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3211622186
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.250922807
Short name T330
Test name
Test status
Simulation time 61840647614 ps
CPU time 101.81 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:06:42 PM PDT 24
Peak memory 233636 kb
Host smart-fc6213d5-8b87-4698-82ac-625a395389c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250922807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.250922807
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3446034401
Short name T965
Test name
Test status
Simulation time 2711949081 ps
CPU time 14.71 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:05:11 PM PDT 24
Peak memory 218588 kb
Host smart-ab3cfc1a-684b-4a4c-a7d8-8693e108bd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446034401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3446034401
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1112808781
Short name T7
Test name
Test status
Simulation time 142468207 ps
CPU time 2.92 seconds
Started Jul 24 05:05:02 PM PDT 24
Finished Jul 24 05:05:05 PM PDT 24
Peak memory 233648 kb
Host smart-d94243b5-f2f6-44bc-8089-7ab2d4170944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112808781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1112808781
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.392887829
Short name T470
Test name
Test status
Simulation time 12698125539 ps
CPU time 40.26 seconds
Started Jul 24 05:05:01 PM PDT 24
Finished Jul 24 05:05:41 PM PDT 24
Peak memory 241896 kb
Host smart-01c20e34-81e8-4bbd-b4c5-66ae410047b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392887829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
392887829
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1944018850
Short name T233
Test name
Test status
Simulation time 5686161561 ps
CPU time 10.55 seconds
Started Jul 24 05:05:20 PM PDT 24
Finished Jul 24 05:05:31 PM PDT 24
Peak memory 225520 kb
Host smart-13a6e29c-324e-421d-8bad-60051260be81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944018850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1944018850
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4221655629
Short name T848
Test name
Test status
Simulation time 2242088479 ps
CPU time 9.92 seconds
Started Jul 24 05:04:56 PM PDT 24
Finished Jul 24 05:05:06 PM PDT 24
Peak memory 237492 kb
Host smart-63305852-fdb8-4f08-8641-932320514666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221655629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4221655629
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.989968887
Short name T511
Test name
Test status
Simulation time 25982534 ps
CPU time 1.02 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:00 PM PDT 24
Peak memory 217264 kb
Host smart-3dee9a82-4f84-4256-8686-e4563a7f1eb5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989968887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.989968887
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.476817307
Short name T654
Test name
Test status
Simulation time 6344271760 ps
CPU time 8.19 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:09 PM PDT 24
Peak memory 234736 kb
Host smart-2747c7bb-c531-4c5d-93b7-9715dbc3c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476817307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
476817307
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.436731413
Short name T696
Test name
Test status
Simulation time 1284196163 ps
CPU time 3.56 seconds
Started Jul 24 05:04:58 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 225328 kb
Host smart-6a439aba-757f-4bbc-9ac0-c637acec0ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436731413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.436731413
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3776266648
Short name T146
Test name
Test status
Simulation time 1156337857 ps
CPU time 8.7 seconds
Started Jul 24 05:04:53 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 221356 kb
Host smart-e5c148c6-a3c4-462a-b7d0-69ba771c118c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3776266648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3776266648
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4003590317
Short name T163
Test name
Test status
Simulation time 53577857758 ps
CPU time 383.62 seconds
Started Jul 24 05:05:07 PM PDT 24
Finished Jul 24 05:11:31 PM PDT 24
Peak memory 266476 kb
Host smart-d83ec2c8-4148-4ed1-9219-9ae23eb72011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003590317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4003590317
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.564606609
Short name T528
Test name
Test status
Simulation time 15240441142 ps
CPU time 19.44 seconds
Started Jul 24 05:05:00 PM PDT 24
Finished Jul 24 05:05:20 PM PDT 24
Peak memory 217072 kb
Host smart-1ea2a8c4-257c-4a5a-97be-fb73ad0cd64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564606609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.564606609
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3308575872
Short name T809
Test name
Test status
Simulation time 298622712 ps
CPU time 2.24 seconds
Started Jul 24 05:04:59 PM PDT 24
Finished Jul 24 05:05:02 PM PDT 24
Peak memory 217104 kb
Host smart-510d9144-9d71-4461-964d-d88c797bcaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308575872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3308575872
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3802758508
Short name T331
Test name
Test status
Simulation time 242141761 ps
CPU time 1.57 seconds
Started Jul 24 05:04:50 PM PDT 24
Finished Jul 24 05:04:52 PM PDT 24
Peak memory 217328 kb
Host smart-bf9bf44f-7ba0-4e47-9705-003135214272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802758508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3802758508
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3635394513
Short name T859
Test name
Test status
Simulation time 19324550 ps
CPU time 0.73 seconds
Started Jul 24 05:05:14 PM PDT 24
Finished Jul 24 05:05:15 PM PDT 24
Peak memory 206812 kb
Host smart-41311715-67b8-4182-b79c-0b260ffdd93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635394513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3635394513
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1158660354
Short name T268
Test name
Test status
Simulation time 1949780662 ps
CPU time 5.32 seconds
Started Jul 24 05:05:23 PM PDT 24
Finished Jul 24 05:05:28 PM PDT 24
Peak memory 241784 kb
Host smart-a5da1df5-eb98-402d-802f-4f872187888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158660354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1158660354
Directory /workspace/9.spi_device_upload/latest
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