Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3000387	1			T1	2664		T2	1		T3	1949
all_values[1]	3000387	1			T1	2664		T2	1		T3	1949
all_values[2]	3000387	1			T1	2664		T2	1		T3	1949
all_values[3]	3000387	1			T1	2664		T2	1		T3	1949
all_values[4]	3000387	1			T1	2664		T2	1		T3	1949
all_values[5]	3000387	1			T1	2664		T2	1		T3	1949
all_values[6]	3000387	1			T1	2664		T2	1		T3	1949
all_values[7]	3000387	1			T1	2664		T2	1		T3	1949

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23197595

1

T1

21312

T2

8

T3

15592

auto[1]

805501

1

T13

26

T15

42

T17

142

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23972209

1

T1

21312

T2

8

T3

15477

auto[1]

30887

1

T3

115

T11

423

T12

964

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2930187	1			T1	2664		T2	1		T3	1863
all_values[0]	auto[0]	auto[1]	14882	1			T3	86		T11	255		T12	545
all_values[0]	auto[1]	auto[0]	55017	1			T13	2		T15	1		T17	10
all_values[0]	auto[1]	auto[1]	301	1			T17	8		T160	109		T146	5
all_values[1]	auto[0]	auto[0]	2879956	1			T1	2664		T2	1		T3	1928
all_values[1]	auto[0]	auto[1]	10018	1			T3	21		T11	116		T12	308
all_values[1]	auto[1]	auto[0]	110110	1			T13	3		T17	12		T19	5
all_values[1]	auto[1]	auto[1]	303	1			T15	4		T17	6		T146	4
all_values[2]	auto[0]	auto[0]	2932511	1			T1	2664		T2	1		T3	1941
all_values[2]	auto[0]	auto[1]	3422	1			T3	8		T11	52		T12	111
all_values[2]	auto[1]	auto[0]	64182	1			T13	4		T15	7		T17	11
all_values[2]	auto[1]	auto[1]	272	1			T13	1		T15	1		T17	2
all_values[3]	auto[0]	auto[0]	2833009	1			T1	2664		T2	1		T3	1949
all_values[3]	auto[0]	auto[1]	149	1			T15	3		T17	7		T160	2
all_values[3]	auto[1]	auto[0]	167035	1			T13	3		T15	3		T17	13
all_values[3]	auto[1]	auto[1]	194	1			T13	2		T15	3		T17	10
all_values[4]	auto[0]	auto[0]	2924739	1			T1	2664		T2	1		T3	1949
all_values[4]	auto[0]	auto[1]	168	1			T15	4		T136	1		T139	2
all_values[4]	auto[1]	auto[0]	75292	1			T17	16		T19	3		T48	1
all_values[4]	auto[1]	auto[1]	188	1			T13	2		T15	3		T17	5
all_values[5]	auto[0]	auto[0]	2889286	1			T1	2664		T2	1		T3	1949
all_values[5]	auto[0]	auto[1]	158	1			T13	1		T15	3		T17	9
all_values[5]	auto[1]	auto[0]	110766	1			T15	4		T17	5		T19	3
all_values[5]	auto[1]	auto[1]	177	1			T13	2		T15	1		T17	9
all_values[6]	auto[0]	auto[0]	2842710	1			T1	2664		T2	1		T3	1949
all_values[6]	auto[0]	auto[1]	180	1			T15	1		T17	10		T48	2
all_values[6]	auto[1]	auto[0]	157345	1			T13	5		T15	6		T17	7
all_values[6]	auto[1]	auto[1]	152	1			T15	2		T17	8		T19	1
all_values[7]	auto[0]	auto[0]	2936053	1			T1	2664		T2	1		T3	1949
all_values[7]	auto[0]	auto[1]	167	1			T15	2		T17	9		T19	3
all_values[7]	auto[1]	auto[0]	64011	1			T13	2		T15	6		T17	14
all_values[7]	auto[1]	auto[1]	156	1			T15	1		T17	6		T19	3