Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33826	1			T2	4		T3	82		T4	20
auto[SpiFlashAddrCfg]	7814	1			T3	23		T4	10		T7	1
auto[SpiFlashAddr3b]	9181	1			T3	24		T4	8		T9	3
auto[SpiFlashAddr4b]	7825	1			T3	16		T4	2		T7	1

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33858

1

T2

4

T3

84

T4

22

auto[1]

24788

1

T3

61

T4

18

T10

8

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31388

1

T3

72

T4

33

T7

1

auto[1]

27258

1

T2

4

T3

73

T4

7

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38558	1			T2	4		T3	96		T4	19
values[1]	1071	1			T11	5		T12	11		T25	7
values[2]	1589	1			T3	1		T4	1		T8	2
values[3]	1589	1			T3	9		T4	2		T11	10
values[4]	1461	1			T3	1		T4	1		T11	4
values[5]	1497	1			T3	2		T4	3		T11	4
values[6]	1456	1			T3	2		T4	2		T11	4
values[7]	1480	1			T3	2		T4	2		T11	5
values[8]	9945	1			T3	32		T4	10		T7	1

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30914

1

T2

4

T3

145

T8

2

auto[1]

27732

1

T4

40

T7

2

T9

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55269

1

T2

4

T3

140

T4

37

write

3377

1

T3

5

T4

3

T11

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19715

1

T3

60

T4

23

T7

2

valids[0x1]

38931

1

T2

4

T3

85

T4

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1605	1			T2	4		T3	1		T10	2
internal_process_ops[0x5a]	1560	1			T3	3		T4	1		T11	12
internal_process_ops[0x05]	19854	1			T3	49		T4	1		T11	61
internal_process_ops[0x35]	1542	1			T3	3		T4	1		T11	6
internal_process_ops[0x15]	1568	1			T3	5		T4	1		T11	6
internal_process_ops[0x03]	1056	1			T3	4		T10	2		T11	2
internal_process_ops[0x0b]	1096	1			T3	3		T11	3		T12	14
internal_process_ops[0x3b]	1131	1			T3	2		T12	16		T25	6
internal_process_ops[0x6b]	1130	1			T3	7		T8	2		T9	3
internal_process_ops[0xbb]	1110	1			T3	2		T4	2		T7	1
internal_process_ops[0xeb]	1090	1			T3	2		T4	2		T7	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56975

1

T2

4

T3

142

T4

39

auto[1]

1671

1

T3

3

T4

1

T11

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56227

1

T2

4

T3

139

T4

40

auto[1]

2419

1

T3

6

T11

17

T12

60

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10278

1

T2

4

T3

45

T12

64

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5923

1

T3

36

T10

2

T12

33

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2031

1

T3

12

T8

2

T12

28

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1962

1

T3

9

T12

27

T25

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2644

1

T3

10

T12

28

T25

29

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2208

1

T3

12

T10

6

T12

23

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2197

1

T3

14

T12

22

T25

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1936

1

T3

2

T12

19

T25

31

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

124

1

T25

2

T26

1

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

102

1

T3

1

T12

2

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

75

1

T12

1

T26

2

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

111

1

T12

2

T44

2

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

156

1

T3

1

T12

3

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

85

1

T12

1

T46

1

T94

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

127

1

T3

1

T12

1

T25

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

112

1

T12

1

T25

1

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

125

1

T12

1

T38

6

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

100

1

T3

1

T25

3

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T25

6

T45

2

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

130

1

T3

1

T44

1

T45

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

126

1

T12

1

T25

2

T26

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T38

1

T44

2

T33

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T26

1

T45

1

T14

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T12

1

T25

1

T44

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10100

1

T4

12

T11

77

T12

338

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6704

1

T4

6

T11

42

T12

159

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1540

1

T4

6

T7

1

T11

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1409

1

T4

4

T11

10

T12

35

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1789

1

T4

2

T9

3

T11

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1687

1

T4

6

T11

16

T12

36

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1533

1

T7

1

T11

10

T12

52

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1328

1

T4

1

T11

15

T12

26

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

90

1

T11

1

T12

1

T163

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T4

1

T11

6

T12

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T4

1

T11

1

T12

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T12

3

T14

3

T164

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

113

1

T12

4

T51

3

T84

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

109

1

T12

11

T123

1

T14

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T15

1

T163

2

T16

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T12

1

T51

2

T123

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

105

1

T11

2

T12

2

T28

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

133

1

T12

1

T123

1

T14

8

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

77

1

T11

2

T12

1

T28

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

99

1

T12

4

T51

1

T123

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T4

1

T11

3

T12

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

95

1

T12

3

T84

1

T163

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

135

1

T11

2

T12

1

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

104

1

T12

4

T51

1

T123

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4047	1			T3	23		T12	41		T24	4
auto[0]	values[0]	valids[0x1]	15131	1			T2	4		T3	73		T10	2
auto[0]	values[1]	valids[0x1]	575	1			T12	3		T25	7		T26	4
auto[0]	values[2]	valids[0x0]	584	1			T3	1		T8	2		T12	7
auto[0]	values[2]	valids[0x1]	328	1			T10	4		T12	7		T25	7
auto[0]	values[3]	valids[0x0]	593	1			T3	8		T12	10		T25	15
auto[0]	values[3]	valids[0x1]	303	1			T3	1		T12	5		T25	4
auto[0]	values[4]	valids[0x0]	577	1			T3	1		T12	10		T25	8
auto[0]	values[4]	valids[0x1]	307	1			T25	5		T26	3		T38	1
auto[0]	values[5]	valids[0x0]	586	1			T3	1		T12	8		T25	6
auto[0]	values[5]	valids[0x1]	322	1			T3	1		T12	7		T25	9
auto[0]	values[6]	valids[0x0]	589	1			T3	2		T12	2		T25	6
auto[0]	values[6]	valids[0x1]	305	1			T12	4		T25	3		T38	6
auto[0]	values[7]	valids[0x0]	603	1			T3	1		T12	7		T25	8
auto[0]	values[7]	valids[0x1]	295	1			T3	1		T12	1		T25	7
auto[0]	values[8]	valids[0x0]	3696	1			T3	23		T10	2		T12	53
auto[0]	values[8]	valids[0x1]	2073	1			T3	9		T12	24		T25	16
auto[1]	values[0]	valids[0x0]	3807	1			T4	10		T7	1		T11	35
auto[1]	values[0]	valids[0x1]	15573	1			T4	9		T11	111		T12	455
auto[1]	values[1]	valids[0x1]	496	1			T11	5		T12	8		T51	2
auto[1]	values[2]	valids[0x0]	402	1			T4	1		T11	4		T12	10
auto[1]	values[2]	valids[0x1]	275	1			T11	5		T12	9		T14	6
auto[1]	values[3]	valids[0x0]	409	1			T4	2		T11	4		T12	11
auto[1]	values[3]	valids[0x1]	284	1			T11	6		T12	6		T28	3
auto[1]	values[4]	valids[0x0]	316	1			T4	1		T12	7		T51	4
auto[1]	values[4]	valids[0x1]	261	1			T11	4		T12	2		T51	3
auto[1]	values[5]	valids[0x0]	353	1			T4	3		T11	3		T12	24
auto[1]	values[5]	valids[0x1]	236	1			T11	1		T12	3		T51	4
auto[1]	values[6]	valids[0x0]	352	1			T11	1		T12	4		T51	1
auto[1]	values[6]	valids[0x1]	210	1			T4	2		T11	3		T12	7
auto[1]	values[7]	valids[0x0]	348	1			T11	1		T12	9		T51	4
auto[1]	values[7]	valids[0x1]	234	1			T4	2		T11	4		T12	1
auto[1]	values[8]	valids[0x0]	2453	1			T4	6		T7	1		T9	3
auto[1]	values[8]	valids[0x1]	1723	1			T4	4		T11	23		T12	45