Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3566253

1

T2

26169

T3

12937

T4

648

auto[1]

26497

1

T3

45

T11

44

T12

333

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1147794

1

T2

26169

T3

34

T4

8

auto[1]

2444956

1

T3

12948

T4

640

T11

16886

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	698723	1			T2	9734		T3	5161		T4	1
auto[524288:1048575]	424054	1			T3	3071		T4	2		T7	232
auto[1048576:1572863]	432643	1			T3	1238		T5	3		T7	66
auto[1572864:2097151]	396324	1			T2	860		T4	640		T8	1
auto[2097152:2621439]	399360	1			T3	2217		T7	9		T9	3
auto[2621440:3145727]	386451	1			T2	6350		T3	1291		T4	3
auto[3145728:3670015]	450609	1			T2	5368		T4	1		T9	82
auto[3670016:4194303]	404586	1			T2	3857		T3	4		T4	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2478191

1

T2

15

T3

12982

T4

648

auto[1]

1114559

1

T2

26154

T5

15

T7

658

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3154051

1

T2

26169

T3

11695

T4

646

auto[1]

438699

1

T3

1287

T4

2

T11

653

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	256546	1			T2	9734		T3	5		T4	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	384547	1			T3	5126		T11	2986		T12	3202
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123795	1			T3	2		T4	1		T7	232
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	238170	1			T3	3069		T11	2		T12	5502
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	126324	1			T3	4		T5	3		T7	66
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	246060	1			T3	1224		T11	3265		T12	5869
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	108857	1			T2	860		T8	1		T11	10
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	229305	1			T4	640		T11	2989		T12	8812
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116957	1			T7	9		T9	3		T11	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	228014	1			T3	2217		T11	3749		T12	9438
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	118501	1			T2	6350		T3	8		T4	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	217565	1			T11	892		T12	10049		T25	257
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	157374	1			T2	5368		T4	1		T9	82
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	239847	1			T11	641		T12	4605		T25	1026
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	124597	1			T2	3857		T3	1		T4	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	216330	1			T3	3		T11	1688		T12	685
auto[0]	auto[1]	auto[0:524287]	auto[0]	846	1			T3	2		T24	3		T25	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	52888	1			T25	3811		T44	2235		T123	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	3613	1			T4	1		T12	7		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	54491	1			T11	512		T12	1947		T33	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1278	1			T3	2		T12	2		T24	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56846	1			T12	256		T25	708		T51	2260
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	630	1			T12	4		T26	34		T38	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54298	1			T12	587		T26	1095		T38	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1562	1			T11	2		T12	9		T38	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	48590	1			T11	134		T12	585		T44	640
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	524	1			T3	4		T4	1		T25	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47039	1			T3	1270		T38	2		T33	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1731	1			T11	1		T12	1		T24	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	49378	1			T11	1		T38	87		T33	2189
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	938	1			T12	1		T25	5		T44	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	58812	1			T12	5		T25	2247		T123	1696
auto[1]	auto[0]	auto[0:524287]	auto[0]	459	1			T3	3		T11	2		T12	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	2464	1			T3	25		T12	5		T25	40
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	402	1			T12	5		T26	5		T28	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3087	1			T12	10		T26	129		T28	50
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	373	1			T3	1		T11	1		T12	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1272	1			T3	7		T11	1		T12	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	323	1			T11	1		T12	8		T25	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2246	1			T11	5		T12	62		T25	9
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	356	1			T11	2		T12	9		T38	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2724	1			T11	3		T12	13		T38	26
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	301	1			T11	2		T12	8		T25	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2034	1			T11	3		T12	24		T25	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	393	1			T11	1		T12	5		T25	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1612	1			T12	10		T25	44		T38	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	422	1			T11	7		T12	9		T44	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2794	1			T11	13		T12	74		T51	18
auto[1]	auto[1]	auto[0:524287]	auto[0]	120	1			T25	1		T95	1		T175	7
auto[1]	auto[1]	auto[0:524287]	auto[1]	853	1			T25	5		T95	6		T175	18
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	95	1			T12	2		T94	2		T15	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	401	1			T12	1		T94	19		T164	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	98	1			T44	7		T95	1		T16	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	392	1			T95	25		T16	4		T196	27
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	105	1			T12	4		T38	1		T45	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	560	1			T12	47		T38	31		T45	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	67	1			T11	1		T12	3		T45	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	1090	1			T11	2		T12	2		T45	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	71	1			T3	2		T44	5		T33	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	416	1			T3	7		T16	45		T196	173
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	66	1			T38	1		T85	6		T16	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	208	1			T38	18		T16	4		T196	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T12	1		T25	1		T123	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	623	1			T25	2		T123	39		T45	10

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2025439	1			T2	15		T3	11659		T4	646
auto[0]	auto[0]	auto[1]	1107350	1			T2	26154		T5	15		T7	658
auto[0]	auto[1]	auto[0]	426852	1			T3	1278		T4	2		T11	650
auto[0]	auto[1]	auto[1]	6612	1			T24	1		T25	1		T38	2
auto[1]	auto[0]	auto[0]	20768	1			T3	36		T11	41		T12	260
auto[1]	auto[0]	auto[1]	494	1			T12	13		T26	4		T38	1
auto[1]	auto[1]	auto[0]	5132	1			T3	9		T11	3		T12	58
auto[1]	auto[1]	auto[1]	103	1			T12	2		T44	2		T94	1