Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[1]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[2]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[3]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[4]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[5]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[6]	3000387	1			T1	2664		T2	1		T3	1949
all_pins[7]	3000387	1			T1	2664		T2	1		T3	1949

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23843503	1			T1	21312		T2	8		T3	15592
values[0x1]	159593	1			T13	7		T15	15		T17	54
transitions[0x0=>0x1]	157433	1			T13	2		T15	13		T17	42
transitions[0x1=>0x0]	157446	1			T13	2		T15	13		T17	42

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3000052	1			T1	2664		T2	1		T3	1949
all_pins[0]	values[0x1]	335	1			T17	8		T160	122		T146	5
all_pins[0]	transitions[0x0=>0x1]	251	1			T17	4		T160	122		T146	3
all_pins[0]	transitions[0x1=>0x0]	247	1			T15	4		T17	2		T146	2
all_pins[1]	values[0x0]	3000056	1			T1	2664		T2	1		T3	1949
all_pins[1]	values[0x1]	331	1			T15	4		T17	6		T146	4
all_pins[1]	transitions[0x0=>0x1]	165	1			T15	3		T17	5		T146	1
all_pins[1]	transitions[0x1=>0x0]	115	1			T13	1		T17	1		T48	1
all_pins[2]	values[0x0]	3000106	1			T1	2664		T2	1		T3	1949
all_pins[2]	values[0x1]	281	1			T13	1		T15	1		T17	2
all_pins[2]	transitions[0x0=>0x1]	233	1			T17	2		T48	1		T146	1
all_pins[2]	transitions[0x1=>0x0]	146	1			T13	1		T15	2		T17	10
all_pins[3]	values[0x0]	3000193	1			T1	2664		T2	1		T3	1949
all_pins[3]	values[0x1]	194	1			T13	2		T15	3		T17	10
all_pins[3]	transitions[0x0=>0x1]	135	1			T15	3		T17	9		T19	1
all_pins[3]	transitions[0x1=>0x0]	129	1			T15	3		T17	4		T146	4
all_pins[4]	values[0x0]	3000199	1			T1	2664		T2	1		T3	1949
all_pins[4]	values[0x1]	188	1			T13	2		T15	3		T17	5
all_pins[4]	transitions[0x0=>0x1]	146	1			T15	3		T17	4		T19	2
all_pins[4]	transitions[0x1=>0x0]	1881	1			T15	1		T17	8		T19	2
all_pins[5]	values[0x0]	2998464	1			T1	2664		T2	1		T3	1949
all_pins[5]	values[0x1]	1923	1			T13	2		T15	1		T17	9
all_pins[5]	transitions[0x0=>0x1]	252	1			T13	2		T15	1		T17	6
all_pins[5]	transitions[0x1=>0x0]	154514	1			T15	2		T17	5		T160	16189
all_pins[6]	values[0x0]	2844202	1			T1	2664		T2	1		T3	1949
all_pins[6]	values[0x1]	156185	1			T15	2		T17	8		T19	1
all_pins[6]	transitions[0x0=>0x1]	156146	1			T15	2		T17	6		T19	1
all_pins[6]	transitions[0x1=>0x0]	117	1			T15	1		T17	4		T19	3
all_pins[7]	values[0x0]	3000231	1			T1	2664		T2	1		T3	1949
all_pins[7]	values[0x1]	156	1			T15	1		T17	6		T19	3
all_pins[7]	transitions[0x0=>0x1]	105	1			T15	1		T17	6		T19	3
all_pins[7]	transitions[0x1=>0x0]	297	1			T17	8		T160	120		T146	4