Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18066

1

T2

4

T3

84

T8

2

auto[1]

12848

1

T3

61

T10

8

T12

108

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3725	1			T3	57		T12	20		T24	4
values[1]	4304	1			T3	20		T10	8		T25	40
values[2]	3357	1			T12	63		T25	20		T26	20
values[3]	3918	1			T12	42		T25	20		T26	40
values[4]	3771	1			T12	42		T25	23		T26	20
values[5]	4100	1			T2	4		T12	20		T25	85
values[6]	3401	1			T12	27		T25	91		T44	20
values[7]	4338	1			T3	68		T8	2		T12	44

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4044	1			T8	2		T12	20		T25	40
values[1]	3260	1			T3	28		T12	20		T24	4
values[2]	4563	1			T3	40		T12	27		T26	20
values[3]	3335	1			T2	4		T3	29		T12	22
values[4]	4086	1			T10	8		T12	86		T25	40
values[5]	4006	1			T3	28		T12	20		T25	20
values[6]	3388	1			T3	20		T12	43		T26	40
values[7]	4232	1			T12	20		T25	158		T38	39

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	246	1			T25	9		T214	12		T94	20
auto[0]	values[0]	values[1]	181	1			T24	4		T14	13		T94	10
auto[0]	values[0]	values[2]	232	1			T33	9		T45	27		T205	31
auto[0]	values[0]	values[3]	286	1			T3	13		T85	13		T202	70
auto[0]	values[0]	values[4]	418	1			T12	14		T44	26		T85	9
auto[0]	values[0]	values[5]	355	1			T3	24		T26	11		T33	8
auto[0]	values[0]	values[6]	278	1			T44	8		T13	14		T188	24
auto[0]	values[0]	values[7]	257	1			T45	24		T15	13		T18	20
auto[0]	values[1]	values[0]	373	1			T46	10		T15	14		T34	12
auto[0]	values[1]	values[1]	319	1			T14	5		T95	12		T16	10
auto[0]	values[1]	values[2]	253	1			T38	10		T85	11		T179	9
auto[0]	values[1]	values[3]	280	1			T95	6		T202	44		T203	7
auto[0]	values[1]	values[4]	318	1			T86	2		T94	10		T188	20
auto[0]	values[1]	values[5]	317	1			T25	9		T38	53		T44	11
auto[0]	values[1]	values[6]	386	1			T3	19		T46	10		T202	13
auto[0]	values[1]	values[7]	324	1			T25	11		T14	24		T181	20
auto[0]	values[2]	values[0]	298	1			T12	13		T15	11		T196	17
auto[0]	values[2]	values[1]	295	1			T33	8		T94	13		T15	9
auto[0]	values[2]	values[2]	285	1			T33	15		T45	13		T15	9
auto[0]	values[2]	values[3]	122	1			T188	12		T215	9		T216	20
auto[0]	values[2]	values[4]	248	1			T12	12		T25	11		T26	15
auto[0]	values[2]	values[5]	401	1			T33	16		T45	12		T15	9
auto[0]	values[2]	values[6]	196	1			T12	10		T13	16		T94	12
auto[0]	values[2]	values[7]	238	1			T217	6		T213	8		T34	17
auto[0]	values[3]	values[0]	230	1			T25	9		T14	12		T195	15
auto[0]	values[3]	values[1]	211	1			T26	9		T38	11		T45	14
auto[0]	values[3]	values[2]	474	1			T122	20		T159	9		T179	12
auto[0]	values[3]	values[3]	263	1			T202	49		T183	14		T205	7
auto[0]	values[3]	values[4]	220	1			T12	16		T13	6		T15	12
auto[0]	values[3]	values[5]	323	1			T45	23		T46	12		T194	15
auto[0]	values[3]	values[6]	279	1			T12	12		T26	13		T15	16
auto[0]	values[3]	values[7]	475	1			T120	125		T46	8		T178	13
auto[0]	values[4]	values[0]	219	1			T188	12		T85	13		T202	24
auto[0]	values[4]	values[1]	285	1			T44	11		T33	10		T94	17
auto[0]	values[4]	values[2]	569	1			T26	7		T38	12		T202	156
auto[0]	values[4]	values[3]	211	1			T12	12		T15	12		T95	36
auto[0]	values[4]	values[4]	211	1			T95	8		T218	6		T196	14
auto[0]	values[4]	values[5]	301	1			T12	9		T186	14		T45	11
auto[0]	values[4]	values[6]	277	1			T38	79		T44	11		T159	12
auto[0]	values[4]	values[7]	221	1			T25	10		T14	9		T219	4
auto[0]	values[5]	values[0]	260	1			T179	8		T196	19		T34	12
auto[0]	values[5]	values[1]	140	1			T46	16		T16	11		T179	13
auto[0]	values[5]	values[2]	188	1			T45	9		T13	11		T95	16
auto[0]	values[5]	values[3]	418	1			T2	4		T26	8		T38	35
auto[0]	values[5]	values[4]	395	1			T188	19		T15	13		T209	14
auto[0]	values[5]	values[5]	374	1			T26	16		T44	14		T94	43
auto[0]	values[5]	values[6]	188	1			T26	10		T38	10		T159	9
auto[0]	values[5]	values[7]	320	1			T12	10		T25	73		T38	27
auto[0]	values[6]	values[0]	299	1			T46	9		T95	13		T178	13
auto[0]	values[6]	values[1]	245	1			T40	26		T33	12		T175	13
auto[0]	values[6]	values[2]	262	1			T12	15		T45	8		T14	13
auto[0]	values[6]	values[3]	155	1			T25	10		T14	36		T188	11
auto[0]	values[6]	values[4]	258	1			T14	11		T196	42		T220	18
auto[0]	values[6]	values[5]	252	1			T44	13		T21	26		T192	7
auto[0]	values[6]	values[6]	173	1			T15	11		T18	22		T192	11
auto[0]	values[6]	values[7]	381	1			T25	9		T46	21		T15	13
auto[0]	values[7]	values[0]	256	1			T8	2		T38	17		T14	12
auto[0]	values[7]	values[1]	191	1			T3	18		T12	9		T33	22
auto[0]	values[7]	values[2]	396	1			T3	10		T33	10		T14	7
auto[0]	values[7]	values[3]	304	1			T25	26		T26	16		T44	10
auto[0]	values[7]	values[4]	335	1			T12	18		T25	16		T208	4
auto[0]	values[7]	values[5]	201	1			T44	16		T221	6		T14	7
auto[0]	values[7]	values[6]	208	1			T33	20		T94	13		T222	8
auto[0]	values[7]	values[7]	192	1			T45	10		T46	11		T18	14
auto[1]	values[0]	values[0]	133	1			T25	11		T94	9		T85	11
auto[1]	values[0]	values[1]	135	1			T14	7		T94	10		T194	9
auto[1]	values[0]	values[2]	233	1			T33	12		T45	7		T223	4
auto[1]	values[0]	values[3]	145	1			T3	16		T85	7		T202	20
auto[1]	values[0]	values[4]	218	1			T12	6		T44	14		T85	11
auto[1]	values[0]	values[5]	174	1			T3	4		T26	9		T33	13
auto[1]	values[0]	values[6]	174	1			T44	12		T13	9		T188	6
auto[1]	values[0]	values[7]	260	1			T45	9		T15	9		T18	9
auto[1]	values[1]	values[0]	223	1			T46	14		T15	7		T224	20
auto[1]	values[1]	values[1]	194	1			T14	15		T95	8		T16	10
auto[1]	values[1]	values[2]	113	1			T38	10		T85	9		T179	11
auto[1]	values[1]	values[3]	136	1			T95	14		T202	6		T203	13
auto[1]	values[1]	values[4]	320	1			T10	8		T94	11		T188	3
auto[1]	values[1]	values[5]	228	1			T25	11		T38	19		T44	9
auto[1]	values[1]	values[6]	242	1			T3	1		T46	11		T202	7
auto[1]	values[1]	values[7]	278	1			T25	9		T14	16		T175	11
auto[1]	values[2]	values[0]	210	1			T12	7		T15	9		T196	3
auto[1]	values[2]	values[1]	163	1			T33	12		T94	7		T15	13
auto[1]	values[2]	values[2]	98	1			T33	5		T45	7		T15	11
auto[1]	values[2]	values[3]	78	1			T188	12		T215	12		T225	16
auto[1]	values[2]	values[4]	253	1			T12	8		T25	9		T26	5
auto[1]	values[2]	values[5]	184	1			T33	5		T45	18		T15	12
auto[1]	values[2]	values[6]	195	1			T12	13		T87	18		T13	4
auto[1]	values[2]	values[7]	93	1			T34	8		T18	4		T200	9
auto[1]	values[3]	values[0]	211	1			T25	11		T14	13		T195	57
auto[1]	values[3]	values[1]	133	1			T26	11		T38	9		T45	9
auto[1]	values[3]	values[2]	318	1			T159	55		T179	8		T18	46
auto[1]	values[3]	values[3]	148	1			T202	5		T183	8		T226	16
auto[1]	values[3]	values[4]	133	1			T12	6		T13	14		T15	8
auto[1]	values[3]	values[5]	192	1			T45	9		T46	13		T194	5
auto[1]	values[3]	values[6]	79	1			T12	8		T26	7		T15	10
auto[1]	values[3]	values[7]	229	1			T46	16		T178	7		T18	18
auto[1]	values[4]	values[0]	99	1			T188	9		T85	7		T202	7
auto[1]	values[4]	values[1]	231	1			T44	9		T33	11		T94	10
auto[1]	values[4]	values[2]	257	1			T26	13		T38	8		T202	9
auto[1]	values[4]	values[3]	222	1			T12	10		T15	9		T95	25
auto[1]	values[4]	values[4]	116	1			T95	39		T196	6		T227	9
auto[1]	values[4]	values[5]	210	1			T12	11		T45	16		T46	9
auto[1]	values[4]	values[6]	184	1			T38	10		T44	9		T159	8
auto[1]	values[4]	values[7]	158	1			T25	13		T14	11		T178	18
auto[1]	values[5]	values[0]	244	1			T179	12		T196	21		T34	9
auto[1]	values[5]	values[1]	228	1			T46	10		T155	4		T16	13
auto[1]	values[5]	values[2]	127	1			T45	11		T13	9		T95	4
auto[1]	values[5]	values[3]	251	1			T26	12		T38	12		T94	15
auto[1]	values[5]	values[4]	283	1			T188	14		T15	9		T209	33
auto[1]	values[5]	values[5]	235	1			T26	4		T44	6		T94	5
auto[1]	values[5]	values[6]	184	1			T26	10		T38	18		T159	11
auto[1]	values[5]	values[7]	265	1			T12	10		T25	12		T38	12
auto[1]	values[6]	values[0]	139	1			T46	13		T95	9		T178	7
auto[1]	values[6]	values[1]	138	1			T33	8		T175	7		T204	29
auto[1]	values[6]	values[2]	279	1			T12	12		T45	33		T14	13
auto[1]	values[6]	values[3]	151	1			T25	51		T14	8		T188	9
auto[1]	values[6]	values[4]	129	1			T14	12		T196	6		T18	9
auto[1]	values[6]	values[5]	172	1			T44	7		T21	14		T192	26
auto[1]	values[6]	values[6]	206	1			T15	14		T18	23		T192	9
auto[1]	values[6]	values[7]	162	1			T25	21		T46	7		T15	7
auto[1]	values[7]	values[0]	604	1			T38	3		T14	8		T85	6
auto[1]	values[7]	values[1]	171	1			T3	10		T12	11		T33	3
auto[1]	values[7]	values[2]	479	1			T3	30		T33	10		T14	14
auto[1]	values[7]	values[3]	165	1			T25	4		T26	4		T44	10
auto[1]	values[7]	values[4]	231	1			T12	6		T25	4		T14	10
auto[1]	values[7]	values[5]	87	1			T44	4		T14	13		T95	8
auto[1]	values[7]	values[6]	139	1			T33	21		T94	7		T21	13
auto[1]	values[7]	values[7]	379	1			T45	143		T46	12		T18	9