Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	456	1			T3	5		T12	3		T25	4
auto[ReadAddrCrossIntoMailbox]	346	1			T3	2		T12	4		T25	5
auto[ReadAddrCrossOutOfMailbox]	381	1			T3	4		T8	2		T12	5
auto[ReadAddrCrossAllMailbox]	254	1			T12	1		T25	4		T26	3
auto[ReadAddrOutsideMailbox]	3558	1			T3	9		T10	2		T12	41

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2483

1

T3

12

T8

1

T10

1

auto[1]

2512

1

T3

8

T8

1

T10

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	804	1			T3	4		T10	2		T12	7
read_ops[0x0b]	802	1			T3	3		T12	8		T25	11
read_ops[0x3b]	869	1			T3	2		T12	9		T25	6
read_ops[0x6b]	861	1			T3	7		T8	2		T12	8
read_ops[0xbb]	841	1			T3	2		T12	13		T25	11
read_ops[0xeb]	818	1			T3	2		T12	9		T25	7

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T3	2		T38	2		T45	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T95	1		T213	1		T179	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T38	2		T44	3		T33	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T25	1		T38	1		T45	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T3	1		T26	1		T44	4
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T12	1		T25	1		T46	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T25	1		T38	1		T44	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	34	1			T45	1		T46	1		T179	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T10	1		T25	4		T44	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T3	1		T10	1		T12	6
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T26	1		T38	3		T33	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T25	2		T38	1		T44	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T25	1		T26	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T26	1		T44	2		T194	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T38	1		T94	1		T179	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T3	1		T12	2		T44	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T26	1		T95	1		T202	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T44	1		T45	1		T14	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T3	2		T12	2		T25	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T12	4		T25	7		T26	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T3	1		T26	1		T44	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T38	1		T44	1		T45	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T3	1		T25	1		T38	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T38	1		T159	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T12	1		T25	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T38	2		T95	1		T202	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T26	2		T44	1		T46	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T14	1		T85	1		T95	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	313	1			T12	2		T25	3		T26	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	319	1			T12	6		T25	1		T26	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	43	1			T12	1		T25	1		T13	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T3	1		T38	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T12	2		T45	1		T14	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T12	1		T14	2		T209	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T8	1		T25	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	42	1			T3	1		T8	1		T44	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T44	1		T45	1		T46	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T25	1		T33	1		T15	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T3	3		T12	2		T25	5
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T3	2		T12	2		T25	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T25	1		T44	1		T13	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	49	1			T12	2		T44	2		T33	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T25	1		T45	1		T95	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T12	1		T26	1		T33	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T25	1		T38	1		T188	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T3	1		T25	1		T26	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T194	1		T179	1		T18	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T12	1		T14	1		T46	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	318	1			T12	2		T25	4		T26	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T3	1		T12	7		T25	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T3	1		T44	1		T45	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T46	2		T195	1		T213	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T3	1		T38	1		T45	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T25	1		T44	1		T14	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T45	1		T94	1		T85	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T12	1		T26	3		T13	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T25	1		T38	1		T14	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T25	1		T194	1		T85	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T12	7		T25	4		T26	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T12	1		T26	3		T44	3