Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4222	1			T12	20		T25	40		T26	80
values[1]	3706	1			T3	28		T25	73		T38	39
values[2]	4073	1			T3	68		T12	23		T44	20
values[3]	3527	1			T25	85		T38	20		T44	20
values[4]	3696	1			T2	4		T3	29		T10	8
values[5]	3789	1			T3	20		T8	2		T12	44
values[6]	3867	1			T12	89		T24	4		T38	28
values[7]	4034	1			T12	20		T25	81		T26	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4067	1			T12	20		T26	20		T38	52
values[1]	3547	1			T3	68		T25	40		T26	40
values[2]	4112	1			T12	65		T26	20		T38	20
values[3]	3927	1			T8	2		T12	40		T25	81
values[4]	3523	1			T12	20		T25	20		T38	20
values[5]	4289	1			T3	29		T10	8		T12	27
values[6]	4063	1			T3	28		T12	66		T25	43
values[7]	3386	1			T2	4		T3	20		T12	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30072

1

T2

4

T3

142

T8

2

auto[1]

842

1

T3

3

T12

7

T25

5

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	645	1			T12	20		T38	52		T80	16
auto[0]	values[0]	values[1]	376	1			T25	20		T26	40		T188	33
auto[0]	values[0]	values[2]	412	1			T26	20		T95	20		T181	20
auto[0]	values[0]	values[3]	837	1			T38	45		T33	19		T45	182
auto[0]	values[0]	values[4]	431	1			T44	20		T45	20		T159	20
auto[0]	values[0]	values[5]	559	1			T46	23		T213	8		T202	50
auto[0]	values[0]	values[6]	613	1			T26	20		T44	20		T33	19
auto[0]	values[0]	values[7]	254	1			T25	20		T16	20		T196	20
auto[0]	values[1]	values[0]	445	1			T33	20		T45	27		T196	133
auto[0]	values[1]	values[1]	457	1			T25	19		T38	38		T46	51
auto[0]	values[1]	values[2]	649	1			T14	43		T85	20		T15	22
auto[0]	values[1]	values[3]	306	1			T208	4		T13	20		T187	10
auto[0]	values[1]	values[4]	421	1			T40	26		T45	20		T18	20
auto[0]	values[1]	values[5]	372	1			T25	30		T33	20		T14	19
auto[0]	values[1]	values[6]	549	1			T3	27		T25	23		T87	18
auto[0]	values[1]	values[7]	415	1			T155	4		T201	20		T48	19
auto[0]	values[2]	values[0]	577	1			T45	33		T13	22		T196	26
auto[0]	values[2]	values[1]	543	1			T3	67		T14	20		T46	20
auto[0]	values[2]	values[2]	412	1			T12	21		T202	53		T192	20
auto[0]	values[2]	values[3]	337	1			T33	19		T217	6		T159	20
auto[0]	values[2]	values[4]	542	1			T44	18		T45	31		T14	20
auto[0]	values[2]	values[5]	335	1			T14	20		T188	30		T201	37
auto[0]	values[2]	values[6]	564	1			T94	27		T85	20		T159	59
auto[0]	values[2]	values[7]	630	1			T120	125		T94	26		T95	21
auto[0]	values[3]	values[0]	500	1			T33	20		T186	14		T196	126
auto[0]	values[3]	values[1]	334	1			T38	20		T45	29		T228	44
auto[0]	values[3]	values[2]	351	1			T94	20		T95	18		T229	4
auto[0]	values[3]	values[3]	515	1			T44	20		T122	20		T46	26
auto[0]	values[3]	values[4]	302	1			T25	20		T46	20		T48	24
auto[0]	values[3]	values[5]	503	1			T33	45		T14	21		T95	19
auto[0]	values[3]	values[6]	423	1			T46	21		T94	20		T85	19
auto[0]	values[3]	values[7]	496	1			T25	62		T45	23		T230	4
auto[0]	values[4]	values[0]	420	1			T14	26		T15	25		T179	20
auto[0]	values[4]	values[1]	548	1			T38	67		T85	20		T15	20
auto[0]	values[4]	values[2]	548	1			T38	20		T13	20		T15	20
auto[0]	values[4]	values[3]	451	1			T12	20		T16	51		T179	18
auto[0]	values[4]	values[4]	447	1			T38	20		T214	12		T231	2
auto[0]	values[4]	values[5]	494	1			T3	28		T10	8		T121	2
auto[0]	values[4]	values[6]	411	1			T12	20		T25	19		T38	20
auto[0]	values[4]	values[7]	280	1			T2	4		T12	20		T26	20
auto[0]	values[5]	values[0]	397	1			T95	45		T201	19		T178	20
auto[0]	values[5]	values[1]	396	1			T178	20		T18	29		T176	20
auto[0]	values[5]	values[2]	416	1			T194	20		T85	20		T95	20
auto[0]	values[5]	values[3]	608	1			T8	2		T12	20		T26	20
auto[0]	values[5]	values[4]	438	1			T45	39		T14	20		T46	23
auto[0]	values[5]	values[5]	721	1			T25	20		T26	20		T38	20
auto[0]	values[5]	values[6]	314	1			T12	23		T26	20		T38	20
auto[0]	values[5]	values[7]	377	1			T3	20		T25	30		T44	20
auto[0]	values[6]	values[0]	452	1			T13	24		T46	43		T94	29
auto[0]	values[6]	values[1]	501	1			T33	40		T209	80		T18	19
auto[0]	values[6]	values[2]	581	1			T12	42		T15	26		T16	20
auto[0]	values[6]	values[3]	377	1			T14	24		T188	20		T34	22
auto[0]	values[6]	values[4]	441	1			T33	20		T14	20		T202	65
auto[0]	values[6]	values[5]	555	1			T12	26		T24	4		T38	28
auto[0]	values[6]	values[6]	503	1			T12	20		T14	20		T15	20
auto[0]	values[6]	values[7]	365	1			T44	20		T86	2		T15	21
auto[0]	values[7]	values[0]	523	1			T26	20		T21	28		T147	36
auto[0]	values[7]	values[1]	301	1			T44	56		T14	38		T198	4
auto[0]	values[7]	values[2]	651	1			T15	22		T232	20		T21	20
auto[0]	values[7]	values[3]	392	1			T25	81		T95	32		T222	8
auto[0]	values[7]	values[4]	390	1			T12	19		T94	19		T179	20
auto[0]	values[7]	values[5]	623	1			T221	6		T94	24		T196	147
auto[0]	values[7]	values[6]	581	1			T14	22		T196	20		T220	18
auto[0]	values[7]	values[7]	465	1			T95	26		T202	162		T233	2
auto[1]	values[0]	values[0]	17	1			T15	1		T18	4		T228	1
auto[1]	values[0]	values[1]	5	1			T227	2		T185	1		T234	1
auto[1]	values[0]	values[2]	10	1			T178	1		T18	1		T176	1
auto[1]	values[0]	values[3]	22	1			T38	2		T33	2		T45	3
auto[1]	values[0]	values[4]	9	1			T16	2		T202	2		T235	1
auto[1]	values[0]	values[5]	13	1			T236	1		T216	1		T207	2
auto[1]	values[0]	values[6]	13	1			T33	1		T85	2		T18	4
auto[1]	values[0]	values[7]	6	1			T236	1		T190	3		T237	1
auto[1]	values[1]	values[0]	6	1			T33	1		T196	1		T125	1
auto[1]	values[1]	values[1]	9	1			T25	1		T38	1		T46	2
auto[1]	values[1]	values[2]	15	1			T14	1		T16	3		T192	1
auto[1]	values[1]	values[3]	7	1			T196	1		T209	1		T160	1
auto[1]	values[1]	values[4]	18	1			T203	1		T227	1		T228	1
auto[1]	values[1]	values[5]	12	1			T33	1		T14	1		T18	3
auto[1]	values[1]	values[6]	8	1			T3	1		T185	2		T238	1
auto[1]	values[1]	values[7]	17	1			T48	2		T147	1		T239	1
auto[1]	values[2]	values[0]	21	1			T13	1		T196	3		T239	1
auto[1]	values[2]	values[1]	21	1			T3	1		T14	1		T46	4
auto[1]	values[2]	values[2]	7	1			T12	2		T202	1		T240	1
auto[1]	values[2]	values[3]	6	1			T33	1		T34	1		T64	1
auto[1]	values[2]	values[4]	23	1			T44	2		T45	3		T66	3
auto[1]	values[2]	values[5]	16	1			T201	3		T34	2		T241	2
auto[1]	values[2]	values[6]	23	1			T159	5		T202	2		T216	2
auto[1]	values[2]	values[7]	16	1			T94	3		T95	4		T178	1
auto[1]	values[3]	values[0]	11	1			T196	4		T18	6		T242	1
auto[1]	values[3]	values[1]	12	1			T45	1		T240	1		T66	1
auto[1]	values[3]	values[2]	15	1			T94	1		T95	2		T125	2
auto[1]	values[3]	values[3]	6	1			T209	1		T215	1		T243	1
auto[1]	values[3]	values[4]	11	1			T48	2		T125	2		T244	2
auto[1]	values[3]	values[5]	12	1			T95	1		T159	1		T175	2
auto[1]	values[3]	values[6]	15	1			T46	1		T85	1		T176	4
auto[1]	values[3]	values[7]	21	1			T25	3		T179	2		T209	2
auto[1]	values[4]	values[0]	22	1			T34	2		T245	14		T234	3
auto[1]	values[4]	values[1]	9	1			T38	2		T195	2		T205	1
auto[1]	values[4]	values[2]	10	1			T21	3		T125	4		T246	1
auto[1]	values[4]	values[3]	7	1			T179	2		T205	1		T247	2
auto[1]	values[4]	values[4]	12	1			T18	2		T239	1		T248	4
auto[1]	values[4]	values[5]	18	1			T3	1		T15	3		T202	2
auto[1]	values[4]	values[6]	11	1			T12	2		T25	1		T202	1
auto[1]	values[4]	values[7]	8	1			T15	2		T234	3		T242	3
auto[1]	values[5]	values[0]	16	1			T95	2		T201	1		T160	2
auto[1]	values[5]	values[1]	10	1			T18	1		T240	1		T239	1
auto[1]	values[5]	values[2]	5	1			T16	1		T196	1		T34	1
auto[1]	values[5]	values[3]	23	1			T179	1		T21	5		T192	2
auto[1]	values[5]	values[4]	18	1			T45	2		T46	1		T15	1
auto[1]	values[5]	values[5]	24	1			T159	1		T205	1		T203	1
auto[1]	values[5]	values[6]	10	1			T12	1		T44	1		T66	4
auto[1]	values[5]	values[7]	16	1			T85	1		T18	4		T48	3
auto[1]	values[6]	values[0]	11	1			T46	3		T202	2		T21	1
auto[1]	values[6]	values[1]	12	1			T33	1		T18	1		T183	1
auto[1]	values[6]	values[2]	12	1			T18	2		T227	2		T236	1
auto[1]	values[6]	values[3]	16	1			T14	1		T188	3		T205	1
auto[1]	values[6]	values[4]	6	1			T202	1		T203	1		T236	1
auto[1]	values[6]	values[5]	14	1			T12	1		T33	2		T66	1
auto[1]	values[6]	values[6]	8	1			T175	3		T16	2		T215	2
auto[1]	values[6]	values[7]	13	1			T249	2		T178	2		T176	1
auto[1]	values[7]	values[0]	4	1			T147	1		T127	1		T250	2
auto[1]	values[7]	values[1]	13	1			T44	4		T14	2		T216	2
auto[1]	values[7]	values[2]	18	1			T227	1		T240	2		T239	1
auto[1]	values[7]	values[3]	17	1			T228	3		T193	6		T251	4
auto[1]	values[7]	values[4]	14	1			T12	1		T94	1		T252	1
auto[1]	values[7]	values[5]	18	1			T94	2		T18	2		T244	1
auto[1]	values[7]	values[6]	17	1			T14	1		T244	1		T253	5
auto[1]	values[7]	values[7]	7	1			T95	1		T202	3		T254	1