Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	704	1			T13	4		T15	10		T17	32
all_values[1]	704	1			T13	4		T15	10		T17	32
all_values[2]	704	1			T13	4		T15	10		T17	32
all_values[3]	704	1			T13	4		T15	10		T17	32
all_values[4]	704	1			T13	4		T15	10		T17	32
all_values[5]	704	1			T13	4		T15	10		T17	32
all_values[6]	704	1			T13	4		T15	10		T17	32
all_values[7]	704	1			T13	4		T15	10		T17	32

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2912

1

T13

14

T15

48

T17

131

auto[1]

2720

1

T13

18

T15

32

T17

125

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2199

1

T13

17

T15

34

T17

93

auto[1]

3433

1

T13

15

T15

46

T17

163

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3169

1

T13

20

T15

44

T17

141

auto[1]

2463

1

T13

12

T15

36

T17

115

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	136	1			T13	1		T15	3		T17	8
all_values[0]	auto[0]	auto[0]	auto[1]	72	1			T13	1		T15	3		T17	4
all_values[0]	auto[0]	auto[1]	auto[0]	123	1			T17	3		T19	2		T146	1
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T17	4		T160	1		T146	1
all_values[0]	auto[1]	auto[0]	auto[1]	153	1			T15	4		T17	6		T19	3
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T13	2		T17	7		T48	1
all_values[1]	auto[0]	auto[0]	auto[0]	140	1			T13	3		T15	3		T17	3
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T17	4		T19	2		T146	3
all_values[1]	auto[0]	auto[1]	auto[0]	127	1			T13	1		T17	8		T19	3
all_values[1]	auto[0]	auto[1]	auto[1]	69	1			T15	2		T17	4		T146	3
all_values[1]	auto[1]	auto[0]	auto[1]	149	1			T15	3		T17	7		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	145	1			T15	2		T17	6		T48	1
all_values[2]	auto[0]	auto[0]	auto[0]	142	1			T15	4		T17	13		T19	4
all_values[2]	auto[0]	auto[0]	auto[1]	55	1			T17	4		T19	1		T161	2
all_values[2]	auto[0]	auto[1]	auto[0]	124	1			T13	2		T15	3		T17	4
all_values[2]	auto[0]	auto[1]	auto[1]	76	1			T146	1		T161	4		T162	1
all_values[2]	auto[1]	auto[0]	auto[1]	144	1			T13	1		T17	6		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T13	1		T15	3		T17	5
all_values[3]	auto[0]	auto[0]	auto[0]	148	1			T17	3		T19	1		T48	1
all_values[3]	auto[0]	auto[0]	auto[1]	59	1			T17	4		T160	1		T147	1
all_values[3]	auto[0]	auto[1]	auto[0]	107	1			T13	1		T15	3		T17	5
all_values[3]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T15	1		T17	2
all_values[3]	auto[1]	auto[0]	auto[1]	161	1			T13	1		T15	4		T17	7
all_values[3]	auto[1]	auto[1]	auto[1]	144	1			T13	1		T15	2		T17	11
all_values[4]	auto[0]	auto[0]	auto[0]	136	1			T13	1		T15	2		T17	2
all_values[4]	auto[0]	auto[0]	auto[1]	62	1			T15	2		T17	4		T146	1
all_values[4]	auto[0]	auto[1]	auto[0]	111	1			T17	8		T19	1		T48	1
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T13	1		T17	3		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	170	1			T13	1		T15	4		T17	9
all_values[4]	auto[1]	auto[1]	auto[1]	144	1			T13	1		T15	2		T17	6
all_values[5]	auto[0]	auto[0]	auto[0]	186	1			T13	1		T15	5		T17	10
all_values[5]	auto[0]	auto[1]	auto[0]	183	1			T15	1		T17	4		T19	1
all_values[5]	auto[1]	auto[0]	auto[1]	170	1			T13	1		T15	3		T17	11
all_values[5]	auto[1]	auto[1]	auto[1]	165	1			T13	2		T15	1		T17	7
all_values[6]	auto[0]	auto[0]	auto[0]	134	1			T13	1		T15	2		T17	6
all_values[6]	auto[0]	auto[0]	auto[1]	80	1			T17	4		T48	1		T146	1
all_values[6]	auto[0]	auto[1]	auto[0]	127	1			T13	2		T15	3		T17	3
all_values[6]	auto[0]	auto[1]	auto[1]	53	1			T15	1		T17	5		T147	3
all_values[6]	auto[1]	auto[0]	auto[1]	160	1			T17	5		T19	1		T48	2
all_values[6]	auto[1]	auto[1]	auto[1]	150	1			T13	1		T15	4		T17	9
all_values[7]	auto[0]	auto[0]	auto[0]	147	1			T13	2		T15	3		T17	2
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T17	3		T19	1		T146	1
all_values[7]	auto[0]	auto[1]	auto[0]	128	1			T13	2		T15	2		T17	11
all_values[7]	auto[0]	auto[1]	auto[1]	64	1			T15	1		T17	3		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	165	1			T15	3		T17	6		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	131	1			T15	1		T17	7		T146	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal