Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1901

1

T1

7

T3

3

T11

3

auto[1]

1839

1

T1

14

T3

4

T11

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2191

1

T1

21

T3

6

T11

4

auto[1]

1549

1

T3

1

T11

4

T31

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2904

1

T1

14

T3

7

T11

6

auto[1]

836

1

T1

7

T11

2

T12

6

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	756	1			T1	6		T3	1		T11	2
valid[1]	748	1			T1	2		T3	1		T31	2
valid[2]	762	1			T1	4		T3	3		T11	2
valid[3]	754	1			T1	3		T11	3		T12	2
valid[4]	720	1			T1	6		T3	2		T11	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	138	1			T1	1		T33	1		T45	3
auto[0]	auto[0]	valid[0]	auto[1]	176	1			T11	1		T31	2		T12	2
auto[0]	auto[0]	valid[1]	auto[0]	129	1			T3	1		T12	1		T270	3
auto[0]	auto[0]	valid[1]	auto[1]	163	1			T23	4		T77	1		T78	3
auto[0]	auto[0]	valid[2]	auto[0]	123	1			T12	1		T33	2		T270	1
auto[0]	auto[0]	valid[2]	auto[1]	170	1			T11	1		T31	2		T12	1
auto[0]	auto[0]	valid[3]	auto[0]	133	1			T1	1		T12	1		T33	2
auto[0]	auto[0]	valid[3]	auto[1]	170	1			T29	5		T77	1		T78	5
auto[0]	auto[0]	valid[4]	auto[0]	119	1			T1	3		T3	2		T12	4
auto[0]	auto[0]	valid[4]	auto[1]	159	1			T31	1		T29	1		T77	3
auto[0]	auto[1]	valid[0]	auto[0]	140	1			T1	3		T12	1		T25	1
auto[0]	auto[1]	valid[0]	auto[1]	139	1			T3	1		T23	1		T25	1
auto[0]	auto[1]	valid[1]	auto[0]	127	1			T1	1		T12	2		T45	1
auto[0]	auto[1]	valid[1]	auto[1]	155	1			T31	2		T12	1		T29	1
auto[0]	auto[1]	valid[2]	auto[0]	151	1			T1	2		T3	3		T33	3
auto[0]	auto[1]	valid[2]	auto[1]	157	1			T11	1		T12	1		T23	2
auto[0]	auto[1]	valid[3]	auto[0]	145	1			T11	1		T270	1		T45	1
auto[0]	auto[1]	valid[3]	auto[1]	127	1			T11	1		T29	1		T78	3
auto[0]	auto[1]	valid[4]	auto[0]	150	1			T1	3		T11	1		T12	2
auto[0]	auto[1]	valid[4]	auto[1]	133	1			T12	2		T23	1		T78	1
auto[1]	auto[0]	valid[0]	auto[0]	84	1			T1	1		T270	1		T271	1
auto[1]	auto[0]	valid[1]	auto[0]	93	1			T25	1		T270	1		T265	2
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T1	1		T25	1		T14	2
auto[1]	auto[0]	valid[3]	auto[0]	83	1			T11	1		T12	1		T33	1
auto[1]	auto[0]	valid[4]	auto[0]	90	1			T12	2		T39	1		T33	1
auto[1]	auto[1]	valid[0]	auto[0]	79	1			T1	1		T11	1		T45	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T1	1		T12	1		T33	2
auto[1]	auto[1]	valid[2]	auto[0]	90	1			T1	1		T12	1		T33	1
auto[1]	auto[1]	valid[3]	auto[0]	96	1			T1	2		T270	2		T13	1
auto[1]	auto[1]	valid[4]	auto[0]	69	1			T12	1		T25	2		T39	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal