Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53050

1

T1

412

T3

203

T6

3

auto[1]

15847

1

T3

42

T11

70

T31

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49603

1

T1

264

T3

172

T6

2

auto[1]

19294

1

T1

148

T3

73

T6

1

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35464	1			T1	206		T3	129		T11	134
others[1]	5787	1			T1	23		T3	21		T11	17
others[2]	5832	1			T1	42		T3	20		T11	23
others[3]	6561	1			T1	50		T3	16		T6	1
interest[1]	3882	1			T1	20		T3	18		T6	1
interest[4]	23160	1			T1	132		T3	81		T11	86
interest[64]	11371	1			T1	71		T3	41		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17304	1			T1	127		T3	73		T11	54
auto[0]	auto[0]	others[1]	2794	1			T1	11		T3	11		T11	7
auto[0]	auto[0]	others[2]	2924	1			T1	28		T3	13		T11	9
auto[0]	auto[0]	others[3]	3215	1			T1	36		T3	8		T6	1
auto[0]	auto[0]	interest[1]	1896	1			T1	16		T3	7		T6	1
auto[0]	auto[0]	interest[4]	11295	1			T1	78		T3	46		T11	34
auto[0]	auto[0]	interest[64]	5623	1			T1	46		T3	18		T11	16
auto[0]	auto[1]	others[0]	8288	1			T3	21		T11	38		T31	7
auto[0]	auto[1]	others[1]	1365	1			T3	1		T11	6		T12	11
auto[0]	auto[1]	others[2]	1316	1			T3	3		T11	7		T12	3
auto[0]	auto[1]	others[3]	1482	1			T3	2		T11	4		T12	9
auto[0]	auto[1]	interest[1]	862	1			T3	4		T11	2		T12	3
auto[0]	auto[1]	interest[4]	5486	1			T3	13		T11	23		T31	7
auto[0]	auto[1]	interest[64]	2534	1			T3	11		T11	13		T12	17
auto[1]	auto[0]	others[0]	9872	1			T1	79		T3	35		T11	42
auto[1]	auto[0]	others[1]	1628	1			T1	12		T3	9		T11	4
auto[1]	auto[0]	others[2]	1592	1			T1	14		T3	4		T11	7
auto[1]	auto[0]	others[3]	1864	1			T1	14		T3	6		T11	7
auto[1]	auto[0]	interest[1]	1124	1			T1	4		T3	7		T11	7
auto[1]	auto[0]	interest[4]	6379	1			T1	54		T3	22		T11	29
auto[1]	auto[0]	interest[64]	3214	1			T1	25		T3	12		T6	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal