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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.08 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1150
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T96 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4134518930 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:47 PM PDT 24 1812528384 ps
T93 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3395971331 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:06 PM PDT 24 110445928 ps
T141 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2237815593 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:06 PM PDT 24 1336328133 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1187213628 Jul 25 06:25:45 PM PDT 24 Jul 25 06:25:48 PM PDT 24 234186374 ps
T101 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.452623892 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:03 PM PDT 24 509717241 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1649041262 Jul 25 06:25:35 PM PDT 24 Jul 25 06:25:37 PM PDT 24 87024472 ps
T1038 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1655537596 Jul 25 06:25:39 PM PDT 24 Jul 25 06:25:40 PM PDT 24 39320325 ps
T1039 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3073179924 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:45 PM PDT 24 234485423 ps
T73 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3269692658 Jul 25 06:25:40 PM PDT 24 Jul 25 06:25:42 PM PDT 24 22011380 ps
T1040 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3778000915 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 12362903 ps
T1041 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1401104654 Jul 25 06:25:49 PM PDT 24 Jul 25 06:25:50 PM PDT 24 65954176 ps
T166 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.253813057 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:57 PM PDT 24 2096294831 ps
T113 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.675470070 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:03 PM PDT 24 99935654 ps
T74 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3806136745 Jul 25 06:25:36 PM PDT 24 Jul 25 06:25:38 PM PDT 24 29257500 ps
T1042 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3410210017 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 29579641 ps
T97 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2375535208 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:06 PM PDT 24 65888560 ps
T99 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3789631617 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:02 PM PDT 24 61325771 ps
T1043 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1475144043 Jul 25 06:26:14 PM PDT 24 Jul 25 06:26:15 PM PDT 24 26654976 ps
T168 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3724530493 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:06 PM PDT 24 430189339 ps
T114 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.847176316 Jul 25 06:25:43 PM PDT 24 Jul 25 06:26:10 PM PDT 24 2870316288 ps
T142 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1952936049 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:45 PM PDT 24 75931256 ps
T105 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.149575197 Jul 25 06:25:44 PM PDT 24 Jul 25 06:25:51 PM PDT 24 798406245 ps
T143 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2462967223 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:52 PM PDT 24 403861196 ps
T1044 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3809895851 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 19030841 ps
T115 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.622692863 Jul 25 06:25:47 PM PDT 24 Jul 25 06:25:49 PM PDT 24 96426437 ps
T116 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3672247955 Jul 25 06:25:46 PM PDT 24 Jul 25 06:25:48 PM PDT 24 27046612 ps
T169 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2789734455 Jul 25 06:25:43 PM PDT 24 Jul 25 06:26:04 PM PDT 24 3820468109 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1731645534 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:44 PM PDT 24 16743094 ps
T1046 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2007494014 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:05 PM PDT 24 99862310 ps
T117 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.658365771 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:00 PM PDT 24 29782580 ps
T1047 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2436094597 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:04 PM PDT 24 114806193 ps
T1048 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3814280361 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:44 PM PDT 24 49092211 ps
T144 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1902929069 Jul 25 06:25:40 PM PDT 24 Jul 25 06:25:57 PM PDT 24 907837041 ps
T1049 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2934166908 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:04 PM PDT 24 61398266 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2172092986 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:43 PM PDT 24 22225758 ps
T100 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3725393456 Jul 25 06:25:47 PM PDT 24 Jul 25 06:25:52 PM PDT 24 265886495 ps
T145 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3734983528 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:07 PM PDT 24 717085306 ps
T104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1974581783 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:03 PM PDT 24 697510963 ps
T170 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2159084525 Jul 25 06:25:39 PM PDT 24 Jul 25 06:25:55 PM PDT 24 1130142121 ps
T1051 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2252262028 Jul 25 06:26:02 PM PDT 24 Jul 25 06:26:03 PM PDT 24 11870936 ps
T1052 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2748909350 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:47 PM PDT 24 53766686 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.990529876 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:52 PM PDT 24 709763259 ps
T1053 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.418176716 Jul 25 06:26:13 PM PDT 24 Jul 25 06:26:14 PM PDT 24 12555025 ps
T1054 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.144773454 Jul 25 06:25:47 PM PDT 24 Jul 25 06:25:51 PM PDT 24 125672714 ps
T1055 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.285363625 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 20297506 ps
T102 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.195449777 Jul 25 06:25:36 PM PDT 24 Jul 25 06:25:41 PM PDT 24 339645502 ps
T1056 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.565977897 Jul 25 06:25:57 PM PDT 24 Jul 25 06:26:00 PM PDT 24 47881417 ps
T1057 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2941725978 Jul 25 06:26:15 PM PDT 24 Jul 25 06:26:16 PM PDT 24 13653155 ps
T119 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2072337931 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:03 PM PDT 24 886514431 ps
T1058 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1181374855 Jul 25 06:25:58 PM PDT 24 Jul 25 06:25:59 PM PDT 24 20367304 ps
T1059 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3461854786 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:02 PM PDT 24 135436574 ps
T1060 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3702121819 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:02 PM PDT 24 240068180 ps
T1061 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2216819625 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 24163319 ps
T1062 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2347799100 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 15789926 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3108974570 Jul 25 06:25:40 PM PDT 24 Jul 25 06:25:45 PM PDT 24 153903560 ps
T1064 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4039919912 Jul 25 06:25:51 PM PDT 24 Jul 25 06:25:55 PM PDT 24 155045566 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1474853558 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:58 PM PDT 24 1226473025 ps
T1066 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1557655142 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 20167000 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2275867210 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:47 PM PDT 24 154942999 ps
T1068 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1579338734 Jul 25 06:25:40 PM PDT 24 Jul 25 06:25:43 PM PDT 24 665260296 ps
T1069 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3628982486 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 13993376 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2473159269 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:47 PM PDT 24 220631075 ps
T1071 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2905487484 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:45 PM PDT 24 199397200 ps
T1072 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.543509730 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 34208504 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.749258081 Jul 25 06:26:03 PM PDT 24 Jul 25 06:26:06 PM PDT 24 174182635 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.525859232 Jul 25 06:25:33 PM PDT 24 Jul 25 06:25:34 PM PDT 24 48957809 ps
T1075 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2210419216 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:44 PM PDT 24 124976764 ps
T1076 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2745575863 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:05 PM PDT 24 516899596 ps
T75 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2002042745 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:43 PM PDT 24 24331486 ps
T1077 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.870611286 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:02 PM PDT 24 68378358 ps
T171 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.997213846 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:19 PM PDT 24 570541289 ps
T1078 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1248448652 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:44 PM PDT 24 24887489 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1197573601 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:46 PM PDT 24 532082812 ps
T172 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3033200185 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:15 PM PDT 24 4851387412 ps
T1080 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1283045338 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:01 PM PDT 24 42546242 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3354268930 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:45 PM PDT 24 168043570 ps
T1082 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2411501820 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:01 PM PDT 24 69814546 ps
T1083 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2651260174 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 36179860 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1321506612 Jul 25 06:25:33 PM PDT 24 Jul 25 06:25:34 PM PDT 24 45629186 ps
T1085 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1480222726 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:02 PM PDT 24 83414778 ps
T1086 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2341658193 Jul 25 06:26:04 PM PDT 24 Jul 25 06:26:05 PM PDT 24 52936755 ps
T1087 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.220910008 Jul 25 06:26:02 PM PDT 24 Jul 25 06:26:06 PM PDT 24 348249203 ps
T1088 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2336807179 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:02 PM PDT 24 40043943 ps
T1089 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1407048547 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 55941886 ps
T1090 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.113789002 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:00 PM PDT 24 22419010 ps
T76 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2301290075 Jul 25 06:25:36 PM PDT 24 Jul 25 06:25:38 PM PDT 24 289177694 ps
T1091 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2922360412 Jul 25 06:25:35 PM PDT 24 Jul 25 06:25:36 PM PDT 24 11954642 ps
T1092 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3519723546 Jul 25 06:26:13 PM PDT 24 Jul 25 06:26:14 PM PDT 24 18187753 ps
T1093 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2796192300 Jul 25 06:25:49 PM PDT 24 Jul 25 06:25:52 PM PDT 24 151613086 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1066193726 Jul 25 06:25:40 PM PDT 24 Jul 25 06:25:41 PM PDT 24 31083806 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1575348072 Jul 25 06:25:48 PM PDT 24 Jul 25 06:25:52 PM PDT 24 153884318 ps
T1096 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1115457903 Jul 25 06:26:12 PM PDT 24 Jul 25 06:26:13 PM PDT 24 32887195 ps
T1097 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3938891185 Jul 25 06:25:46 PM PDT 24 Jul 25 06:25:47 PM PDT 24 19734168 ps
T1098 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.350610483 Jul 25 06:26:13 PM PDT 24 Jul 25 06:26:14 PM PDT 24 16501570 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.966937659 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:42 PM PDT 24 51790180 ps
T1100 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2245417135 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:02 PM PDT 24 23452787 ps
T1101 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.170372397 Jul 25 06:25:44 PM PDT 24 Jul 25 06:25:47 PM PDT 24 377543506 ps
T1102 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2049989565 Jul 25 06:25:45 PM PDT 24 Jul 25 06:25:47 PM PDT 24 80083789 ps
T1103 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4034640654 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:59 PM PDT 24 2317340343 ps
T1104 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1851060916 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:02 PM PDT 24 107262130 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2517754311 Jul 25 06:25:39 PM PDT 24 Jul 25 06:26:02 PM PDT 24 5432070101 ps
T165 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.402978975 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:03 PM PDT 24 221057930 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2711241106 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:01 PM PDT 24 122071028 ps
T1107 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.996257369 Jul 25 06:26:13 PM PDT 24 Jul 25 06:26:14 PM PDT 24 18289459 ps
T1108 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2806217986 Jul 25 06:25:57 PM PDT 24 Jul 25 06:26:00 PM PDT 24 98739382 ps
T1109 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4249388489 Jul 25 06:25:39 PM PDT 24 Jul 25 06:25:42 PM PDT 24 436182218 ps
T1110 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1313987860 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:03 PM PDT 24 58113895 ps
T1111 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1082427826 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:42 PM PDT 24 40618209 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3869165166 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:03 PM PDT 24 219877443 ps
T1113 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1521988386 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 24829604 ps
T1114 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1614604742 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 14698358 ps
T1115 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3570370080 Jul 25 06:26:02 PM PDT 24 Jul 25 06:26:03 PM PDT 24 52137673 ps
T1116 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1120040636 Jul 25 06:25:37 PM PDT 24 Jul 25 06:26:00 PM PDT 24 3725799477 ps
T1117 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4029611905 Jul 25 06:25:45 PM PDT 24 Jul 25 06:25:46 PM PDT 24 29734869 ps
T1118 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.265145608 Jul 25 06:25:40 PM PDT 24 Jul 25 06:26:05 PM PDT 24 1250807140 ps
T1119 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2547417371 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:45 PM PDT 24 82087394 ps
T1120 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3046687865 Jul 25 06:25:47 PM PDT 24 Jul 25 06:25:49 PM PDT 24 39205859 ps
T1121 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2519881510 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:12 PM PDT 24 13286877 ps
T1122 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.540539226 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:03 PM PDT 24 87029836 ps
T1123 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2579288589 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:02 PM PDT 24 42714544 ps
T1124 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.174260856 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:50 PM PDT 24 646228857 ps
T1125 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.349392204 Jul 25 06:25:46 PM PDT 24 Jul 25 06:25:53 PM PDT 24 616769315 ps
T1126 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2508342715 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 54230101 ps
T1127 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4099304669 Jul 25 06:26:13 PM PDT 24 Jul 25 06:26:14 PM PDT 24 13735700 ps
T1128 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1897274530 Jul 25 06:25:45 PM PDT 24 Jul 25 06:25:50 PM PDT 24 229463834 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3576288919 Jul 25 06:25:49 PM PDT 24 Jul 25 06:26:11 PM PDT 24 816387222 ps
T1130 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.802036789 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:05 PM PDT 24 120528189 ps
T1131 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2014660 Jul 25 06:26:11 PM PDT 24 Jul 25 06:26:11 PM PDT 24 94324163 ps
T1132 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3907300712 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:47 PM PDT 24 1120044329 ps
T174 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2557791567 Jul 25 06:25:42 PM PDT 24 Jul 25 06:26:01 PM PDT 24 1169555601 ps
T1133 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.857791935 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 25014139 ps
T1134 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3910564013 Jul 25 06:26:02 PM PDT 24 Jul 25 06:26:12 PM PDT 24 1445549611 ps
T1135 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.262169387 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:04 PM PDT 24 881870280 ps
T1136 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3648822015 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:01 PM PDT 24 18537057 ps
T1137 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3860674795 Jul 25 06:25:46 PM PDT 24 Jul 25 06:25:47 PM PDT 24 39408718 ps
T1138 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2633440384 Jul 25 06:26:02 PM PDT 24 Jul 25 06:26:06 PM PDT 24 109801705 ps
T1139 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2475299293 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:02 PM PDT 24 145342480 ps
T167 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2258662622 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:12 PM PDT 24 392060010 ps
T1140 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3816288913 Jul 25 06:26:01 PM PDT 24 Jul 25 06:26:03 PM PDT 24 73071058 ps
T1141 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1484901125 Jul 25 06:26:00 PM PDT 24 Jul 25 06:26:03 PM PDT 24 100199815 ps
T173 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.936820757 Jul 25 06:25:42 PM PDT 24 Jul 25 06:26:01 PM PDT 24 1139297835 ps
T1142 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3807425867 Jul 25 06:25:58 PM PDT 24 Jul 25 06:26:02 PM PDT 24 147526927 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4177576067 Jul 25 06:25:42 PM PDT 24 Jul 25 06:25:46 PM PDT 24 147905423 ps
T1144 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1735292585 Jul 25 06:25:43 PM PDT 24 Jul 25 06:25:44 PM PDT 24 20999818 ps
T1145 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.809793594 Jul 25 06:25:49 PM PDT 24 Jul 25 06:25:51 PM PDT 24 47320258 ps
T1146 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2756066130 Jul 25 06:25:41 PM PDT 24 Jul 25 06:25:43 PM PDT 24 144121537 ps
T1147 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1797840598 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:04 PM PDT 24 856231417 ps
T1148 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.416747073 Jul 25 06:25:40 PM PDT 24 Jul 25 06:26:14 PM PDT 24 551444985 ps
T1149 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.628403468 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:00 PM PDT 24 91443101 ps
T1150 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2319020773 Jul 25 06:25:59 PM PDT 24 Jul 25 06:26:02 PM PDT 24 54790123 ps

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2809116352
Short name T3
Test name
Test status
Simulation time 5486940964 ps
CPU time 53.4 seconds
Started Jul 25 05:50:05 PM PDT 24
Finished Jul 25 05:50:59 PM PDT 24
Peak memory 253468 kb
Host smart-5d2d20f3-625a-4375-a7c7-b0e219d03612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809116352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2809116352
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.780772944
Short name T12
Test name
Test status
Simulation time 94512680802 ps
CPU time 961.25 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 06:07:22 PM PDT 24
Peak memory 282956 kb
Host smart-1b12f4f4-65db-4c18-b42c-ca7253d6ae1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780772944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.780772944
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2548969453
Short name T15
Test name
Test status
Simulation time 479173107805 ps
CPU time 868.31 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 270708 kb
Host smart-724c893b-a72a-47b2-86c1-539866673695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548969453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2548969453
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4019607688
Short name T88
Test name
Test status
Simulation time 371511130 ps
CPU time 8.93 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:09 PM PDT 24
Peak memory 216624 kb
Host smart-baab7244-95f8-4f52-9262-41bb342ec4ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019607688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4019607688
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3839151509
Short name T18
Test name
Test status
Simulation time 72160195339 ps
CPU time 829.37 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 06:01:42 PM PDT 24
Peak memory 304008 kb
Host smart-de91dc2b-453f-48d6-9c3c-4df8231d1752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839151509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3839151509
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.766045029
Short name T58
Test name
Test status
Simulation time 30784712 ps
CPU time 0.8 seconds
Started Jul 25 05:47:43 PM PDT 24
Finished Jul 25 05:47:44 PM PDT 24
Peak memory 216860 kb
Host smart-07a150f5-72a8-4f3d-8cb1-c75332701042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766045029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.766045029
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1224142137
Short name T14
Test name
Test status
Simulation time 479872228771 ps
CPU time 1115.62 seconds
Started Jul 25 05:51:43 PM PDT 24
Finished Jul 25 06:10:19 PM PDT 24
Peak memory 285480 kb
Host smart-249a7ed7-b1cf-4e50-b1e7-de73fc12a4e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224142137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1224142137
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.613553245
Short name T48
Test name
Test status
Simulation time 97066874839 ps
CPU time 943.91 seconds
Started Jul 25 05:48:18 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 267908 kb
Host smart-fdc65e4a-eb0e-47f8-8ba3-6fb30ba83f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613553245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.613553245
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4134518930
Short name T96
Test name
Test status
Simulation time 1812528384 ps
CPU time 4.14 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 216176 kb
Host smart-fcd6d741-3167-44c7-9801-dc0ab3ec86d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134518930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
134518930
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2569430468
Short name T21
Test name
Test status
Simulation time 59262781686 ps
CPU time 564.27 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:59:46 PM PDT 24
Peak memory 286460 kb
Host smart-006ccdfc-7828-4364-a673-47f10b426b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569430468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2569430468
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.555666416
Short name T300
Test name
Test status
Simulation time 24320595 ps
CPU time 0.71 seconds
Started Jul 25 05:49:09 PM PDT 24
Finished Jul 25 05:49:10 PM PDT 24
Peak memory 205464 kb
Host smart-c1007a57-f781-4f75-9850-f340af314973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555666416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.555666416
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2691848269
Short name T42
Test name
Test status
Simulation time 926895511 ps
CPU time 8.09 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 233640 kb
Host smart-de460282-3877-43a5-97b2-b477ac8cdca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691848269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2691848269
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2942091979
Short name T33
Test name
Test status
Simulation time 339086484553 ps
CPU time 822.24 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 06:05:20 PM PDT 24
Peak memory 268536 kb
Host smart-92ec9a58-424a-4586-9f62-27d5dab8f3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942091979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2942091979
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2718538048
Short name T95
Test name
Test status
Simulation time 129818477002 ps
CPU time 505.4 seconds
Started Jul 25 05:49:33 PM PDT 24
Finished Jul 25 05:57:59 PM PDT 24
Peak memory 262776 kb
Host smart-5712e583-5d8c-4cd4-9332-febf6a6c01b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718538048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2718538048
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3269692658
Short name T73
Test name
Test status
Simulation time 22011380 ps
CPU time 1.39 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:25:42 PM PDT 24
Peak memory 216988 kb
Host smart-d135294f-d7d2-45e7-a82a-4e50daa807d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269692658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3269692658
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1972360003
Short name T147
Test name
Test status
Simulation time 11818326301 ps
CPU time 178.92 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:53:20 PM PDT 24
Peak memory 255128 kb
Host smart-6261ea2f-890a-4ed3-992a-74b5660235e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972360003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1972360003
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.143213741
Short name T35
Test name
Test status
Simulation time 48114960 ps
CPU time 1.04 seconds
Started Jul 25 05:47:43 PM PDT 24
Finished Jul 25 05:47:44 PM PDT 24
Peak memory 217444 kb
Host smart-f9327084-8378-49bb-9072-f13af91ad32c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143213741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.143213741
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4258318669
Short name T16
Test name
Test status
Simulation time 223462080210 ps
CPU time 578 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:59:52 PM PDT 24
Peak memory 290732 kb
Host smart-83dd3405-bcae-483a-a76a-86b69b44f748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258318669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4258318669
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1107032924
Short name T25
Test name
Test status
Simulation time 24128456119 ps
CPU time 120.09 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:50:49 PM PDT 24
Peak memory 267796 kb
Host smart-16a9f031-377c-4490-8921-f65ce8b6c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107032924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1107032924
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.218634802
Short name T59
Test name
Test status
Simulation time 35135427 ps
CPU time 0.97 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:47:56 PM PDT 24
Peak memory 236204 kb
Host smart-cb44aaa7-b5d1-46ea-8f07-f757fb7c5320
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218634802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.218634802
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2775332875
Short name T205
Test name
Test status
Simulation time 37222511708 ps
CPU time 338.9 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:56:36 PM PDT 24
Peak memory 254624 kb
Host smart-38528ff6-9378-4879-ba83-214562d5e75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775332875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2775332875
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3403673833
Short name T246
Test name
Test status
Simulation time 15660411449 ps
CPU time 78.8 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:51:19 PM PDT 24
Peak memory 255784 kb
Host smart-c78d385d-b6ca-4319-a798-d03fefe799ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403673833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3403673833
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3770359826
Short name T243
Test name
Test status
Simulation time 15028134451 ps
CPU time 155.74 seconds
Started Jul 25 05:49:28 PM PDT 24
Finished Jul 25 05:52:04 PM PDT 24
Peak memory 251772 kb
Host smart-aee3fdc5-4856-4d8d-a783-741bd561a51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770359826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3770359826
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3215650100
Short name T236
Test name
Test status
Simulation time 84015092540 ps
CPU time 475.72 seconds
Started Jul 25 05:50:53 PM PDT 24
Finished Jul 25 05:58:49 PM PDT 24
Peak memory 258312 kb
Host smart-0bf49fd8-af56-4e5b-9668-96c19a81fdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215650100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3215650100
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3725393456
Short name T100
Test name
Test status
Simulation time 265886495 ps
CPU time 4.48 seconds
Started Jul 25 06:25:47 PM PDT 24
Finished Jul 25 06:25:52 PM PDT 24
Peak memory 217292 kb
Host smart-2e6f6ad6-ab48-441a-82f6-1b411fc57c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725393456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
725393456
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2974994303
Short name T176
Test name
Test status
Simulation time 32760831635 ps
CPU time 243.19 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:55:22 PM PDT 24
Peak memory 269048 kb
Host smart-f89a1f09-10a6-4e21-a3b8-2ed6ed10a7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974994303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2974994303
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1855657563
Short name T161
Test name
Test status
Simulation time 77130784 ps
CPU time 0.88 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 207312 kb
Host smart-5cae934c-777c-4ff2-a28e-11c93dc71edf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855657563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1855657563
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2258662622
Short name T167
Test name
Test status
Simulation time 392060010 ps
CPU time 12.25 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 216040 kb
Host smart-a105099b-d4af-4e62-8e79-6b8469fd0ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258662622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2258662622
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1649101470
Short name T10
Test name
Test status
Simulation time 10482877231 ps
CPU time 7.23 seconds
Started Jul 25 05:47:42 PM PDT 24
Finished Jul 25 05:47:49 PM PDT 24
Peak memory 233644 kb
Host smart-90aa9404-3494-46ce-a484-4c1105727eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649101470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1649101470
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.538010739
Short name T659
Test name
Test status
Simulation time 16193683817 ps
CPU time 90.52 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:50:47 PM PDT 24
Peak memory 258304 kb
Host smart-b74823fe-d9b4-43f3-8983-e4cbe63c0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538010739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.538010739
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.544963625
Short name T138
Test name
Test status
Simulation time 13126120153 ps
CPU time 44.55 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:51:07 PM PDT 24
Peak memory 233688 kb
Host smart-4607e6fb-057e-4a70-b59e-49983c8bf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544963625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.544963625
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4034640654
Short name T1103
Test name
Test status
Simulation time 2317340343 ps
CPU time 16.1 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:59 PM PDT 24
Peak memory 216208 kb
Host smart-bf5ed966-fa3d-428d-ada2-f0b0cbc90fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034640654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4034640654
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3603586525
Short name T239
Test name
Test status
Simulation time 13086514653 ps
CPU time 198.1 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 05:51:10 PM PDT 24
Peak memory 256312 kb
Host smart-b8132537-8b42-44c3-a1ae-aa80e9ff29f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603586525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3603586525
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3281249607
Short name T34
Test name
Test status
Simulation time 189707616077 ps
CPU time 583.07 seconds
Started Jul 25 05:47:57 PM PDT 24
Finished Jul 25 05:57:40 PM PDT 24
Peak memory 253364 kb
Host smart-72b110fc-9e9b-4fcf-a43a-55b2d9f6bbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281249607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3281249607
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1125626925
Short name T679
Test name
Test status
Simulation time 319620838126 ps
CPU time 511.06 seconds
Started Jul 25 05:50:25 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 274160 kb
Host smart-a4ce422b-c1a5-40de-b2b2-475f36e40350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125626925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1125626925
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2557791567
Short name T174
Test name
Test status
Simulation time 1169555601 ps
CPU time 19.17 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 216636 kb
Host smart-1d885d17-52a4-4211-ac1f-38053d2e0b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557791567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2557791567
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.936820757
Short name T173
Test name
Test status
Simulation time 1139297835 ps
CPU time 17.79 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 216004 kb
Host smart-bb3f5196-4512-4313-9c1d-02cf4a4ccbcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936820757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.936820757
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3025044556
Short name T261
Test name
Test status
Simulation time 4467141615 ps
CPU time 20.59 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 233708 kb
Host smart-23f4f79f-7fb4-4d9b-9ab6-81d18c28c3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025044556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3025044556
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3639884329
Short name T234
Test name
Test status
Simulation time 36020620466 ps
CPU time 116.21 seconds
Started Jul 25 05:50:36 PM PDT 24
Finished Jul 25 05:52:32 PM PDT 24
Peak memory 265268 kb
Host smart-42e27b66-2133-4a08-8b0a-4353dcf79e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639884329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3639884329
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3381294520
Short name T255
Test name
Test status
Simulation time 25294600856 ps
CPU time 49.39 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:51:46 PM PDT 24
Peak memory 225372 kb
Host smart-75accb34-ab42-436c-8cff-e77f688b320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381294520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3381294520
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3485873021
Short name T439
Test name
Test status
Simulation time 847709865 ps
CPU time 10.37 seconds
Started Jul 25 05:47:47 PM PDT 24
Finished Jul 25 05:47:58 PM PDT 24
Peak memory 233584 kb
Host smart-ea839881-4068-4968-b5e0-88bbb42f155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485873021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3485873021
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2838765477
Short name T220
Test name
Test status
Simulation time 34710949721 ps
CPU time 22.83 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 233664 kb
Host smart-71936970-130b-4fad-a1c5-be530491ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838765477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2838765477
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1974581783
Short name T104
Test name
Test status
Simulation time 697510963 ps
CPU time 5.17 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216208 kb
Host smart-25764f67-c2f9-44e0-b053-d4ddd4dc7aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974581783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1974581783
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2517754311
Short name T1105
Test name
Test status
Simulation time 5432070101 ps
CPU time 22.42 seconds
Started Jul 25 06:25:39 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 216116 kb
Host smart-edf3bd32-87b6-450e-920f-4aadfff86426
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517754311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2517754311
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.416747073
Short name T1148
Test name
Test status
Simulation time 551444985 ps
CPU time 34.2 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 207820 kb
Host smart-2ba9b71a-3e0a-4e79-a119-2116f3bb4472
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416747073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.416747073
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2301290075
Short name T76
Test name
Test status
Simulation time 289177694 ps
CPU time 1.44 seconds
Started Jul 25 06:25:36 PM PDT 24
Finished Jul 25 06:25:38 PM PDT 24
Peak memory 207848 kb
Host smart-c023a2a5-63b2-4301-96b8-3d6ed5e6c816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301290075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2301290075
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2905487484
Short name T1071
Test name
Test status
Simulation time 199397200 ps
CPU time 2.83 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 217064 kb
Host smart-17868a58-72fa-4fb0-95d9-e6b4779c37d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905487484 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2905487484
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2547417371
Short name T1119
Test name
Test status
Simulation time 82087394 ps
CPU time 1.33 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 207904 kb
Host smart-624b2c35-1814-4152-92fa-e5ae6ca77685
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547417371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
547417371
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.966937659
Short name T1099
Test name
Test status
Simulation time 51790180 ps
CPU time 0.8 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:42 PM PDT 24
Peak memory 204496 kb
Host smart-faed3341-463f-4e9d-985b-83518d550f8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966937659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.966937659
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1649041262
Short name T112
Test name
Test status
Simulation time 87024472 ps
CPU time 1.76 seconds
Started Jul 25 06:25:35 PM PDT 24
Finished Jul 25 06:25:37 PM PDT 24
Peak memory 216088 kb
Host smart-e9793132-5c22-492f-8e9b-deb1e2217d04
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649041262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1649041262
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.525859232
Short name T1074
Test name
Test status
Simulation time 48957809 ps
CPU time 0.64 seconds
Started Jul 25 06:25:33 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 204388 kb
Host smart-551a1b8c-e945-49d2-a3c9-ad31c0302de1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525859232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.525859232
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3045137463
Short name T1033
Test name
Test status
Simulation time 82045576 ps
CPU time 2.72 seconds
Started Jul 25 06:25:37 PM PDT 24
Finished Jul 25 06:25:40 PM PDT 24
Peak memory 216020 kb
Host smart-e1d9ccab-4083-488d-8601-c12c4b044f85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045137463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3045137463
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.4249388489
Short name T1109
Test name
Test status
Simulation time 436182218 ps
CPU time 1.86 seconds
Started Jul 25 06:25:39 PM PDT 24
Finished Jul 25 06:25:42 PM PDT 24
Peak memory 216216 kb
Host smart-54c27cbf-fb78-4ab8-930b-9a7b409c6e13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249388489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.4
249388489
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1120040636
Short name T1116
Test name
Test status
Simulation time 3725799477 ps
CPU time 23.01 seconds
Started Jul 25 06:25:37 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 207924 kb
Host smart-7ac57940-e4c0-4ae3-ae16-6235cb326e2e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120040636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1120040636
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.265145608
Short name T1118
Test name
Test status
Simulation time 1250807140 ps
CPU time 24.34 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:26:05 PM PDT 24
Peak memory 207884 kb
Host smart-c4f88d5e-bf28-4e8d-b1ba-f4c44f1a2245
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265145608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.265145608
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1066193726
Short name T1094
Test name
Test status
Simulation time 31083806 ps
CPU time 1.13 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:25:41 PM PDT 24
Peak memory 207828 kb
Host smart-e9cec2b3-83b1-47b2-87b5-e89014662427
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066193726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1066193726
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2756066130
Short name T1146
Test name
Test status
Simulation time 144121537 ps
CPU time 1.94 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 217140 kb
Host smart-63ebf889-ca7f-43bc-a782-c23573406eec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756066130 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2756066130
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1082427826
Short name T1111
Test name
Test status
Simulation time 40618209 ps
CPU time 1.33 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:42 PM PDT 24
Peak memory 207880 kb
Host smart-19adcb04-14c3-40fb-b45b-f806540a1b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082427826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
082427826
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1655537596
Short name T1038
Test name
Test status
Simulation time 39320325 ps
CPU time 0.67 seconds
Started Jul 25 06:25:39 PM PDT 24
Finished Jul 25 06:25:40 PM PDT 24
Peak memory 204480 kb
Host smart-23718ce9-c1db-4641-b9df-bb754c80eef5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655537596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
655537596
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3354268930
Short name T1081
Test name
Test status
Simulation time 168043570 ps
CPU time 1.53 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 216140 kb
Host smart-9450434d-017c-4dab-8ceb-4a6b30cc69cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354268930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3354268930
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3814280361
Short name T1048
Test name
Test status
Simulation time 49092211 ps
CPU time 0.67 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 204416 kb
Host smart-9f49e98f-be31-4001-836e-3156e8d86d19
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814280361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3814280361
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1952936049
Short name T142
Test name
Test status
Simulation time 75931256 ps
CPU time 1.83 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 215976 kb
Host smart-1f49e8cf-37f7-49a4-98c5-d4fc68625076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952936049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1952936049
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3108974570
Short name T1063
Test name
Test status
Simulation time 153903560 ps
CPU time 4.35 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 216244 kb
Host smart-3f15371b-1fc2-4728-8217-521eaf478547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108974570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
108974570
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2159084525
Short name T170
Test name
Test status
Simulation time 1130142121 ps
CPU time 15.09 seconds
Started Jul 25 06:25:39 PM PDT 24
Finished Jul 25 06:25:55 PM PDT 24
Peak memory 216112 kb
Host smart-de7c522e-e879-4f95-9d5c-6eff176eb927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159084525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2159084525
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2796192300
Short name T1093
Test name
Test status
Simulation time 151613086 ps
CPU time 2.89 seconds
Started Jul 25 06:25:49 PM PDT 24
Finished Jul 25 06:25:52 PM PDT 24
Peak memory 218596 kb
Host smart-e25bedfc-e879-457b-89d0-78e4132328b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796192300 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2796192300
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3046687865
Short name T1120
Test name
Test status
Simulation time 39205859 ps
CPU time 2.48 seconds
Started Jul 25 06:25:47 PM PDT 24
Finished Jul 25 06:25:49 PM PDT 24
Peak memory 207972 kb
Host smart-a12f105e-41a5-4009-a398-8de5e70833c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046687865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3046687865
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3350444222
Short name T1035
Test name
Test status
Simulation time 15626626 ps
CPU time 0.78 seconds
Started Jul 25 06:25:57 PM PDT 24
Finished Jul 25 06:25:58 PM PDT 24
Peak memory 204840 kb
Host smart-25fec760-bf12-4e57-982f-c6b79ead20a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350444222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3350444222
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3542386685
Short name T140
Test name
Test status
Simulation time 194721159 ps
CPU time 4.47 seconds
Started Jul 25 06:25:57 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 215832 kb
Host smart-a93b252a-1129-4c2c-85d2-61a1ef6585e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542386685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3542386685
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3576288919
Short name T1129
Test name
Test status
Simulation time 816387222 ps
CPU time 21.59 seconds
Started Jul 25 06:25:49 PM PDT 24
Finished Jul 25 06:26:11 PM PDT 24
Peak memory 216076 kb
Host smart-f4a529b8-4e12-46fb-bd26-3e99edfc4bac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576288919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3576288919
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2806217986
Short name T1108
Test name
Test status
Simulation time 98739382 ps
CPU time 2.62 seconds
Started Jul 25 06:25:57 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 217656 kb
Host smart-2a9c42d3-be76-4b66-b545-55fefe9cdfbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806217986 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2806217986
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.658365771
Short name T117
Test name
Test status
Simulation time 29782580 ps
CPU time 1.99 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 216072 kb
Host smart-c950b6ef-a2ec-4e70-8fe0-4f7312715e1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658365771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.658365771
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3778000915
Short name T1040
Test name
Test status
Simulation time 12362903 ps
CPU time 0.69 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 204452 kb
Host smart-b5db8805-931b-4bd1-b3cf-7c20e6da66e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778000915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3778000915
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.220910008
Short name T1087
Test name
Test status
Simulation time 348249203 ps
CPU time 3.36 seconds
Started Jul 25 06:26:02 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216028 kb
Host smart-90b2e9ec-daa4-4cd9-9622-ac2eb509342d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220910008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.220910008
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1897274530
Short name T1128
Test name
Test status
Simulation time 229463834 ps
CPU time 4.09 seconds
Started Jul 25 06:25:45 PM PDT 24
Finished Jul 25 06:25:50 PM PDT 24
Peak memory 216176 kb
Host smart-af85fd65-c530-4633-bc8f-91b409dd09a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897274530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1897274530
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2633440384
Short name T1138
Test name
Test status
Simulation time 109801705 ps
CPU time 3.64 seconds
Started Jul 25 06:26:02 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 217804 kb
Host smart-bb9325d1-8eeb-440d-9886-02acadfd2c3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633440384 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2633440384
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3065965249
Short name T1036
Test name
Test status
Simulation time 37125689 ps
CPU time 1.34 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 207816 kb
Host smart-ed58ef28-cbfa-4e71-a91b-3947358efdaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065965249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3065965249
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2336807179
Short name T1088
Test name
Test status
Simulation time 40043943 ps
CPU time 0.71 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 204516 kb
Host smart-0ef54ea3-0236-4750-a644-1a09c1eff9ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336807179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2336807179
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2319020773
Short name T1150
Test name
Test status
Simulation time 54790123 ps
CPU time 2.99 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 216116 kb
Host smart-f8a7892b-a8c4-4b39-890a-1960c059baca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319020773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2319020773
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.306401842
Short name T98
Test name
Test status
Simulation time 268781207 ps
CPU time 2.06 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216176 kb
Host smart-15ce21e2-b3d4-4e40-9372-e19f1b140663
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306401842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.306401842
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2237815593
Short name T141
Test name
Test status
Simulation time 1336328133 ps
CPU time 8.06 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216212 kb
Host smart-0ef521ba-7d69-4190-814f-88de54a9c3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237815593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2237815593
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2745575863
Short name T1076
Test name
Test status
Simulation time 516899596 ps
CPU time 4.14 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:05 PM PDT 24
Peak memory 217860 kb
Host smart-79db15ec-1038-4aef-a34c-70821c70023e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745575863 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2745575863
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1851060916
Short name T1104
Test name
Test status
Simulation time 107262130 ps
CPU time 2.8 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 216060 kb
Host smart-3a7ebf4b-222a-4ee0-800a-033f648fd417
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851060916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1851060916
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.857791935
Short name T1133
Test name
Test status
Simulation time 25014139 ps
CPU time 0.73 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 204548 kb
Host smart-f5298ae3-3faf-4279-9159-6841cef52f31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857791935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.857791935
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.802036789
Short name T1130
Test name
Test status
Simulation time 120528189 ps
CPU time 4.17 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:05 PM PDT 24
Peak memory 216036 kb
Host smart-067951fb-da1d-41c5-87fa-c4f5da52bb1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802036789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.802036789
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2475299293
Short name T1139
Test name
Test status
Simulation time 145342480 ps
CPU time 2.18 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 216288 kb
Host smart-14602d9b-ab14-4217-94b0-76167527ddde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475299293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2475299293
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3033200185
Short name T172
Test name
Test status
Simulation time 4851387412 ps
CPU time 14.35 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:15 PM PDT 24
Peak memory 216088 kb
Host smart-32d96ccb-2228-447c-9699-ed52c8b26125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033200185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3033200185
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3807425867
Short name T1142
Test name
Test status
Simulation time 147526927 ps
CPU time 4.18 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 218884 kb
Host smart-570a7a9f-c2a0-4caa-ad56-841141a5fe59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807425867 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3807425867
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1283045338
Short name T1080
Test name
Test status
Simulation time 42546242 ps
CPU time 2.62 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 216064 kb
Host smart-886e668c-681d-4468-9c78-cbfcda2088b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283045338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1283045338
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1521988386
Short name T1113
Test name
Test status
Simulation time 24829604 ps
CPU time 0.72 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 204840 kb
Host smart-b308c441-b55c-4c2d-a59c-7862b2abf8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521988386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1521988386
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2436094597
Short name T1047
Test name
Test status
Simulation time 114806193 ps
CPU time 3.61 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:04 PM PDT 24
Peak memory 216032 kb
Host smart-dcba1e05-8b1f-467a-ad3c-8485fba09a60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436094597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2436094597
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3789631617
Short name T99
Test name
Test status
Simulation time 61325771 ps
CPU time 2.01 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 216368 kb
Host smart-5ef7ea98-c2c3-4bff-b76b-24844a5c27dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789631617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3789631617
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.997213846
Short name T171
Test name
Test status
Simulation time 570541289 ps
CPU time 18.93 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:19 PM PDT 24
Peak memory 216060 kb
Host smart-0624e1c2-d2c0-499c-950d-c865c2f47975
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997213846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.997213846
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1484901125
Short name T1141
Test name
Test status
Simulation time 100199815 ps
CPU time 2.69 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 217628 kb
Host smart-498ad6af-3fd0-4b14-8441-0cc8f660293b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484901125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1484901125
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2411501820
Short name T1082
Test name
Test status
Simulation time 69814546 ps
CPU time 1.94 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 215968 kb
Host smart-54aedf21-43b9-43b9-8a96-23eb43c70762
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411501820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2411501820
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.113789002
Short name T1090
Test name
Test status
Simulation time 22419010 ps
CPU time 0.71 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 204512 kb
Host smart-2679ee8b-85ad-4c37-bb86-08653a950453
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113789002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.113789002
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.565977897
Short name T1056
Test name
Test status
Simulation time 47881417 ps
CPU time 1.81 seconds
Started Jul 25 06:25:57 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 216100 kb
Host smart-fa6fe6dd-02c8-4886-94ce-b5bb38f6be2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565977897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.565977897
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3781102578
Short name T90
Test name
Test status
Simulation time 62769689 ps
CPU time 1.87 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 216408 kb
Host smart-7c7ebe62-a45e-4b08-92c4-11ffa0f3fdea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781102578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3781102578
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3724530493
Short name T168
Test name
Test status
Simulation time 430189339 ps
CPU time 6.43 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216060 kb
Host smart-c4a35282-1f89-4782-8fdb-157d4701b693
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724530493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3724530493
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3816288913
Short name T1140
Test name
Test status
Simulation time 73071058 ps
CPU time 1.9 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 215704 kb
Host smart-f30a5c12-b61d-47fd-bde3-e01c4df10bb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816288913 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3816288913
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2072337931
Short name T119
Test name
Test status
Simulation time 886514431 ps
CPU time 3.16 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 215960 kb
Host smart-9cb00dd2-ea1a-4b95-a2e8-e9248732bf95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072337931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2072337931
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.628403468
Short name T1149
Test name
Test status
Simulation time 91443101 ps
CPU time 0.72 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 204508 kb
Host smart-32aaa341-6c93-4d12-96ae-dfbfe55c24ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628403468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.628403468
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2934166908
Short name T1049
Test name
Test status
Simulation time 61398266 ps
CPU time 3.82 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:04 PM PDT 24
Peak memory 216040 kb
Host smart-065237ec-9baa-462c-92cc-142fcfe4d86f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934166908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2934166908
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.540539226
Short name T1122
Test name
Test status
Simulation time 87029836 ps
CPU time 2.27 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216308 kb
Host smart-3be66537-a886-48cf-94db-670039414887
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540539226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.540539226
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3734983528
Short name T145
Test name
Test status
Simulation time 717085306 ps
CPU time 8.47 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:07 PM PDT 24
Peak memory 216072 kb
Host smart-9cffbc5f-a862-4c32-acc5-498d44a4bd97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734983528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3734983528
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3461854786
Short name T1059
Test name
Test status
Simulation time 135436574 ps
CPU time 2.7 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 217064 kb
Host smart-cd46c936-3456-4c84-b3f4-892efb0a76be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461854786 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3461854786
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.675470070
Short name T113
Test name
Test status
Simulation time 99935654 ps
CPU time 2.62 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216032 kb
Host smart-6092092b-fc00-4e68-a099-3dddf16d38dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675470070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.675470070
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1614604742
Short name T1114
Test name
Test status
Simulation time 14698358 ps
CPU time 0.76 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 204844 kb
Host smart-ce7251d2-ee14-4d7b-a646-7634310d71ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614604742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1614604742
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1797840598
Short name T1147
Test name
Test status
Simulation time 856231417 ps
CPU time 4.62 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:04 PM PDT 24
Peak memory 216024 kb
Host smart-b2715285-a339-40d1-bd97-0473c9ed0e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797840598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1797840598
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.402978975
Short name T165
Test name
Test status
Simulation time 221057930 ps
CPU time 1.92 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216220 kb
Host smart-f4044326-1401-4e51-9ec8-c58d9ce17f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402978975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.402978975
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2711241106
Short name T1106
Test name
Test status
Simulation time 122071028 ps
CPU time 3.57 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 218356 kb
Host smart-a7223838-9f83-4ae4-a8e4-32a9f5572eef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711241106 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2711241106
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3442633208
Short name T1032
Test name
Test status
Simulation time 21946519 ps
CPU time 1.36 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 207816 kb
Host smart-2b094786-df50-4993-ad07-3a6bb3f2ede8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442633208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3442633208
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.870611286
Short name T1077
Test name
Test status
Simulation time 68378358 ps
CPU time 0.77 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 204496 kb
Host smart-9031a738-106c-4e7e-b527-b504cad8ff35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870611286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.870611286
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1313987860
Short name T1110
Test name
Test status
Simulation time 58113895 ps
CPU time 3.66 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 215980 kb
Host smart-bc7f24f1-ad5a-4661-acfe-24798ab9bde3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313987860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1313987860
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3702121819
Short name T1060
Test name
Test status
Simulation time 240068180 ps
CPU time 3.13 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 217372 kb
Host smart-202efe44-af3e-461a-a4e8-46f4abcf61a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702121819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3702121819
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3910564013
Short name T1134
Test name
Test status
Simulation time 1445549611 ps
CPU time 9.47 seconds
Started Jul 25 06:26:02 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 216652 kb
Host smart-b5ab56dd-3da2-49d9-8d8b-ef41dd084b86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910564013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3910564013
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2007494014
Short name T1046
Test name
Test status
Simulation time 99862310 ps
CPU time 3.88 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:05 PM PDT 24
Peak memory 218844 kb
Host smart-cfd07241-1f60-41d5-b779-3e1f72b51db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007494014 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2007494014
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3648822015
Short name T1136
Test name
Test status
Simulation time 18537057 ps
CPU time 1.3 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 207816 kb
Host smart-903dd35f-c362-41b5-bdc8-882be5716bb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648822015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3648822015
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2252262028
Short name T1051
Test name
Test status
Simulation time 11870936 ps
CPU time 0.76 seconds
Started Jul 25 06:26:02 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 204500 kb
Host smart-353d9057-de67-41f4-ac1a-7058e1053f3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252262028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2252262028
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.262169387
Short name T1135
Test name
Test status
Simulation time 881870280 ps
CPU time 4.74 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:04 PM PDT 24
Peak memory 216104 kb
Host smart-9f5be391-88b8-40b3-bd70-cfd2a4dbfb37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262169387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.262169387
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2375535208
Short name T97
Test name
Test status
Simulation time 65888560 ps
CPU time 4.38 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216404 kb
Host smart-19bb4b9b-71cd-4d81-8bf2-2ffab80b0ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375535208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2375535208
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3395971331
Short name T93
Test name
Test status
Simulation time 110445928 ps
CPU time 7.07 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216344 kb
Host smart-3bba9145-60fc-4dc0-9742-170bd6e897e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395971331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3395971331
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2462967223
Short name T143
Test name
Test status
Simulation time 403861196 ps
CPU time 8.55 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:52 PM PDT 24
Peak memory 207800 kb
Host smart-7402475a-e5c8-4735-bceb-7180f1b738cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462967223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2462967223
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.847176316
Short name T114
Test name
Test status
Simulation time 2870316288 ps
CPU time 26.43 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:26:10 PM PDT 24
Peak memory 216136 kb
Host smart-69cc6729-af3d-4043-8d43-31c534db5822
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847176316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.847176316
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3806136745
Short name T74
Test name
Test status
Simulation time 29257500 ps
CPU time 1.19 seconds
Started Jul 25 06:25:36 PM PDT 24
Finished Jul 25 06:25:38 PM PDT 24
Peak memory 207856 kb
Host smart-539eb72d-8fd2-4160-8e13-161fb707337b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806136745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3806136745
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4177576067
Short name T1143
Test name
Test status
Simulation time 147905423 ps
CPU time 2.59 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:46 PM PDT 24
Peak memory 218668 kb
Host smart-45f4520d-e018-4b6d-bee4-9d6a9cfc905e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177576067 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4177576067
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1579338734
Short name T1068
Test name
Test status
Simulation time 665260296 ps
CPU time 2.85 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 216064 kb
Host smart-1e25a588-b6f6-4ec0-8173-9c4558ba69a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579338734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
579338734
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1321506612
Short name T1084
Test name
Test status
Simulation time 45629186 ps
CPU time 0.73 seconds
Started Jul 25 06:25:33 PM PDT 24
Finished Jul 25 06:25:34 PM PDT 24
Peak memory 204512 kb
Host smart-b2eea59a-2a0d-4ea5-a5c4-64577367c044
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321506612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
321506612
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.332320888
Short name T108
Test name
Test status
Simulation time 62386727 ps
CPU time 1.24 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:42 PM PDT 24
Peak memory 216108 kb
Host smart-36f52805-8955-4a08-bf7c-ee05565974bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332320888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.332320888
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2922360412
Short name T1091
Test name
Test status
Simulation time 11954642 ps
CPU time 0.67 seconds
Started Jul 25 06:25:35 PM PDT 24
Finished Jul 25 06:25:36 PM PDT 24
Peak memory 204416 kb
Host smart-4249e28d-1b25-4157-a2da-01e4689581c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922360412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2922360412
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1197573601
Short name T1079
Test name
Test status
Simulation time 532082812 ps
CPU time 2.99 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:46 PM PDT 24
Peak memory 216028 kb
Host smart-f3ea7fe4-909a-4905-9bd9-b46ec486fbdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197573601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1197573601
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.195449777
Short name T102
Test name
Test status
Simulation time 339645502 ps
CPU time 4.26 seconds
Started Jul 25 06:25:36 PM PDT 24
Finished Jul 25 06:25:41 PM PDT 24
Peak memory 216260 kb
Host smart-ed2f8262-4769-46ec-8a17-0077977105a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195449777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.195449777
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1902929069
Short name T144
Test name
Test status
Simulation time 907837041 ps
CPU time 16.08 seconds
Started Jul 25 06:25:40 PM PDT 24
Finished Jul 25 06:25:57 PM PDT 24
Peak memory 216052 kb
Host smart-1f9520f8-fba4-4137-bdfc-c70b3e241b9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902929069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1902929069
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.1181374855
Short name T1058
Test name
Test status
Simulation time 20367304 ps
CPU time 0.79 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:25:59 PM PDT 24
Peak memory 204508 kb
Host smart-974414a4-5262-4f2d-b2f4-4a3fe8a333c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181374855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
1181374855
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2245417135
Short name T1100
Test name
Test status
Simulation time 23452787 ps
CPU time 0.74 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 204620 kb
Host smart-d52619a4-7331-4e88-9ddd-be8265fd977a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245417135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2245417135
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1480222726
Short name T1085
Test name
Test status
Simulation time 83414778 ps
CPU time 0.7 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 204480 kb
Host smart-52e8ecfb-3074-4413-a805-802f6a9e52ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480222726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1480222726
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2579288589
Short name T1123
Test name
Test status
Simulation time 42714544 ps
CPU time 0.78 seconds
Started Jul 25 06:26:01 PM PDT 24
Finished Jul 25 06:26:02 PM PDT 24
Peak memory 204220 kb
Host smart-989af3b8-9e54-4b4e-86b2-ef55f441ff38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579288589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2579288589
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3570370080
Short name T1115
Test name
Test status
Simulation time 52137673 ps
CPU time 0.76 seconds
Started Jul 25 06:26:02 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 204516 kb
Host smart-07a79e5d-1d76-4391-8180-beb50a5c7947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570370080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3570370080
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2508342715
Short name T1126
Test name
Test status
Simulation time 54230101 ps
CPU time 0.74 seconds
Started Jul 25 06:26:00 PM PDT 24
Finished Jul 25 06:26:01 PM PDT 24
Peak memory 204504 kb
Host smart-12a9d9d4-c171-4693-bb66-ec7a5c5308bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508342715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2508342715
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.784003126
Short name T1030
Test name
Test status
Simulation time 50251911 ps
CPU time 0.69 seconds
Started Jul 25 06:25:59 PM PDT 24
Finished Jul 25 06:26:00 PM PDT 24
Peak memory 204832 kb
Host smart-2b0556d2-527e-4dc6-94b5-62b33d12d7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784003126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.784003126
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.418176716
Short name T1053
Test name
Test status
Simulation time 12555025 ps
CPU time 0.7 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204520 kb
Host smart-468c0796-a441-49a0-be33-daa0ca95727f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418176716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.418176716
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.285363625
Short name T1055
Test name
Test status
Simulation time 20297506 ps
CPU time 0.73 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204472 kb
Host smart-b9244750-8048-4ab9-b907-e22f4f751d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285363625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.285363625
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3809895851
Short name T1044
Test name
Test status
Simulation time 19030841 ps
CPU time 0.75 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204500 kb
Host smart-438adb95-12b1-4e18-8654-3b24b8c14765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809895851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3809895851
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1474853558
Short name T1065
Test name
Test status
Simulation time 1226473025 ps
CPU time 16.59 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:58 PM PDT 24
Peak memory 207868 kb
Host smart-833da7a0-4927-4171-85fc-0d7ed62919b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474853558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1474853558
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.956651101
Short name T1028
Test name
Test status
Simulation time 634973051 ps
CPU time 12.93 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:59 PM PDT 24
Peak memory 207620 kb
Host smart-8766c190-f4ea-415c-8222-69b3462753ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956651101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.956651101
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2002042745
Short name T75
Test name
Test status
Simulation time 24331486 ps
CPU time 1 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 207636 kb
Host smart-2c45d47f-a80a-41c7-b148-25052b76a3d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002042745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2002042745
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2021178015
Short name T106
Test name
Test status
Simulation time 27425125 ps
CPU time 1.7 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 216132 kb
Host smart-d6cdc92a-306a-447e-93dc-9fe060540c01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021178015 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2021178015
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1187213628
Short name T111
Test name
Test status
Simulation time 234186374 ps
CPU time 2.54 seconds
Started Jul 25 06:25:45 PM PDT 24
Finished Jul 25 06:25:48 PM PDT 24
Peak memory 215992 kb
Host smart-00d4867d-58ea-4994-a374-28f20815ae55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187213628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
187213628
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1248448652
Short name T1078
Test name
Test status
Simulation time 24887489 ps
CPU time 0.71 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 204780 kb
Host smart-0419f13f-3e1a-4b22-aefb-16bfe6528d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248448652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
248448652
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3860674795
Short name T1137
Test name
Test status
Simulation time 39408718 ps
CPU time 1.32 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 215976 kb
Host smart-aa38f331-9f86-473e-8971-8379b4cf87d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860674795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3860674795
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.955595410
Short name T1029
Test name
Test status
Simulation time 10464842 ps
CPU time 0.66 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 204732 kb
Host smart-a44003e5-cc4c-4306-ae81-82aa0d5dcb38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955595410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.955595410
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3073179924
Short name T1039
Test name
Test status
Simulation time 234485423 ps
CPU time 1.73 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:45 PM PDT 24
Peak memory 207776 kb
Host smart-6c571071-c276-497c-b5b3-0d3c427a5890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073179924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3073179924
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.741516567
Short name T92
Test name
Test status
Simulation time 47961760 ps
CPU time 1.71 seconds
Started Jul 25 06:25:35 PM PDT 24
Finished Jul 25 06:25:37 PM PDT 24
Peak memory 217308 kb
Host smart-9e2558ec-2faa-4d58-ab8e-3fbb8d24d885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741516567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.741516567
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.253813057
Short name T166
Test name
Test status
Simulation time 2096294831 ps
CPU time 16.42 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:57 PM PDT 24
Peak memory 216332 kb
Host smart-fa480b29-9cc5-4085-b98f-ad43888ff782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253813057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.253813057
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3519723546
Short name T1092
Test name
Test status
Simulation time 18187753 ps
CPU time 0.75 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204552 kb
Host smart-aebdd83b-d2f1-4b33-bc63-4b515fea5a99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519723546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3519723546
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1115457903
Short name T1096
Test name
Test status
Simulation time 32887195 ps
CPU time 0.72 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204548 kb
Host smart-9e8a34e6-c749-4014-899d-92dde728c4fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115457903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1115457903
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2519881510
Short name T1121
Test name
Test status
Simulation time 13286877 ps
CPU time 0.76 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204772 kb
Host smart-cc1a3020-5d31-46f2-8f6b-b75b6a101d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519881510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2519881510
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.350610483
Short name T1098
Test name
Test status
Simulation time 16501570 ps
CPU time 0.78 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204512 kb
Host smart-2cca6be3-4cd2-4922-bf16-0a984a965999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350610483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.350610483
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2216819625
Short name T1061
Test name
Test status
Simulation time 24163319 ps
CPU time 0.67 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204796 kb
Host smart-5bde9ddc-8fc2-4ebf-a09b-0a9f60b6fba8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216819625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2216819625
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2941725978
Short name T1057
Test name
Test status
Simulation time 13653155 ps
CPU time 0.72 seconds
Started Jul 25 06:26:15 PM PDT 24
Finished Jul 25 06:26:16 PM PDT 24
Peak memory 204520 kb
Host smart-2344b278-6cbb-4e29-8f05-48cbb93742fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941725978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2941725978
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.430309665
Short name T1026
Test name
Test status
Simulation time 14673456 ps
CPU time 0.69 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204512 kb
Host smart-b7cee09e-9fb5-4bf1-8925-b10b0b699a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430309665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.430309665
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1407048547
Short name T1089
Test name
Test status
Simulation time 55941886 ps
CPU time 0.72 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204500 kb
Host smart-fd2d52fa-6a39-4333-b62c-2c7f590de281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407048547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1407048547
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1557655142
Short name T1066
Test name
Test status
Simulation time 20167000 ps
CPU time 0.75 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204448 kb
Host smart-9e5af4aa-6ce3-47fb-a3b3-29bfc7b0dc02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557655142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1557655142
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.543509730
Short name T1072
Test name
Test status
Simulation time 34208504 ps
CPU time 0.78 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204508 kb
Host smart-8913b4ce-d992-4337-85d1-09e14d86c5cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543509730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.543509730
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.990529876
Short name T118
Test name
Test status
Simulation time 709763259 ps
CPU time 8.51 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:52 PM PDT 24
Peak memory 216088 kb
Host smart-15114b34-1b80-476b-ad19-28c2ec7423c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990529876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.990529876
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3435375694
Short name T109
Test name
Test status
Simulation time 19354786965 ps
CPU time 41.33 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:26:24 PM PDT 24
Peak memory 207868 kb
Host smart-de280f38-3a5e-4172-bb52-a283bd4c9084
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435375694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3435375694
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4039919912
Short name T1064
Test name
Test status
Simulation time 155045566 ps
CPU time 3.97 seconds
Started Jul 25 06:25:51 PM PDT 24
Finished Jul 25 06:25:55 PM PDT 24
Peak memory 218292 kb
Host smart-ce64eb25-d119-4619-a5b0-aaf38a467bd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039919912 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4039919912
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1735292585
Short name T1144
Test name
Test status
Simulation time 20999818 ps
CPU time 1.26 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 207960 kb
Host smart-e886ef41-ddfc-4567-84e3-8dbfa02cdb05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735292585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
735292585
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.520557445
Short name T1031
Test name
Test status
Simulation time 52895872 ps
CPU time 0.74 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 204680 kb
Host smart-af6b7852-00b9-44a4-add2-7ef8907050d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520557445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.520557445
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2210419216
Short name T1075
Test name
Test status
Simulation time 124976764 ps
CPU time 1.36 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 216080 kb
Host smart-1a753c2d-c35d-467a-bcce-44dabc0eeae3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210419216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2210419216
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2172092986
Short name T1050
Test name
Test status
Simulation time 22225758 ps
CPU time 0.65 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:43 PM PDT 24
Peak memory 204364 kb
Host smart-617866f4-5ef3-462c-a9a1-700f6362bf3a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172092986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2172092986
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2275867210
Short name T1067
Test name
Test status
Simulation time 154942999 ps
CPU time 2.88 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 216056 kb
Host smart-e1674a2b-0f20-4d24-b262-427aeebc8873
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275867210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2275867210
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3410210017
Short name T1042
Test name
Test status
Simulation time 29579641 ps
CPU time 0.7 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204520 kb
Host smart-03e3c6af-1abf-4db7-a97d-2ed699d33fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410210017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3410210017
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3628982486
Short name T1069
Test name
Test status
Simulation time 13993376 ps
CPU time 0.71 seconds
Started Jul 25 06:26:12 PM PDT 24
Finished Jul 25 06:26:13 PM PDT 24
Peak memory 204840 kb
Host smart-58333c63-f918-4bcc-8248-72b9332015a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628982486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3628982486
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4099304669
Short name T1127
Test name
Test status
Simulation time 13735700 ps
CPU time 0.74 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204840 kb
Host smart-48e9e1bd-3932-4fcc-85ce-4d52f6c0b8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099304669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4099304669
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2058225478
Short name T1027
Test name
Test status
Simulation time 28123764 ps
CPU time 0.77 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204828 kb
Host smart-f89c641e-5cde-458f-b33e-75adb0378c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058225478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2058225478
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1475144043
Short name T1043
Test name
Test status
Simulation time 26654976 ps
CPU time 0.71 seconds
Started Jul 25 06:26:14 PM PDT 24
Finished Jul 25 06:26:15 PM PDT 24
Peak memory 204540 kb
Host smart-23071f60-72b1-4662-bdd9-a556f51b3336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475144043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1475144043
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2347799100
Short name T1062
Test name
Test status
Simulation time 15789926 ps
CPU time 0.71 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204484 kb
Host smart-f126526d-5bfa-4a83-bcc1-32c973fec6cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347799100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2347799100
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.996257369
Short name T1107
Test name
Test status
Simulation time 18289459 ps
CPU time 0.74 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204516 kb
Host smart-1023ba4a-4795-4642-8989-fbdb41ac244e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996257369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.996257369
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3592376009
Short name T1034
Test name
Test status
Simulation time 40578298 ps
CPU time 0.71 seconds
Started Jul 25 06:26:13 PM PDT 24
Finished Jul 25 06:26:14 PM PDT 24
Peak memory 204520 kb
Host smart-6662f72c-4179-4bbd-8518-ffb63c57f0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592376009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3592376009
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2651260174
Short name T1083
Test name
Test status
Simulation time 36179860 ps
CPU time 0.77 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:12 PM PDT 24
Peak memory 204552 kb
Host smart-04c242f4-1fcd-4440-a543-63cb5f36853d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651260174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2651260174
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2014660
Short name T1131
Test name
Test status
Simulation time 94324163 ps
CPU time 0.72 seconds
Started Jul 25 06:26:11 PM PDT 24
Finished Jul 25 06:26:11 PM PDT 24
Peak memory 204852 kb
Host smart-72f78985-84cb-4087-9959-aa56e50ed82d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2014660
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1097252515
Short name T107
Test name
Test status
Simulation time 149454707 ps
CPU time 2.36 seconds
Started Jul 25 06:25:45 PM PDT 24
Finished Jul 25 06:25:48 PM PDT 24
Peak memory 217776 kb
Host smart-768363b4-3ed2-4552-92ba-29eec83e4e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097252515 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1097252515
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.136059579
Short name T110
Test name
Test status
Simulation time 52953033 ps
CPU time 1.88 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:46 PM PDT 24
Peak memory 207796 kb
Host smart-24a9aa09-5495-49ca-b8e6-21da104ef3a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136059579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.136059579
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1731645534
Short name T1045
Test name
Test status
Simulation time 16743094 ps
CPU time 0.81 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:44 PM PDT 24
Peak memory 204448 kb
Host smart-1839e838-2084-4faa-8a1e-553f8ca983e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731645534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
731645534
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2473159269
Short name T1070
Test name
Test status
Simulation time 220631075 ps
CPU time 3.91 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 216056 kb
Host smart-2673025c-e509-4bdc-83ef-388ab2ba7365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473159269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2473159269
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1747785742
Short name T91
Test name
Test status
Simulation time 306077139 ps
CPU time 2.4 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:46 PM PDT 24
Peak memory 216196 kb
Host smart-55e4ede5-05af-4358-8888-308f7739c58a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747785742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
747785742
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.174260856
Short name T1124
Test name
Test status
Simulation time 646228857 ps
CPU time 8.57 seconds
Started Jul 25 06:25:41 PM PDT 24
Finished Jul 25 06:25:50 PM PDT 24
Peak memory 216116 kb
Host smart-73984c50-4f59-4c5c-8141-a7e507186adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174260856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.174260856
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.144773454
Short name T1054
Test name
Test status
Simulation time 125672714 ps
CPU time 3.71 seconds
Started Jul 25 06:25:47 PM PDT 24
Finished Jul 25 06:25:51 PM PDT 24
Peak memory 219228 kb
Host smart-78537584-2d6a-46a8-969b-a0c15b4a7572
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144773454 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.144773454
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3672247955
Short name T116
Test name
Test status
Simulation time 27046612 ps
CPU time 1.78 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:48 PM PDT 24
Peak memory 216060 kb
Host smart-9baf8e09-8d07-4f18-ae0f-8b1941af8db9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672247955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
672247955
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3938891185
Short name T1097
Test name
Test status
Simulation time 19734168 ps
CPU time 0.72 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 204480 kb
Host smart-07b81bcd-29c5-42f6-bd03-45689ddfa59b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938891185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
938891185
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2049989565
Short name T1102
Test name
Test status
Simulation time 80083789 ps
CPU time 1.88 seconds
Started Jul 25 06:25:45 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 216060 kb
Host smart-812d4193-d7cf-4e2d-af48-a2cf9964c4b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049989565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2049989565
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.170372397
Short name T1101
Test name
Test status
Simulation time 377543506 ps
CPU time 3.13 seconds
Started Jul 25 06:25:44 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 216256 kb
Host smart-42bd74a1-bd25-42fa-88d0-54b3ac2388b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170372397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.170372397
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2789734455
Short name T169
Test name
Test status
Simulation time 3820468109 ps
CPU time 20.78 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:26:04 PM PDT 24
Peak memory 216664 kb
Host smart-c9305ec2-a597-4738-8b4f-6d6f1114a5d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789734455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2789734455
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2748909350
Short name T1052
Test name
Test status
Simulation time 53766686 ps
CPU time 3.65 seconds
Started Jul 25 06:25:43 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 217928 kb
Host smart-bc549ed9-1408-4f09-bad3-023399d56f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748909350 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2748909350
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1032012218
Short name T1037
Test name
Test status
Simulation time 373104613 ps
CPU time 2.35 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:49 PM PDT 24
Peak memory 216056 kb
Host smart-ec45f08a-728f-419c-bbde-04bb33eca7d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032012218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
032012218
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4029611905
Short name T1117
Test name
Test status
Simulation time 29734869 ps
CPU time 0.71 seconds
Started Jul 25 06:25:45 PM PDT 24
Finished Jul 25 06:25:46 PM PDT 24
Peak memory 204492 kb
Host smart-dae18bad-9e5e-4ee1-83b2-26f55172130f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029611905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
029611905
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3907300712
Short name T1132
Test name
Test status
Simulation time 1120044329 ps
CPU time 4.37 seconds
Started Jul 25 06:25:42 PM PDT 24
Finished Jul 25 06:25:47 PM PDT 24
Peak memory 215540 kb
Host smart-c7a8d1c3-a21b-49dd-98b2-266ea37db6e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907300712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3907300712
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1575348072
Short name T1095
Test name
Test status
Simulation time 153884318 ps
CPU time 3.99 seconds
Started Jul 25 06:25:48 PM PDT 24
Finished Jul 25 06:25:52 PM PDT 24
Peak memory 216284 kb
Host smart-924b3a71-a02a-4538-bd7c-5c2e7025a7b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575348072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
575348072
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2392397057
Short name T103
Test name
Test status
Simulation time 295505972 ps
CPU time 5 seconds
Started Jul 25 06:25:57 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 218084 kb
Host smart-b78400b9-c362-4e8c-867a-e2372b809f9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392397057 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2392397057
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.809793594
Short name T1145
Test name
Test status
Simulation time 47320258 ps
CPU time 1.35 seconds
Started Jul 25 06:25:49 PM PDT 24
Finished Jul 25 06:25:51 PM PDT 24
Peak memory 207860 kb
Host smart-a2dfa3ea-09b2-4232-81de-bbce11a5eac4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809793594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.809793594
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2341658193
Short name T1086
Test name
Test status
Simulation time 52936755 ps
CPU time 0.72 seconds
Started Jul 25 06:26:04 PM PDT 24
Finished Jul 25 06:26:05 PM PDT 24
Peak memory 204852 kb
Host smart-d39266a9-00f5-4c64-b177-49f7099480a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341658193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
341658193
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.749258081
Short name T1073
Test name
Test status
Simulation time 174182635 ps
CPU time 2.79 seconds
Started Jul 25 06:26:03 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216024 kb
Host smart-7342e571-578e-4d0e-afac-1e2580120ffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749258081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.749258081
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.548600963
Short name T89
Test name
Test status
Simulation time 1347694727 ps
CPU time 7.8 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:06 PM PDT 24
Peak memory 216028 kb
Host smart-94f144a7-079b-49e2-86de-dcf2285a16ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548600963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.548600963
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.452623892
Short name T101
Test name
Test status
Simulation time 509717241 ps
CPU time 3.92 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 218316 kb
Host smart-390127a1-8da5-40c1-b6e1-e4b671b9eee4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452623892 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.452623892
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.622692863
Short name T115
Test name
Test status
Simulation time 96426437 ps
CPU time 2.33 seconds
Started Jul 25 06:25:47 PM PDT 24
Finished Jul 25 06:25:49 PM PDT 24
Peak memory 216032 kb
Host smart-de21bcd0-3c7d-4ffe-a05c-c95a467656d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622692863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.622692863
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1401104654
Short name T1041
Test name
Test status
Simulation time 65954176 ps
CPU time 0.76 seconds
Started Jul 25 06:25:49 PM PDT 24
Finished Jul 25 06:25:50 PM PDT 24
Peak memory 204832 kb
Host smart-92afd5db-3814-4f8b-905e-332ad585dd87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401104654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
401104654
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3869165166
Short name T1112
Test name
Test status
Simulation time 219877443 ps
CPU time 4.9 seconds
Started Jul 25 06:25:58 PM PDT 24
Finished Jul 25 06:26:03 PM PDT 24
Peak memory 216096 kb
Host smart-e9c7475f-0761-4e28-9728-be91f384f394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869165166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3869165166
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.149575197
Short name T105
Test name
Test status
Simulation time 798406245 ps
CPU time 6.18 seconds
Started Jul 25 06:25:44 PM PDT 24
Finished Jul 25 06:25:51 PM PDT 24
Peak memory 216328 kb
Host smart-61038e03-db67-466c-aa5e-42574d273c94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149575197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.149575197
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.349392204
Short name T1125
Test name
Test status
Simulation time 616769315 ps
CPU time 7 seconds
Started Jul 25 06:25:46 PM PDT 24
Finished Jul 25 06:25:53 PM PDT 24
Peak memory 215984 kb
Host smart-d2489f2d-bf61-4ad8-a26b-c5d651e0c31d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349392204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.349392204
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1739757860
Short name T593
Test name
Test status
Simulation time 45575871 ps
CPU time 0.72 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:47:56 PM PDT 24
Peak memory 205484 kb
Host smart-60cd2cdb-2abd-4855-b4b4-7349683bb4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739757860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
739757860
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3540237753
Short name T397
Test name
Test status
Simulation time 27778555 ps
CPU time 0.76 seconds
Started Jul 25 05:47:45 PM PDT 24
Finished Jul 25 05:47:46 PM PDT 24
Peak memory 207248 kb
Host smart-c04ea291-04f2-49cf-a1b9-8a3a38af03a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540237753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3540237753
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2981219625
Short name T576
Test name
Test status
Simulation time 13414444795 ps
CPU time 56.51 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:48:51 PM PDT 24
Peak memory 250028 kb
Host smart-3c848d0b-e6c8-4730-8fad-c119005addb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981219625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2981219625
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.4074679855
Short name T159
Test name
Test status
Simulation time 75872755956 ps
CPU time 185.58 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:50:58 PM PDT 24
Peak memory 250172 kb
Host smart-311a4bc2-7ee9-4a8e-97bc-80a1370c4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074679855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.4074679855
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3617716998
Short name T986
Test name
Test status
Simulation time 2633791623 ps
CPU time 35.97 seconds
Started Jul 25 05:47:47 PM PDT 24
Finished Jul 25 05:48:23 PM PDT 24
Peak memory 241164 kb
Host smart-ddcdac20-a535-4f8f-9c76-94fa001117d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617716998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3617716998
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1847651130
Short name T456
Test name
Test status
Simulation time 3802698919 ps
CPU time 79.13 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 252152 kb
Host smart-9804d70e-46d9-4b05-9410-d14d6a09c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847651130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1847651130
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1741158698
Short name T487
Test name
Test status
Simulation time 5156491612 ps
CPU time 11.81 seconds
Started Jul 25 05:47:43 PM PDT 24
Finished Jul 25 05:47:55 PM PDT 24
Peak memory 225556 kb
Host smart-ce04dac6-8140-4ef2-a650-778428d5b7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741158698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1741158698
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2225125399
Short name T198
Test name
Test status
Simulation time 18539354885 ps
CPU time 36.53 seconds
Started Jul 25 05:47:44 PM PDT 24
Finished Jul 25 05:48:21 PM PDT 24
Peak memory 225500 kb
Host smart-6d7ade8a-73e3-48c2-8049-99edec8714e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225125399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2225125399
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2082071945
Short name T572
Test name
Test status
Simulation time 1272283035 ps
CPU time 6.17 seconds
Started Jul 25 05:47:44 PM PDT 24
Finished Jul 25 05:47:51 PM PDT 24
Peak memory 225436 kb
Host smart-9c98c763-3275-4f2e-924f-498f58f8fea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082071945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2082071945
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3296151454
Short name T472
Test name
Test status
Simulation time 1664667405 ps
CPU time 6.26 seconds
Started Jul 25 05:47:57 PM PDT 24
Finished Jul 25 05:48:04 PM PDT 24
Peak memory 221496 kb
Host smart-b2d5be74-4692-4654-9112-f1dfa1445e1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3296151454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3296151454
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.503969167
Short name T274
Test name
Test status
Simulation time 6964300949 ps
CPU time 11.11 seconds
Started Jul 25 05:47:43 PM PDT 24
Finished Jul 25 05:47:54 PM PDT 24
Peak memory 217280 kb
Host smart-2e87d03a-48c0-4a92-b7a4-f5fe7163ca40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503969167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.503969167
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1344622223
Short name T809
Test name
Test status
Simulation time 2147465308 ps
CPU time 3.97 seconds
Started Jul 25 05:47:43 PM PDT 24
Finished Jul 25 05:47:47 PM PDT 24
Peak memory 217092 kb
Host smart-0f9f425d-5347-438d-840f-902ba4fe57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344622223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1344622223
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.945504429
Short name T444
Test name
Test status
Simulation time 43580613 ps
CPU time 1.32 seconds
Started Jul 25 05:47:50 PM PDT 24
Finished Jul 25 05:47:52 PM PDT 24
Peak memory 217172 kb
Host smart-25b59ea1-95df-4f34-a805-6cafa5d2787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945504429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.945504429
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.626722793
Short name T668
Test name
Test status
Simulation time 114602609 ps
CPU time 0.87 seconds
Started Jul 25 05:47:47 PM PDT 24
Finished Jul 25 05:47:48 PM PDT 24
Peak memory 206744 kb
Host smart-84302b1f-c38a-4da4-9ebf-68020d894f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626722793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.626722793
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.544788783
Short name T937
Test name
Test status
Simulation time 935699548 ps
CPU time 4.9 seconds
Started Jul 25 05:47:42 PM PDT 24
Finished Jul 25 05:47:47 PM PDT 24
Peak memory 225428 kb
Host smart-66a77c3c-e91b-4396-a0ec-8bde9b211904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544788783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.544788783
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3236781671
Short name T994
Test name
Test status
Simulation time 12098091 ps
CPU time 0.7 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:47:54 PM PDT 24
Peak memory 205476 kb
Host smart-8f481542-82b7-4cf3-bf99-f1c0c2046ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236781671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
236781671
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1038022132
Short name T558
Test name
Test status
Simulation time 388717264 ps
CPU time 5.25 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:09 PM PDT 24
Peak memory 233608 kb
Host smart-06ccff4d-5586-4db8-a2b6-887f85616bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038022132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1038022132
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.907489956
Short name T616
Test name
Test status
Simulation time 23285763 ps
CPU time 0.79 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 05:47:53 PM PDT 24
Peak memory 207248 kb
Host smart-fedef3e7-dfb0-4977-9e78-07c796bcbae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907489956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.907489956
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.4004340224
Short name T1020
Test name
Test status
Simulation time 25799224718 ps
CPU time 191.26 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:51:06 PM PDT 24
Peak memory 253784 kb
Host smart-e7638fb9-053e-4da7-a2f6-b371fe178583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004340224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.4004340224
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.618155600
Short name T132
Test name
Test status
Simulation time 17680176327 ps
CPU time 128.47 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 05:50:01 PM PDT 24
Peak memory 268236 kb
Host smart-c6b83a70-ae1e-430f-9e21-0aa96dad30f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618155600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.618155600
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1190397792
Short name T362
Test name
Test status
Simulation time 130091689 ps
CPU time 3.06 seconds
Started Jul 25 05:48:01 PM PDT 24
Finished Jul 25 05:48:04 PM PDT 24
Peak memory 225460 kb
Host smart-7dd2976d-c38f-40d1-afe4-123ed40c536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190397792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1190397792
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2180020694
Short name T244
Test name
Test status
Simulation time 95256359933 ps
CPU time 381.81 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:54:15 PM PDT 24
Peak memory 263616 kb
Host smart-9bc285a2-9e18-4524-9d55-83ea2e96aad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180020694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2180020694
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.4046244670
Short name T212
Test name
Test status
Simulation time 2680438936 ps
CPU time 19.61 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:48:13 PM PDT 24
Peak memory 225508 kb
Host smart-867e256d-3488-4879-810b-a451b348b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046244670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.4046244670
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3681972098
Short name T940
Test name
Test status
Simulation time 349315763 ps
CPU time 10.88 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 05:48:03 PM PDT 24
Peak memory 233648 kb
Host smart-ecaaafc4-b290-414d-952e-2e9e9a75a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681972098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3681972098
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.809733039
Short name T804
Test name
Test status
Simulation time 65092711 ps
CPU time 1.03 seconds
Started Jul 25 05:47:52 PM PDT 24
Finished Jul 25 05:47:54 PM PDT 24
Peak memory 217320 kb
Host smart-64152c01-3fcc-4c84-8b62-84156d3f2198
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809733039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.809733039
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3663194341
Short name T767
Test name
Test status
Simulation time 1133337067 ps
CPU time 5.52 seconds
Started Jul 25 05:47:50 PM PDT 24
Finished Jul 25 05:47:56 PM PDT 24
Peak memory 233540 kb
Host smart-c0515f26-b453-4c7b-bf7a-5b5f113f2592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663194341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3663194341
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3743307416
Short name T493
Test name
Test status
Simulation time 123634115 ps
CPU time 2.22 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:47:57 PM PDT 24
Peak memory 224732 kb
Host smart-8c68b886-51f4-414e-9d8b-3e58f12f970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743307416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3743307416
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2953630037
Short name T137
Test name
Test status
Simulation time 128949122 ps
CPU time 3.85 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:47:59 PM PDT 24
Peak memory 223316 kb
Host smart-9eaf4d2f-35e0-4f3f-88af-2fb22a135799
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2953630037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2953630037
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.667734675
Short name T62
Test name
Test status
Simulation time 183922122 ps
CPU time 1.18 seconds
Started Jul 25 05:48:01 PM PDT 24
Finished Jul 25 05:48:02 PM PDT 24
Peak memory 235932 kb
Host smart-67f5e614-581d-41a3-b3fc-d8ea97c4d317
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667734675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.667734675
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2470335506
Short name T152
Test name
Test status
Simulation time 82517346831 ps
CPU time 399.85 seconds
Started Jul 25 05:47:56 PM PDT 24
Finished Jul 25 05:54:36 PM PDT 24
Peak memory 258352 kb
Host smart-c2167be8-1c16-42f9-beb2-5525aeded151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470335506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2470335506
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1927942654
Short name T431
Test name
Test status
Simulation time 6327018263 ps
CPU time 9.2 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:48:45 PM PDT 24
Peak memory 217184 kb
Host smart-37a64219-19aa-43b3-b88f-029088cb653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927942654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1927942654
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3177079927
Short name T952
Test name
Test status
Simulation time 1192736628 ps
CPU time 2.56 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:47:58 PM PDT 24
Peak memory 217156 kb
Host smart-486a427f-7851-46b5-b17c-0cb0342ada2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177079927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3177079927
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2878936040
Short name T880
Test name
Test status
Simulation time 30530628 ps
CPU time 0.84 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:47:54 PM PDT 24
Peak memory 206752 kb
Host smart-cbdc24e6-7cab-4b0c-a7e7-70ff445ac3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878936040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2878936040
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2076841373
Short name T335
Test name
Test status
Simulation time 76396912 ps
CPU time 0.85 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:47:55 PM PDT 24
Peak memory 206796 kb
Host smart-dbeff0b3-8219-4fe6-afee-f580b96ecc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076841373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2076841373
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3840033784
Short name T609
Test name
Test status
Simulation time 557593969 ps
CPU time 6.16 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:10 PM PDT 24
Peak memory 233568 kb
Host smart-f9c02806-ccdb-4963-9c06-d1a848e76d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840033784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3840033784
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.147539064
Short name T505
Test name
Test status
Simulation time 13862490 ps
CPU time 0.74 seconds
Started Jul 25 05:48:37 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 205480 kb
Host smart-f90064c2-3297-49c3-976a-d3b3bb3b63fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147539064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.147539064
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.815059249
Short name T484
Test name
Test status
Simulation time 301005630 ps
CPU time 2.49 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:36 PM PDT 24
Peak memory 233612 kb
Host smart-1023ca54-9a07-4d32-9e83-04bcb30a8c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815059249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.815059249
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3819001299
Short name T1005
Test name
Test status
Simulation time 28520047 ps
CPU time 0.78 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 206580 kb
Host smart-d2a7a536-3adf-4383-8128-7e7896db0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819001299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3819001299
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4220251799
Short name T351
Test name
Test status
Simulation time 1110690962 ps
CPU time 27.43 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 241908 kb
Host smart-f75e769a-3083-4307-b158-cd92b0fceaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220251799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4220251799
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4032765837
Short name T386
Test name
Test status
Simulation time 20240294860 ps
CPU time 120.41 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:50:35 PM PDT 24
Peak memory 250120 kb
Host smart-b5f439d8-8173-4124-b7f0-0188b4ab7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032765837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4032765837
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3679914436
Short name T654
Test name
Test status
Simulation time 7778215924 ps
CPU time 47.98 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 218412 kb
Host smart-aa5aa1ad-1e9a-4a69-8393-b536718f9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679914436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3679914436
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3349540497
Short name T7
Test name
Test status
Simulation time 571400434 ps
CPU time 6.98 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:41 PM PDT 24
Peak memory 225456 kb
Host smart-bf326780-ee4a-4635-9dd0-ae97324ea0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349540497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3349540497
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3406774999
Short name T203
Test name
Test status
Simulation time 9213882358 ps
CPU time 85.3 seconds
Started Jul 25 05:48:36 PM PDT 24
Finished Jul 25 05:50:01 PM PDT 24
Peak memory 250080 kb
Host smart-b901759a-0ae8-4491-be51-f823a5e50c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406774999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3406774999
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2434612445
Short name T747
Test name
Test status
Simulation time 418844258 ps
CPU time 4.84 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 225392 kb
Host smart-39e06188-d04f-46b5-b63d-f8503a0723d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434612445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2434612445
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1532575965
Short name T624
Test name
Test status
Simulation time 1224223078 ps
CPU time 9.89 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:48:51 PM PDT 24
Peak memory 225444 kb
Host smart-9895ab8b-7a45-4ebe-a38d-4907fb915cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532575965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1532575965
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3307806626
Short name T587
Test name
Test status
Simulation time 28354308 ps
CPU time 1.04 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 218676 kb
Host smart-0ee6ff12-0b02-46eb-accf-0105613c2829
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307806626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3307806626
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2134022363
Short name T793
Test name
Test status
Simulation time 12585766260 ps
CPU time 19.69 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:48:54 PM PDT 24
Peak memory 233732 kb
Host smart-24fbb532-a712-4ff9-97fb-bc55c029d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134022363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2134022363
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3989515415
Short name T402
Test name
Test status
Simulation time 943972040 ps
CPU time 10.29 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:43 PM PDT 24
Peak memory 251864 kb
Host smart-0a0ebd8f-814c-45bb-b81e-0e6a28854593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989515415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3989515415
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3251955137
Short name T646
Test name
Test status
Simulation time 3065383115 ps
CPU time 6.06 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:48:41 PM PDT 24
Peak memory 219976 kb
Host smart-02d847bc-6c46-4524-9bcc-80eb82d799ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3251955137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3251955137
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.4032568940
Short name T146
Test name
Test status
Simulation time 5792911599 ps
CPU time 37.81 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:49:11 PM PDT 24
Peak memory 241972 kb
Host smart-25e2f1ec-3dc6-460f-a1ba-1b0891dc9038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032568940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.4032568940
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1858722927
Short name T801
Test name
Test status
Simulation time 3046343648 ps
CPU time 10.14 seconds
Started Jul 25 05:48:32 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 217364 kb
Host smart-7638f7ca-decf-49c8-8b48-4bd639d1b5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858722927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1858722927
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2876049835
Short name T423
Test name
Test status
Simulation time 4251459241 ps
CPU time 3.15 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:48:39 PM PDT 24
Peak memory 217020 kb
Host smart-9086ce6e-64ff-4c45-a001-9d4879fba048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876049835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2876049835
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2636419055
Short name T633
Test name
Test status
Simulation time 93610375 ps
CPU time 1.69 seconds
Started Jul 25 05:48:32 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 217120 kb
Host smart-786bb821-f74d-4bd3-a58d-f15c2767bb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636419055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2636419055
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.552697181
Short name T539
Test name
Test status
Simulation time 22515566 ps
CPU time 0.77 seconds
Started Jul 25 05:48:32 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 206696 kb
Host smart-848c809c-66e6-41d9-a4b9-cdca0a2736b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552697181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.552697181
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1084367169
Short name T549
Test name
Test status
Simulation time 372154971 ps
CPU time 5.57 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:40 PM PDT 24
Peak memory 233628 kb
Host smart-da95da1c-8618-46b7-b772-1abadd0dc4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084367169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1084367169
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.837100227
Short name T555
Test name
Test status
Simulation time 47095453 ps
CPU time 0.75 seconds
Started Jul 25 05:48:40 PM PDT 24
Finished Jul 25 05:48:40 PM PDT 24
Peak memory 206416 kb
Host smart-4476a5c4-3e21-481c-9770-179460cd4ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837100227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.837100227
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1961838209
Short name T588
Test name
Test status
Simulation time 2602169407 ps
CPU time 9.76 seconds
Started Jul 25 05:48:39 PM PDT 24
Finished Jul 25 05:48:49 PM PDT 24
Peak memory 225508 kb
Host smart-473e4d41-a2f2-431c-8538-f73e29d59916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961838209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1961838209
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1364086085
Short name T984
Test name
Test status
Simulation time 168345771 ps
CPU time 0.72 seconds
Started Jul 25 05:48:39 PM PDT 24
Finished Jul 25 05:48:40 PM PDT 24
Peak memory 206268 kb
Host smart-89c390d8-029a-4b02-b623-b5894e508982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364086085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1364086085
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1456516236
Short name T719
Test name
Test status
Simulation time 736514755 ps
CPU time 15.08 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:48 PM PDT 24
Peak memory 241784 kb
Host smart-259a4623-fa99-45cd-8486-7e7af7234c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456516236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1456516236
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1694700092
Short name T125
Test name
Test status
Simulation time 46258716188 ps
CPU time 208.86 seconds
Started Jul 25 05:48:39 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 266528 kb
Host smart-73967078-29c3-42f3-8c17-f80e74bf23f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694700092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1694700092
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4014348697
Short name T400
Test name
Test status
Simulation time 349294778 ps
CPU time 5.17 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:47 PM PDT 24
Peak memory 219536 kb
Host smart-5f2d2038-35b7-4155-be05-f7e3278ab6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014348697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4014348697
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.910875488
Short name T133
Test name
Test status
Simulation time 4077167985 ps
CPU time 31.99 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 250108 kb
Host smart-2221d56c-9385-4b8d-905d-da43ec4ee6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910875488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.910875488
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3481225320
Short name T712
Test name
Test status
Simulation time 9260836018 ps
CPU time 28.07 seconds
Started Jul 25 05:48:35 PM PDT 24
Finished Jul 25 05:49:03 PM PDT 24
Peak memory 233696 kb
Host smart-80593919-aa48-4fa7-bc2d-c01009c5929d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481225320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3481225320
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2184762363
Short name T437
Test name
Test status
Simulation time 9362346756 ps
CPU time 21.87 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:56 PM PDT 24
Peak memory 225472 kb
Host smart-44a7df71-cf45-4a8e-95d6-414ccade42b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184762363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2184762363
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.987720311
Short name T346
Test name
Test status
Simulation time 12119488752 ps
CPU time 103.75 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:50:25 PM PDT 24
Peak memory 250152 kb
Host smart-dfb8ff76-83e5-4df6-8e1d-046bfe3b0054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987720311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.987720311
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.962999546
Short name T469
Test name
Test status
Simulation time 91043657 ps
CPU time 1.09 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:36 PM PDT 24
Peak memory 217380 kb
Host smart-2f37e1cf-ebc3-4508-804a-0c48d122adb0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962999546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.962999546
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3099840510
Short name T602
Test name
Test status
Simulation time 5824841493 ps
CPU time 18.13 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 233684 kb
Host smart-e0f0363e-ddaf-4a61-973b-1041056c2dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099840510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3099840510
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.425472400
Short name T878
Test name
Test status
Simulation time 1101873791 ps
CPU time 3.8 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 225356 kb
Host smart-1e01ad96-2ad1-4aff-90ab-d39eb2f36583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425472400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.425472400
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4236255094
Short name T135
Test name
Test status
Simulation time 5346237855 ps
CPU time 7 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:41 PM PDT 24
Peak memory 220060 kb
Host smart-201685da-02e1-4cce-b5ad-11e6be2f07ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236255094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4236255094
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3336417329
Short name T977
Test name
Test status
Simulation time 73524145 ps
CPU time 0.9 seconds
Started Jul 25 05:48:43 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 207632 kb
Host smart-6c597ffc-526e-44cc-b354-63b242250b65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336417329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3336417329
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.471339076
Short name T715
Test name
Test status
Simulation time 2045918555 ps
CPU time 16.88 seconds
Started Jul 25 05:48:34 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 217304 kb
Host smart-cf423dc4-def7-4d01-a61d-c06865e3c08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471339076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.471339076
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1332390627
Short name T78
Test name
Test status
Simulation time 13959546066 ps
CPU time 14.39 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:48:46 PM PDT 24
Peak memory 217260 kb
Host smart-06b0e187-7074-4ca0-930c-5d1af11f6071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332390627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1332390627
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1989926721
Short name T670
Test name
Test status
Simulation time 50881765 ps
CPU time 1.56 seconds
Started Jul 25 05:48:39 PM PDT 24
Finished Jul 25 05:48:41 PM PDT 24
Peak memory 217168 kb
Host smart-7fab02bb-4dde-4f61-8ee1-379d793608c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989926721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1989926721
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.392777642
Short name T357
Test name
Test status
Simulation time 43170493 ps
CPU time 0.75 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:48:32 PM PDT 24
Peak memory 206752 kb
Host smart-2218f185-9409-4386-aac7-de4c1dc4c8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392777642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.392777642
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2983649927
Short name T765
Test name
Test status
Simulation time 1190302851 ps
CPU time 3.25 seconds
Started Jul 25 05:48:33 PM PDT 24
Finished Jul 25 05:48:37 PM PDT 24
Peak memory 225440 kb
Host smart-7f3d5f5a-5939-499a-9141-f0b66fbeb00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983649927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2983649927
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1594287014
Short name T373
Test name
Test status
Simulation time 14335237 ps
CPU time 0.75 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:48:51 PM PDT 24
Peak memory 205532 kb
Host smart-1f6bbbb2-5394-413a-b97d-fcbc79dc10b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594287014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1594287014
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3128118094
Short name T513
Test name
Test status
Simulation time 2912988487 ps
CPU time 6.24 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:49 PM PDT 24
Peak memory 233644 kb
Host smart-2603b4bd-237c-4c91-a9c8-fa50d7454d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128118094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3128118094
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1934766995
Short name T27
Test name
Test status
Simulation time 40898445 ps
CPU time 0.8 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 207232 kb
Host smart-997f969b-fa14-4d56-b4f1-08f6618d3a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934766995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1934766995
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2018522160
Short name T123
Test name
Test status
Simulation time 15626979867 ps
CPU time 29.4 seconds
Started Jul 25 05:48:43 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 242256 kb
Host smart-35c08d79-36f9-4f46-833b-36a2a1f7ea47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018522160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2018522160
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.4176697413
Short name T1003
Test name
Test status
Simulation time 5051300942 ps
CPU time 35.75 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:49:25 PM PDT 24
Peak memory 252448 kb
Host smart-d806a151-2ccf-47c0-9bdc-ac5fcf604959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176697413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.4176697413
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.920079612
Short name T698
Test name
Test status
Simulation time 5935909478 ps
CPU time 30.49 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:49:20 PM PDT 24
Peak memory 225608 kb
Host smart-e1ca3633-5125-4d44-9770-a3ca09f70deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920079612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.920079612
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3847968781
Short name T134
Test name
Test status
Simulation time 626930166 ps
CPU time 7.21 seconds
Started Jul 25 05:48:39 PM PDT 24
Finished Jul 25 05:48:46 PM PDT 24
Peak memory 233672 kb
Host smart-d6c1d3b5-4753-475f-8bb8-510acef483b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847968781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3847968781
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3379829933
Short name T179
Test name
Test status
Simulation time 31177944954 ps
CPU time 76.72 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:49:58 PM PDT 24
Peak memory 251108 kb
Host smart-c364d7f8-8b42-4a2e-adc0-e2621279b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379829933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3379829933
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1575245782
Short name T928
Test name
Test status
Simulation time 2628143377 ps
CPU time 16.47 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:48:57 PM PDT 24
Peak memory 225460 kb
Host smart-874f9156-505a-4769-ad9c-5c00ecaf388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575245782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1575245782
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1990234499
Short name T553
Test name
Test status
Simulation time 63261574445 ps
CPU time 114.51 seconds
Started Jul 25 05:48:40 PM PDT 24
Finished Jul 25 05:50:35 PM PDT 24
Peak memory 241668 kb
Host smart-27547039-6e17-440b-8cd6-146678f3d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990234499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1990234499
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.481795326
Short name T510
Test name
Test status
Simulation time 15991032 ps
CPU time 1.04 seconds
Started Jul 25 05:48:45 PM PDT 24
Finished Jul 25 05:48:46 PM PDT 24
Peak memory 217424 kb
Host smart-0342e268-4e9a-434f-ad71-b21ab5df7a13
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481795326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.481795326
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2399688541
Short name T464
Test name
Test status
Simulation time 32619116 ps
CPU time 2.53 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 233628 kb
Host smart-0f5ba1c6-8b9e-458c-93ab-5113dda3636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399688541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2399688541
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2312899717
Short name T705
Test name
Test status
Simulation time 639992849 ps
CPU time 3.96 seconds
Started Jul 25 05:48:40 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 220732 kb
Host smart-d292bc66-d94b-41c1-84cc-5e880a2aefa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2312899717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2312899717
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4062120932
Short name T275
Test name
Test status
Simulation time 2514719040 ps
CPU time 9.29 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 217396 kb
Host smart-ee53d0db-f3ac-444c-b755-3d9053a0f96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062120932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4062120932
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1043367073
Short name T291
Test name
Test status
Simulation time 3562868953 ps
CPU time 11.49 seconds
Started Jul 25 05:48:44 PM PDT 24
Finished Jul 25 05:48:55 PM PDT 24
Peak memory 217180 kb
Host smart-9fd8433f-7ba1-49e6-97a4-7f1ce00f73ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043367073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1043367073
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3178818488
Short name T504
Test name
Test status
Simulation time 80732823 ps
CPU time 1.08 seconds
Started Jul 25 05:48:42 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 208548 kb
Host smart-26535652-583f-4967-a3c6-e3218425cf92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178818488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3178818488
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1967710593
Short name T594
Test name
Test status
Simulation time 34023385 ps
CPU time 0.82 seconds
Started Jul 25 05:48:43 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 206788 kb
Host smart-73b6a6b5-2cc1-4490-900d-7530ca19ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967710593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1967710593
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1711285397
Short name T798
Test name
Test status
Simulation time 613594502 ps
CPU time 4.74 seconds
Started Jul 25 05:48:41 PM PDT 24
Finished Jul 25 05:48:46 PM PDT 24
Peak memory 225440 kb
Host smart-0291d625-241a-4b5a-b3f2-5fd5d4b86e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711285397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1711285397
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3189685479
Short name T800
Test name
Test status
Simulation time 43725540 ps
CPU time 0.79 seconds
Started Jul 25 05:48:51 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 206388 kb
Host smart-2350ded3-ba95-43e5-9e28-648fc3984b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189685479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3189685479
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4189329898
Short name T600
Test name
Test status
Simulation time 473738085 ps
CPU time 2.44 seconds
Started Jul 25 05:48:56 PM PDT 24
Finished Jul 25 05:48:59 PM PDT 24
Peak memory 225416 kb
Host smart-0c0b3a5f-b55d-4530-931e-ad33eec4fa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189329898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4189329898
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1012338518
Short name T736
Test name
Test status
Simulation time 30607908 ps
CPU time 0.77 seconds
Started Jul 25 05:48:48 PM PDT 24
Finished Jul 25 05:48:49 PM PDT 24
Peak memory 207280 kb
Host smart-5b40cb9b-bbdf-40fc-b391-578ecc4a08c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012338518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1012338518
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.848157550
Short name T202
Test name
Test status
Simulation time 13221984915 ps
CPU time 172.02 seconds
Started Jul 25 05:48:55 PM PDT 24
Finished Jul 25 05:51:47 PM PDT 24
Peak memory 263468 kb
Host smart-c643da65-f91f-4b14-ad26-3562313ac45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848157550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.848157550
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2851215010
Short name T430
Test name
Test status
Simulation time 3790338623 ps
CPU time 25.4 seconds
Started Jul 25 05:48:55 PM PDT 24
Finished Jul 25 05:49:21 PM PDT 24
Peak memory 218544 kb
Host smart-0a52157d-da85-472f-94fa-5d7ef6819f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851215010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2851215010
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3519672860
Short name T680
Test name
Test status
Simulation time 174677027 ps
CPU time 6.97 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:48:57 PM PDT 24
Peak memory 233664 kb
Host smart-145d4895-e576-43e1-a2b8-d5a1373bacd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519672860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3519672860
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1117104327
Short name T175
Test name
Test status
Simulation time 2133479909 ps
CPU time 17.77 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 250120 kb
Host smart-8c06059a-4cb7-4f83-b282-2f6edd4ad57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117104327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1117104327
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4101409415
Short name T121
Test name
Test status
Simulation time 999851065 ps
CPU time 2.97 seconds
Started Jul 25 05:48:52 PM PDT 24
Finished Jul 25 05:48:56 PM PDT 24
Peak memory 233608 kb
Host smart-a751d0f3-2195-4e50-8bf5-adacc93531ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101409415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4101409415
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3506030330
Short name T991
Test name
Test status
Simulation time 1220753917 ps
CPU time 14.31 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:49:05 PM PDT 24
Peak memory 241588 kb
Host smart-5f4baf3c-1384-4f91-aceb-b1583a3d199c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506030330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3506030330
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3008157016
Short name T883
Test name
Test status
Simulation time 80800052 ps
CPU time 1.12 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:48:50 PM PDT 24
Peak memory 217380 kb
Host smart-5f7e6200-d96a-4c14-885d-5ad841b7dce6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008157016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3008157016
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3757731720
Short name T334
Test name
Test status
Simulation time 757652198 ps
CPU time 5.72 seconds
Started Jul 25 05:48:52 PM PDT 24
Finished Jul 25 05:48:58 PM PDT 24
Peak memory 233600 kb
Host smart-48c8091c-4979-4084-bc20-82297defbe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757731720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3757731720
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4194034488
Short name T222
Test name
Test status
Simulation time 2096008371 ps
CPU time 7.9 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:48:58 PM PDT 24
Peak memory 225384 kb
Host smart-dd6ac7dd-71fa-4dc1-9a97-b15c04b5b2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194034488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4194034488
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.933033383
Short name T544
Test name
Test status
Simulation time 953550825 ps
CPU time 5.34 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:48:55 PM PDT 24
Peak memory 220120 kb
Host smart-4c527125-7917-4150-8ccb-5897ca7411a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=933033383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.933033383
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.174188064
Short name T126
Test name
Test status
Simulation time 128616681683 ps
CPU time 201.07 seconds
Started Jul 25 05:48:47 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 282880 kb
Host smart-c4d501f0-4d37-4511-a99d-eb710908fef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174188064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.174188064
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.86074520
Short name T421
Test name
Test status
Simulation time 932133916 ps
CPU time 10.41 seconds
Started Jul 25 05:48:56 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 217196 kb
Host smart-03bc6276-1fe6-49ca-a9d0-2350f2905229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86074520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.86074520
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1086234389
Short name T518
Test name
Test status
Simulation time 19450452416 ps
CPU time 13.41 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:49:04 PM PDT 24
Peak memory 217316 kb
Host smart-ef8fe49d-b6f0-4fcd-81ea-19792d8e3b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086234389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1086234389
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2214699814
Short name T671
Test name
Test status
Simulation time 216664875 ps
CPU time 2.55 seconds
Started Jul 25 05:48:51 PM PDT 24
Finished Jul 25 05:48:54 PM PDT 24
Peak memory 208960 kb
Host smart-e25b13e7-fab2-47f1-9c13-19ce6c1f40ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214699814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2214699814
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2150199576
Short name T355
Test name
Test status
Simulation time 52853299 ps
CPU time 0.83 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:48:50 PM PDT 24
Peak memory 206764 kb
Host smart-526e7c4b-97ec-4690-b1ce-cb3a79c7e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150199576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2150199576
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3470515113
Short name T563
Test name
Test status
Simulation time 513378192 ps
CPU time 2.43 seconds
Started Jul 25 05:48:53 PM PDT 24
Finished Jul 25 05:48:56 PM PDT 24
Peak memory 224892 kb
Host smart-59173308-2ace-4a31-9902-047fa6227f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470515113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3470515113
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1261678090
Short name T483
Test name
Test status
Simulation time 17619448 ps
CPU time 0.72 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:00 PM PDT 24
Peak memory 206384 kb
Host smart-b106390c-d97b-4813-9d3c-9835fa35c2e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261678090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1261678090
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1841744573
Short name T808
Test name
Test status
Simulation time 825195326 ps
CPU time 12.77 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:14 PM PDT 24
Peak memory 225424 kb
Host smart-7b46b47a-b480-4450-a2fe-94cb7063febe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841744573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1841744573
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.326021155
Short name T285
Test name
Test status
Simulation time 33389352 ps
CPU time 0.75 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:48:50 PM PDT 24
Peak memory 206200 kb
Host smart-832e5f44-fa73-4265-a050-d709cbc10e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326021155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.326021155
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1096362435
Short name T554
Test name
Test status
Simulation time 7294223240 ps
CPU time 65.83 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 250088 kb
Host smart-3eb6048c-7fdf-45b9-a2a3-01d344119dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096362435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1096362435
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1250991606
Short name T810
Test name
Test status
Simulation time 45675382232 ps
CPU time 209.18 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 251052 kb
Host smart-4daccdde-a00a-4c2a-b6bc-4a712d0c5e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250991606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1250991606
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1348701593
Short name T50
Test name
Test status
Simulation time 13305791780 ps
CPU time 68.99 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:50:07 PM PDT 24
Peak memory 250160 kb
Host smart-93cd8548-883b-4a1b-ac87-574a127ce3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348701593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1348701593
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.679396166
Short name T677
Test name
Test status
Simulation time 87374516701 ps
CPU time 110.3 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:50:49 PM PDT 24
Peak memory 254012 kb
Host smart-42ef15ba-bcdb-4e5d-98c0-0757b309f555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679396166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.679396166
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1628582573
Short name T229
Test name
Test status
Simulation time 6425384784 ps
CPU time 17.53 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:16 PM PDT 24
Peak memory 225416 kb
Host smart-a1f8625c-3431-4125-ad5a-475c86fecae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628582573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1628582573
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2265726185
Short name T40
Test name
Test status
Simulation time 570275233 ps
CPU time 13.96 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 225444 kb
Host smart-2cd82419-0cdb-420d-877b-cf5623fbf513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265726185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2265726185
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2205707321
Short name T638
Test name
Test status
Simulation time 105346592 ps
CPU time 1.11 seconds
Started Jul 25 05:48:49 PM PDT 24
Finished Jul 25 05:48:50 PM PDT 24
Peak memory 218740 kb
Host smart-0bcb7345-fc86-4839-bb44-5795e0fd8b6b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205707321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2205707321
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2663414787
Short name T844
Test name
Test status
Simulation time 2193877690 ps
CPU time 4.6 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 233652 kb
Host smart-54504b02-3590-4df7-99a4-9e16fd42c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663414787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2663414787
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2433424008
Short name T313
Test name
Test status
Simulation time 1411006607 ps
CPU time 6.6 seconds
Started Jul 25 05:49:00 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 225404 kb
Host smart-49ebd0bc-d105-4818-9a46-812f33300447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433424008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2433424008
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1401309421
Short name T81
Test name
Test status
Simulation time 1736821541 ps
CPU time 6.83 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 220656 kb
Host smart-af820ac8-4142-41f9-b204-c01f05ab0954
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1401309421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1401309421
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4064487513
Short name T684
Test name
Test status
Simulation time 690806135515 ps
CPU time 538.69 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:57:57 PM PDT 24
Peak memory 290188 kb
Host smart-1209e64a-850b-44b4-ad35-2fe4b2f142b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064487513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4064487513
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2936764470
Short name T913
Test name
Test status
Simulation time 4173005138 ps
CPU time 21 seconds
Started Jul 25 05:48:50 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 217236 kb
Host smart-7045bfb0-6c31-4b24-a73e-1d3e5c45b0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936764470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2936764470
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3757740602
Short name T468
Test name
Test status
Simulation time 454017208 ps
CPU time 4.27 seconds
Started Jul 25 05:48:52 PM PDT 24
Finished Jul 25 05:48:56 PM PDT 24
Peak memory 217216 kb
Host smart-6edff75f-150d-4afa-839b-45e7b86339e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757740602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3757740602
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1133682695
Short name T6
Test name
Test status
Simulation time 82691814 ps
CPU time 3.02 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 217116 kb
Host smart-b32e3594-7240-4760-9ae8-5e530b513707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133682695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1133682695
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3633225791
Short name T623
Test name
Test status
Simulation time 112980827 ps
CPU time 0.75 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:00 PM PDT 24
Peak memory 206744 kb
Host smart-ad8304c1-e5e1-4dac-b9b1-087db3883784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633225791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3633225791
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1480588095
Short name T208
Test name
Test status
Simulation time 225463875 ps
CPU time 2.2 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:48:59 PM PDT 24
Peak memory 225460 kb
Host smart-829e8f26-4b89-442f-b612-19a7f369a6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480588095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1480588095
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2815179811
Short name T655
Test name
Test status
Simulation time 25905274 ps
CPU time 0.7 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:48:58 PM PDT 24
Peak memory 205544 kb
Host smart-6f0a8454-0216-4a49-8bca-a22d0dfcd162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815179811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2815179811
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.569545769
Short name T24
Test name
Test status
Simulation time 31423521 ps
CPU time 2.12 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:49:00 PM PDT 24
Peak memory 225480 kb
Host smart-c7a7c478-53f9-46e8-91e5-b88c5b91c12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569545769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.569545769
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3307735949
Short name T750
Test name
Test status
Simulation time 15531679 ps
CPU time 0.76 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 207276 kb
Host smart-e30eb83f-8946-4d09-aacc-d40ee69426d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307735949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3307735949
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3645034087
Short name T662
Test name
Test status
Simulation time 45704005177 ps
CPU time 97.59 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 241948 kb
Host smart-176c2cd0-66a1-4de8-bd28-6fc2dec8f101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645034087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3645034087
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2654813474
Short name T569
Test name
Test status
Simulation time 280104363 ps
CPU time 3.39 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 218684 kb
Host smart-48de074d-e2b4-4a6e-85e1-e33842a470b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654813474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2654813474
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1973824722
Short name T881
Test name
Test status
Simulation time 40871619578 ps
CPU time 183.99 seconds
Started Jul 25 05:49:02 PM PDT 24
Finished Jul 25 05:52:06 PM PDT 24
Peak memory 249448 kb
Host smart-6f32a0e5-2eb7-4911-9d89-0d75afca407b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973824722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1973824722
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1701336428
Short name T136
Test name
Test status
Simulation time 242583831 ps
CPU time 8.24 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:49:05 PM PDT 24
Peak memory 241864 kb
Host smart-c317113d-5358-44a2-a204-59047cb169c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701336428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1701336428
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.530038194
Short name T888
Test name
Test status
Simulation time 156261996815 ps
CPU time 149.95 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:51:27 PM PDT 24
Peak memory 253904 kb
Host smart-0f1eebd5-812d-4bb1-9421-c7c8b1092894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530038194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.530038194
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1613848389
Short name T755
Test name
Test status
Simulation time 784208273 ps
CPU time 10.51 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 233640 kb
Host smart-3a17d8d5-bbc1-4a6f-a3e6-4013232a35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613848389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1613848389
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1473840134
Short name T714
Test name
Test status
Simulation time 535335660 ps
CPU time 4.18 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:03 PM PDT 24
Peak memory 233636 kb
Host smart-8dba1517-6b38-40d7-8f49-134a92a1bc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473840134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1473840134
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3056242499
Short name T723
Test name
Test status
Simulation time 42946300 ps
CPU time 1.02 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 217416 kb
Host smart-9c4b8656-b10c-44c2-8ddb-8f5851451838
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056242499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3056242499
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2665670733
Short name T245
Test name
Test status
Simulation time 768402668 ps
CPU time 5.7 seconds
Started Jul 25 05:49:00 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 233632 kb
Host smart-dc1e0183-d78e-448c-b082-51ef9a269149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665670733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2665670733
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.487866387
Short name T740
Test name
Test status
Simulation time 2828823859 ps
CPU time 10.28 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 233660 kb
Host smart-ab545891-9f03-4dbe-9efa-b528c0cead1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487866387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.487866387
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1084081931
Short name T330
Test name
Test status
Simulation time 392012199 ps
CPU time 4.78 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 222716 kb
Host smart-4c4c5d22-b068-4358-89a4-0acc89953165
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1084081931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1084081931
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3618838230
Short name T647
Test name
Test status
Simulation time 53943699 ps
CPU time 1.23 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:49:00 PM PDT 24
Peak memory 208556 kb
Host smart-a90fbe76-bd6b-439a-96e3-58cdefc2f345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618838230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3618838230
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1393039399
Short name T1
Test name
Test status
Simulation time 2893465223 ps
CPU time 30.42 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:29 PM PDT 24
Peak memory 217276 kb
Host smart-89d083ec-a1b1-44cd-8351-be19aeb890d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393039399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1393039399
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1462034764
Short name T432
Test name
Test status
Simulation time 5162733660 ps
CPU time 16.35 seconds
Started Jul 25 05:48:59 PM PDT 24
Finished Jul 25 05:49:15 PM PDT 24
Peak memory 217224 kb
Host smart-995b742b-93df-4257-81c2-bf555836b62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462034764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1462034764
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2056059676
Short name T664
Test name
Test status
Simulation time 109929520 ps
CPU time 1.43 seconds
Started Jul 25 05:48:58 PM PDT 24
Finished Jul 25 05:48:59 PM PDT 24
Peak memory 208932 kb
Host smart-0a9a113d-c90a-4be3-8431-fa6878a5e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056059676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2056059676
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.318212490
Short name T615
Test name
Test status
Simulation time 11824220 ps
CPU time 0.71 seconds
Started Jul 25 05:49:01 PM PDT 24
Finished Jul 25 05:49:02 PM PDT 24
Peak memory 206304 kb
Host smart-b2df65c3-5464-4d4b-8b1c-29cc8817c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318212490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.318212490
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.4147867793
Short name T120
Test name
Test status
Simulation time 4865084791 ps
CPU time 8.43 seconds
Started Jul 25 05:48:57 PM PDT 24
Finished Jul 25 05:49:06 PM PDT 24
Peak memory 233724 kb
Host smart-045354fb-619b-4153-a2ea-99cb4dc3edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147867793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4147867793
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.495927072
Short name T971
Test name
Test status
Simulation time 1267438536 ps
CPU time 4.92 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 233676 kb
Host smart-569a0121-16e5-4168-87fa-93c91443aaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495927072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.495927072
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.359258350
Short name T54
Test name
Test status
Simulation time 82486642 ps
CPU time 0.76 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 207268 kb
Host smart-cebc8e25-38b4-4104-9e0c-c93c0492f94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359258350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.359258350
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2282637688
Short name T195
Test name
Test status
Simulation time 12162146521 ps
CPU time 88.91 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 252560 kb
Host smart-7ec3e4c0-8544-459b-a8af-bd611fe1da98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282637688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2282637688
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.524333938
Short name T192
Test name
Test status
Simulation time 6453554912 ps
CPU time 79.16 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:50:26 PM PDT 24
Peak memory 255208 kb
Host smart-369d84e1-7759-4099-89e9-32da6246e21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524333938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.524333938
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1421054068
Short name T973
Test name
Test status
Simulation time 718350974 ps
CPU time 3.41 seconds
Started Jul 25 05:49:09 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 218620 kb
Host smart-637ac893-895b-4602-b4f9-84f77ecc809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421054068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1421054068
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3043172272
Short name T790
Test name
Test status
Simulation time 186607686 ps
CPU time 6.74 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:14 PM PDT 24
Peak memory 233704 kb
Host smart-acc7ac8c-cdbd-4612-a86d-a485c8fbad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043172272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3043172272
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.1342797450
Short name T178
Test name
Test status
Simulation time 24392707787 ps
CPU time 67.13 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:50:16 PM PDT 24
Peak memory 263060 kb
Host smart-89974ebc-a9e1-4399-8ae1-143cefd50445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342797450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.1342797450
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1941852893
Short name T894
Test name
Test status
Simulation time 136237610 ps
CPU time 4.21 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:12 PM PDT 24
Peak memory 225408 kb
Host smart-852a134f-7776-43f1-9837-63c892cdc82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941852893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1941852893
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2486062058
Short name T574
Test name
Test status
Simulation time 622040533 ps
CPU time 4.69 seconds
Started Jul 25 05:54:59 PM PDT 24
Finished Jul 25 05:55:04 PM PDT 24
Peak memory 233584 kb
Host smart-50fbc894-dc8f-477d-9bb2-43768864d041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486062058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2486062058
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4061746410
Short name T860
Test name
Test status
Simulation time 15194175 ps
CPU time 1.01 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 217392 kb
Host smart-090d9d9f-adfa-4319-a983-8ec2157521fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061746410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4061746410
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2844105270
Short name T251
Test name
Test status
Simulation time 79467892775 ps
CPU time 30.28 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:49:37 PM PDT 24
Peak memory 241488 kb
Host smart-f483b642-f1f9-4a63-bc4a-f150982abae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844105270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2844105270
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2143444569
Short name T634
Test name
Test status
Simulation time 106212060 ps
CPU time 2.44 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 233248 kb
Host smart-9bf46394-88ed-4e2e-80b6-f621b3702e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143444569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2143444569
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2659721784
Short name T479
Test name
Test status
Simulation time 326957530 ps
CPU time 5.07 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:13 PM PDT 24
Peak memory 223824 kb
Host smart-05c6ebde-c747-4228-92fd-50f09a9ddf1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2659721784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2659721784
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3743052130
Short name T805
Test name
Test status
Simulation time 37905608727 ps
CPU time 385.11 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:55:33 PM PDT 24
Peak memory 258368 kb
Host smart-626f4ddf-8af4-4efa-b992-1a31501ffaf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743052130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3743052130
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4205438141
Short name T950
Test name
Test status
Simulation time 1711571972 ps
CPU time 13.05 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:21 PM PDT 24
Peak memory 217388 kb
Host smart-52f4b1cd-209d-403d-8f2e-bdde38022685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205438141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4205438141
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3713579856
Short name T732
Test name
Test status
Simulation time 23613420 ps
CPU time 0.68 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 206424 kb
Host smart-3f4999bd-6a30-47fc-be52-9c46f5cb2bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713579856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3713579856
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.961815591
Short name T375
Test name
Test status
Simulation time 146994708 ps
CPU time 1.43 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 217216 kb
Host smart-4820cfeb-b1b2-416e-9e61-f029b0b27c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961815591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.961815591
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.206265803
Short name T739
Test name
Test status
Simulation time 36622982 ps
CPU time 0.81 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 206804 kb
Host smart-439915b7-a541-42f8-ad95-8dc32e98878a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206265803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.206265803
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.312166233
Short name T401
Test name
Test status
Simulation time 1713762893 ps
CPU time 10.47 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:17 PM PDT 24
Peak memory 233620 kb
Host smart-1f650d88-7f91-4782-a91b-74607ea39054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312166233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.312166233
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.673989866
Short name T315
Test name
Test status
Simulation time 47425000 ps
CPU time 0.72 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 206088 kb
Host smart-d79b99c3-093f-4038-ac1b-12f79cc5d209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673989866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.673989866
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.4108871891
Short name T847
Test name
Test status
Simulation time 1184317131 ps
CPU time 6.4 seconds
Started Jul 25 05:49:08 PM PDT 24
Finished Jul 25 05:49:15 PM PDT 24
Peak memory 225432 kb
Host smart-b690fac4-0e34-4acf-8162-3742020f2301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108871891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.4108871891
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1087330723
Short name T967
Test name
Test status
Simulation time 51690690 ps
CPU time 0.8 seconds
Started Jul 25 05:49:10 PM PDT 24
Finished Jul 25 05:49:11 PM PDT 24
Peak memory 207292 kb
Host smart-5f1dfd4c-a8f4-49d6-b1d0-6960b12cdab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087330723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1087330723
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1530719258
Short name T38
Test name
Test status
Simulation time 6113105615 ps
CPU time 86.69 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 265048 kb
Host smart-91f156d6-2317-43f1-916f-96c386c0da3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530719258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1530719258
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3550401797
Short name T949
Test name
Test status
Simulation time 5922175959 ps
CPU time 96.36 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:50:42 PM PDT 24
Peak memory 254072 kb
Host smart-440a9997-cd42-42b9-8cf8-f2dfb640c5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550401797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3550401797
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1857775627
Short name T784
Test name
Test status
Simulation time 31158964486 ps
CPU time 28.91 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:46 PM PDT 24
Peak memory 218708 kb
Host smart-cd15231a-ed8d-472d-87d3-465dba55a053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857775627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1857775627
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3259645315
Short name T323
Test name
Test status
Simulation time 3117604287 ps
CPU time 13.43 seconds
Started Jul 25 05:49:10 PM PDT 24
Finished Jul 25 05:49:23 PM PDT 24
Peak memory 225524 kb
Host smart-c40c17d0-79d2-415e-a29b-e5cd6fea2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259645315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3259645315
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.352903207
Short name T803
Test name
Test status
Simulation time 11252611008 ps
CPU time 24.42 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:49:30 PM PDT 24
Peak memory 241820 kb
Host smart-f3a854b4-de45-4328-a7be-e5131b85d88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352903207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.352903207
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3339944270
Short name T86
Test name
Test status
Simulation time 1313517463 ps
CPU time 3.18 seconds
Started Jul 25 05:49:10 PM PDT 24
Finished Jul 25 05:49:14 PM PDT 24
Peak memory 225424 kb
Host smart-2886d979-1074-4887-8c30-f36cbe5d343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339944270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3339944270
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2815193479
Short name T547
Test name
Test status
Simulation time 7354872127 ps
CPU time 67.4 seconds
Started Jul 25 05:49:10 PM PDT 24
Finished Jul 25 05:50:17 PM PDT 24
Peak memory 241548 kb
Host smart-f86d147c-163f-4813-a16e-57dff2f509e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815193479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2815193479
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2101704589
Short name T442
Test name
Test status
Simulation time 111926696 ps
CPU time 1.05 seconds
Started Jul 25 05:49:10 PM PDT 24
Finished Jul 25 05:49:11 PM PDT 24
Peak memory 218604 kb
Host smart-58e45fc6-de2b-4c70-87bd-38b47aebe01a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101704589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2101704589
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1214559086
Short name T559
Test name
Test status
Simulation time 253755061 ps
CPU time 3.1 seconds
Started Jul 25 05:49:05 PM PDT 24
Finished Jul 25 05:49:08 PM PDT 24
Peak memory 225432 kb
Host smart-41a27a78-eb6b-46d6-a76c-467fbe2a130f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214559086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1214559086
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.546577160
Short name T786
Test name
Test status
Simulation time 670889523 ps
CPU time 4.89 seconds
Started Jul 25 05:49:09 PM PDT 24
Finished Jul 25 05:49:14 PM PDT 24
Peak memory 238868 kb
Host smart-eeca52ba-49ec-4bdf-bd81-ed33ca89e972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546577160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.546577160
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4219493593
Short name T911
Test name
Test status
Simulation time 2405724410 ps
CPU time 8.62 seconds
Started Jul 25 05:49:09 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 220592 kb
Host smart-ef59f61d-820f-4d51-b445-aaa79c4c7138
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4219493593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4219493593
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.179731550
Short name T17
Test name
Test status
Simulation time 47809560 ps
CPU time 1.1 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 207564 kb
Host smart-fab9f6d3-abe4-4040-8418-4930b30befe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179731550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.179731550
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.138715610
Short name T608
Test name
Test status
Simulation time 1200209726 ps
CPU time 17.4 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:24 PM PDT 24
Peak memory 217208 kb
Host smart-b05a7b2a-6532-4e12-9983-d44901bde29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138715610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.138715610
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1886036472
Short name T899
Test name
Test status
Simulation time 5961044242 ps
CPU time 2.21 seconds
Started Jul 25 05:49:07 PM PDT 24
Finished Jul 25 05:49:10 PM PDT 24
Peak memory 208744 kb
Host smart-f89ecf00-f5e7-4f7f-b146-be6f666fa082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886036472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1886036472
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1753906360
Short name T815
Test name
Test status
Simulation time 50735073 ps
CPU time 2.7 seconds
Started Jul 25 05:49:04 PM PDT 24
Finished Jul 25 05:49:07 PM PDT 24
Peak memory 217072 kb
Host smart-1bf9307d-d382-454d-b7e0-7746219a0f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753906360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1753906360
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.346072170
Short name T614
Test name
Test status
Simulation time 127437858 ps
CPU time 0.94 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 207764 kb
Host smart-cd15bf69-7dee-475e-beb5-4e568a77cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346072170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.346072170
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.852573012
Short name T496
Test name
Test status
Simulation time 2500893775 ps
CPU time 10.76 seconds
Started Jul 25 05:49:06 PM PDT 24
Finished Jul 25 05:49:17 PM PDT 24
Peak memory 225560 kb
Host smart-0cff2429-aef1-4e4e-a365-d81ba29d3150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852573012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.852573012
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2988202431
Short name T579
Test name
Test status
Simulation time 15454930 ps
CPU time 0.75 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 206072 kb
Host smart-5d44a610-3b7a-46dc-807f-3aa30222177e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988202431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2988202431
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.573090008
Short name T512
Test name
Test status
Simulation time 824264574 ps
CPU time 4.48 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:20 PM PDT 24
Peak memory 233656 kb
Host smart-4e4b5f8f-930c-4c17-a714-bb8d1ca957c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573090008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.573090008
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.322672415
Short name T821
Test name
Test status
Simulation time 19434276 ps
CPU time 0.8 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 207552 kb
Host smart-5c4c29b2-5b47-4e60-9620-d5b68bb0c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322672415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.322672415
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2400784792
Short name T237
Test name
Test status
Simulation time 46677895192 ps
CPU time 115.58 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:51:13 PM PDT 24
Peak memory 251960 kb
Host smart-e32456ed-d3fd-4401-9f68-b61029a722a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400784792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2400784792
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1145047518
Short name T906
Test name
Test status
Simulation time 31675199151 ps
CPU time 361.18 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:55:17 PM PDT 24
Peak memory 263880 kb
Host smart-be05b935-7c26-4b49-b080-9587638f98cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145047518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1145047518
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3665371413
Short name T519
Test name
Test status
Simulation time 856285516 ps
CPU time 9.81 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:25 PM PDT 24
Peak memory 233632 kb
Host smart-038f089c-9a51-4bf4-aa1c-ea051a0756cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665371413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3665371413
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2810690174
Short name T254
Test name
Test status
Simulation time 5116482607 ps
CPU time 58.3 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:50:16 PM PDT 24
Peak memory 252068 kb
Host smart-19df9944-f090-4611-92f3-534f15dc3214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810690174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2810690174
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3535704410
Short name T935
Test name
Test status
Simulation time 343596773 ps
CPU time 3.84 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 233680 kb
Host smart-0981ac02-b266-4a86-a0a4-85ba826e14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535704410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3535704410
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2996971190
Short name T436
Test name
Test status
Simulation time 5068093123 ps
CPU time 29.16 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 225480 kb
Host smart-b833c1fb-871d-4a0f-8166-91fb1380c44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996971190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2996971190
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.254726035
Short name T725
Test name
Test status
Simulation time 53053205 ps
CPU time 1.01 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:16 PM PDT 24
Peak memory 218620 kb
Host smart-2ead56f3-8f50-480e-8898-928098869ee4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254726035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.254726035
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2195033251
Short name T550
Test name
Test status
Simulation time 306973194 ps
CPU time 3.62 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 233580 kb
Host smart-cde8efc8-648a-45cc-adcb-7a31f397502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195033251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2195033251
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1040931727
Short name T910
Test name
Test status
Simulation time 1080844152 ps
CPU time 4.73 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 225428 kb
Host smart-17eeaadf-306a-4dcc-a3a6-bc5aa5d28929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040931727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1040931727
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4192058685
Short name T470
Test name
Test status
Simulation time 4869917903 ps
CPU time 10.35 seconds
Started Jul 25 05:49:20 PM PDT 24
Finished Jul 25 05:49:30 PM PDT 24
Peak memory 223556 kb
Host smart-854d5ed6-e742-4cd8-9c5c-5a463110a32c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4192058685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4192058685
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3939178005
Short name T508
Test name
Test status
Simulation time 2227886900 ps
CPU time 14.9 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:30 PM PDT 24
Peak memory 217300 kb
Host smart-73bbe1d6-868a-455c-b67d-a928c444f606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939178005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3939178005
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1540770782
Short name T789
Test name
Test status
Simulation time 3360209994 ps
CPU time 9.73 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:25 PM PDT 24
Peak memory 217140 kb
Host smart-66f19ec0-5455-48a1-a9d0-d90af2ea51b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540770782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1540770782
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2294973401
Short name T738
Test name
Test status
Simulation time 147399559 ps
CPU time 1.09 seconds
Started Jul 25 05:49:19 PM PDT 24
Finished Jul 25 05:49:20 PM PDT 24
Peak memory 208728 kb
Host smart-3afd2417-c7fa-4bad-9b64-cdf71734c5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294973401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2294973401
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3505168059
Short name T391
Test name
Test status
Simulation time 129913327 ps
CPU time 0.93 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 207796 kb
Host smart-35063287-f105-4181-8607-957174863eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505168059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3505168059
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.859312474
Short name T385
Test name
Test status
Simulation time 306156506 ps
CPU time 5.34 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 233676 kb
Host smart-e6662413-6202-447d-aa5a-2336fc966f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859312474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.859312474
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3346307547
Short name T757
Test name
Test status
Simulation time 12742240 ps
CPU time 0.71 seconds
Started Jul 25 05:49:31 PM PDT 24
Finished Jul 25 05:49:32 PM PDT 24
Peak memory 206404 kb
Host smart-aab3dd9e-d9bc-4903-80fc-4dcb561b42cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346307547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3346307547
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2322567170
Short name T218
Test name
Test status
Simulation time 562249224 ps
CPU time 3.68 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 225440 kb
Host smart-97050020-d7ff-4858-a19c-3009b549f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322567170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2322567170
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2771294392
Short name T799
Test name
Test status
Simulation time 14753303 ps
CPU time 0.77 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:49:17 PM PDT 24
Peak memory 206268 kb
Host smart-56e4a28c-ee33-419b-9f8a-6e4888b8fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771294392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2771294392
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2075840988
Short name T28
Test name
Test status
Simulation time 4090740534 ps
CPU time 11.5 seconds
Started Jul 25 05:49:19 PM PDT 24
Finished Jul 25 05:49:31 PM PDT 24
Peak memory 238484 kb
Host smart-6e3c2137-6460-4c16-ad7c-426becbc9f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075840988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2075840988
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.777759580
Short name T1019
Test name
Test status
Simulation time 45265241789 ps
CPU time 113.78 seconds
Started Jul 25 05:49:27 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 241280 kb
Host smart-d9546cc8-eb88-4d3d-a166-719279028d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777759580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.777759580
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.724498795
Short name T270
Test name
Test status
Simulation time 11359222462 ps
CPU time 35.39 seconds
Started Jul 25 05:49:27 PM PDT 24
Finished Jul 25 05:50:03 PM PDT 24
Peak memory 219672 kb
Host smart-12b23a0b-0dca-4eef-bdae-12cf87d3727c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724498795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.724498795
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.675418757
Short name T260
Test name
Test status
Simulation time 393705857 ps
CPU time 6.28 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:23 PM PDT 24
Peak memory 225460 kb
Host smart-c6ef0962-139c-4db0-86de-ba9840f88f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675418757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.675418757
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.718062664
Short name T791
Test name
Test status
Simulation time 9331480698 ps
CPU time 77.53 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:50:33 PM PDT 24
Peak memory 258252 kb
Host smart-de4eea41-7bec-4788-ab1a-31bd6fb3dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718062664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.718062664
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1944207226
Short name T693
Test name
Test status
Simulation time 832881794 ps
CPU time 11.48 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:49:27 PM PDT 24
Peak memory 225432 kb
Host smart-c2c9ac77-abfc-4958-936d-2c739151ec45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944207226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1944207226
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2777433566
Short name T302
Test name
Test status
Simulation time 469682705 ps
CPU time 4.28 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:50 PM PDT 24
Peak memory 225440 kb
Host smart-040e60c0-3ab5-49da-a19b-87e64c41403b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777433566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2777433566
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1229802482
Short name T711
Test name
Test status
Simulation time 21573382 ps
CPU time 1.09 seconds
Started Jul 25 05:49:15 PM PDT 24
Finished Jul 25 05:49:16 PM PDT 24
Peak memory 217312 kb
Host smart-e61cd04f-2dd8-4797-b051-940ff2bb46d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229802482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1229802482
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1901495877
Short name T635
Test name
Test status
Simulation time 144450745 ps
CPU time 4.4 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:49:21 PM PDT 24
Peak memory 233556 kb
Host smart-ad7ab94c-c284-496b-94fd-8ddb29a67f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901495877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1901495877
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3981782184
Short name T523
Test name
Test status
Simulation time 1147852953 ps
CPU time 6.11 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:23 PM PDT 24
Peak memory 225360 kb
Host smart-ea54e2a1-446e-45ee-8cc1-5a9827936809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981782184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3981782184
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3194099111
Short name T433
Test name
Test status
Simulation time 5814585285 ps
CPU time 18.92 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:37 PM PDT 24
Peak memory 222860 kb
Host smart-4df4b907-13bd-4a2f-8bcc-211a9211dbf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3194099111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3194099111
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4139120364
Short name T1011
Test name
Test status
Simulation time 38790723960 ps
CPU time 377.97 seconds
Started Jul 25 05:49:32 PM PDT 24
Finished Jul 25 05:55:51 PM PDT 24
Peak memory 262952 kb
Host smart-8ba7607e-4693-4b5d-acf0-e07cf1e03bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139120364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4139120364
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3492103242
Short name T641
Test name
Test status
Simulation time 11335728029 ps
CPU time 24.03 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:42 PM PDT 24
Peak memory 217244 kb
Host smart-b98c832e-4955-400e-9163-7a3ea4167d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492103242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3492103242
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3390238140
Short name T329
Test name
Test status
Simulation time 937282099 ps
CPU time 3.24 seconds
Started Jul 25 05:49:16 PM PDT 24
Finished Jul 25 05:49:19 PM PDT 24
Peak memory 217220 kb
Host smart-ec81ff3f-1202-4502-a0dd-19c33067eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390238140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3390238140
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2715383148
Short name T1016
Test name
Test status
Simulation time 269677413 ps
CPU time 5.99 seconds
Started Jul 25 05:49:18 PM PDT 24
Finished Jul 25 05:49:24 PM PDT 24
Peak memory 217224 kb
Host smart-6f281a68-3942-42c2-8281-4dad5ecbd976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715383148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2715383148
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4046034787
Short name T31
Test name
Test status
Simulation time 22013364 ps
CPU time 0.8 seconds
Started Jul 25 05:49:17 PM PDT 24
Finished Jul 25 05:49:18 PM PDT 24
Peak memory 206720 kb
Host smart-82da70cc-839d-4832-81e6-917bf81de173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046034787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4046034787
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3726865906
Short name T758
Test name
Test status
Simulation time 131179181 ps
CPU time 2.68 seconds
Started Jul 25 05:49:20 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 233212 kb
Host smart-927f8d87-e433-434a-96a7-49cdb5547ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726865906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3726865906
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.194898232
Short name T57
Test name
Test status
Simulation time 11878099 ps
CPU time 0.72 seconds
Started Jul 25 05:48:02 PM PDT 24
Finished Jul 25 05:48:02 PM PDT 24
Peak memory 205428 kb
Host smart-60c25bba-f109-40c9-95e7-536e08ab2aab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194898232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.194898232
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4271289945
Short name T644
Test name
Test status
Simulation time 2202065580 ps
CPU time 21.76 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:48:14 PM PDT 24
Peak memory 233760 kb
Host smart-5044c3ea-3869-4f6a-9110-3d6859ca120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271289945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4271289945
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3572354000
Short name T921
Test name
Test status
Simulation time 88704162 ps
CPU time 0.77 seconds
Started Jul 25 05:47:56 PM PDT 24
Finished Jul 25 05:47:57 PM PDT 24
Peak memory 206260 kb
Host smart-e02bf19e-efbd-4687-a551-78de9f69e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572354000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3572354000
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1883673731
Short name T562
Test name
Test status
Simulation time 4472628657 ps
CPU time 73.17 seconds
Started Jul 25 05:48:09 PM PDT 24
Finished Jul 25 05:49:22 PM PDT 24
Peak memory 258244 kb
Host smart-a452c259-0db3-43d7-a254-df385dbdd29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883673731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1883673731
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2540707770
Short name T796
Test name
Test status
Simulation time 39127251249 ps
CPU time 72.19 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:49:16 PM PDT 24
Peak memory 240916 kb
Host smart-f4e37a37-7892-4813-b8b2-8155dabc2af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540707770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2540707770
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.912998079
Short name T897
Test name
Test status
Simulation time 14933650683 ps
CPU time 151.47 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:50:36 PM PDT 24
Peak memory 250256 kb
Host smart-278faae9-a6cb-44d7-8953-b1ae5f2fd618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912998079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
912998079
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.205568758
Short name T263
Test name
Test status
Simulation time 386788991 ps
CPU time 4.57 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:47:58 PM PDT 24
Peak memory 225472 kb
Host smart-23ad2042-206d-4c61-8628-b3cc1e71babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205568758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.205568758
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1627650801
Short name T653
Test name
Test status
Simulation time 27319356907 ps
CPU time 205.76 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:51:39 PM PDT 24
Peak memory 252740 kb
Host smart-4af30076-654b-41fe-94fb-3b9af43ddaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627650801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1627650801
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4160684322
Short name T895
Test name
Test status
Simulation time 560993859 ps
CPU time 5.82 seconds
Started Jul 25 05:47:57 PM PDT 24
Finished Jul 25 05:48:02 PM PDT 24
Peak memory 225400 kb
Host smart-7d4599c3-6abc-4480-ada5-1f02a60c42a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160684322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4160684322
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.289372552
Short name T492
Test name
Test status
Simulation time 2810854316 ps
CPU time 41.24 seconds
Started Jul 25 05:48:01 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 249992 kb
Host smart-4fb54cb4-3d95-4897-b020-1e94e31aeb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289372552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.289372552
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3814344188
Short name T691
Test name
Test status
Simulation time 27085983 ps
CPU time 1.02 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:47:55 PM PDT 24
Peak memory 217376 kb
Host smart-70049061-54ef-41cc-a472-868a72809336
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814344188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3814344188
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.885310937
Short name T958
Test name
Test status
Simulation time 1979412438 ps
CPU time 7.8 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:48:01 PM PDT 24
Peak memory 225444 kb
Host smart-3e9fb761-ad66-4622-8bb9-fefee39bf5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885310937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
885310937
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1857992620
Short name T214
Test name
Test status
Simulation time 2337729416 ps
CPU time 4.84 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:48:00 PM PDT 24
Peak memory 225540 kb
Host smart-fde06e35-7868-459f-bfb3-bada60b68a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857992620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1857992620
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.865142966
Short name T628
Test name
Test status
Simulation time 1094001890 ps
CPU time 10.93 seconds
Started Jul 25 05:48:10 PM PDT 24
Finished Jul 25 05:48:21 PM PDT 24
Peak memory 223396 kb
Host smart-8ceb47b2-5bfd-4ef8-8934-e7eb4417ac13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=865142966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.865142966
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2733979805
Short name T61
Test name
Test status
Simulation time 322549421 ps
CPU time 1.15 seconds
Started Jul 25 05:48:06 PM PDT 24
Finished Jul 25 05:48:07 PM PDT 24
Peak memory 235940 kb
Host smart-f1d44fe3-351a-45c9-847d-6dfe35d4847d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733979805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2733979805
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.522653045
Short name T148
Test name
Test status
Simulation time 141399641 ps
CPU time 1.12 seconds
Started Jul 25 05:48:09 PM PDT 24
Finished Jul 25 05:48:10 PM PDT 24
Peak memory 208440 kb
Host smart-6dcf7c18-52c1-4871-9cc8-7eaceed72af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522653045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.522653045
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3630413725
Short name T389
Test name
Test status
Simulation time 1762616940 ps
CPU time 12.64 seconds
Started Jul 25 05:47:54 PM PDT 24
Finished Jul 25 05:48:07 PM PDT 24
Peak memory 219916 kb
Host smart-3e4bb9ca-035d-454f-b395-ab7e699fb9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630413725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3630413725
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.162448001
Short name T985
Test name
Test status
Simulation time 3222313182 ps
CPU time 7.21 seconds
Started Jul 25 05:47:57 PM PDT 24
Finished Jul 25 05:48:05 PM PDT 24
Peak memory 217236 kb
Host smart-04722ebb-e002-4050-b10d-e56dfc45f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162448001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.162448001
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2828772928
Short name T276
Test name
Test status
Simulation time 678548492 ps
CPU time 4.49 seconds
Started Jul 25 05:47:53 PM PDT 24
Finished Jul 25 05:47:58 PM PDT 24
Peak memory 217136 kb
Host smart-ff847061-2749-4335-8809-21da2d78ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828772928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2828772928
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.292876077
Short name T345
Test name
Test status
Simulation time 24763037 ps
CPU time 0.86 seconds
Started Jul 25 05:47:55 PM PDT 24
Finished Jul 25 05:47:56 PM PDT 24
Peak memory 206780 kb
Host smart-5e6a65c2-a93e-4108-b3a0-deab4c771f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292876077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.292876077
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3143207623
Short name T871
Test name
Test status
Simulation time 14727714291 ps
CPU time 12.91 seconds
Started Jul 25 05:47:51 PM PDT 24
Finished Jul 25 05:48:04 PM PDT 24
Peak memory 241876 kb
Host smart-494cc4bf-2eca-4811-9109-d18ea172233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143207623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3143207623
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1822842861
Short name T441
Test name
Test status
Simulation time 45126555 ps
CPU time 0.73 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:49:27 PM PDT 24
Peak memory 206060 kb
Host smart-664eedcb-8020-4b9a-9456-56458ab4515f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822842861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1822842861
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1744410395
Short name T999
Test name
Test status
Simulation time 7849088479 ps
CPU time 18.6 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:49:44 PM PDT 24
Peak memory 225512 kb
Host smart-0d47202f-4472-46fd-a3a2-81b9de936761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744410395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1744410395
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1445910134
Short name T542
Test name
Test status
Simulation time 27560450 ps
CPU time 0.75 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 206560 kb
Host smart-a2e8b9c3-53ca-48c8-b06e-8308aa60fe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445910134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1445910134
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2912349927
Short name T528
Test name
Test status
Simulation time 18942234199 ps
CPU time 65.6 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 266336 kb
Host smart-ed29710a-1bd6-41e5-a4a3-10d94c72b1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912349927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2912349927
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3264012764
Short name T164
Test name
Test status
Simulation time 21294185492 ps
CPU time 220.63 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:53:05 PM PDT 24
Peak memory 254036 kb
Host smart-f5de67ce-8b3a-47dd-82d2-62b948efe34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264012764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3264012764
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3058075300
Short name T962
Test name
Test status
Simulation time 2595919203 ps
CPU time 29.32 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:54 PM PDT 24
Peak memory 241868 kb
Host smart-5971d3ca-e7e8-4e32-8903-503c32c1a32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058075300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3058075300
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.332778264
Short name T1004
Test name
Test status
Simulation time 9401804382 ps
CPU time 72.13 seconds
Started Jul 25 05:49:29 PM PDT 24
Finished Jul 25 05:50:42 PM PDT 24
Peak memory 241136 kb
Host smart-063101ee-5a64-4761-8c6e-9d4c440064e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332778264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.332778264
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4093618475
Short name T191
Test name
Test status
Simulation time 1450645628 ps
CPU time 12.63 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:37 PM PDT 24
Peak memory 225428 kb
Host smart-fa26d553-2560-4ec0-8da9-0b510edb4b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093618475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4093618475
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2478901298
Short name T308
Test name
Test status
Simulation time 5147235234 ps
CPU time 39.94 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 241672 kb
Host smart-a7ac1b47-1989-44ae-b520-829e40ed3753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478901298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2478901298
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2113445563
Short name T369
Test name
Test status
Simulation time 16017231061 ps
CPU time 13.95 seconds
Started Jul 25 05:49:23 PM PDT 24
Finished Jul 25 05:49:38 PM PDT 24
Peak memory 233656 kb
Host smart-58764351-c751-4242-95c2-456448d5a1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113445563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2113445563
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1457100330
Short name T978
Test name
Test status
Simulation time 258069665 ps
CPU time 2.93 seconds
Started Jul 25 05:49:23 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 225432 kb
Host smart-8726c296-ec3c-4516-b6ff-b8331f3d9a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457100330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1457100330
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2068054895
Short name T581
Test name
Test status
Simulation time 987739843 ps
CPU time 8.69 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:34 PM PDT 24
Peak memory 222952 kb
Host smart-c9afb1d7-7cc8-4ff2-91c8-4e07b99fd40c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2068054895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2068054895
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2288568608
Short name T619
Test name
Test status
Simulation time 226936282829 ps
CPU time 546.88 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:58:33 PM PDT 24
Peak memory 269676 kb
Host smart-4b70e8cf-03fa-4445-8a4b-6b37378a80bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288568608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2288568608
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2867060113
Short name T976
Test name
Test status
Simulation time 9389190598 ps
CPU time 23.79 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 221784 kb
Host smart-ce64b5c3-4e66-4414-9b16-15453f0a2caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867060113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2867060113
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3648209725
Short name T316
Test name
Test status
Simulation time 1474318791 ps
CPU time 4.42 seconds
Started Jul 25 05:49:23 PM PDT 24
Finished Jul 25 05:49:27 PM PDT 24
Peak memory 217188 kb
Host smart-51bfdac6-301e-4e2b-8040-341c3252372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648209725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3648209725
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3988791673
Short name T381
Test name
Test status
Simulation time 18811221 ps
CPU time 0.93 seconds
Started Jul 25 05:49:27 PM PDT 24
Finished Jul 25 05:49:28 PM PDT 24
Peak memory 207792 kb
Host smart-24d97ca9-85ee-4a60-afa4-ec7ae1435bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988791673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3988791673
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2595605358
Short name T658
Test name
Test status
Simulation time 59524750 ps
CPU time 0.72 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 206764 kb
Host smart-05280600-46ce-46d0-bfea-fc0394252e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595605358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2595605358
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1315033532
Short name T406
Test name
Test status
Simulation time 14422572356 ps
CPU time 14.27 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 233668 kb
Host smart-74c65654-ca5d-4b49-8e8f-a68cf569b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315033532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1315033532
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2135894056
Short name T548
Test name
Test status
Simulation time 19051311 ps
CPU time 0.77 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:25 PM PDT 24
Peak memory 206020 kb
Host smart-4db198ba-6e25-4da1-b1b9-8438acc71b6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135894056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2135894056
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2050473770
Short name T124
Test name
Test status
Simulation time 465776071 ps
CPU time 2.52 seconds
Started Jul 25 05:49:33 PM PDT 24
Finished Jul 25 05:49:36 PM PDT 24
Peak memory 225460 kb
Host smart-46eaa5eb-6d4b-4f5c-9bb0-0ccf1efe2bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050473770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2050473770
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.709117292
Short name T349
Test name
Test status
Simulation time 74360260 ps
CPU time 0.76 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 207220 kb
Host smart-da8a7b20-c20a-43e4-aa5c-238705b94d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709117292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.709117292
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.385174272
Short name T599
Test name
Test status
Simulation time 10102698757 ps
CPU time 70.15 seconds
Started Jul 25 05:49:33 PM PDT 24
Finished Jul 25 05:50:43 PM PDT 24
Peak memory 252260 kb
Host smart-fc0fd0e2-a9ac-424f-a4f5-40dc6d128f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385174272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.385174272
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2596164834
Short name T49
Test name
Test status
Simulation time 46732159191 ps
CPU time 119.05 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:51:25 PM PDT 24
Peak memory 256436 kb
Host smart-89bd6dcc-7b01-40ca-994a-ac2e6da3b80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596164834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2596164834
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2690704805
Short name T22
Test name
Test status
Simulation time 24368276786 ps
CPU time 46.62 seconds
Started Jul 25 05:49:30 PM PDT 24
Finished Jul 25 05:50:17 PM PDT 24
Peak memory 251252 kb
Host smart-b32fd2e3-8a70-401a-8856-ba086d45baa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690704805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2690704805
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2281862284
Short name T941
Test name
Test status
Simulation time 14292062024 ps
CPU time 27.6 seconds
Started Jul 25 05:49:28 PM PDT 24
Finished Jul 25 05:49:56 PM PDT 24
Peak memory 238288 kb
Host smart-41e3d566-140f-4faa-8d93-9dc84d409e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281862284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2281862284
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2657010470
Short name T501
Test name
Test status
Simulation time 832676140 ps
CPU time 7.96 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:33 PM PDT 24
Peak memory 233600 kb
Host smart-b562aa04-b86e-4768-b41a-b7c7c5f37291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657010470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2657010470
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3348657364
Short name T534
Test name
Test status
Simulation time 1149074994 ps
CPU time 20.81 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:45 PM PDT 24
Peak memory 233640 kb
Host smart-394320e7-e4a8-4516-824d-42f5c27c1b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348657364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3348657364
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2835530464
Short name T521
Test name
Test status
Simulation time 4875243081 ps
CPU time 14.88 seconds
Started Jul 25 05:49:33 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 233656 kb
Host smart-9af08dc0-683c-404c-a7e0-c501d85c523a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835530464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2835530464
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1053473009
Short name T901
Test name
Test status
Simulation time 2128422663 ps
CPU time 13.97 seconds
Started Jul 25 05:49:27 PM PDT 24
Finished Jul 25 05:49:41 PM PDT 24
Peak memory 233652 kb
Host smart-f5a1ce66-d26f-47b2-86e0-63ee626f6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053473009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1053473009
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3133037766
Short name T697
Test name
Test status
Simulation time 566785489 ps
CPU time 3.41 seconds
Started Jul 25 05:49:30 PM PDT 24
Finished Jul 25 05:49:33 PM PDT 24
Peak memory 223444 kb
Host smart-bc0ca111-10f6-4e83-b14c-75bd6fb98163
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3133037766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3133037766
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1337270948
Short name T520
Test name
Test status
Simulation time 5858120702 ps
CPU time 45.44 seconds
Started Jul 25 05:49:27 PM PDT 24
Finished Jul 25 05:50:13 PM PDT 24
Peak memory 222900 kb
Host smart-279c67f5-940c-49d8-a3da-b9fdd0472680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337270948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1337270948
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1811715685
Short name T1001
Test name
Test status
Simulation time 5030554973 ps
CPU time 21.34 seconds
Started Jul 25 05:49:30 PM PDT 24
Finished Jul 25 05:49:51 PM PDT 24
Peak memory 217256 kb
Host smart-f77b7040-a663-4927-830d-178f1cb9e326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811715685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1811715685
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3102526791
Short name T648
Test name
Test status
Simulation time 2963545075 ps
CPU time 2.81 seconds
Started Jul 25 05:49:23 PM PDT 24
Finished Jul 25 05:49:25 PM PDT 24
Peak memory 217064 kb
Host smart-c2bf6d7b-2665-408f-b873-f2e3623b323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102526791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3102526791
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2584873169
Short name T855
Test name
Test status
Simulation time 224833778 ps
CPU time 3.23 seconds
Started Jul 25 05:49:24 PM PDT 24
Finished Jul 25 05:49:27 PM PDT 24
Peak memory 217128 kb
Host smart-07ab83cd-93b3-47fa-8ae2-7fa2f8292d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584873169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2584873169
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.518832360
Short name T661
Test name
Test status
Simulation time 45388740 ps
CPU time 0.75 seconds
Started Jul 25 05:49:25 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 206756 kb
Host smart-e4eb60e2-61bd-4797-841f-de4204886508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518832360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.518832360
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.4072580061
Short name T879
Test name
Test status
Simulation time 4184209836 ps
CPU time 13.93 seconds
Started Jul 25 05:49:26 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 225512 kb
Host smart-18da5b38-efc3-4cdf-b3ce-036c272f8a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072580061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4072580061
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1103659609
Short name T284
Test name
Test status
Simulation time 31625465 ps
CPU time 0.73 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:36 PM PDT 24
Peak memory 206112 kb
Host smart-cfefa247-6dc3-42b2-89f1-6436830947bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103659609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1103659609
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.4272770785
Short name T902
Test name
Test status
Simulation time 818072380 ps
CPU time 2.43 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:39 PM PDT 24
Peak memory 225372 kb
Host smart-4e8380d1-cfe8-4f60-946c-fb2fe2ac84e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272770785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.4272770785
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.328310168
Short name T416
Test name
Test status
Simulation time 19554685 ps
CPU time 0.79 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:36 PM PDT 24
Peak memory 207240 kb
Host smart-6416708c-e5b3-42c3-b3fd-3d3c2870483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328310168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.328310168
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3962751080
Short name T194
Test name
Test status
Simulation time 63366394673 ps
CPU time 62.98 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:50:38 PM PDT 24
Peak memory 237740 kb
Host smart-81f92006-0d2c-4a3c-8645-3115a5f04e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962751080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3962751080
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.798375319
Short name T365
Test name
Test status
Simulation time 11291340281 ps
CPU time 23.67 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:50:00 PM PDT 24
Peak memory 223364 kb
Host smart-bd2dfc7a-84d4-4a8a-896d-c48dd5ec0bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798375319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.798375319
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.249613737
Short name T514
Test name
Test status
Simulation time 7197973869 ps
CPU time 54.78 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 250164 kb
Host smart-c48e76f3-5bd4-41dd-a492-966cdc4ca042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249613737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.249613737
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2153914905
Short name T304
Test name
Test status
Simulation time 398253121 ps
CPU time 6.03 seconds
Started Jul 25 05:49:39 PM PDT 24
Finished Jul 25 05:49:45 PM PDT 24
Peak memory 241860 kb
Host smart-46334e7b-f168-4920-8f96-87e92ba862f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153914905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2153914905
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3686171168
Short name T85
Test name
Test status
Simulation time 13527942358 ps
CPU time 94.42 seconds
Started Jul 25 05:49:34 PM PDT 24
Finished Jul 25 05:51:09 PM PDT 24
Peak memory 255680 kb
Host smart-e2effee1-f2db-44ee-9883-b6dc39d72810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686171168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3686171168
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1580175630
Short name T728
Test name
Test status
Simulation time 485188480 ps
CPU time 4.27 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:39 PM PDT 24
Peak memory 233616 kb
Host smart-76240129-9ff3-450a-9cf5-1cfd25cdc5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580175630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1580175630
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3750990461
Short name T453
Test name
Test status
Simulation time 218979595 ps
CPU time 1.94 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:38 PM PDT 24
Peak memory 224460 kb
Host smart-44336557-0eed-4815-98c1-9ebde4922051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750990461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3750990461
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1715243642
Short name T964
Test name
Test status
Simulation time 349837179 ps
CPU time 5.2 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:41 PM PDT 24
Peak memory 225384 kb
Host smart-5e034f57-ec4a-4ef3-9109-90b4d4e17ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715243642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1715243642
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2378062893
Short name T277
Test name
Test status
Simulation time 5626159854 ps
CPU time 7.57 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:43 PM PDT 24
Peak memory 225460 kb
Host smart-e40cc02f-58d1-4471-84f3-c47988cdda7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378062893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2378062893
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.367730076
Short name T465
Test name
Test status
Simulation time 1141978170 ps
CPU time 4.84 seconds
Started Jul 25 05:49:34 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 219532 kb
Host smart-eed6ab3a-957e-4f40-8d27-bb7505d3fa22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=367730076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.367730076
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1788728190
Short name T565
Test name
Test status
Simulation time 15572035661 ps
CPU time 84.69 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:51:00 PM PDT 24
Peak memory 256944 kb
Host smart-8a7d1f1b-a446-425f-9250-4ad842e24ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788728190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1788728190
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2539117884
Short name T626
Test name
Test status
Simulation time 7568539759 ps
CPU time 19.3 seconds
Started Jul 25 05:49:38 PM PDT 24
Finished Jul 25 05:49:57 PM PDT 24
Peak memory 217264 kb
Host smart-8d63e000-6994-4549-8765-00ac57159c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539117884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2539117884
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3819361066
Short name T392
Test name
Test status
Simulation time 1996685799 ps
CPU time 4.16 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 217248 kb
Host smart-25e05109-eaf1-4b87-8cbc-0f7810bbad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819361066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3819361066
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1301633017
Short name T507
Test name
Test status
Simulation time 1089405496 ps
CPU time 6.08 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:42 PM PDT 24
Peak memory 217176 kb
Host smart-c83279fe-7099-445e-b7b7-63f1d086edc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301633017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1301633017
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2398923752
Short name T295
Test name
Test status
Simulation time 84901993 ps
CPU time 0.97 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:37 PM PDT 24
Peak memory 207852 kb
Host smart-d14de91c-ad8e-4d63-ae74-a2ad281f1997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398923752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2398923752
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3370441664
Short name T770
Test name
Test status
Simulation time 373995249 ps
CPU time 4.29 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:39 PM PDT 24
Peak memory 233596 kb
Host smart-a54d1043-76b0-4693-a10d-caf992f6f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370441664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3370441664
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1147699993
Short name T489
Test name
Test status
Simulation time 52685213 ps
CPU time 0.74 seconds
Started Jul 25 05:49:48 PM PDT 24
Finished Jul 25 05:49:49 PM PDT 24
Peak memory 206060 kb
Host smart-8e9e6450-982a-4de1-a989-998d23009afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147699993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1147699993
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2397243076
Short name T818
Test name
Test status
Simulation time 34349507 ps
CPU time 2.86 seconds
Started Jul 25 05:49:49 PM PDT 24
Finished Jul 25 05:49:52 PM PDT 24
Peak memory 233684 kb
Host smart-ce0ee172-76b8-48ad-8f22-04c0a542e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397243076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2397243076
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.538104456
Short name T463
Test name
Test status
Simulation time 20261647 ps
CPU time 0.82 seconds
Started Jul 25 05:49:34 PM PDT 24
Finished Jul 25 05:49:35 PM PDT 24
Peak memory 207280 kb
Host smart-95ba30c6-ce31-4e6d-b56d-d01c2bdbfeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538104456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.538104456
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2344683047
Short name T590
Test name
Test status
Simulation time 10372516375 ps
CPU time 70.72 seconds
Started Jul 25 05:49:43 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 255096 kb
Host smart-74597431-1c23-47d7-b4fa-984c8f88ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344683047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2344683047
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.590601456
Short name T450
Test name
Test status
Simulation time 17103365603 ps
CPU time 48.3 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:50:35 PM PDT 24
Peak memory 239560 kb
Host smart-1c3a0612-ebbc-4b4c-9e58-d6c28ce01a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590601456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.590601456
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.853843708
Short name T45
Test name
Test status
Simulation time 3542211831 ps
CPU time 93 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:51:19 PM PDT 24
Peak memory 266616 kb
Host smart-12c8308c-4a1a-4494-97ee-8a42e7d0d6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853843708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.853843708
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1964096288
Short name T262
Test name
Test status
Simulation time 785526065 ps
CPU time 6.16 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:53 PM PDT 24
Peak memory 225396 kb
Host smart-335a0c56-dc40-4031-accf-d1cda691fdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964096288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1964096288
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3209559683
Short name T992
Test name
Test status
Simulation time 6242147604 ps
CPU time 91.36 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:51:18 PM PDT 24
Peak memory 251096 kb
Host smart-17ac997d-4a50-42fb-8f99-81662098356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209559683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3209559683
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.437797964
Short name T836
Test name
Test status
Simulation time 205184344 ps
CPU time 4.47 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 233644 kb
Host smart-e183fdd8-4cd9-4ed6-b11a-72512dd4eefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437797964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.437797964
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.900419704
Short name T829
Test name
Test status
Simulation time 368256749 ps
CPU time 10.33 seconds
Started Jul 25 05:49:37 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 233680 kb
Host smart-017047c3-2b66-4e83-a249-d23c8c00b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900419704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.900419704
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1948866411
Short name T363
Test name
Test status
Simulation time 5798252029 ps
CPU time 4.17 seconds
Started Jul 25 05:49:39 PM PDT 24
Finished Jul 25 05:49:43 PM PDT 24
Peak memory 233660 kb
Host smart-3cbc8e78-8f3f-43df-bb8a-467c219a7e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948866411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1948866411
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.442705966
Short name T983
Test name
Test status
Simulation time 7014951932 ps
CPU time 7.12 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:43 PM PDT 24
Peak memory 225512 kb
Host smart-8a660a74-c2a3-4336-ab09-080ea8beac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442705966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.442705966
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2517949698
Short name T870
Test name
Test status
Simulation time 457227388 ps
CPU time 3.44 seconds
Started Jul 25 05:49:48 PM PDT 24
Finished Jul 25 05:49:52 PM PDT 24
Peak memory 220868 kb
Host smart-ca77c301-49c0-4556-91e2-f13080e258fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2517949698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2517949698
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1781030290
Short name T130
Test name
Test status
Simulation time 54785495354 ps
CPU time 144.1 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:52:11 PM PDT 24
Peak memory 250132 kb
Host smart-399da959-583c-4565-b76d-5e7b0695d5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781030290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1781030290
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1361617427
Short name T153
Test name
Test status
Simulation time 8917971662 ps
CPU time 54.79 seconds
Started Jul 25 05:49:33 PM PDT 24
Finished Jul 25 05:50:28 PM PDT 24
Peak memory 217352 kb
Host smart-0b7e010f-70f7-414b-9f77-832554690fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361617427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1361617427
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.4060596720
Short name T358
Test name
Test status
Simulation time 4694678180 ps
CPU time 13.21 seconds
Started Jul 25 05:49:36 PM PDT 24
Finished Jul 25 05:49:49 PM PDT 24
Peak memory 217288 kb
Host smart-0147a360-01a8-4825-8153-5d279f20fffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060596720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.4060596720
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2637846862
Short name T52
Test name
Test status
Simulation time 36601614 ps
CPU time 1.58 seconds
Started Jul 25 05:49:34 PM PDT 24
Finished Jul 25 05:49:36 PM PDT 24
Peak memory 217168 kb
Host smart-a3e684fb-8500-4fe8-a13b-a77e79a79743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637846862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2637846862
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1748162274
Short name T424
Test name
Test status
Simulation time 224097131 ps
CPU time 0.79 seconds
Started Jul 25 05:49:35 PM PDT 24
Finished Jul 25 05:49:36 PM PDT 24
Peak memory 206808 kb
Host smart-2f4515c8-3558-4818-8ca6-1317bbee17eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748162274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1748162274
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1250444009
Short name T979
Test name
Test status
Simulation time 689052863 ps
CPU time 2.08 seconds
Started Jul 25 05:49:38 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 224964 kb
Host smart-5579ebd9-3f82-4d78-83ae-efc8df5caf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250444009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1250444009
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4135118540
Short name T292
Test name
Test status
Simulation time 24273459 ps
CPU time 0.75 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 206080 kb
Host smart-ab91609b-904d-4599-a5e0-88f95a9a1c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135118540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4135118540
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2375045524
Short name T997
Test name
Test status
Simulation time 3132698918 ps
CPU time 7.72 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:49:53 PM PDT 24
Peak memory 225528 kb
Host smart-dc36e824-1cc6-421d-b421-9bb291ccea16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375045524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2375045524
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2131779866
Short name T281
Test name
Test status
Simulation time 14455838 ps
CPU time 0.74 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:49:45 PM PDT 24
Peak memory 207220 kb
Host smart-305f6f1a-7ec8-4276-878d-c0a5ea6961fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131779866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2131779866
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3963536866
Short name T30
Test name
Test status
Simulation time 23157121 ps
CPU time 0.77 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 216576 kb
Host smart-c7c8d31c-c4a4-4a0d-a82a-da37b10bc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963536866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3963536866
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1337060039
Short name T378
Test name
Test status
Simulation time 14913734331 ps
CPU time 45.53 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 241960 kb
Host smart-cdcdf96f-51b0-4296-a7e2-a9582c1fabe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337060039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1337060039
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3616115590
Short name T240
Test name
Test status
Simulation time 35181458069 ps
CPU time 144.08 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:52:09 PM PDT 24
Peak memory 257412 kb
Host smart-e64b95b2-3a69-4525-8a77-d1b291fe2454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616115590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3616115590
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3068087851
Short name T792
Test name
Test status
Simulation time 1727824277 ps
CPU time 8.52 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:55 PM PDT 24
Peak memory 225432 kb
Host smart-df1e1da4-f45d-46da-a9e8-46103d649b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068087851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3068087851
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2360517858
Short name T862
Test name
Test status
Simulation time 1128811683 ps
CPU time 23.89 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:50:11 PM PDT 24
Peak memory 250812 kb
Host smart-42acc144-e2e8-489f-9fad-586922e69761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360517858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2360517858
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1704045423
Short name T326
Test name
Test status
Simulation time 2393257901 ps
CPU time 6.46 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:53 PM PDT 24
Peak memory 225552 kb
Host smart-3275419a-a867-4ad0-9932-49479fa0ee35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704045423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1704045423
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2296987533
Short name T667
Test name
Test status
Simulation time 117363081 ps
CPU time 3.64 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:49:49 PM PDT 24
Peak memory 225500 kb
Host smart-70633906-ddbe-45ef-afea-135e1cfc66f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296987533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2296987533
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2054859880
Short name T393
Test name
Test status
Simulation time 7189302266 ps
CPU time 18.3 seconds
Started Jul 25 05:49:49 PM PDT 24
Finished Jul 25 05:50:08 PM PDT 24
Peak memory 225508 kb
Host smart-6b43c94e-98f3-40e9-aa42-1d8f6f27dc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054859880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2054859880
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2526628727
Short name T322
Test name
Test status
Simulation time 90663482 ps
CPU time 2.42 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 225448 kb
Host smart-587a8f9c-1dcc-40a6-8eb1-c712cbf72ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526628727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2526628727
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.90006338
Short name T310
Test name
Test status
Simulation time 170753894 ps
CPU time 4.3 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:51 PM PDT 24
Peak memory 221088 kb
Host smart-b93a515c-69b4-4da7-8b76-c99d95d999dd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=90006338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direc
t.90006338
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.327554204
Short name T206
Test name
Test status
Simulation time 32714273150 ps
CPU time 371.03 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:55:57 PM PDT 24
Peak memory 274404 kb
Host smart-552fb3ee-58ae-4956-9144-fd46779b3ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327554204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.327554204
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1596798355
Short name T458
Test name
Test status
Simulation time 890642034 ps
CPU time 9.55 seconds
Started Jul 25 05:49:45 PM PDT 24
Finished Jul 25 05:49:55 PM PDT 24
Peak memory 220680 kb
Host smart-97c20280-3208-47a5-a346-f9805ba68b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596798355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1596798355
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1675276048
Short name T812
Test name
Test status
Simulation time 17436840735 ps
CPU time 17.51 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:50:04 PM PDT 24
Peak memory 217284 kb
Host smart-b21a7381-c815-4be2-9b42-7eeb6b7cddfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675276048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1675276048
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1997849450
Short name T524
Test name
Test status
Simulation time 32835128 ps
CPU time 1.12 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 216888 kb
Host smart-92bc0d75-e0a2-43ae-9e3d-01cf240cca4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997849450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1997849450
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.92581467
Short name T929
Test name
Test status
Simulation time 201768378 ps
CPU time 0.83 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 206752 kb
Host smart-77482afd-2451-4a10-ba4f-fef1c627e8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92581467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.92581467
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2122741989
Short name T694
Test name
Test status
Simulation time 1189907350 ps
CPU time 7.29 seconds
Started Jul 25 05:49:48 PM PDT 24
Finished Jul 25 05:49:56 PM PDT 24
Peak memory 233692 kb
Host smart-980a27ae-10e2-451f-98dc-77c9f67a792c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122741989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2122741989
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4084784674
Short name T387
Test name
Test status
Simulation time 59326435 ps
CPU time 0.73 seconds
Started Jul 25 05:50:06 PM PDT 24
Finished Jul 25 05:50:07 PM PDT 24
Peak memory 205492 kb
Host smart-c10ad875-edae-4802-b876-9724a6901612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084784674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4084784674
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3389895110
Short name T398
Test name
Test status
Simulation time 2360577547 ps
CPU time 13.49 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 234648 kb
Host smart-306f9d38-1938-44f7-8b04-4210c208413b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389895110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3389895110
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2705665333
Short name T596
Test name
Test status
Simulation time 48882151 ps
CPU time 0.78 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 207556 kb
Host smart-e875380d-c180-46a7-ad37-c497d37d02ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705665333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2705665333
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.136543773
Short name T451
Test name
Test status
Simulation time 5689706393 ps
CPU time 12.12 seconds
Started Jul 25 05:50:03 PM PDT 24
Finished Jul 25 05:50:15 PM PDT 24
Peak memory 225528 kb
Host smart-71a3be52-d7f9-4357-9e48-4876f047019b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136543773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.136543773
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1084967728
Short name T690
Test name
Test status
Simulation time 7097096840 ps
CPU time 45.33 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:46 PM PDT 24
Peak memory 225564 kb
Host smart-39dea18f-3be1-46fb-94dd-d31c3481709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084967728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1084967728
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1784610811
Short name T734
Test name
Test status
Simulation time 13154321561 ps
CPU time 95.06 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:51:43 PM PDT 24
Peak memory 266616 kb
Host smart-beab207a-e2ca-4463-82f7-e2d18bda1d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784610811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1784610811
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3914018049
Short name T5
Test name
Test status
Simulation time 108432217 ps
CPU time 2.6 seconds
Started Jul 25 05:49:59 PM PDT 24
Finished Jul 25 05:50:02 PM PDT 24
Peak memory 233604 kb
Host smart-8a1a13f6-d4bd-4c45-aa67-0c083020ff02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914018049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3914018049
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.208093209
Short name T541
Test name
Test status
Simulation time 3969853896 ps
CPU time 23.97 seconds
Started Jul 25 05:50:09 PM PDT 24
Finished Jul 25 05:50:33 PM PDT 24
Peak memory 225536 kb
Host smart-40c86697-9216-41b3-805a-0ef0d8a0d6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208093209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.208093209
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1766563772
Short name T618
Test name
Test status
Simulation time 7128065316 ps
CPU time 19.48 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:20 PM PDT 24
Peak memory 241776 kb
Host smart-887c8572-2fd3-40df-9ce5-d50aab5957d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766563772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1766563772
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3336987584
Short name T418
Test name
Test status
Simulation time 13471533647 ps
CPU time 12.28 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 241524 kb
Host smart-de09b544-fc4f-41ea-ab99-ed19e26a60c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336987584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3336987584
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3270215789
Short name T374
Test name
Test status
Simulation time 9098155076 ps
CPU time 8.75 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:11 PM PDT 24
Peak memory 233588 kb
Host smart-6151ccd1-1253-4808-9261-098f4a419ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270215789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3270215789
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.4134564926
Short name T459
Test name
Test status
Simulation time 773268926 ps
CPU time 11.62 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:11 PM PDT 24
Peak memory 222888 kb
Host smart-342bc1c3-ce9d-4fc9-bcbd-f882544faea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4134564926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.4134564926
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1599633819
Short name T764
Test name
Test status
Simulation time 31171240505 ps
CPU time 135.22 seconds
Started Jul 25 05:50:08 PM PDT 24
Finished Jul 25 05:52:23 PM PDT 24
Peak memory 256176 kb
Host smart-8140b1b5-415a-47dc-895e-7249c0416f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599633819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1599633819
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3278372079
Short name T319
Test name
Test status
Simulation time 53866348 ps
CPU time 0.73 seconds
Started Jul 25 05:49:47 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 206376 kb
Host smart-2a4bdacc-5cc0-42d7-a09a-68359443c33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278372079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3278372079
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.141220544
Short name T722
Test name
Test status
Simulation time 1494374615 ps
CPU time 5.25 seconds
Started Jul 25 05:49:48 PM PDT 24
Finished Jul 25 05:49:54 PM PDT 24
Peak memory 217188 kb
Host smart-0fc8b600-1021-4a41-ac48-856afb8a0535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141220544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.141220544
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.438234701
Short name T69
Test name
Test status
Simulation time 1031039763 ps
CPU time 1.8 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:02 PM PDT 24
Peak memory 217152 kb
Host smart-52efa6e8-e9aa-482d-9f03-3d0498d77925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438234701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.438234701
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1868168326
Short name T676
Test name
Test status
Simulation time 36721680 ps
CPU time 0.89 seconds
Started Jul 25 05:49:46 PM PDT 24
Finished Jul 25 05:49:47 PM PDT 24
Peak memory 206764 kb
Host smart-cc626cfa-6352-43a5-af35-e8d22b29029b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868168326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1868168326
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1643251596
Short name T589
Test name
Test status
Simulation time 14741384940 ps
CPU time 11.42 seconds
Started Jul 25 05:50:03 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 225504 kb
Host smart-270d3793-e76b-4603-8ad6-22d0483e3e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643251596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1643251596
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.611012671
Short name T320
Test name
Test status
Simulation time 15922908 ps
CPU time 0.73 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:01 PM PDT 24
Peak memory 206024 kb
Host smart-8c403a79-8af9-499a-926d-1438f782c798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611012671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.611012671
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3463151581
Short name T735
Test name
Test status
Simulation time 82048023 ps
CPU time 2.98 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:04 PM PDT 24
Peak memory 233632 kb
Host smart-64e0155d-2f6b-4400-9077-9fe17ae034c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463151581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3463151581
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3108680415
Short name T561
Test name
Test status
Simulation time 16229667 ps
CPU time 0.78 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:03 PM PDT 24
Peak memory 207276 kb
Host smart-39ff9e6b-2337-4d28-90d8-ec81f3ba7123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108680415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3108680415
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2317319941
Short name T766
Test name
Test status
Simulation time 33445826693 ps
CPU time 90.33 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 256088 kb
Host smart-497468cd-b161-40f0-b3be-be213987cc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317319941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2317319941
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.252140062
Short name T779
Test name
Test status
Simulation time 168711446784 ps
CPU time 418.11 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:57:00 PM PDT 24
Peak memory 267284 kb
Host smart-bbeccaed-dc0d-4841-a126-979a995dd061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252140062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.252140062
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2457287000
Short name T139
Test name
Test status
Simulation time 324330024 ps
CPU time 5.5 seconds
Started Jul 25 05:50:04 PM PDT 24
Finished Jul 25 05:50:09 PM PDT 24
Peak memory 225456 kb
Host smart-a4c17bf6-2994-4798-afdb-e0cbfafc51da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457287000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2457287000
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1308671483
Short name T592
Test name
Test status
Simulation time 28869907278 ps
CPU time 116.34 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 250076 kb
Host smart-0223948c-f35f-458e-8c04-b33fc076aead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308671483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1308671483
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3120486583
Short name T462
Test name
Test status
Simulation time 3199336052 ps
CPU time 11.63 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:13 PM PDT 24
Peak memory 233660 kb
Host smart-25ddb7c3-ba85-476f-af06-b9f5ffe1f16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120486583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3120486583
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1780760005
Short name T982
Test name
Test status
Simulation time 61697626 ps
CPU time 2.46 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:03 PM PDT 24
Peak memory 233236 kb
Host smart-c8dbc616-760c-493a-9af9-de350f4ca48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780760005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1780760005
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2055875934
Short name T540
Test name
Test status
Simulation time 157503829 ps
CPU time 2.49 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:04 PM PDT 24
Peak memory 233628 kb
Host smart-f78d04ae-3059-4541-8027-159dd2b4c1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055875934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2055875934
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.747529881
Short name T283
Test name
Test status
Simulation time 1033988609 ps
CPU time 10.78 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:12 PM PDT 24
Peak memory 241512 kb
Host smart-1fdbfeff-398e-4725-97b2-c692667ad678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747529881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.747529881
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2730818174
Short name T761
Test name
Test status
Simulation time 2957125698 ps
CPU time 13.97 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 220860 kb
Host smart-3408674b-c683-4288-a84c-16c9d039d240
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2730818174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2730818174
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3897328614
Short name T601
Test name
Test status
Simulation time 9262503872 ps
CPU time 73.89 seconds
Started Jul 25 05:50:04 PM PDT 24
Finished Jul 25 05:51:17 PM PDT 24
Peak memory 253452 kb
Host smart-b6348f49-c4d6-4300-846b-ac5954e521fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897328614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3897328614
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3063079201
Short name T39
Test name
Test status
Simulation time 589958504 ps
CPU time 6.49 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 217224 kb
Host smart-10c408dd-ccc0-43ec-b791-252b40477e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063079201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3063079201
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2594529065
Short name T564
Test name
Test status
Simulation time 624040034 ps
CPU time 4.73 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:50:12 PM PDT 24
Peak memory 217188 kb
Host smart-24abff25-1a6e-4654-9e29-5952b6ed42e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594529065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2594529065
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3478624869
Short name T342
Test name
Test status
Simulation time 16478806 ps
CPU time 0.84 seconds
Started Jul 25 05:50:04 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 207456 kb
Host smart-0dd9bfa9-ce49-471b-8b6c-6719c6af36e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478624869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3478624869
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3292481599
Short name T584
Test name
Test status
Simulation time 152153956 ps
CPU time 0.89 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:02 PM PDT 24
Peak memory 207784 kb
Host smart-af39ed76-161b-4b9d-9691-953f8ed108f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292481599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3292481599
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2427772750
Short name T731
Test name
Test status
Simulation time 125235585 ps
CPU time 2.55 seconds
Started Jul 25 05:50:03 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 225012 kb
Host smart-c3bdeddf-396b-4b18-a7a0-a0dabb59e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427772750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2427772750
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1678429953
Short name T586
Test name
Test status
Simulation time 14375652 ps
CPU time 0.74 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:23 PM PDT 24
Peak memory 206084 kb
Host smart-38e2d4e9-32ba-43f7-bb30-3e63f3a3450d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678429953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1678429953
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1873362139
Short name T954
Test name
Test status
Simulation time 39130567 ps
CPU time 0.77 seconds
Started Jul 25 05:50:10 PM PDT 24
Finished Jul 25 05:50:10 PM PDT 24
Peak memory 207620 kb
Host smart-0ee7ea7e-866d-4796-b94e-9c276a33b832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873362139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1873362139
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3015868223
Short name T752
Test name
Test status
Simulation time 5787580647 ps
CPU time 74.94 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:51:29 PM PDT 24
Peak memory 250132 kb
Host smart-90239a68-42ea-42be-a860-e8b3f2c8409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015868223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3015868223
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3766973298
Short name T642
Test name
Test status
Simulation time 23330333217 ps
CPU time 69.06 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:51:30 PM PDT 24
Peak memory 250340 kb
Host smart-40619b82-3911-45ed-92da-5d9045149e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766973298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3766973298
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2296765064
Short name T776
Test name
Test status
Simulation time 7492806006 ps
CPU time 96.99 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:51:56 PM PDT 24
Peak memory 266468 kb
Host smart-18ca4b09-065f-4c44-904c-bb730c977436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296765064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2296765064
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2563219255
Short name T427
Test name
Test status
Simulation time 118718255 ps
CPU time 5.46 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:50:13 PM PDT 24
Peak memory 225456 kb
Host smart-04c963bf-ab94-4c6c-b70c-da858ce82335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563219255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2563219255
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3818664755
Short name T1014
Test name
Test status
Simulation time 8200381563 ps
CPU time 109.22 seconds
Started Jul 25 05:50:10 PM PDT 24
Finished Jul 25 05:51:59 PM PDT 24
Peak memory 263980 kb
Host smart-f63c8d87-70e2-435c-8df6-27587b02ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818664755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3818664755
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1739234478
Short name T852
Test name
Test status
Simulation time 148164242 ps
CPU time 4.29 seconds
Started Jul 25 05:50:05 PM PDT 24
Finished Jul 25 05:50:09 PM PDT 24
Peak memory 233612 kb
Host smart-d9cdcbd7-f98d-422e-8274-2f01775f3fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739234478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1739234478
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1278114473
Short name T535
Test name
Test status
Simulation time 14219615290 ps
CPU time 36.51 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:39 PM PDT 24
Peak memory 225484 kb
Host smart-87121b09-6fa7-4df8-8223-76d78651b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278114473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1278114473
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4272549679
Short name T957
Test name
Test status
Simulation time 241644379 ps
CPU time 2.06 seconds
Started Jul 25 05:50:08 PM PDT 24
Finished Jul 25 05:50:10 PM PDT 24
Peak memory 223888 kb
Host smart-21ddb291-f067-44ee-a45d-2b1cc417f48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272549679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4272549679
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2368419047
Short name T332
Test name
Test status
Simulation time 80893079703 ps
CPU time 25.4 seconds
Started Jul 25 05:50:00 PM PDT 24
Finished Jul 25 05:50:26 PM PDT 24
Peak memory 249196 kb
Host smart-80e73cab-3ab5-4b43-9e4d-d4e2b8d0b769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368419047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2368419047
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1486454834
Short name T595
Test name
Test status
Simulation time 1992246368 ps
CPU time 17.83 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 222996 kb
Host smart-7f955332-9219-4ee2-82bf-8999a51e9124
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1486454834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1486454834
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3580782073
Short name T649
Test name
Test status
Simulation time 2064452676 ps
CPU time 35.3 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 217228 kb
Host smart-9196ab28-1920-49f9-8fe4-a795619ca12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580782073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3580782073
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3779170958
Short name T683
Test name
Test status
Simulation time 306329934 ps
CPU time 1.04 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:03 PM PDT 24
Peak memory 207924 kb
Host smart-6362f64c-fd33-4e85-8318-25abe3606101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779170958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3779170958
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.318958639
Short name T447
Test name
Test status
Simulation time 1072576685 ps
CPU time 3.53 seconds
Started Jul 25 05:50:01 PM PDT 24
Finished Jul 25 05:50:05 PM PDT 24
Peak memory 217184 kb
Host smart-1499f089-8661-411c-b16d-5c861ae7b764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318958639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.318958639
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3160755647
Short name T864
Test name
Test status
Simulation time 77042584 ps
CPU time 0.97 seconds
Started Jul 25 05:50:07 PM PDT 24
Finished Jul 25 05:50:08 PM PDT 24
Peak memory 206748 kb
Host smart-fbacbfd0-fa8c-4bd9-a21f-2d942e6728fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160755647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3160755647
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2282914378
Short name T622
Test name
Test status
Simulation time 909036794 ps
CPU time 5.9 seconds
Started Jul 25 05:50:02 PM PDT 24
Finished Jul 25 05:50:08 PM PDT 24
Peak memory 228328 kb
Host smart-eb1ae254-1d7f-4952-b137-7de7381aa9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282914378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2282914378
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1099863361
Short name T827
Test name
Test status
Simulation time 19446982 ps
CPU time 0.73 seconds
Started Jul 25 05:50:17 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 206052 kb
Host smart-a8e924e9-b804-485b-a7b0-c7ac428a8852
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099863361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1099863361
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1493397749
Short name T716
Test name
Test status
Simulation time 6625912631 ps
CPU time 8.97 seconds
Started Jul 25 05:50:12 PM PDT 24
Finished Jul 25 05:50:21 PM PDT 24
Peak memory 233692 kb
Host smart-2036e712-da53-405a-8dff-078247120c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493397749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1493397749
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.487463588
Short name T388
Test name
Test status
Simulation time 20505989 ps
CPU time 0.78 seconds
Started Jul 25 05:50:10 PM PDT 24
Finished Jul 25 05:50:11 PM PDT 24
Peak memory 207600 kb
Host smart-32985ce3-08e6-4215-81f3-55082aec1df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487463588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.487463588
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3465848734
Short name T756
Test name
Test status
Simulation time 136455390483 ps
CPU time 253.73 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:54:37 PM PDT 24
Peak memory 250116 kb
Host smart-808a2d6c-babd-4cb7-8fe6-3fe5d3606399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465848734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3465848734
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3390622055
Short name T127
Test name
Test status
Simulation time 96812229339 ps
CPU time 118.98 seconds
Started Jul 25 05:50:11 PM PDT 24
Finished Jul 25 05:52:10 PM PDT 24
Peak memory 269592 kb
Host smart-3a391093-ac6a-4045-bddf-6b96faf36d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390622055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3390622055
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3533522377
Short name T920
Test name
Test status
Simulation time 764784669981 ps
CPU time 359.25 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:56:20 PM PDT 24
Peak memory 252348 kb
Host smart-c4f77490-a581-4b8c-9d43-4154caf3fb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533522377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3533522377
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2455943686
Short name T414
Test name
Test status
Simulation time 2493300643 ps
CPU time 33.08 seconds
Started Jul 25 05:50:17 PM PDT 24
Finished Jul 25 05:50:51 PM PDT 24
Peak memory 250068 kb
Host smart-d674eee6-e3ea-4e65-b869-017b4bca4ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455943686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2455943686
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1939585223
Short name T177
Test name
Test status
Simulation time 5108452532 ps
CPU time 36.63 seconds
Started Jul 25 05:50:15 PM PDT 24
Finished Jul 25 05:50:52 PM PDT 24
Peak memory 240348 kb
Host smart-49eee4c9-f855-41fa-816c-d34f5ecf8c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939585223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1939585223
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1301604304
Short name T651
Test name
Test status
Simulation time 360601873 ps
CPU time 4.19 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:50:21 PM PDT 24
Peak memory 225380 kb
Host smart-a3eda038-c46a-4874-bbf5-6c18279d00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301604304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1301604304
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2488082364
Short name T560
Test name
Test status
Simulation time 516274188 ps
CPU time 3.63 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 241508 kb
Host smart-3fa54142-c36b-4bfd-b491-1cd36ed50bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488082364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2488082364
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4039323932
Short name T636
Test name
Test status
Simulation time 11809382880 ps
CPU time 18.95 seconds
Started Jul 25 05:50:12 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 233640 kb
Host smart-8976acff-837c-4d36-9384-0e98bef6774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039323932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4039323932
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2486181807
Short name T573
Test name
Test status
Simulation time 10092276126 ps
CPU time 10.88 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 233684 kb
Host smart-f724b0d0-1139-4e78-a9c0-7138f270bee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486181807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2486181807
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1975912628
Short name T678
Test name
Test status
Simulation time 3932629340 ps
CPU time 10.07 seconds
Started Jul 25 05:50:12 PM PDT 24
Finished Jul 25 05:50:22 PM PDT 24
Peak memory 223900 kb
Host smart-7c1e1dcb-18ab-4078-89fe-e5c444fab7e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1975912628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1975912628
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.200460277
Short name T886
Test name
Test status
Simulation time 150446572575 ps
CPU time 179.94 seconds
Started Jul 25 05:50:15 PM PDT 24
Finished Jul 25 05:53:15 PM PDT 24
Peak memory 258328 kb
Host smart-74a384c8-5d80-409d-87c4-b91648304dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200460277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.200460277
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3822580370
Short name T301
Test name
Test status
Simulation time 442474464 ps
CPU time 2.29 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:16 PM PDT 24
Peak memory 217216 kb
Host smart-36f7d4b4-01e2-40fc-842e-4d611c601857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822580370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3822580370
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.962320757
Short name T372
Test name
Test status
Simulation time 6692742430 ps
CPU time 5.29 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:19 PM PDT 24
Peak memory 217256 kb
Host smart-7867b10e-a86f-4b06-a285-bee33fc15b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962320757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.962320757
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1978228255
Short name T939
Test name
Test status
Simulation time 2357681966 ps
CPU time 2.91 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:50:19 PM PDT 24
Peak memory 217240 kb
Host smart-fe97010e-ae8b-4434-9ba5-ec8b286bf162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978228255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1978228255
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3376761040
Short name T482
Test name
Test status
Simulation time 234187734 ps
CPU time 1.08 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:50:21 PM PDT 24
Peak memory 207768 kb
Host smart-f0316802-3c01-440f-94cf-7ecd3b9f133b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376761040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3376761040
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.658861568
Short name T157
Test name
Test status
Simulation time 171717282 ps
CPU time 3.24 seconds
Started Jul 25 05:50:17 PM PDT 24
Finished Jul 25 05:50:20 PM PDT 24
Peak memory 225384 kb
Host smart-429f0fcf-8f58-4d73-98a8-91c19990b6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658861568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.658861568
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3554546777
Short name T293
Test name
Test status
Simulation time 14491466 ps
CPU time 0.74 seconds
Started Jul 25 05:50:17 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 206364 kb
Host smart-4c5307a7-f844-4e5f-be30-48751756ab06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554546777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3554546777
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1306969580
Short name T280
Test name
Test status
Simulation time 1325468317 ps
CPU time 14.47 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:28 PM PDT 24
Peak memory 233644 kb
Host smart-33aa2e6d-8c76-4233-be62-f818bc74140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306969580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1306969580
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3156517305
Short name T53
Test name
Test status
Simulation time 33025037 ps
CPU time 0.72 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:50:17 PM PDT 24
Peak memory 206208 kb
Host smart-1477356e-59aa-45b9-a3d1-6057c7cb06bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156517305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3156517305
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1434515413
Short name T817
Test name
Test status
Simulation time 19919706 ps
CPU time 0.78 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 216608 kb
Host smart-045d806b-137c-4330-84c4-52f4515039af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434515413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1434515413
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.747766183
Short name T207
Test name
Test status
Simulation time 23291357989 ps
CPU time 245.81 seconds
Started Jul 25 05:50:17 PM PDT 24
Finished Jul 25 05:54:23 PM PDT 24
Peak memory 258320 kb
Host smart-c6164f8d-6ae0-4d66-a0ff-4d389eb27a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747766183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.747766183
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2938640097
Short name T797
Test name
Test status
Simulation time 12274382869 ps
CPU time 86.05 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 250340 kb
Host smart-3e1f952b-f69f-4cac-8455-9a6b5691cd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938640097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2938640097
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.58597911
Short name T154
Test name
Test status
Simulation time 179439663 ps
CPU time 4.72 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 233636 kb
Host smart-740ccf33-05c3-4b60-9f9c-57bffe4b6ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58597911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.58597911
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3950802126
Short name T415
Test name
Test status
Simulation time 2589295263 ps
CPU time 29.65 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 238728 kb
Host smart-72ba7fa4-2fad-4677-b542-ce8ac54ca3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950802126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3950802126
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.595704207
Short name T425
Test name
Test status
Simulation time 574400059 ps
CPU time 4.88 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 225472 kb
Host smart-4a25428c-f805-4e12-8bb5-6f97460ebc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595704207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.595704207
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3863862413
Short name T848
Test name
Test status
Simulation time 32303888157 ps
CPU time 180.77 seconds
Started Jul 25 05:50:11 PM PDT 24
Finished Jul 25 05:53:12 PM PDT 24
Peak memory 233688 kb
Host smart-1fcf6624-f9f7-46ca-9c5b-5ae75e30328e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863862413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3863862413
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.286106978
Short name T249
Test name
Test status
Simulation time 24466161612 ps
CPU time 15.72 seconds
Started Jul 25 05:50:11 PM PDT 24
Finished Jul 25 05:50:27 PM PDT 24
Peak memory 239660 kb
Host smart-70906f73-c663-47a9-b307-04e3e9a74db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286106978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.286106978
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2039203839
Short name T536
Test name
Test status
Simulation time 2082244498 ps
CPU time 5.51 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:28 PM PDT 24
Peak memory 233696 kb
Host smart-aeb4f311-0c8b-4258-9ded-5cd0bbc162e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039203839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2039203839
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2219497077
Short name T366
Test name
Test status
Simulation time 18623487670 ps
CPU time 9.07 seconds
Started Jul 25 05:50:12 PM PDT 24
Finished Jul 25 05:50:21 PM PDT 24
Peak memory 220024 kb
Host smart-451d1c55-de37-437f-be6c-65dc85180eb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2219497077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2219497077
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2426567990
Short name T617
Test name
Test status
Simulation time 63882334641 ps
CPU time 324.09 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:55:37 PM PDT 24
Peak memory 258004 kb
Host smart-7f512382-b2ff-4754-b15b-a0390f1d79ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426567990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2426567990
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.486160027
Short name T778
Test name
Test status
Simulation time 4644613688 ps
CPU time 13.11 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 217452 kb
Host smart-e81083e5-23fc-461b-af3b-3fa626295a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486160027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.486160027
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1334980643
Short name T996
Test name
Test status
Simulation time 940475032 ps
CPU time 5.34 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:20 PM PDT 24
Peak memory 217216 kb
Host smart-b4853804-05de-4b6f-84db-da5234863e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334980643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1334980643
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.946435437
Short name T830
Test name
Test status
Simulation time 22035785 ps
CPU time 1 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 208560 kb
Host smart-9bf60fda-bb91-4cd7-a0a7-1b050e7d5aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946435437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.946435437
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2512124476
Short name T411
Test name
Test status
Simulation time 191050808 ps
CPU time 0.95 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:16 PM PDT 24
Peak memory 207852 kb
Host smart-ffc3deaf-248b-4002-b161-45a39d3a5c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512124476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2512124476
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.295921948
Short name T917
Test name
Test status
Simulation time 277288028 ps
CPU time 4.41 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 225412 kb
Host smart-b6327f3e-c9cf-4c5e-b648-2b3a8397c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295921948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.295921948
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3311964440
Short name T56
Test name
Test status
Simulation time 20550043 ps
CPU time 0.7 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:08 PM PDT 24
Peak memory 206076 kb
Host smart-171c910b-fdd3-43c5-8af9-5c06a34fe377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311964440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
311964440
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3036149971
Short name T972
Test name
Test status
Simulation time 8057091978 ps
CPU time 14.51 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 233640 kb
Host smart-23555173-6641-4e1d-8913-1090ee677ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036149971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3036149971
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.154452999
Short name T360
Test name
Test status
Simulation time 65379293 ps
CPU time 0.82 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:14 PM PDT 24
Peak memory 207236 kb
Host smart-f1536a58-e8d9-4f11-8d2d-a4dd1a3e235d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154452999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.154452999
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3103482861
Short name T909
Test name
Test status
Simulation time 3162289761 ps
CPU time 25.01 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 235176 kb
Host smart-5024fc2b-3b82-4a68-9912-dae51ca947c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103482861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3103482861
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.286465560
Short name T196
Test name
Test status
Simulation time 4856228510 ps
CPU time 90.7 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:49:35 PM PDT 24
Peak memory 263904 kb
Host smart-5e97ceea-2652-49fa-a489-a9305ee50c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286465560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.286465560
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3206399376
Short name T11
Test name
Test status
Simulation time 15427479796 ps
CPU time 176.22 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:51:00 PM PDT 24
Peak memory 256640 kb
Host smart-08b22423-f72b-4fa0-bdb3-13abb3d2ba38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206399376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3206399376
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3532014017
Short name T538
Test name
Test status
Simulation time 1074271556 ps
CPU time 4.17 seconds
Started Jul 25 05:48:06 PM PDT 24
Finished Jul 25 05:48:10 PM PDT 24
Peak memory 225456 kb
Host smart-ec176a8f-8a5f-4703-acea-ca4977ecc447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532014017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3532014017
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1245204787
Short name T700
Test name
Test status
Simulation time 125808010 ps
CPU time 4.05 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:17 PM PDT 24
Peak memory 234680 kb
Host smart-5e2c06a2-a879-44e0-ae19-e0382789fa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245204787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1245204787
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.452009636
Short name T457
Test name
Test status
Simulation time 2575796153 ps
CPU time 18.42 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:25 PM PDT 24
Peak memory 233708 kb
Host smart-9f848766-e00d-4cec-bd35-51a080ea7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452009636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.452009636
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3478384923
Short name T578
Test name
Test status
Simulation time 1215210632 ps
CPU time 4.46 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:48:09 PM PDT 24
Peak memory 233648 kb
Host smart-4eff2f58-eb49-4f90-a724-62a8441817f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478384923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3478384923
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.85263004
Short name T914
Test name
Test status
Simulation time 35298398 ps
CPU time 1.13 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:48:06 PM PDT 24
Peak memory 217424 kb
Host smart-ed23f019-7b92-4aae-be96-3caa7e749784
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85263004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.85263004
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3425775664
Short name T226
Test name
Test status
Simulation time 7946929123 ps
CPU time 22.07 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:29 PM PDT 24
Peak memory 225448 kb
Host smart-b5b14443-ba89-48a0-a70e-196e170b47e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425775664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3425775664
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.400724707
Short name T629
Test name
Test status
Simulation time 16059116432 ps
CPU time 19.88 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:23 PM PDT 24
Peak memory 233748 kb
Host smart-cd7b9f59-48bf-42dc-b5fb-74a6a3b89ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400724707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.400724707
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2030644217
Short name T710
Test name
Test status
Simulation time 209909440 ps
CPU time 4.21 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:12 PM PDT 24
Peak memory 221520 kb
Host smart-98bc8db2-8be1-47ad-91c6-46672004e93e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2030644217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2030644217
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2079217842
Short name T60
Test name
Test status
Simulation time 88199709 ps
CPU time 1.17 seconds
Started Jul 25 05:48:05 PM PDT 24
Finished Jul 25 05:48:06 PM PDT 24
Peak memory 236964 kb
Host smart-bacfc3dc-3daa-4760-b99e-06083258ac5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079217842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2079217842
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1361023207
Short name T149
Test name
Test status
Simulation time 2179486009 ps
CPU time 44.61 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:48:49 PM PDT 24
Peak memory 236500 kb
Host smart-d934b48b-f43e-4a24-b9e4-81e64bbab750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361023207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1361023207
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2057223191
Short name T268
Test name
Test status
Simulation time 6015749760 ps
CPU time 7.24 seconds
Started Jul 25 05:48:05 PM PDT 24
Finished Jul 25 05:48:12 PM PDT 24
Peak memory 218456 kb
Host smart-73ed1eb9-cba9-4093-a2bc-2cec4f2dde0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057223191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2057223191
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3040093212
Short name T974
Test name
Test status
Simulation time 37200066172 ps
CPU time 24 seconds
Started Jul 25 05:48:08 PM PDT 24
Finished Jul 25 05:48:32 PM PDT 24
Peak memory 217260 kb
Host smart-77952fd7-1b50-40b9-afdd-9c7ebc4e02a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040093212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3040093212
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2506271835
Short name T299
Test name
Test status
Simulation time 38183096 ps
CPU time 0.95 seconds
Started Jul 25 05:48:05 PM PDT 24
Finished Jul 25 05:48:06 PM PDT 24
Peak memory 207724 kb
Host smart-ffeeb7db-570e-40dd-893e-33d6ffefe15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506271835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2506271835
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1028238428
Short name T857
Test name
Test status
Simulation time 576770232 ps
CPU time 0.92 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:04 PM PDT 24
Peak memory 207848 kb
Host smart-72418065-5302-4426-bd54-fde89bcc62b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028238428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1028238428
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.800036838
Short name T495
Test name
Test status
Simulation time 13660371203 ps
CPU time 6.41 seconds
Started Jul 25 05:48:06 PM PDT 24
Finished Jul 25 05:48:13 PM PDT 24
Peak memory 225500 kb
Host smart-01262f71-2a41-45e4-93db-de37bc17823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800036838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.800036838
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3771324208
Short name T726
Test name
Test status
Simulation time 11294467 ps
CPU time 0.76 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:22 PM PDT 24
Peak memory 206032 kb
Host smart-111d5d10-651c-4980-a2b3-ff815aa90653
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771324208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3771324208
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.158626336
Short name T122
Test name
Test status
Simulation time 626379737 ps
CPU time 2.75 seconds
Started Jul 25 05:50:16 PM PDT 24
Finished Jul 25 05:50:18 PM PDT 24
Peak memory 225436 kb
Host smart-95cd0916-143d-465a-b55f-8990475a9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158626336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.158626336
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.527169188
Short name T297
Test name
Test status
Simulation time 44378922 ps
CPU time 0.76 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 207288 kb
Host smart-c7837a60-96bb-4da4-971a-c6469c8e60dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527169188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.527169188
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2708322929
Short name T383
Test name
Test status
Simulation time 4533369623 ps
CPU time 10.2 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:50:29 PM PDT 24
Peak memory 241904 kb
Host smart-4087c7c4-86a7-41b6-835b-a4ca6eb808e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708322929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2708322929
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2171972024
Short name T324
Test name
Test status
Simulation time 9310300820 ps
CPU time 61.28 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:51:23 PM PDT 24
Peak memory 257752 kb
Host smart-5423fa59-4901-46c6-b01d-ce9b9f9c2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171972024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2171972024
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3634949879
Short name T241
Test name
Test status
Simulation time 232387953184 ps
CPU time 305.39 seconds
Started Jul 25 05:50:24 PM PDT 24
Finished Jul 25 05:55:30 PM PDT 24
Peak memory 258160 kb
Host smart-33ed0b27-9728-4828-b16c-946bffb1c76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634949879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3634949879
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1915055938
Short name T9
Test name
Test status
Simulation time 192927514 ps
CPU time 5.12 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:26 PM PDT 24
Peak memory 241896 kb
Host smart-ee5211ee-931c-453e-aa6e-8b8988fda3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915055938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1915055938
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.80505099
Short name T248
Test name
Test status
Simulation time 17703932783 ps
CPU time 12.1 seconds
Started Jul 25 05:50:18 PM PDT 24
Finished Jul 25 05:50:30 PM PDT 24
Peak memory 233692 kb
Host smart-8786de1b-58cc-42c4-85cf-56f660a2b834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80505099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.80505099
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2022709646
Short name T637
Test name
Test status
Simulation time 839537591 ps
CPU time 10.59 seconds
Started Jul 25 05:50:14 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 220680 kb
Host smart-b7782904-4ece-40c8-8079-a3a103dcc900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022709646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2022709646
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3876921773
Short name T557
Test name
Test status
Simulation time 76176098143 ps
CPU time 150.96 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:52:53 PM PDT 24
Peak memory 233736 kb
Host smart-756f6651-b34b-4a24-837c-ae9e2cef7c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876921773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3876921773
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3733091586
Short name T231
Test name
Test status
Simulation time 48038468 ps
CPU time 3.03 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:25 PM PDT 24
Peak memory 233636 kb
Host smart-4ee1f548-a82f-4f38-8d07-2a5a073361ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733091586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3733091586
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3218826663
Short name T327
Test name
Test status
Simulation time 7707385930 ps
CPU time 15.96 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:29 PM PDT 24
Peak memory 225432 kb
Host smart-582cc2ea-ac1a-43cb-86b7-3eccb5b295e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218826663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3218826663
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3916257864
Short name T874
Test name
Test status
Simulation time 2349059238 ps
CPU time 7.24 seconds
Started Jul 25 05:50:23 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 222912 kb
Host smart-490d7ef1-4b93-4c0e-9028-ac212c69ac19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3916257864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3916257864
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.39881698
Short name T429
Test name
Test status
Simulation time 12133797 ps
CPU time 0.76 seconds
Started Jul 25 05:50:12 PM PDT 24
Finished Jul 25 05:50:12 PM PDT 24
Peak memory 206340 kb
Host smart-ba239531-4a27-40c4-8abd-af715e293ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39881698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.39881698
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3851963773
Short name T762
Test name
Test status
Simulation time 2681186574 ps
CPU time 6.02 seconds
Started Jul 25 05:50:11 PM PDT 24
Finished Jul 25 05:50:17 PM PDT 24
Peak memory 217264 kb
Host smart-5e61ff50-ce83-4756-bcd6-d7ffddb05cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851963773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3851963773
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4157837680
Short name T32
Test name
Test status
Simulation time 15936493 ps
CPU time 0.85 seconds
Started Jul 25 05:50:13 PM PDT 24
Finished Jul 25 05:50:14 PM PDT 24
Peak memory 207376 kb
Host smart-4f7e54d4-25b6-49f1-8a01-fe76f1227d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157837680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4157837680
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4267962116
Short name T488
Test name
Test status
Simulation time 36464043 ps
CPU time 0.68 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:23 PM PDT 24
Peak memory 206336 kb
Host smart-df906e98-8b95-4550-8fd8-13acfb6c7ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267962116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4267962116
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2324270714
Short name T904
Test name
Test status
Simulation time 846590892 ps
CPU time 10.18 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:31 PM PDT 24
Peak memory 249964 kb
Host smart-89a5dbb5-286d-4241-8d90-0f20da33d7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324270714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2324270714
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1331705876
Short name T813
Test name
Test status
Simulation time 12972475 ps
CPU time 0.7 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:50:20 PM PDT 24
Peak memory 206400 kb
Host smart-a1359837-c7d9-48d3-b0a5-a12cd6613104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331705876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1331705876
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3000777610
Short name T532
Test name
Test status
Simulation time 35559816 ps
CPU time 2.31 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 233556 kb
Host smart-36829c03-7057-486e-b08e-ca726d0dfc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000777610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3000777610
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3383549935
Short name T785
Test name
Test status
Simulation time 17531048 ps
CPU time 0.82 seconds
Started Jul 25 05:50:27 PM PDT 24
Finished Jul 25 05:50:28 PM PDT 24
Peak memory 207240 kb
Host smart-2507e7d2-a5c4-429b-bace-85f5aba65a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383549935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3383549935
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2252482388
Short name T772
Test name
Test status
Simulation time 12498403713 ps
CPU time 93.37 seconds
Started Jul 25 05:50:25 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 250076 kb
Host smart-ac290b66-6a41-4d73-9d96-c626f3a5966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252482388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2252482388
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2923319854
Short name T163
Test name
Test status
Simulation time 5852357508 ps
CPU time 119.24 seconds
Started Jul 25 05:50:28 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 260384 kb
Host smart-e3987a20-1b2b-47bd-9b73-9ccdf7bd4c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923319854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2923319854
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3939608670
Short name T556
Test name
Test status
Simulation time 973524519 ps
CPU time 5.58 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:50:25 PM PDT 24
Peak memory 225496 kb
Host smart-1801df32-6479-49c5-9416-5dacb0fa2f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939608670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3939608670
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1496272617
Short name T201
Test name
Test status
Simulation time 20632615035 ps
CPU time 93.68 seconds
Started Jul 25 05:50:25 PM PDT 24
Finished Jul 25 05:51:59 PM PDT 24
Peak memory 250092 kb
Host smart-675b9af3-09bf-4d8e-8b53-13d089339919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496272617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1496272617
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.601841966
Short name T405
Test name
Test status
Simulation time 870097191 ps
CPU time 3.39 seconds
Started Jul 25 05:50:23 PM PDT 24
Finished Jul 25 05:50:27 PM PDT 24
Peak memory 225392 kb
Host smart-e3083ad6-b167-4cbd-94c3-742511da6358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601841966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.601841966
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2723609222
Short name T703
Test name
Test status
Simulation time 5645602246 ps
CPU time 20.47 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:50:41 PM PDT 24
Peak memory 233672 kb
Host smart-d27e01a1-4d8f-4320-b3fb-ea3f6a771b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723609222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2723609222
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.893596780
Short name T783
Test name
Test status
Simulation time 1278684389 ps
CPU time 10.69 seconds
Started Jul 25 05:50:23 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 225432 kb
Host smart-4ff5e74c-3776-4dad-9eb7-bad1bf87f60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893596780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.893596780
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3680155661
Short name T990
Test name
Test status
Simulation time 4536950134 ps
CPU time 18.15 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:39 PM PDT 24
Peak memory 235684 kb
Host smart-d0abb009-22a1-444d-9fb1-d8cfa6cab260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680155661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3680155661
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1265110355
Short name T748
Test name
Test status
Simulation time 4765853858 ps
CPU time 7.18 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:30 PM PDT 24
Peak memory 221480 kb
Host smart-420d6805-414d-4e34-960b-f87fecbe5576
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265110355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1265110355
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1987989479
Short name T266
Test name
Test status
Simulation time 27498253632 ps
CPU time 33.98 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:50:53 PM PDT 24
Peak memory 217244 kb
Host smart-18132b04-ea11-4e95-9079-a89cbb0b1673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987989479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1987989479
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2617715121
Short name T426
Test name
Test status
Simulation time 290227375 ps
CPU time 1.64 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 208708 kb
Host smart-9749ea75-b869-438e-ab91-03aad56f233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617715121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2617715121
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2157497866
Short name T922
Test name
Test status
Simulation time 735350283 ps
CPU time 4.19 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 217144 kb
Host smart-a229faa3-e7f8-4eca-850b-02ba8e156db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157497866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2157497866
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.648448605
Short name T290
Test name
Test status
Simulation time 154457683 ps
CPU time 0.91 seconds
Started Jul 25 05:50:20 PM PDT 24
Finished Jul 25 05:50:21 PM PDT 24
Peak memory 206788 kb
Host smart-ae08e0eb-324c-4189-8faa-62100fe53ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648448605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.648448605
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1720813160
Short name T480
Test name
Test status
Simulation time 9039050639 ps
CPU time 28.92 seconds
Started Jul 25 05:50:21 PM PDT 24
Finished Jul 25 05:50:50 PM PDT 24
Peak memory 225460 kb
Host smart-8c15754a-e51f-48a0-9f74-198949e8ceaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720813160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1720813160
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3019052854
Short name T721
Test name
Test status
Simulation time 15272120 ps
CPU time 0.73 seconds
Started Jul 25 05:50:34 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 205428 kb
Host smart-a4bf2f47-16f5-44a7-9d94-1d5aa315707f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019052854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3019052854
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1368427835
Short name T866
Test name
Test status
Simulation time 1979944023 ps
CPU time 3.98 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:27 PM PDT 24
Peak memory 225460 kb
Host smart-b2a2e427-ec7f-43e4-90f6-5b091b5b9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368427835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1368427835
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.797543177
Short name T627
Test name
Test status
Simulation time 29318512 ps
CPU time 0.81 seconds
Started Jul 25 05:50:27 PM PDT 24
Finished Jul 25 05:50:28 PM PDT 24
Peak memory 207244 kb
Host smart-285edae4-a929-4284-a099-4841e31e5da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797543177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.797543177
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.259858273
Short name T890
Test name
Test status
Simulation time 180452788946 ps
CPU time 113.06 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:52:26 PM PDT 24
Peak memory 253184 kb
Host smart-2b2c453f-fbd7-47d2-9451-807d442f8bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259858273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.259858273
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1761380975
Short name T200
Test name
Test status
Simulation time 37287766895 ps
CPU time 380.19 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:56:52 PM PDT 24
Peak memory 262324 kb
Host smart-d26ce7d3-d8a0-45c0-8fb3-d64681e7a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761380975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1761380975
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.537139697
Short name T84
Test name
Test status
Simulation time 5597059006 ps
CPU time 34.77 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 238420 kb
Host smart-8edd26a9-ce95-42b5-9591-1b8084bd22f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537139697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.537139697
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4149918244
Short name T356
Test name
Test status
Simulation time 2189707059 ps
CPU time 21.43 seconds
Started Jul 25 05:50:24 PM PDT 24
Finished Jul 25 05:50:45 PM PDT 24
Peak memory 225492 kb
Host smart-bd67b5ff-00ff-4573-9bf7-7fad84afb671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149918244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4149918244
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2226727546
Short name T217
Test name
Test status
Simulation time 13100498011 ps
CPU time 25.07 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:48 PM PDT 24
Peak memory 241692 kb
Host smart-448c653f-2957-42f8-bf1f-5704bd8b60fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226727546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2226727546
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4231531625
Short name T926
Test name
Test status
Simulation time 2025906907 ps
CPU time 7.74 seconds
Started Jul 25 05:50:25 PM PDT 24
Finished Jul 25 05:50:33 PM PDT 24
Peak memory 225356 kb
Host smart-a258192d-908f-4ed0-b35a-a9b6a1d0e03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231531625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4231531625
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2697652357
Short name T333
Test name
Test status
Simulation time 4238572185 ps
CPU time 9 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:32 PM PDT 24
Peak memory 241872 kb
Host smart-b4975ee1-1531-4876-9031-2baf69e67d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697652357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2697652357
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4127406919
Short name T1023
Test name
Test status
Simulation time 844073861 ps
CPU time 4.32 seconds
Started Jul 25 05:50:25 PM PDT 24
Finished Jul 25 05:50:29 PM PDT 24
Peak memory 219884 kb
Host smart-9d813e0b-f31d-44ee-b669-2972d9460812
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4127406919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4127406919
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.391672005
Short name T591
Test name
Test status
Simulation time 224804742 ps
CPU time 0.98 seconds
Started Jul 25 05:50:36 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 206304 kb
Host smart-1f3e75ff-fb24-4696-87d5-651cc489ad00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391672005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.391672005
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1483498257
Short name T998
Test name
Test status
Simulation time 34082539733 ps
CPU time 36.97 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:59 PM PDT 24
Peak memory 217260 kb
Host smart-bc85622e-6b2e-47dd-ab6c-55f094068308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483498257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1483498257
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3683846444
Short name T868
Test name
Test status
Simulation time 30328190 ps
CPU time 0.72 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:23 PM PDT 24
Peak memory 206392 kb
Host smart-f96f0f6a-dac5-4dbe-bea4-3617cf681de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683846444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3683846444
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1133147618
Short name T47
Test name
Test status
Simulation time 307336242 ps
CPU time 4.06 seconds
Started Jul 25 05:50:19 PM PDT 24
Finished Jul 25 05:50:23 PM PDT 24
Peak memory 217216 kb
Host smart-9a84e386-fdfb-4847-b8b0-17bb6eda1da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133147618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1133147618
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.262796259
Short name T746
Test name
Test status
Simulation time 365603329 ps
CPU time 0.98 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 206756 kb
Host smart-8edee658-6538-4739-8ca0-36e601a14f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262796259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.262796259
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.912361119
Short name T763
Test name
Test status
Simulation time 276974887 ps
CPU time 2.67 seconds
Started Jul 25 05:50:22 PM PDT 24
Finished Jul 25 05:50:25 PM PDT 24
Peak memory 233660 kb
Host smart-0144a335-e582-4618-af8d-0edf7fe7287c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912361119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.912361119
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2109923188
Short name T934
Test name
Test status
Simulation time 18098984 ps
CPU time 0.72 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:50:33 PM PDT 24
Peak memory 206100 kb
Host smart-ac230fe3-b699-4bcf-9c0a-772871ab03d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109923188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2109923188
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.4076258041
Short name T865
Test name
Test status
Simulation time 151682005 ps
CPU time 3.39 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:50:36 PM PDT 24
Peak memory 225412 kb
Host smart-535d4b95-9101-4adb-bbdb-f7c213c8d69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076258041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.4076258041
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2008875698
Short name T795
Test name
Test status
Simulation time 15703288 ps
CPU time 0.77 seconds
Started Jul 25 05:50:35 PM PDT 24
Finished Jul 25 05:50:36 PM PDT 24
Peak memory 207288 kb
Host smart-497ca0d2-e71e-4c7e-b05f-706e218b14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008875698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2008875698
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.4157297237
Short name T197
Test name
Test status
Simulation time 1864550407 ps
CPU time 20.75 seconds
Started Jul 25 05:50:34 PM PDT 24
Finished Jul 25 05:50:55 PM PDT 24
Peak memory 233636 kb
Host smart-cfee4493-c1fd-435c-bc62-8cfda6cb14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157297237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.4157297237
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2091173887
Short name T46
Test name
Test status
Simulation time 95039252345 ps
CPU time 636.33 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 06:01:09 PM PDT 24
Peak memory 265828 kb
Host smart-d0b6c890-8cfe-4726-bc36-3c6cffa8acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091173887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2091173887
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1205978365
Short name T675
Test name
Test status
Simulation time 115489611122 ps
CPU time 279.58 seconds
Started Jul 25 05:50:36 PM PDT 24
Finished Jul 25 05:55:15 PM PDT 24
Peak memory 250168 kb
Host smart-23857236-c4a1-4a74-8d70-78991afe80e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205978365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1205978365
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1617248286
Short name T968
Test name
Test status
Simulation time 13766156869 ps
CPU time 23.11 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:50:55 PM PDT 24
Peak memory 239400 kb
Host smart-45f12161-f66a-4aa6-9498-2cbdecf40ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617248286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1617248286
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3591366912
Short name T82
Test name
Test status
Simulation time 23655147203 ps
CPU time 33.43 seconds
Started Jul 25 05:50:33 PM PDT 24
Finished Jul 25 05:51:06 PM PDT 24
Peak memory 254864 kb
Host smart-f506c41b-5367-46f9-bad9-b6edaecfd28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591366912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3591366912
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.831970515
Short name T605
Test name
Test status
Simulation time 111037558 ps
CPU time 2.15 seconds
Started Jul 25 05:50:35 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 233264 kb
Host smart-fcc6987c-603f-4fab-8815-387aae988088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831970515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.831970515
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.307751428
Short name T912
Test name
Test status
Simulation time 2187993300 ps
CPU time 41.32 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:51:13 PM PDT 24
Peak memory 234704 kb
Host smart-ff0012ab-281c-4c56-8b5a-740b1abfae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307751428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.307751428
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2536537331
Short name T889
Test name
Test status
Simulation time 121447051 ps
CPU time 2.5 seconds
Started Jul 25 05:50:36 PM PDT 24
Finished Jul 25 05:50:39 PM PDT 24
Peak memory 225424 kb
Host smart-0a048cd4-078b-4000-8bf9-fb1ade4f5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536537331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2536537331
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.403474113
Short name T580
Test name
Test status
Simulation time 5714896207 ps
CPU time 19.22 seconds
Started Jul 25 05:50:35 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 240700 kb
Host smart-7d21287d-56f1-41d9-b825-c8038e0b88e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403474113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.403474113
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1723673609
Short name T980
Test name
Test status
Simulation time 328400406 ps
CPU time 4.07 seconds
Started Jul 25 05:50:34 PM PDT 24
Finished Jul 25 05:50:38 PM PDT 24
Peak memory 223840 kb
Host smart-43e7155d-cd37-4f16-bb48-8529f4f17c55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1723673609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1723673609
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1012518624
Short name T825
Test name
Test status
Simulation time 76289338205 ps
CPU time 176.61 seconds
Started Jul 25 05:50:31 PM PDT 24
Finished Jul 25 05:53:28 PM PDT 24
Peak memory 257980 kb
Host smart-45c16c3e-e16f-415c-815a-88790634629b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012518624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1012518624
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4003831829
Short name T443
Test name
Test status
Simulation time 125605283 ps
CPU time 1.82 seconds
Started Jul 25 05:50:32 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 217220 kb
Host smart-6ef0eb57-c227-4e04-be33-c27b809d5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003831829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4003831829
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4044462119
Short name T611
Test name
Test status
Simulation time 33088022 ps
CPU time 0.95 seconds
Started Jul 25 05:50:31 PM PDT 24
Finished Jul 25 05:50:32 PM PDT 24
Peak memory 206888 kb
Host smart-2c36ceaf-87df-4a33-8d4b-9b0420567670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044462119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4044462119
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2603693752
Short name T338
Test name
Test status
Simulation time 187979087 ps
CPU time 1.52 seconds
Started Jul 25 05:50:35 PM PDT 24
Finished Jul 25 05:50:37 PM PDT 24
Peak memory 217176 kb
Host smart-0ed07167-95f4-414a-8aec-373893fe83ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603693752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2603693752
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3962102559
Short name T781
Test name
Test status
Simulation time 12998862 ps
CPU time 0.67 seconds
Started Jul 25 05:50:33 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 206232 kb
Host smart-774211a4-fb5f-4f3b-b333-f6cc1b3cf867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962102559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3962102559
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2944273276
Short name T686
Test name
Test status
Simulation time 1092334821 ps
CPU time 6.73 seconds
Started Jul 25 05:50:31 PM PDT 24
Finished Jul 25 05:50:38 PM PDT 24
Peak memory 257572 kb
Host smart-e53fc694-f38e-4674-9d2c-53fb62de61e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944273276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2944273276
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.641570780
Short name T995
Test name
Test status
Simulation time 40589240 ps
CPU time 0.72 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 206376 kb
Host smart-4d897bae-5066-434f-a8c8-8e3d102ea75d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641570780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.641570780
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.568003324
Short name T597
Test name
Test status
Simulation time 7163936428 ps
CPU time 18.2 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:51:01 PM PDT 24
Peak memory 233664 kb
Host smart-f0042a33-601c-46f3-b375-70ebdab68b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568003324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.568003324
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.438150284
Short name T981
Test name
Test status
Simulation time 43006397 ps
CPU time 0.75 seconds
Started Jul 25 05:50:42 PM PDT 24
Finished Jul 25 05:50:43 PM PDT 24
Peak memory 207280 kb
Host smart-10543985-ca4d-4eec-834d-7d13263adda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438150284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.438150284
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2348553137
Short name T942
Test name
Test status
Simulation time 10954191365 ps
CPU time 10.15 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 225484 kb
Host smart-ba43816e-aed0-4241-b2bd-ce0ab58ff795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348553137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2348553137
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2056428008
Short name T718
Test name
Test status
Simulation time 3938931696 ps
CPU time 93.22 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:52:17 PM PDT 24
Peak memory 268496 kb
Host smart-c207dcf8-2263-45a3-be5f-57910000e369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056428008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2056428008
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2651528815
Short name T851
Test name
Test status
Simulation time 4475098879 ps
CPU time 29.73 seconds
Started Jul 25 05:50:45 PM PDT 24
Finished Jul 25 05:51:15 PM PDT 24
Peak memory 233768 kb
Host smart-70debc07-0bb1-4e64-82c2-bbd28e3ac130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651528815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2651528815
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3695138361
Short name T259
Test name
Test status
Simulation time 2053425579 ps
CPU time 35.49 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 233600 kb
Host smart-fafc26ff-86f2-4c47-8952-1cc8431ea21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695138361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3695138361
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3311288063
Short name T849
Test name
Test status
Simulation time 140375494106 ps
CPU time 249.06 seconds
Started Jul 25 05:50:45 PM PDT 24
Finished Jul 25 05:54:54 PM PDT 24
Peak memory 264668 kb
Host smart-ea815c4d-39a9-48d9-958a-ac5b316037c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311288063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3311288063
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1055855709
Short name T885
Test name
Test status
Simulation time 370244587 ps
CPU time 6.69 seconds
Started Jul 25 05:50:46 PM PDT 24
Finished Jul 25 05:50:53 PM PDT 24
Peak memory 225420 kb
Host smart-00801303-9821-4939-9d15-0e4a5a8f5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055855709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1055855709
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1267525110
Short name T839
Test name
Test status
Simulation time 4476648959 ps
CPU time 12.75 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 241704 kb
Host smart-58d778e4-3921-4946-807c-5cf68793818b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267525110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1267525110
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2345469113
Short name T777
Test name
Test status
Simulation time 3639783296 ps
CPU time 4.07 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:48 PM PDT 24
Peak memory 225476 kb
Host smart-b0fbe0cd-f32b-4004-b337-b8cf7166c6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345469113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2345469113
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1807543147
Short name T233
Test name
Test status
Simulation time 566688621 ps
CPU time 3.41 seconds
Started Jul 25 05:50:41 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 225328 kb
Host smart-88ea2a0a-6888-457c-8875-e4916fda73c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807543147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1807543147
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1314614561
Short name T337
Test name
Test status
Simulation time 1224981246 ps
CPU time 5.48 seconds
Started Jul 25 05:50:46 PM PDT 24
Finished Jul 25 05:50:52 PM PDT 24
Peak memory 221120 kb
Host smart-89ff885f-79a3-4282-b5f8-0e7c5ab3533a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1314614561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1314614561
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.3911347672
Short name T20
Test name
Test status
Simulation time 6558284962 ps
CPU time 156.2 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:53:21 PM PDT 24
Peak memory 266560 kb
Host smart-dd7aa818-0f56-4415-9455-8d74b684349c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911347672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.3911347672
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1518023411
Short name T403
Test name
Test status
Simulation time 1670745158 ps
CPU time 18.38 seconds
Started Jul 25 05:50:46 PM PDT 24
Finished Jul 25 05:51:04 PM PDT 24
Peak memory 217172 kb
Host smart-d0a766a5-fabc-445b-9c83-263e40f5f1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518023411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1518023411
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1995820220
Short name T347
Test name
Test status
Simulation time 1936291788 ps
CPU time 8.35 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:53 PM PDT 24
Peak memory 217088 kb
Host smart-0a62685b-f049-45d7-9eba-4cf47bfe5d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995820220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1995820220
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4084383724
Short name T963
Test name
Test status
Simulation time 42844952 ps
CPU time 1.55 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:45 PM PDT 24
Peak memory 217128 kb
Host smart-a859c07a-b311-4492-901a-f71c0c244fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084383724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4084383724
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1683854938
Short name T840
Test name
Test status
Simulation time 109102163 ps
CPU time 0.8 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 206768 kb
Host smart-ce402318-76a4-4aaa-8651-cf93500c6c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683854938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1683854938
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1656123654
Short name T509
Test name
Test status
Simulation time 8813898970 ps
CPU time 9.15 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:53 PM PDT 24
Peak memory 241840 kb
Host smart-109c110f-18c4-4d1c-bf39-2588d116c2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656123654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1656123654
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2089492735
Short name T1024
Test name
Test status
Simulation time 14351580 ps
CPU time 0.73 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 205476 kb
Host smart-adbca64e-8af1-4050-8a5e-7c08fd0d3df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089492735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2089492735
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2516783804
Short name T331
Test name
Test status
Simulation time 100630546 ps
CPU time 3.84 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:48 PM PDT 24
Peak memory 233684 kb
Host smart-40c50b5e-2cde-4b74-a178-9b0dc2beaaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516783804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2516783804
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1010402514
Short name T774
Test name
Test status
Simulation time 19097341 ps
CPU time 0.8 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 207232 kb
Host smart-6f94b480-0086-45ce-bdb9-42bba2b0c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010402514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1010402514
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.162559044
Short name T682
Test name
Test status
Simulation time 66039388725 ps
CPU time 131.12 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:53:07 PM PDT 24
Peak memory 252596 kb
Host smart-c1e3cc32-b1a0-48da-8836-0656f75db48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162559044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.162559044
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1484844520
Short name T907
Test name
Test status
Simulation time 17030832683 ps
CPU time 177.13 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:53:54 PM PDT 24
Peak memory 258272 kb
Host smart-14c54d34-76af-4402-a384-7171a53616c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484844520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1484844520
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4231655932
Short name T288
Test name
Test status
Simulation time 1750173107 ps
CPU time 30.86 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:27 PM PDT 24
Peak memory 233636 kb
Host smart-697ec441-b594-4772-91e2-49ae051dacf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231655932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4231655932
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1697359358
Short name T753
Test name
Test status
Simulation time 60066829783 ps
CPU time 149.56 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:53:24 PM PDT 24
Peak memory 255772 kb
Host smart-8fdda348-e9f0-4a1a-b2be-efe589575b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697359358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1697359358
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3774765820
Short name T83
Test name
Test status
Simulation time 210761447 ps
CPU time 5.79 seconds
Started Jul 25 05:57:48 PM PDT 24
Finished Jul 25 05:57:54 PM PDT 24
Peak memory 231512 kb
Host smart-a85db671-03d1-45b9-bafc-a7bd00cd2cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774765820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3774765820
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3699947897
Short name T379
Test name
Test status
Simulation time 202656888 ps
CPU time 2.8 seconds
Started Jul 25 05:50:42 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 225432 kb
Host smart-fffef227-5df1-4075-a4c8-45122e355249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699947897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3699947897
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2827591873
Short name T887
Test name
Test status
Simulation time 30038266728 ps
CPU time 22.42 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:51:06 PM PDT 24
Peak memory 238820 kb
Host smart-da4c3ad3-aa18-4e4e-ae0e-16a61ee77f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827591873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2827591873
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.404135756
Short name T944
Test name
Test status
Simulation time 132958259 ps
CPU time 2.75 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:45 PM PDT 24
Peak memory 233584 kb
Host smart-9127d089-da7a-4656-965a-f27e7f622cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404135756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.404135756
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3856338684
Short name T473
Test name
Test status
Simulation time 72275339 ps
CPU time 3.75 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:50:58 PM PDT 24
Peak memory 223448 kb
Host smart-01bcc28b-a2bc-4cc7-9ae9-ee11f9794842
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3856338684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3856338684
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.345393053
Short name T150
Test name
Test status
Simulation time 9008597201 ps
CPU time 59.9 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:51:54 PM PDT 24
Peak memory 225600 kb
Host smart-14e137cf-7335-4cae-a6c4-0463ac804ae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345393053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.345393053
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2354530771
Short name T272
Test name
Test status
Simulation time 1523721823 ps
CPU time 14.59 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 217172 kb
Host smart-0ed2e2d4-9dfa-42d1-85a9-75950c584e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354530771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2354530771
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.316276463
Short name T771
Test name
Test status
Simulation time 20283028003 ps
CPU time 11.78 seconds
Started Jul 25 05:50:44 PM PDT 24
Finished Jul 25 05:50:56 PM PDT 24
Peak memory 218400 kb
Host smart-14c85606-349a-46e7-b41c-8679f7fdd8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316276463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.316276463
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.891744272
Short name T287
Test name
Test status
Simulation time 73737813 ps
CPU time 0.88 seconds
Started Jul 25 05:50:41 PM PDT 24
Finished Jul 25 05:50:42 PM PDT 24
Peak memory 207940 kb
Host smart-8a5e87b6-59ed-4c34-94a7-2ff51147239e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891744272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.891744272
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1512954998
Short name T350
Test name
Test status
Simulation time 134474274 ps
CPU time 0.79 seconds
Started Jul 25 05:50:45 PM PDT 24
Finished Jul 25 05:50:46 PM PDT 24
Peak memory 206808 kb
Host smart-9eed11cd-d8ae-4aef-981f-04cb1552d70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512954998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1512954998
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2808456232
Short name T730
Test name
Test status
Simulation time 280903899 ps
CPU time 2.99 seconds
Started Jul 25 05:50:43 PM PDT 24
Finished Jul 25 05:50:46 PM PDT 24
Peak memory 233720 kb
Host smart-da80ad73-c6a8-4341-a205-39a20d791441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808456232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2808456232
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.766320332
Short name T306
Test name
Test status
Simulation time 105799816 ps
CPU time 0.73 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 205512 kb
Host smart-3f3dee00-e24a-4f22-991a-16adb92e8789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766320332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.766320332
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3036005167
Short name T531
Test name
Test status
Simulation time 137829755 ps
CPU time 2.26 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 225424 kb
Host smart-ae05b881-c55f-4b91-ad31-75ac8691ace9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036005167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3036005167
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1966160812
Short name T298
Test name
Test status
Simulation time 15616385 ps
CPU time 0.8 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:50:55 PM PDT 24
Peak memory 206276 kb
Host smart-6ab1b716-da3d-442c-89b1-628a7820f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966160812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1966160812
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.921497743
Short name T663
Test name
Test status
Simulation time 19454841786 ps
CPU time 157.96 seconds
Started Jul 25 05:50:53 PM PDT 24
Finished Jul 25 05:53:31 PM PDT 24
Peak memory 250216 kb
Host smart-65b7fe75-c854-48e7-a219-8c5a4c83b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921497743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.921497743
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3819498980
Short name T1018
Test name
Test status
Simulation time 12857331673 ps
CPU time 94.31 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:52:31 PM PDT 24
Peak memory 264572 kb
Host smart-6f82f24f-6332-4d7b-aa27-6aea670bd55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819498980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3819498980
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3370768040
Short name T802
Test name
Test status
Simulation time 56614655284 ps
CPU time 138.07 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 254044 kb
Host smart-fce3b608-9d60-4722-b8e7-319927c50334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370768040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3370768040
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2826103838
Short name T737
Test name
Test status
Simulation time 12188370787 ps
CPU time 31.11 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:27 PM PDT 24
Peak memory 238700 kb
Host smart-ca723d6e-25b8-429f-9a4f-34ee1253d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826103838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2826103838
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2682956345
Short name T318
Test name
Test status
Simulation time 1610495779 ps
CPU time 7.12 seconds
Started Jul 25 05:50:52 PM PDT 24
Finished Jul 25 05:50:59 PM PDT 24
Peak memory 233592 kb
Host smart-e44e6a08-a5e2-4974-930a-fac1f46a4af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682956345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2682956345
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1819136200
Short name T396
Test name
Test status
Simulation time 4091591938 ps
CPU time 8.8 seconds
Started Jul 25 05:50:53 PM PDT 24
Finished Jul 25 05:51:02 PM PDT 24
Peak memory 225536 kb
Host smart-97c66845-8f6b-459f-8f9b-cbae1603c87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819136200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1819136200
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2032296058
Short name T908
Test name
Test status
Simulation time 13644312748 ps
CPU time 7.31 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:51:02 PM PDT 24
Peak memory 225456 kb
Host smart-5e0e9bd8-b565-408e-8fcc-583f06b0c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032296058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2032296058
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2217783866
Short name T478
Test name
Test status
Simulation time 1089103272 ps
CPU time 6.45 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:51:00 PM PDT 24
Peak memory 233572 kb
Host smart-64b25f73-84ba-43c6-b4b0-146f9063254a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217783866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2217783866
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3934168360
Short name T460
Test name
Test status
Simulation time 2440717646 ps
CPU time 13.87 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:10 PM PDT 24
Peak memory 222604 kb
Host smart-2ef83090-75df-452b-b39f-4a607cee20a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3934168360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3934168360
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.317545580
Short name T477
Test name
Test status
Simulation time 19184164606 ps
CPU time 218.99 seconds
Started Jul 25 05:50:58 PM PDT 24
Finished Jul 25 05:54:37 PM PDT 24
Peak memory 267648 kb
Host smart-d4ed4d9e-bda5-424d-ab26-17de61f08ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317545580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.317545580
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.721106827
Short name T265
Test name
Test status
Simulation time 1735013532 ps
CPU time 14.68 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:11 PM PDT 24
Peak memory 217372 kb
Host smart-4e0f1ae5-ee40-4e59-af03-9ae9e594d922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721106827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.721106827
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1647575684
Short name T448
Test name
Test status
Simulation time 383604976 ps
CPU time 2.94 seconds
Started Jul 25 05:50:53 PM PDT 24
Finished Jul 25 05:50:56 PM PDT 24
Peak memory 217212 kb
Host smart-254e1980-2db0-4cdb-8ab1-f3e0bd6fed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647575684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1647575684
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2396727086
Short name T413
Test name
Test status
Simulation time 20111058 ps
CPU time 0.92 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 208044 kb
Host smart-87f43d40-41d8-4665-86bd-c86fe442fb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396727086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2396727086
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.589211600
Short name T530
Test name
Test status
Simulation time 189348865 ps
CPU time 0.84 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:50:56 PM PDT 24
Peak memory 206816 kb
Host smart-afb6c871-accf-4505-bef3-bc95366be0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589211600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.589211600
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1308255780
Short name T186
Test name
Test status
Simulation time 793645733 ps
CPU time 7.02 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:51:03 PM PDT 24
Peak memory 233668 kb
Host smart-1eef0f4f-afff-4d92-93a3-72d20de5af6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308255780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1308255780
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.907020871
Short name T325
Test name
Test status
Simulation time 27035979 ps
CPU time 0.69 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 206132 kb
Host smart-7f0da1af-d05c-45ed-8ffe-f3e159ccef8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907020871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.907020871
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3081722451
Short name T948
Test name
Test status
Simulation time 46723838 ps
CPU time 2.95 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:51:00 PM PDT 24
Peak memory 233532 kb
Host smart-26164da7-2ae7-4572-8543-b2f7654b8980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081722451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3081722451
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.328015781
Short name T529
Test name
Test status
Simulation time 136160854 ps
CPU time 0.76 seconds
Started Jul 25 05:50:53 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 206600 kb
Host smart-113ba913-25f2-4868-b1d9-95c878b01d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328015781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.328015781
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1339748859
Short name T923
Test name
Test status
Simulation time 20796071010 ps
CPU time 50.9 seconds
Started Jul 25 05:50:59 PM PDT 24
Finished Jul 25 05:51:50 PM PDT 24
Peak memory 238808 kb
Host smart-db607e4a-b2ed-4f49-8c56-5b4b5599b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339748859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1339748859
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.589899919
Short name T476
Test name
Test status
Simulation time 73909867251 ps
CPU time 70.69 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 240940 kb
Host smart-667031c3-9290-4867-9972-cfba91fe8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589899919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.589899919
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.751456823
Short name T824
Test name
Test status
Simulation time 25002361537 ps
CPU time 53.79 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:50 PM PDT 24
Peak memory 252488 kb
Host smart-9c773227-2db5-439c-aaa1-36aa41e04211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751456823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.751456823
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.173694130
Short name T278
Test name
Test status
Simulation time 58607558 ps
CPU time 0.95 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:50:56 PM PDT 24
Peak memory 216928 kb
Host smart-c18e8b28-6ff0-4c7d-b410-5405a9baced7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173694130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.173694130
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2834824981
Short name T230
Test name
Test status
Simulation time 526665400 ps
CPU time 7.72 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:04 PM PDT 24
Peak memory 233592 kb
Host smart-15811846-39f1-49e5-b156-c13fde5a91b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834824981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2834824981
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3765626944
Short name T640
Test name
Test status
Simulation time 5096765607 ps
CPU time 17.17 seconds
Started Jul 25 05:50:58 PM PDT 24
Finished Jul 25 05:51:15 PM PDT 24
Peak memory 239716 kb
Host smart-30d6f98c-2ceb-44f3-b034-fec3531f12d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765626944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3765626944
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2071566700
Short name T843
Test name
Test status
Simulation time 1272919893 ps
CPU time 6.03 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:51:01 PM PDT 24
Peak memory 250012 kb
Host smart-082bcfbc-70b9-450e-a7cf-94c7c94b1606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071566700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2071566700
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2660918355
Short name T708
Test name
Test status
Simulation time 592439374 ps
CPU time 7.66 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:04 PM PDT 24
Peak memory 233660 kb
Host smart-0b82ee99-34b5-454c-832c-0c9880c049fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660918355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2660918355
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2428634251
Short name T43
Test name
Test status
Simulation time 1177845069 ps
CPU time 9.73 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:51:04 PM PDT 24
Peak memory 223400 kb
Host smart-b6052fea-983d-405d-a8db-1f5ff90b2de4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2428634251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2428634251
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4248101796
Short name T811
Test name
Test status
Simulation time 9263335852 ps
CPU time 72.74 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 241996 kb
Host smart-8a1116a3-7db4-440f-a279-8e52a9287e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248101796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4248101796
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1556350531
Short name T158
Test name
Test status
Simulation time 43362657613 ps
CPU time 38.61 seconds
Started Jul 25 05:50:58 PM PDT 24
Finished Jul 25 05:51:37 PM PDT 24
Peak memory 217232 kb
Host smart-e387e58a-146e-45bf-a7e4-746519d13991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556350531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1556350531
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1736272583
Short name T394
Test name
Test status
Simulation time 251621258 ps
CPU time 2.21 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:50:57 PM PDT 24
Peak memory 217124 kb
Host smart-8de7fc17-8ca9-4a25-974a-340ee443a77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736272583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1736272583
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2434865532
Short name T289
Test name
Test status
Simulation time 105716556 ps
CPU time 1.99 seconds
Started Jul 25 05:50:58 PM PDT 24
Finished Jul 25 05:51:00 PM PDT 24
Peak memory 217172 kb
Host smart-8be69753-75a3-40ff-8eb1-3c20b9fa872e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434865532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2434865532
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3594956998
Short name T672
Test name
Test status
Simulation time 573665439 ps
CPU time 0.94 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:50:56 PM PDT 24
Peak memory 207220 kb
Host smart-3bb39bf8-34ae-4222-b375-4f6420e72655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594956998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3594956998
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3604881790
Short name T474
Test name
Test status
Simulation time 2347744125 ps
CPU time 8.86 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:51:05 PM PDT 24
Peak memory 233716 kb
Host smart-8304d352-5de7-44cf-b214-f83ffdfbd385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604881790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3604881790
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2020858653
Short name T727
Test name
Test status
Simulation time 11741555 ps
CPU time 0.73 seconds
Started Jul 25 05:51:06 PM PDT 24
Finished Jul 25 05:51:07 PM PDT 24
Peak memory 205480 kb
Host smart-95f682ca-45c2-4d8b-9e68-3862ff701a8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020858653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2020858653
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1628392953
Short name T181
Test name
Test status
Simulation time 387451757 ps
CPU time 3.41 seconds
Started Jul 25 05:51:06 PM PDT 24
Finished Jul 25 05:51:09 PM PDT 24
Peak memory 233684 kb
Host smart-73fff200-e282-4d04-a652-5033b814747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628392953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1628392953
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2391724156
Short name T294
Test name
Test status
Simulation time 20851732 ps
CPU time 0.8 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:50:58 PM PDT 24
Peak memory 207552 kb
Host smart-6d4746bc-0941-4eb7-80d1-0756cde984c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391724156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2391724156
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.493514069
Short name T454
Test name
Test status
Simulation time 11394262082 ps
CPU time 16.81 seconds
Started Jul 25 05:51:05 PM PDT 24
Finished Jul 25 05:51:22 PM PDT 24
Peak memory 239328 kb
Host smart-1d260154-3975-42b2-80ff-f04f294a77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493514069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.493514069
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.371492321
Short name T238
Test name
Test status
Simulation time 32559683705 ps
CPU time 349.35 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:56:58 PM PDT 24
Peak memory 263608 kb
Host smart-254cebab-994f-4e58-a0f3-d97f94096fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371492321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.371492321
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.288507831
Short name T775
Test name
Test status
Simulation time 7911324636 ps
CPU time 82.24 seconds
Started Jul 25 05:51:15 PM PDT 24
Finished Jul 25 05:52:38 PM PDT 24
Peak memory 250232 kb
Host smart-2875a29c-3914-4545-b92d-a7602ce199fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288507831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.288507831
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1039055518
Short name T311
Test name
Test status
Simulation time 113897473 ps
CPU time 4.36 seconds
Started Jul 25 05:51:15 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 233712 kb
Host smart-f06194fe-a3fa-491e-920d-ce09a3a7deb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039055518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1039055518
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.136283189
Short name T193
Test name
Test status
Simulation time 49903674312 ps
CPU time 336.77 seconds
Started Jul 25 05:51:07 PM PDT 24
Finished Jul 25 05:56:44 PM PDT 24
Peak memory 257244 kb
Host smart-252c458c-48bc-448e-b7a9-cf36075786ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136283189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.136283189
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1784279458
Short name T960
Test name
Test status
Simulation time 630407647 ps
CPU time 7.15 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:16 PM PDT 24
Peak memory 233624 kb
Host smart-8c196802-afbd-4fe1-9a8e-bbbac76ef654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784279458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1784279458
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3929009824
Short name T336
Test name
Test status
Simulation time 1715713851 ps
CPU time 23.34 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 225464 kb
Host smart-79c8b328-8874-4b9c-9a0e-1cffacf9ce51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929009824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3929009824
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3606143522
Short name T930
Test name
Test status
Simulation time 780881827 ps
CPU time 6.28 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:15 PM PDT 24
Peak memory 233596 kb
Host smart-79e6a006-cb6f-4fae-bb57-eed37bbbf566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606143522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3606143522
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2539676899
Short name T782
Test name
Test status
Simulation time 10440614904 ps
CPU time 9.7 seconds
Started Jul 25 05:51:07 PM PDT 24
Finished Jul 25 05:51:17 PM PDT 24
Peak memory 233692 kb
Host smart-aa2f1411-593b-4174-8b9f-b27f67f12636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539676899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2539676899
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.811636964
Short name T461
Test name
Test status
Simulation time 9018623636 ps
CPU time 16.48 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:26 PM PDT 24
Peak memory 221424 kb
Host smart-5d1f6d58-7759-4494-bdac-0004480824e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811636964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.811636964
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3377227456
Short name T903
Test name
Test status
Simulation time 62425208122 ps
CPU time 90.92 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:52:39 PM PDT 24
Peak memory 240156 kb
Host smart-fca70d6c-6dc5-4652-bbd7-a900ac2d79b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377227456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3377227456
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2340959233
Short name T720
Test name
Test status
Simulation time 691834330 ps
CPU time 7.85 seconds
Started Jul 25 05:50:55 PM PDT 24
Finished Jul 25 05:51:03 PM PDT 24
Peak memory 217160 kb
Host smart-ff942e1b-8b37-4036-b2d4-4d7a2cfb61a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340959233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2340959233
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4100032047
Short name T833
Test name
Test status
Simulation time 1980559166 ps
CPU time 3.45 seconds
Started Jul 25 05:50:56 PM PDT 24
Finished Jul 25 05:50:59 PM PDT 24
Peak memory 217144 kb
Host smart-bdc8058b-6429-4001-bffc-bc9c4f16ffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100032047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4100032047
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.689485336
Short name T933
Test name
Test status
Simulation time 324995879 ps
CPU time 1.28 seconds
Started Jul 25 05:50:57 PM PDT 24
Finished Jul 25 05:50:58 PM PDT 24
Peak memory 217136 kb
Host smart-013cab40-505b-4350-bd4e-5660fc486d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689485336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.689485336
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2920323707
Short name T645
Test name
Test status
Simulation time 24313664 ps
CPU time 0.73 seconds
Started Jul 25 05:50:54 PM PDT 24
Finished Jul 25 05:50:55 PM PDT 24
Peak memory 206780 kb
Host smart-48a6bd7c-14c3-4610-9301-972308bc60b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920323707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2920323707
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3098850632
Short name T867
Test name
Test status
Simulation time 2175354607 ps
CPU time 3.73 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:12 PM PDT 24
Peak memory 225264 kb
Host smart-ef6101c6-f2f8-4820-9b6b-b82fe2a8d138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098850632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3098850632
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4089482741
Short name T1021
Test name
Test status
Simulation time 31564380 ps
CPU time 0.7 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:11 PM PDT 24
Peak memory 205520 kb
Host smart-5bb77bfe-e2d8-4612-bd4f-d9631719085b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089482741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4089482741
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2331659011
Short name T877
Test name
Test status
Simulation time 12886132569 ps
CPU time 27.01 seconds
Started Jul 25 05:51:06 PM PDT 24
Finished Jul 25 05:51:34 PM PDT 24
Peak memory 225392 kb
Host smart-e78efd3f-e80f-4a22-96fb-36e6c581c556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331659011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2331659011
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2996446349
Short name T428
Test name
Test status
Simulation time 18653269 ps
CPU time 0.76 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:09 PM PDT 24
Peak memory 206244 kb
Host smart-61a0fafa-7d77-4bb6-9915-b33d07c7cdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996446349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2996446349
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3753729378
Short name T51
Test name
Test status
Simulation time 4224691956 ps
CPU time 44.34 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:55 PM PDT 24
Peak memory 239092 kb
Host smart-7fe962e0-c8ff-4e79-a28b-041b589cf9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753729378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3753729378
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.776139149
Short name T854
Test name
Test status
Simulation time 8032859779 ps
CPU time 54.07 seconds
Started Jul 25 05:51:10 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 221920 kb
Host smart-0581a2ae-1898-4053-9cac-add0d5f17a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776139149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.776139149
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2934326773
Short name T435
Test name
Test status
Simulation time 106603991471 ps
CPU time 129.93 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:53:18 PM PDT 24
Peak memory 258324 kb
Host smart-fc6916f1-6d29-488c-9d2d-f84ae9b57893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934326773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2934326773
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3251127804
Short name T537
Test name
Test status
Simulation time 3880929858 ps
CPU time 26.25 seconds
Started Jul 25 05:51:10 PM PDT 24
Finished Jul 25 05:51:36 PM PDT 24
Peak memory 241888 kb
Host smart-2919d4e8-c9bf-4154-9386-2a6631d08aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251127804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3251127804
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3426823649
Short name T819
Test name
Test status
Simulation time 2136902341 ps
CPU time 23.11 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:34 PM PDT 24
Peak memory 240184 kb
Host smart-12b5f4a3-f4bc-4a7b-95c1-faec47e16961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426823649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3426823649
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1967900807
Short name T850
Test name
Test status
Simulation time 2302473074 ps
CPU time 24.47 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 233700 kb
Host smart-98eedbe1-2dec-40c0-a2ce-f11bfafa2287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967900807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1967900807
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.4285027554
Short name T533
Test name
Test status
Simulation time 4634337773 ps
CPU time 20.21 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 241336 kb
Host smart-28c926a1-11cf-4cf3-9295-167de72aa26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285027554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.4285027554
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2088036506
Short name T607
Test name
Test status
Simulation time 1794627934 ps
CPU time 8.08 seconds
Started Jul 25 05:51:07 PM PDT 24
Finished Jul 25 05:51:16 PM PDT 24
Peak memory 239644 kb
Host smart-2f324405-88a6-484b-afac-d05d5dda558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088036506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2088036506
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3859336613
Short name T71
Test name
Test status
Simulation time 831555789 ps
CPU time 10.4 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:18 PM PDT 24
Peak memory 250588 kb
Host smart-79f8d3a2-8206-4667-9717-8a6acfa6540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859336613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3859336613
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.689960354
Short name T296
Test name
Test status
Simulation time 8146146737 ps
CPU time 10.77 seconds
Started Jul 25 05:51:07 PM PDT 24
Finished Jul 25 05:51:18 PM PDT 24
Peak memory 223896 kb
Host smart-0ef97c5d-a915-444c-a5f0-3824daee2c64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=689960354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.689960354
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.960863671
Short name T160
Test name
Test status
Simulation time 38985364665 ps
CPU time 468.36 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:58:57 PM PDT 24
Peak memory 273736 kb
Host smart-a48a914b-af94-4777-8051-e078f466b699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960863671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.960863671
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.367093580
Short name T768
Test name
Test status
Simulation time 8555477544 ps
CPU time 31.73 seconds
Started Jul 25 05:51:15 PM PDT 24
Finished Jul 25 05:51:47 PM PDT 24
Peak memory 217272 kb
Host smart-ce0e8fa5-f00d-402a-ad8f-a5ccf32115eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367093580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.367093580
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1428386725
Short name T390
Test name
Test status
Simulation time 1485240846 ps
CPU time 9.35 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 217124 kb
Host smart-2b94a42b-501a-4469-8a74-aee3c93c8a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428386725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1428386725
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.945708155
Short name T869
Test name
Test status
Simulation time 185170501 ps
CPU time 2.19 seconds
Started Jul 25 05:51:06 PM PDT 24
Finished Jul 25 05:51:09 PM PDT 24
Peak memory 217204 kb
Host smart-5238ae28-e241-4317-8711-7e14d9de805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945708155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.945708155
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.4212621556
Short name T515
Test name
Test status
Simulation time 21758824 ps
CPU time 0.84 seconds
Started Jul 25 05:51:05 PM PDT 24
Finished Jul 25 05:51:06 PM PDT 24
Peak memory 206800 kb
Host smart-aa8bdd3d-e8f7-4145-89dc-9abfd764e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212621556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.4212621556
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3339456254
Short name T380
Test name
Test status
Simulation time 954475268 ps
CPU time 11.81 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 233636 kb
Host smart-d0020271-1333-45aa-81ad-5d4cd71379d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339456254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3339456254
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.153931679
Short name T932
Test name
Test status
Simulation time 45490406 ps
CPU time 0.71 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:16 PM PDT 24
Peak memory 206112 kb
Host smart-fff50aac-44e2-4bbb-8384-6f3b73881664
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153931679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.153931679
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3891878386
Short name T585
Test name
Test status
Simulation time 83307782 ps
CPU time 2.76 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:06 PM PDT 24
Peak memory 233636 kb
Host smart-4f8e568d-ae8c-430c-b305-654a5da8e461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891878386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3891878386
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1693635405
Short name T831
Test name
Test status
Simulation time 23522121 ps
CPU time 0.84 seconds
Started Jul 25 05:48:02 PM PDT 24
Finished Jul 25 05:48:03 PM PDT 24
Peak memory 207316 kb
Host smart-188d64f2-bd4b-4de3-8549-52a9504ca626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693635405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1693635405
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3052246809
Short name T64
Test name
Test status
Simulation time 52379128361 ps
CPU time 357.85 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:54:05 PM PDT 24
Peak memory 254140 kb
Host smart-269af2c1-b888-4866-8b5d-9a9dbcc6c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052246809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3052246809
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4067782787
Short name T232
Test name
Test status
Simulation time 77260536522 ps
CPU time 184.62 seconds
Started Jul 25 05:48:06 PM PDT 24
Finished Jul 25 05:51:11 PM PDT 24
Peak memory 239592 kb
Host smart-43b9bd82-e506-49c5-8c08-9eb1fc17896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067782787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4067782787
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2716257244
Short name T598
Test name
Test status
Simulation time 9407042719 ps
CPU time 9.15 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:25 PM PDT 24
Peak memory 218516 kb
Host smart-1a78accc-f53a-4d32-993a-4d4d4f9e64c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716257244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2716257244
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.545329008
Short name T692
Test name
Test status
Simulation time 171485798 ps
CPU time 5.54 seconds
Started Jul 25 05:48:02 PM PDT 24
Finished Jul 25 05:48:08 PM PDT 24
Peak memory 235400 kb
Host smart-7ca004f6-43fc-4de6-923e-49a37931de80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545329008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.545329008
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.965506558
Short name T26
Test name
Test status
Simulation time 16153184687 ps
CPU time 109.23 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:49:56 PM PDT 24
Peak memory 253676 kb
Host smart-f0b99c24-15a2-4760-b100-8d4f55e663d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965506558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
965506558
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2416486955
Short name T80
Test name
Test status
Simulation time 273424308 ps
CPU time 5.4 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:48:09 PM PDT 24
Peak memory 233628 kb
Host smart-972f21de-8e7d-4d28-97e2-22dd8a275d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416486955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2416486955
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4215391064
Short name T945
Test name
Test status
Simulation time 20532517253 ps
CPU time 48.68 seconds
Started Jul 25 05:48:03 PM PDT 24
Finished Jul 25 05:48:52 PM PDT 24
Peak memory 240520 kb
Host smart-e661c466-5ee1-4eea-90e8-08c3d48060cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215391064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4215391064
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3469164462
Short name T583
Test name
Test status
Simulation time 92285838 ps
CPU time 1.11 seconds
Started Jul 25 05:48:04 PM PDT 24
Finished Jul 25 05:48:06 PM PDT 24
Peak memory 217412 kb
Host smart-4e5a0902-92d8-4710-88fa-f6acad31f471
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469164462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3469164462
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2392224758
Short name T155
Test name
Test status
Simulation time 985071811 ps
CPU time 4.43 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:12 PM PDT 24
Peak memory 225436 kb
Host smart-c30c3a95-b9d1-4ddc-8c0d-1a42e4b063c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392224758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2392224758
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3994766939
Short name T702
Test name
Test status
Simulation time 395562951 ps
CPU time 3.12 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:10 PM PDT 24
Peak memory 225432 kb
Host smart-1caf7dc5-273c-4473-bcb2-91f09f6f6de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994766939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3994766939
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1211092548
Short name T657
Test name
Test status
Simulation time 2775106480 ps
CPU time 10.3 seconds
Started Jul 25 05:48:02 PM PDT 24
Finished Jul 25 05:48:12 PM PDT 24
Peak memory 220868 kb
Host smart-c62390ea-38a1-429d-ac06-d66c914a1913
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1211092548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1211092548
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.980178591
Short name T63
Test name
Test status
Simulation time 34695531 ps
CPU time 0.98 seconds
Started Jul 25 05:48:14 PM PDT 24
Finished Jul 25 05:48:15 PM PDT 24
Peak memory 235924 kb
Host smart-c729aa41-b81b-451b-8f33-d733d0388c03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980178591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.980178591
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1020387188
Short name T665
Test name
Test status
Simulation time 120506669 ps
CPU time 1.14 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:17 PM PDT 24
Peak memory 208368 kb
Host smart-7346cf47-f5be-481f-8189-099816171f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020387188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1020387188
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2625064097
Short name T807
Test name
Test status
Simulation time 10283995797 ps
CPU time 30.28 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:43 PM PDT 24
Peak memory 217192 kb
Host smart-66a9e9dd-4d47-4a69-a4e7-1c331740dbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625064097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2625064097
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2806753047
Short name T23
Test name
Test status
Simulation time 707573799 ps
CPU time 2.36 seconds
Started Jul 25 05:48:07 PM PDT 24
Finished Jul 25 05:48:10 PM PDT 24
Peak memory 208744 kb
Host smart-49cca2a9-eca7-4cf2-b761-18e3130141e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806753047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2806753047
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3322790051
Short name T1017
Test name
Test status
Simulation time 908573448 ps
CPU time 10.07 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:23 PM PDT 24
Peak memory 216716 kb
Host smart-c9a4a9a6-8dcc-40a6-9ad7-8da4c08c4b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322790051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3322790051
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2942769128
Short name T884
Test name
Test status
Simulation time 54824110 ps
CPU time 0.83 seconds
Started Jul 25 05:48:06 PM PDT 24
Finished Jul 25 05:48:07 PM PDT 24
Peak memory 206780 kb
Host smart-5418f1cd-1a4a-443f-9ce0-f7062da92f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942769128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2942769128
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.993815547
Short name T545
Test name
Test status
Simulation time 457671663 ps
CPU time 4.87 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 233076 kb
Host smart-337ff702-b56a-4ee8-8f2c-82b500540deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993815547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.993815547
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.939863699
Short name T639
Test name
Test status
Simulation time 23822159 ps
CPU time 0.71 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:22 PM PDT 24
Peak memory 205428 kb
Host smart-47b2d6be-6a5b-4acd-8e3f-35cbadd9c5ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939863699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.939863699
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.511627417
Short name T660
Test name
Test status
Simulation time 158174866 ps
CPU time 4.19 seconds
Started Jul 25 05:51:15 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 233728 kb
Host smart-0d4c425f-64f7-48ff-86c6-4454690744f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511627417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.511627417
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1605978354
Short name T551
Test name
Test status
Simulation time 48797048 ps
CPU time 0.75 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:09 PM PDT 24
Peak memory 206196 kb
Host smart-a693fd4a-0884-4585-9832-2b0573e813d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605978354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1605978354
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3949282476
Short name T184
Test name
Test status
Simulation time 22872449961 ps
CPU time 164.16 seconds
Started Jul 25 05:51:12 PM PDT 24
Finished Jul 25 05:53:56 PM PDT 24
Peak memory 254448 kb
Host smart-e89cfbe1-f491-4ddc-bdf7-98a3e0e910b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949282476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3949282476
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.134106767
Short name T215
Test name
Test status
Simulation time 181863399328 ps
CPU time 351.64 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:57:01 PM PDT 24
Peak memory 258340 kb
Host smart-01ea96dc-e122-460f-ba91-13c43f3fd316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134106767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.134106767
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1946779243
Short name T183
Test name
Test status
Simulation time 7402675326 ps
CPU time 64.88 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:52:14 PM PDT 24
Peak memory 224232 kb
Host smart-a613aa77-2492-4c65-8d2d-8e3d6fa98fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946779243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1946779243
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1007357375
Short name T837
Test name
Test status
Simulation time 139095820 ps
CPU time 5.82 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:15 PM PDT 24
Peak memory 241784 kb
Host smart-1dc7bbf4-ce17-4541-9469-1413358e611e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007357375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1007357375
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.108645018
Short name T689
Test name
Test status
Simulation time 103373222586 ps
CPU time 399.27 seconds
Started Jul 25 05:51:10 PM PDT 24
Finished Jul 25 05:57:50 PM PDT 24
Peak memory 265744 kb
Host smart-a63feb18-8970-4210-8e9a-ded6159b6f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108645018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.108645018
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2744877019
Short name T943
Test name
Test status
Simulation time 349599915 ps
CPU time 6.67 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:15 PM PDT 24
Peak memory 233716 kb
Host smart-17eda5af-f16d-4fcf-a0dc-50c1ffeb91bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744877019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2744877019
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2199148803
Short name T279
Test name
Test status
Simulation time 13238518022 ps
CPU time 114.64 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 241092 kb
Host smart-2289fe9b-29db-49f2-89ad-7415fe8e5e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199148803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2199148803
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3412563550
Short name T353
Test name
Test status
Simulation time 2619389420 ps
CPU time 10.6 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:19 PM PDT 24
Peak memory 239248 kb
Host smart-c9bf9c80-f184-4553-ad3e-21a425728941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412563550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3412563550
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1112885394
Short name T1025
Test name
Test status
Simulation time 454461961 ps
CPU time 4.48 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:13 PM PDT 24
Peak memory 233656 kb
Host smart-c919fafa-cf53-45f3-a062-f43f2409bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112885394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1112885394
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3877470234
Short name T70
Test name
Test status
Simulation time 418570104 ps
CPU time 4.85 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:16 PM PDT 24
Peak memory 223416 kb
Host smart-4880716c-2107-4c2c-9423-d03100f43988
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3877470234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3877470234
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2423162394
Short name T151
Test name
Test status
Simulation time 265957008 ps
CPU time 0.89 seconds
Started Jul 25 05:51:09 PM PDT 24
Finished Jul 25 05:51:10 PM PDT 24
Peak memory 206304 kb
Host smart-73cb82cc-ddb7-4b1d-ac08-2ee842897acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423162394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2423162394
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3969785669
Short name T610
Test name
Test status
Simulation time 2339464589 ps
CPU time 12.95 seconds
Started Jul 25 05:51:08 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 217208 kb
Host smart-94e772cc-9789-4f01-8fcf-fa9c160cc3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969785669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3969785669
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3743548555
Short name T312
Test name
Test status
Simulation time 1720000437 ps
CPU time 3.94 seconds
Started Jul 25 05:51:07 PM PDT 24
Finished Jul 25 05:51:11 PM PDT 24
Peak memory 217072 kb
Host smart-771cd9fb-f727-4a28-b5c3-0262da2342ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743548555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3743548555
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1188997129
Short name T566
Test name
Test status
Simulation time 133646201 ps
CPU time 2.02 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:13 PM PDT 24
Peak memory 217104 kb
Host smart-b807a6aa-ea10-4886-b0dd-0344fcdd06f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188997129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1188997129
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.521570755
Short name T826
Test name
Test status
Simulation time 327736463 ps
CPU time 1.02 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:12 PM PDT 24
Peak memory 207792 kb
Host smart-20ccd058-5d96-4563-ad84-6220b32cfa28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521570755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.521570755
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2157479773
Short name T455
Test name
Test status
Simulation time 38847703747 ps
CPU time 32.13 seconds
Started Jul 25 05:51:11 PM PDT 24
Finished Jul 25 05:51:43 PM PDT 24
Peak memory 233708 kb
Host smart-b81dfc4a-71b1-4347-9f3e-4d592f0a8a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157479773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2157479773
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1927569808
Short name T307
Test name
Test status
Simulation time 78166447 ps
CPU time 0.7 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 205496 kb
Host smart-81e52c60-0bb7-4783-81bd-57d392c626b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927569808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1927569808
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3911760304
Short name T863
Test name
Test status
Simulation time 252627218 ps
CPU time 2.52 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:24 PM PDT 24
Peak memory 225420 kb
Host smart-408c8bb6-5f53-414a-aae3-c0dd21db09d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911760304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3911760304
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.968389437
Short name T503
Test name
Test status
Simulation time 15713918 ps
CPU time 0.8 seconds
Started Jul 25 05:51:18 PM PDT 24
Finished Jul 25 05:51:19 PM PDT 24
Peak memory 207204 kb
Host smart-c6b8f94c-4a66-44fb-9be2-a5aae54e1211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968389437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.968389437
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3575314665
Short name T552
Test name
Test status
Simulation time 16114840146 ps
CPU time 145.17 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:53:45 PM PDT 24
Peak memory 256772 kb
Host smart-20c1b285-0937-4018-8f28-3ca09f5c38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575314665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3575314665
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1259254908
Short name T408
Test name
Test status
Simulation time 64500815645 ps
CPU time 243.77 seconds
Started Jul 25 05:51:17 PM PDT 24
Finished Jul 25 05:55:21 PM PDT 24
Peak memory 254488 kb
Host smart-6610d000-892e-4bc8-8aac-e84c04b64a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259254908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1259254908
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3219504434
Short name T190
Test name
Test status
Simulation time 52364810754 ps
CPU time 441.36 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:58:41 PM PDT 24
Peak memory 264704 kb
Host smart-ccbed827-f4ea-43ee-abb9-f235607d9d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219504434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3219504434
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3714724167
Short name T264
Test name
Test status
Simulation time 1449389983 ps
CPU time 17.05 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 225420 kb
Host smart-feb6482b-ab40-4ce8-af45-e21b9cf859c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714724167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3714724167
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1479281964
Short name T743
Test name
Test status
Simulation time 16257063 ps
CPU time 0.78 seconds
Started Jul 25 05:51:22 PM PDT 24
Finished Jul 25 05:51:23 PM PDT 24
Peak memory 216632 kb
Host smart-3154d121-fc7a-4a4f-8856-7d58936e9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479281964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1479281964
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.526923076
Short name T724
Test name
Test status
Simulation time 207853597 ps
CPU time 2.46 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 223900 kb
Host smart-8b898017-8d96-4b21-89f6-54706eca1298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526923076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.526923076
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.970562216
Short name T652
Test name
Test status
Simulation time 793850466 ps
CPU time 13.81 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:35 PM PDT 24
Peak memory 239200 kb
Host smart-62ec0d7e-fa50-4519-98ee-6fedfb43f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970562216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.970562216
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3444778258
Short name T814
Test name
Test status
Simulation time 702802721 ps
CPU time 3.88 seconds
Started Jul 25 05:51:22 PM PDT 24
Finished Jul 25 05:51:26 PM PDT 24
Peak memory 225416 kb
Host smart-e8299325-0702-4c1e-9c6e-36d29daaa7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444778258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3444778258
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3020923786
Short name T467
Test name
Test status
Simulation time 3381874289 ps
CPU time 9.7 seconds
Started Jul 25 05:51:16 PM PDT 24
Finished Jul 25 05:51:26 PM PDT 24
Peak memory 233576 kb
Host smart-f2bf3a59-8c80-48a4-81b8-85a3da727523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020923786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3020923786
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2077068781
Short name T67
Test name
Test status
Simulation time 1077943729 ps
CPU time 8.36 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:29 PM PDT 24
Peak memory 223756 kb
Host smart-bb731b70-6bd1-48b2-8e22-f0e4675182ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077068781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2077068781
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1326180251
Short name T228
Test name
Test status
Simulation time 237845661882 ps
CPU time 650.47 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 06:02:10 PM PDT 24
Peak memory 290996 kb
Host smart-fca55a86-9bfe-4b0a-917d-2bbe1e2f931b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326180251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1326180251
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3900589902
Short name T526
Test name
Test status
Simulation time 14313910511 ps
CPU time 22.14 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:43 PM PDT 24
Peak memory 220892 kb
Host smart-84f20a2e-d480-404d-aa02-05d75e093376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900589902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3900589902
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2483914254
Short name T845
Test name
Test status
Simulation time 14026405602 ps
CPU time 9.75 seconds
Started Jul 25 05:51:26 PM PDT 24
Finished Jul 25 05:51:36 PM PDT 24
Peak memory 217324 kb
Host smart-888bec35-a8b1-41a1-aafb-fd46ee6da0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483914254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2483914254
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1365797176
Short name T567
Test name
Test status
Simulation time 19361096 ps
CPU time 1.06 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 208788 kb
Host smart-9705ce37-8343-4c25-8d67-13b877ab2cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365797176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1365797176
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3446153785
Short name T370
Test name
Test status
Simulation time 115753656 ps
CPU time 0.86 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 207768 kb
Host smart-e924d7eb-4d45-49e0-a32d-e0613412bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446153785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3446153785
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3671868121
Short name T893
Test name
Test status
Simulation time 828129930 ps
CPU time 6.73 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:51:25 PM PDT 24
Peak memory 233640 kb
Host smart-74865784-c740-437b-b40b-bd81ca0c3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671868121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3671868121
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3008745848
Short name T516
Test name
Test status
Simulation time 57488532 ps
CPU time 0.69 seconds
Started Jul 25 05:51:24 PM PDT 24
Finished Jul 25 05:51:25 PM PDT 24
Peak memory 205484 kb
Host smart-913fe43c-1eb8-498a-9f6e-6f187c946060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008745848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3008745848
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2216725504
Short name T631
Test name
Test status
Simulation time 2584220920 ps
CPU time 18.21 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 233740 kb
Host smart-abb3d38e-cf19-480c-b394-eaaf8fbf49d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216725504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2216725504
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2736694304
Short name T368
Test name
Test status
Simulation time 162750315 ps
CPU time 0.8 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:51:26 PM PDT 24
Peak memory 207232 kb
Host smart-02b64913-10ea-48f5-a6b5-b5d27a4afb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736694304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2736694304
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2354593358
Short name T709
Test name
Test status
Simulation time 45805589678 ps
CPU time 79.93 seconds
Started Jul 25 05:51:17 PM PDT 24
Finished Jul 25 05:52:38 PM PDT 24
Peak memory 240580 kb
Host smart-2fdfe0e6-9b1a-42b6-8a3a-756906e78948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354593358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2354593358
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3465728722
Short name T253
Test name
Test status
Simulation time 6097057313 ps
CPU time 47.94 seconds
Started Jul 25 05:51:18 PM PDT 24
Finished Jul 25 05:52:06 PM PDT 24
Peak memory 258384 kb
Host smart-7e51c79c-4c79-440d-9654-7e96405ce4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465728722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3465728722
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2489051028
Short name T822
Test name
Test status
Simulation time 27049917692 ps
CPU time 100.98 seconds
Started Jul 25 05:51:22 PM PDT 24
Finished Jul 25 05:53:03 PM PDT 24
Peak memory 250160 kb
Host smart-b2bbee9a-d5cc-41be-8722-f29291f86826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489051028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2489051028
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1259803733
Short name T321
Test name
Test status
Simulation time 283137427 ps
CPU time 5.87 seconds
Started Jul 25 05:51:18 PM PDT 24
Finished Jul 25 05:51:24 PM PDT 24
Peak memory 225380 kb
Host smart-a3440ae9-6a32-4e57-b607-5b79669cdcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259803733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1259803733
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2265431955
Short name T211
Test name
Test status
Simulation time 13735798025 ps
CPU time 98.32 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:52:58 PM PDT 24
Peak memory 240932 kb
Host smart-94967a5a-2bba-4992-970a-ca10982ad504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265431955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2265431955
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.925410960
Short name T953
Test name
Test status
Simulation time 74309745 ps
CPU time 2.25 seconds
Started Jul 25 05:51:23 PM PDT 24
Finished Jul 25 05:51:26 PM PDT 24
Peak memory 224308 kb
Host smart-943372e0-8ef6-48b6-a5ca-b42303b1009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925410960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.925410960
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1648619420
Short name T399
Test name
Test status
Simulation time 299858680 ps
CPU time 4 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:24 PM PDT 24
Peak memory 233648 kb
Host smart-bb090147-c922-460f-8965-280f4ea18152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648619420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1648619420
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1670588146
Short name T769
Test name
Test status
Simulation time 1325102551 ps
CPU time 8.06 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 219732 kb
Host smart-0eb5d18c-6ec2-4eca-aa69-0007d0010bb2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1670588146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1670588146
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.247092176
Short name T267
Test name
Test status
Simulation time 16877915599 ps
CPU time 31.47 seconds
Started Jul 25 05:51:26 PM PDT 24
Finished Jul 25 05:51:57 PM PDT 24
Peak memory 217324 kb
Host smart-850144d1-68a1-4f32-b71c-12bc6e203bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247092176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.247092176
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2336074064
Short name T452
Test name
Test status
Simulation time 37882958 ps
CPU time 0.73 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 206392 kb
Host smart-7b01badb-0972-409f-bfe4-55ce44daca10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336074064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2336074064
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3272267269
Short name T749
Test name
Test status
Simulation time 32827732 ps
CPU time 0.84 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 207820 kb
Host smart-05acd104-5cdd-418a-86ad-29d00c195586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272267269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3272267269
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.445902394
Short name T846
Test name
Test status
Simulation time 42620768 ps
CPU time 0.8 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 206816 kb
Host smart-28fb23f3-4b6d-4ef0-80d1-214ab0728e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445902394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.445902394
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2781775681
Short name T955
Test name
Test status
Simulation time 3443770156 ps
CPU time 7.66 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 233660 kb
Host smart-02b36539-395f-48f8-be6f-ad4507645b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781775681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2781775681
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1720971152
Short name T343
Test name
Test status
Simulation time 45088874 ps
CPU time 0.72 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:51:30 PM PDT 24
Peak memory 206392 kb
Host smart-130af7e0-bd22-429f-9139-73d58f3b849e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720971152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1720971152
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1994464089
Short name T853
Test name
Test status
Simulation time 4550873586 ps
CPU time 12.29 seconds
Started Jul 25 05:51:18 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 225516 kb
Host smart-c9b8d1a1-ce9b-4d71-ae04-c4af7daa5336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994464089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1994464089
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4232327217
Short name T502
Test name
Test status
Simulation time 203909768 ps
CPU time 0.78 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 207300 kb
Host smart-bf953e90-907c-447f-934e-3e5f22a6142d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232327217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4232327217
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.77332667
Short name T210
Test name
Test status
Simulation time 35036820373 ps
CPU time 133.93 seconds
Started Jul 25 05:51:22 PM PDT 24
Finished Jul 25 05:53:36 PM PDT 24
Peak memory 250088 kb
Host smart-93b02d3b-82a4-42f9-9ddf-f537e3030d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77332667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.77332667
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.342566391
Short name T395
Test name
Test status
Simulation time 12470511822 ps
CPU time 76.4 seconds
Started Jul 25 05:51:26 PM PDT 24
Finished Jul 25 05:52:43 PM PDT 24
Peak memory 256812 kb
Host smart-d9a7f220-b3fa-4ef0-ba5f-59ff8d7823af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342566391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.342566391
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.34779316
Short name T497
Test name
Test status
Simulation time 36187167067 ps
CPU time 313.46 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:56:38 PM PDT 24
Peak memory 250240 kb
Host smart-40400643-38c7-40ce-acae-678f37ac330f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34779316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.34779316
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3233876007
Short name T256
Test name
Test status
Simulation time 18493693946 ps
CPU time 53.14 seconds
Started Jul 25 05:51:15 PM PDT 24
Finished Jul 25 05:52:09 PM PDT 24
Peak memory 251436 kb
Host smart-b0d127ba-1b94-48ac-9dff-c755d393c02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233876007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3233876007
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3586167218
Short name T317
Test name
Test status
Simulation time 6563245732 ps
CPU time 26.2 seconds
Started Jul 25 05:51:21 PM PDT 24
Finished Jul 25 05:51:48 PM PDT 24
Peak memory 225492 kb
Host smart-c222e2c5-e81c-4e56-a36d-1db9a961f8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586167218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3586167218
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3729947083
Short name T213
Test name
Test status
Simulation time 1344512143 ps
CPU time 14.79 seconds
Started Jul 25 05:51:22 PM PDT 24
Finished Jul 25 05:51:37 PM PDT 24
Peak memory 220680 kb
Host smart-55c24afa-5e15-409d-9c8a-4258e5bdad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729947083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3729947083
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2860449844
Short name T517
Test name
Test status
Simulation time 29565379805 ps
CPU time 69.15 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:52:29 PM PDT 24
Peak memory 233664 kb
Host smart-4dfddac5-e3ff-430e-99f4-d9def1c5c4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860449844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2860449844
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2275161629
Short name T225
Test name
Test status
Simulation time 77465413095 ps
CPU time 15.59 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:51:41 PM PDT 24
Peak memory 241812 kb
Host smart-64067cd7-aa67-44d8-a824-736ad9ee0fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275161629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2275161629
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.242138253
Short name T688
Test name
Test status
Simulation time 32207333 ps
CPU time 2.41 seconds
Started Jul 25 05:51:26 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 233252 kb
Host smart-d7952eba-bec4-4754-ac7b-fd8dbc418289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242138253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.242138253
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3882633760
Short name T876
Test name
Test status
Simulation time 972808487 ps
CPU time 9.27 seconds
Started Jul 25 05:51:19 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 221704 kb
Host smart-8fe08ff9-0697-4c34-9b3a-44b016c8ddb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3882633760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3882633760
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2324822497
Short name T13
Test name
Test status
Simulation time 8547475573 ps
CPU time 43.3 seconds
Started Jul 25 05:51:27 PM PDT 24
Finished Jul 25 05:52:10 PM PDT 24
Peak memory 238812 kb
Host smart-a7288e33-19b7-4c1e-946e-68ae952adc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324822497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2324822497
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1179802220
Short name T780
Test name
Test status
Simulation time 3227158446 ps
CPU time 33.92 seconds
Started Jul 25 05:51:18 PM PDT 24
Finished Jul 25 05:51:52 PM PDT 24
Peak memory 217300 kb
Host smart-7bb6c986-a547-43d0-a088-4b4d9a5d9e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179802220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1179802220
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.41550848
Short name T341
Test name
Test status
Simulation time 76514073 ps
CPU time 1.02 seconds
Started Jul 25 05:51:17 PM PDT 24
Finished Jul 25 05:51:18 PM PDT 24
Peak memory 207868 kb
Host smart-76389fa4-7b7e-41a2-9a04-29120d307506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41550848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.41550848
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.163276848
Short name T873
Test name
Test status
Simulation time 70979739 ps
CPU time 0.79 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 206780 kb
Host smart-aacfc592-7d2a-4260-ba8e-755360cf06a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163276848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.163276848
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4010962330
Short name T309
Test name
Test status
Simulation time 270141206 ps
CPU time 1.02 seconds
Started Jul 25 05:51:20 PM PDT 24
Finished Jul 25 05:51:21 PM PDT 24
Peak memory 207752 kb
Host smart-38a707bc-2fda-4e1a-85e0-40505d0e9a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010962330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4010962330
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3165851078
Short name T706
Test name
Test status
Simulation time 315975142 ps
CPU time 4.62 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:51:30 PM PDT 24
Peak memory 225396 kb
Host smart-e03b68c2-87cf-478d-bdf7-004b5f5a8e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165851078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3165851078
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3485279672
Short name T947
Test name
Test status
Simulation time 51718799 ps
CPU time 0.73 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 205600 kb
Host smart-2b45ca4e-e152-4f4e-8b99-f735db0a2a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485279672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3485279672
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1540525213
Short name T382
Test name
Test status
Simulation time 447085197 ps
CPU time 4.04 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:51:29 PM PDT 24
Peak memory 233644 kb
Host smart-b29d072c-076b-447a-9a95-588f693a1539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540525213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1540525213
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1539051086
Short name T419
Test name
Test status
Simulation time 15464640 ps
CPU time 0.77 seconds
Started Jul 25 05:51:27 PM PDT 24
Finished Jul 25 05:51:28 PM PDT 24
Peak memory 207604 kb
Host smart-2e322de3-b214-42d0-a4ba-0d4a5671d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539051086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1539051086
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2738070710
Short name T66
Test name
Test status
Simulation time 128907803727 ps
CPU time 464.99 seconds
Started Jul 25 05:51:31 PM PDT 24
Finished Jul 25 05:59:17 PM PDT 24
Peak memory 266468 kb
Host smart-0e2ce4f9-eab1-46e7-b9a8-28bdedd5fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738070710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2738070710
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4266471013
Short name T931
Test name
Test status
Simulation time 5300957445 ps
CPU time 35.39 seconds
Started Jul 25 05:51:32 PM PDT 24
Finished Jul 25 05:52:07 PM PDT 24
Peak memory 241972 kb
Host smart-15833faf-104f-46f5-9850-d18aaf50061e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266471013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4266471013
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1304373244
Short name T575
Test name
Test status
Simulation time 19643428397 ps
CPU time 184.4 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:54:29 PM PDT 24
Peak memory 257728 kb
Host smart-8f766ee3-797a-4f5c-a8c1-4bcc3da2ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304373244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1304373244
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.171574495
Short name T258
Test name
Test status
Simulation time 5949303249 ps
CPU time 46.93 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:52:12 PM PDT 24
Peak memory 241552 kb
Host smart-e33a9d66-a8fa-4613-89fd-538b85eb3387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171574495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.171574495
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2939162178
Short name T788
Test name
Test status
Simulation time 1004655012 ps
CPU time 5.27 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:34 PM PDT 24
Peak memory 225372 kb
Host smart-7db483f4-ff86-453e-9f42-c15cc28ee3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939162178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2939162178
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.406373532
Short name T794
Test name
Test status
Simulation time 1517952575 ps
CPU time 5.86 seconds
Started Jul 25 05:51:32 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 225392 kb
Host smart-cc27a631-8409-441a-89da-6917070d858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406373532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.406373532
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.733192351
Short name T1006
Test name
Test status
Simulation time 3830606187 ps
CPU time 43.28 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:52:13 PM PDT 24
Peak memory 233632 kb
Host smart-15980e69-32cd-4c9e-a10b-780b0abe39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733192351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.733192351
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2355720581
Short name T975
Test name
Test status
Simulation time 110296628 ps
CPU time 2.41 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 233244 kb
Host smart-56c8302a-1bc7-4d7c-8104-10d94f486c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355720581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2355720581
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4124158179
Short name T305
Test name
Test status
Simulation time 14510292391 ps
CPU time 24.88 seconds
Started Jul 25 05:51:26 PM PDT 24
Finished Jul 25 05:51:51 PM PDT 24
Peak memory 241576 kb
Host smart-b1dca093-0bc6-4d3b-a340-bd4d9a6e4797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124158179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4124158179
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1349889701
Short name T41
Test name
Test status
Simulation time 3369481229 ps
CPU time 10.23 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:39 PM PDT 24
Peak memory 224060 kb
Host smart-f2b48227-0e7d-4508-8483-a14145c9bfee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1349889701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1349889701
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3064796114
Short name T407
Test name
Test status
Simulation time 304248656 ps
CPU time 1 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:51:30 PM PDT 24
Peak memory 207352 kb
Host smart-84fa1191-e601-4995-953d-621e5638fd18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064796114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3064796114
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2449394085
Short name T841
Test name
Test status
Simulation time 1911353092 ps
CPU time 16.41 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:45 PM PDT 24
Peak memory 217388 kb
Host smart-4acdff3d-8329-4447-904a-691ff69231ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449394085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2449394085
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.252141242
Short name T72
Test name
Test status
Simulation time 1876210103 ps
CPU time 6.67 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:51:35 PM PDT 24
Peak memory 217084 kb
Host smart-961ffbc3-cd43-4e03-bd25-5ff5abef4901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252141242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.252141242
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2953381715
Short name T699
Test name
Test status
Simulation time 12251040 ps
CPU time 0.7 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 206284 kb
Host smart-19228c21-778a-4a04-b44c-911d17044c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953381715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2953381715
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4278860473
Short name T970
Test name
Test status
Simulation time 692609605 ps
CPU time 0.92 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:29 PM PDT 24
Peak memory 206720 kb
Host smart-a0d41788-7cb3-4734-a1ce-0b026e308a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278860473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4278860473
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.717652012
Short name T494
Test name
Test status
Simulation time 706293447 ps
CPU time 10.78 seconds
Started Jul 25 05:51:25 PM PDT 24
Finished Jul 25 05:51:36 PM PDT 24
Peak memory 233636 kb
Host smart-6a2f333f-4e66-4e64-8053-557266f99aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717652012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.717652012
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4145938832
Short name T1002
Test name
Test status
Simulation time 14812882 ps
CPU time 0.76 seconds
Started Jul 25 05:51:34 PM PDT 24
Finished Jul 25 05:51:35 PM PDT 24
Peak memory 206080 kb
Host smart-1c8fa3dc-2e1a-4623-adf6-69dddbae8c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145938832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4145938832
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3676088070
Short name T543
Test name
Test status
Simulation time 45109943 ps
CPU time 2.4 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:30 PM PDT 24
Peak memory 233252 kb
Host smart-0f42f38a-66bb-44b9-9d86-9074f421cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676088070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3676088070
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3031172095
Short name T838
Test name
Test status
Simulation time 35320071 ps
CPU time 0.78 seconds
Started Jul 25 05:51:33 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 207572 kb
Host smart-96ffeb3b-c283-4e99-bada-2dd8626ae09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031172095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3031172095
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2984891192
Short name T717
Test name
Test status
Simulation time 33187345523 ps
CPU time 226.31 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:55:24 PM PDT 24
Peak memory 255360 kb
Host smart-772cc16d-ce39-45c0-9b70-fedc5ba38707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984891192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2984891192
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4193329471
Short name T128
Test name
Test status
Simulation time 118699737596 ps
CPU time 265.79 seconds
Started Jul 25 05:51:36 PM PDT 24
Finished Jul 25 05:56:02 PM PDT 24
Peak memory 250228 kb
Host smart-595d199f-83e7-49b8-8899-a942ec8a5c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193329471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4193329471
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3229730452
Short name T787
Test name
Test status
Simulation time 44293652822 ps
CPU time 68.53 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:52:48 PM PDT 24
Peak memory 237276 kb
Host smart-b75b7592-cca2-4313-855b-ea68ea2dcbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229730452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3229730452
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.882318162
Short name T527
Test name
Test status
Simulation time 1334827152 ps
CPU time 10.79 seconds
Started Jul 25 05:51:36 PM PDT 24
Finished Jul 25 05:51:47 PM PDT 24
Peak memory 225424 kb
Host smart-79b26f88-3445-4d29-aa27-23dad57af7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882318162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.882318162
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.599357559
Short name T361
Test name
Test status
Simulation time 2630373138 ps
CPU time 23.53 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:52:01 PM PDT 24
Peak memory 241872 kb
Host smart-fcdce9e4-f7a5-40ad-b7b8-7aecf8e25d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599357559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.599357559
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1531015417
Short name T1000
Test name
Test status
Simulation time 152296794 ps
CPU time 4.16 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:34 PM PDT 24
Peak memory 233688 kb
Host smart-5060d834-d0eb-4c5c-9fff-b38918d037bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531015417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1531015417
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2637944694
Short name T2
Test name
Test status
Simulation time 7156263456 ps
CPU time 64.09 seconds
Started Jul 25 05:51:29 PM PDT 24
Finished Jul 25 05:52:33 PM PDT 24
Peak memory 240416 kb
Host smart-52a78785-fb48-4b9c-bcf1-5273ae357d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637944694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2637944694
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3771246951
Short name T224
Test name
Test status
Simulation time 34705059028 ps
CPU time 29.47 seconds
Started Jul 25 05:51:27 PM PDT 24
Finished Jul 25 05:51:56 PM PDT 24
Peak memory 233684 kb
Host smart-e6bec8d3-762f-4e34-83e2-7a9fd4fc281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771246951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3771246951
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1845589337
Short name T156
Test name
Test status
Simulation time 8697334490 ps
CPU time 9.91 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:40 PM PDT 24
Peak memory 225584 kb
Host smart-8247a76c-fa5e-4b65-bb2a-30c9f431a1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845589337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1845589337
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3183175185
Short name T656
Test name
Test status
Simulation time 453864960 ps
CPU time 6.19 seconds
Started Jul 25 05:51:35 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 221348 kb
Host smart-34ce9c02-bab6-4f71-961e-c0c0c977ffc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3183175185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3183175185
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1799087908
Short name T417
Test name
Test status
Simulation time 43075755678 ps
CPU time 485.47 seconds
Started Jul 25 05:51:42 PM PDT 24
Finished Jul 25 05:59:48 PM PDT 24
Peak memory 274708 kb
Host smart-173043fe-ed22-4e01-b12e-24cad24db1e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799087908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1799087908
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.780965713
Short name T271
Test name
Test status
Simulation time 7411997705 ps
CPU time 25.77 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:56 PM PDT 24
Peak memory 217316 kb
Host smart-4ec756cb-f58b-4c3d-b9ce-c8bba97cf2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780965713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.780965713
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3537501040
Short name T29
Test name
Test status
Simulation time 760032209 ps
CPU time 2.64 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 217148 kb
Host smart-5235a834-9af5-4c25-b185-307e9ac73f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537501040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3537501040
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.802030484
Short name T328
Test name
Test status
Simulation time 532323858 ps
CPU time 2.32 seconds
Started Jul 25 05:51:30 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 217184 kb
Host smart-ff915106-2ee6-4959-9689-329423f5e883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802030484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.802030484
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3072959795
Short name T79
Test name
Test status
Simulation time 254151076 ps
CPU time 0.95 seconds
Started Jul 25 05:51:27 PM PDT 24
Finished Jul 25 05:51:29 PM PDT 24
Peak memory 206752 kb
Host smart-114af8d0-b75e-48d3-93d1-393631b99b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072959795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3072959795
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2473115011
Short name T187
Test name
Test status
Simulation time 4470400100 ps
CPU time 8.3 seconds
Started Jul 25 05:51:28 PM PDT 24
Finished Jul 25 05:51:36 PM PDT 24
Peak memory 233708 kb
Host smart-a5e93fa6-bcc5-4674-bcc2-0b4f487eb9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473115011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2473115011
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.600322998
Short name T55
Test name
Test status
Simulation time 14858303 ps
CPU time 0.73 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 206028 kb
Host smart-f695e57f-c1ef-43cb-a16a-a01ec796ad86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600322998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.600322998
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2308108230
Short name T339
Test name
Test status
Simulation time 427404392 ps
CPU time 2.45 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:51:41 PM PDT 24
Peak memory 225456 kb
Host smart-5b0a0e1d-e964-405c-ab9c-2b7edab2e8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308108230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2308108230
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.480309457
Short name T773
Test name
Test status
Simulation time 22187581 ps
CPU time 0.8 seconds
Started Jul 25 05:51:41 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 207284 kb
Host smart-3a751814-02ba-475d-bf04-8004f4714797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480309457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.480309457
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2373715221
Short name T701
Test name
Test status
Simulation time 10762167557 ps
CPU time 42.71 seconds
Started Jul 25 05:51:41 PM PDT 24
Finished Jul 25 05:52:24 PM PDT 24
Peak memory 252632 kb
Host smart-c3a08eb1-df00-4cd2-abd5-7df33b1e139b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373715221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2373715221
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1739600229
Short name T188
Test name
Test status
Simulation time 12880163547 ps
CPU time 161.58 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:54:20 PM PDT 24
Peak memory 254060 kb
Host smart-3c6a29da-59d1-4212-bf73-c8ec1615bd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739600229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1739600229
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2633246126
Short name T511
Test name
Test status
Simulation time 1485979442 ps
CPU time 23.59 seconds
Started Jul 25 05:51:42 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 252388 kb
Host smart-7fb1b662-740c-41e3-b2fd-f4f5b7b5cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633246126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2633246126
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1114567564
Short name T257
Test name
Test status
Simulation time 982528860 ps
CPU time 26.97 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 225396 kb
Host smart-62a52e3e-34c0-4575-8629-5a3473654c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114567564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1114567564
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4169981985
Short name T956
Test name
Test status
Simulation time 110827449431 ps
CPU time 268.39 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:56:08 PM PDT 24
Peak memory 252912 kb
Host smart-8270cccb-ec27-49b9-aa76-5dba980755af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169981985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4169981985
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.635457356
Short name T632
Test name
Test status
Simulation time 1690723873 ps
CPU time 6.35 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:44 PM PDT 24
Peak memory 228900 kb
Host smart-60dc06fa-bc5c-458a-ae1d-b48ff262a674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635457356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.635457356
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2612861775
Short name T834
Test name
Test status
Simulation time 48537749088 ps
CPU time 49.85 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 250028 kb
Host smart-e888c389-d410-4096-bfbf-aead2a669263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612861775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2612861775
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1017638565
Short name T199
Test name
Test status
Simulation time 21569205696 ps
CPU time 17.6 seconds
Started Jul 25 05:51:41 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 233696 kb
Host smart-1be39ddb-cf6b-4634-8e78-803109bbe207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017638565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1017638565
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.572606158
Short name T613
Test name
Test status
Simulation time 32363899 ps
CPU time 2.37 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 233316 kb
Host smart-85f6ce92-4c58-4461-91b3-c8bbb88134e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572606158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.572606158
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3220073247
Short name T525
Test name
Test status
Simulation time 287121835 ps
CPU time 3.62 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 223952 kb
Host smart-e5a3e3b7-2e60-4f96-b6d6-03073b257c9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3220073247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3220073247
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3359967530
Short name T273
Test name
Test status
Simulation time 1480873373 ps
CPU time 17.48 seconds
Started Jul 25 05:51:43 PM PDT 24
Finished Jul 25 05:52:01 PM PDT 24
Peak memory 217128 kb
Host smart-2847cd4c-0379-4ff7-add4-6f05736c7752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359967530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3359967530
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2766934892
Short name T760
Test name
Test status
Simulation time 3522288131 ps
CPU time 3.15 seconds
Started Jul 25 05:51:36 PM PDT 24
Finished Jul 25 05:51:39 PM PDT 24
Peak memory 217272 kb
Host smart-e900160a-ef32-4906-940c-487cd6912179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766934892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2766934892
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2363958698
Short name T643
Test name
Test status
Simulation time 2412727432 ps
CPU time 4.77 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:51:44 PM PDT 24
Peak memory 217252 kb
Host smart-45b6f89a-ad6b-423b-bf7b-b45b247c16e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363958698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2363958698
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2104555881
Short name T842
Test name
Test status
Simulation time 32842603 ps
CPU time 0.72 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 206820 kb
Host smart-989bcf6a-b242-4a96-b528-faf9bad27eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104555881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2104555881
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1684459813
Short name T348
Test name
Test status
Simulation time 4593419881 ps
CPU time 8.16 seconds
Started Jul 25 05:51:44 PM PDT 24
Finished Jul 25 05:51:52 PM PDT 24
Peak memory 250076 kb
Host smart-b3e51640-cc0e-4fa4-82d7-96a65e45bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684459813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1684459813
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2866894920
Short name T835
Test name
Test status
Simulation time 34859715 ps
CPU time 0.74 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:51:40 PM PDT 24
Peak memory 205508 kb
Host smart-539c4a4b-5d81-4709-8413-cc16a51475b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866894920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2866894920
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2461547401
Short name T359
Test name
Test status
Simulation time 144649436 ps
CPU time 3.83 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 233620 kb
Host smart-ec566a80-8428-4341-a752-58a5daed2b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461547401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2461547401
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3630032482
Short name T65
Test name
Test status
Simulation time 23957082 ps
CPU time 0.82 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:38 PM PDT 24
Peak memory 207284 kb
Host smart-aa25ac7e-5a5f-4ca2-8a81-e8c940744b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630032482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3630032482
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3379797867
Short name T209
Test name
Test status
Simulation time 17933324160 ps
CPU time 132.76 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:53:50 PM PDT 24
Peak memory 257792 kb
Host smart-43a73406-5416-4b3c-920a-1ca5d14a7468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379797867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3379797867
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.263278052
Short name T759
Test name
Test status
Simulation time 17791305830 ps
CPU time 125.32 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:53:43 PM PDT 24
Peak memory 250752 kb
Host smart-2fa6103a-f178-4dd2-b1f8-147ab2aed1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263278052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.263278052
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3342418874
Short name T742
Test name
Test status
Simulation time 2683022518 ps
CPU time 20.49 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 233780 kb
Host smart-0312699b-5989-40fd-953f-29c7be3c858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342418874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3342418874
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.4156477932
Short name T650
Test name
Test status
Simulation time 6004630218 ps
CPU time 11.73 seconds
Started Jul 25 05:51:43 PM PDT 24
Finished Jul 25 05:51:55 PM PDT 24
Peak memory 225492 kb
Host smart-72626e25-f400-4980-b5dd-5c204745a7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156477932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.4156477932
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4013301880
Short name T674
Test name
Test status
Simulation time 170842946 ps
CPU time 3.57 seconds
Started Jul 25 05:51:39 PM PDT 24
Finished Jul 25 05:51:42 PM PDT 24
Peak memory 233640 kb
Host smart-485a6dba-b179-4e4e-bd33-07e25fab1380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013301880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4013301880
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.177118049
Short name T8
Test name
Test status
Simulation time 613346561 ps
CPU time 3.11 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:40 PM PDT 24
Peak memory 233600 kb
Host smart-b85c8b4a-eee2-45bc-b788-275f5e3e0187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177118049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.177118049
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.38416794
Short name T377
Test name
Test status
Simulation time 16631509164 ps
CPU time 14.07 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:51 PM PDT 24
Peak memory 233632 kb
Host smart-d73ee9e9-5ed3-403c-a594-bc6a2b18a43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38416794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.38416794
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3917604693
Short name T577
Test name
Test status
Simulation time 661606987 ps
CPU time 5.46 seconds
Started Jul 25 05:51:42 PM PDT 24
Finished Jul 25 05:51:48 PM PDT 24
Peak memory 225456 kb
Host smart-e0a1ad4f-a346-4333-a199-b32224010794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917604693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3917604693
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1245167359
Short name T951
Test name
Test status
Simulation time 640940890 ps
CPU time 3.93 seconds
Started Jul 25 05:51:43 PM PDT 24
Finished Jul 25 05:51:47 PM PDT 24
Peak memory 220260 kb
Host smart-ed5de69e-1d92-4405-a91c-682c64836fd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1245167359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1245167359
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3619829672
Short name T131
Test name
Test status
Simulation time 364750048306 ps
CPU time 422.29 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:58:41 PM PDT 24
Peak memory 265180 kb
Host smart-59906e2a-4ad6-48ad-9705-08a801d6a168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619829672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3619829672
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1917306231
Short name T282
Test name
Test status
Simulation time 21628525 ps
CPU time 0.77 seconds
Started Jul 25 05:51:42 PM PDT 24
Finished Jul 25 05:51:43 PM PDT 24
Peak memory 206456 kb
Host smart-08a22527-872a-47f6-a018-f2f1e177993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917306231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1917306231
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4275901780
Short name T816
Test name
Test status
Simulation time 1600069260 ps
CPU time 7.04 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:44 PM PDT 24
Peak memory 217248 kb
Host smart-589d3c49-07e4-48f2-89a2-27bf5b8b968b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275901780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4275901780
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.203785417
Short name T1013
Test name
Test status
Simulation time 733406849 ps
CPU time 6.54 seconds
Started Jul 25 05:51:37 PM PDT 24
Finished Jul 25 05:51:44 PM PDT 24
Peak memory 217272 kb
Host smart-28c1dd22-bf63-45d2-b4ae-cefab5dff270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203785417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.203785417
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3787466553
Short name T466
Test name
Test status
Simulation time 205949681 ps
CPU time 0.84 seconds
Started Jul 25 05:51:38 PM PDT 24
Finished Jul 25 05:51:39 PM PDT 24
Peak memory 206820 kb
Host smart-1081c7f2-1d23-4bc4-bdd1-93c2bc52642d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787466553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3787466553
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1733572488
Short name T352
Test name
Test status
Simulation time 7900188283 ps
CPU time 4.97 seconds
Started Jul 25 05:51:40 PM PDT 24
Finished Jul 25 05:51:45 PM PDT 24
Peak memory 225532 kb
Host smart-c363cb67-b2de-4a7e-86c9-c82c7751078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733572488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1733572488
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2066232107
Short name T924
Test name
Test status
Simulation time 46582166 ps
CPU time 0.74 seconds
Started Jul 25 05:51:51 PM PDT 24
Finished Jul 25 05:51:52 PM PDT 24
Peak memory 205980 kb
Host smart-76a1a806-4248-401f-b0be-29350a2513bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066232107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2066232107
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.581449397
Short name T872
Test name
Test status
Simulation time 418741304 ps
CPU time 6.61 seconds
Started Jul 25 05:51:50 PM PDT 24
Finished Jul 25 05:51:57 PM PDT 24
Peak memory 225472 kb
Host smart-ae79b405-e661-4145-a3bd-96be4419435d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581449397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.581449397
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.223225137
Short name T927
Test name
Test status
Simulation time 15432545 ps
CPU time 0.73 seconds
Started Jul 25 05:51:42 PM PDT 24
Finished Jul 25 05:51:43 PM PDT 24
Peak memory 206556 kb
Host smart-811c6210-dda7-49ed-81c5-26c5c9a5ffae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223225137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.223225137
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3576899545
Short name T905
Test name
Test status
Simulation time 8777653091 ps
CPU time 45.32 seconds
Started Jul 25 05:51:48 PM PDT 24
Finished Jul 25 05:52:34 PM PDT 24
Peak memory 258324 kb
Host smart-bacea170-d2ca-443d-90df-934616fe4f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576899545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3576899545
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2612555797
Short name T247
Test name
Test status
Simulation time 4682371737 ps
CPU time 23.86 seconds
Started Jul 25 05:51:46 PM PDT 24
Finished Jul 25 05:52:10 PM PDT 24
Peak memory 225596 kb
Host smart-06b1fa85-e7fa-40b9-9758-7bc796287680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612555797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2612555797
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4165610269
Short name T235
Test name
Test status
Simulation time 10457988859 ps
CPU time 114.31 seconds
Started Jul 25 05:51:47 PM PDT 24
Finished Jul 25 05:53:41 PM PDT 24
Peak memory 258260 kb
Host smart-638017c3-a38f-4a85-b336-77b5bf4260be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165610269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4165610269
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2563039705
Short name T823
Test name
Test status
Simulation time 8792492154 ps
CPU time 36.39 seconds
Started Jul 25 05:51:47 PM PDT 24
Finished Jul 25 05:52:23 PM PDT 24
Peak memory 239200 kb
Host smart-5938df9f-adf2-4b53-890c-e1ba3c7ed1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563039705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2563039705
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1941628999
Short name T919
Test name
Test status
Simulation time 40948874 ps
CPU time 0.82 seconds
Started Jul 25 05:51:49 PM PDT 24
Finished Jul 25 05:51:50 PM PDT 24
Peak memory 216860 kb
Host smart-5dc812e4-2c15-4126-a4e9-9b0ffd7af5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941628999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1941628999
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2349503207
Short name T434
Test name
Test status
Simulation time 3681619229 ps
CPU time 6.55 seconds
Started Jul 25 05:51:51 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 225564 kb
Host smart-242c0a90-3a70-4d1d-b872-5c073e2c33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349503207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2349503207
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1818346605
Short name T666
Test name
Test status
Simulation time 19968631805 ps
CPU time 52.14 seconds
Started Jul 25 05:51:45 PM PDT 24
Finished Jul 25 05:52:38 PM PDT 24
Peak memory 233708 kb
Host smart-f221f410-f6f3-4291-85b8-2e13dfb30a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818346605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1818346605
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1029018134
Short name T223
Test name
Test status
Simulation time 3558979976 ps
CPU time 15.37 seconds
Started Jul 25 05:51:46 PM PDT 24
Finished Jul 25 05:52:02 PM PDT 24
Peak memory 233660 kb
Host smart-5801f694-3689-43cf-9a5a-c9f14e736042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029018134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1029018134
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3552165982
Short name T988
Test name
Test status
Simulation time 29143026870 ps
CPU time 40.31 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:37 PM PDT 24
Peak memory 236188 kb
Host smart-f16a43f6-661c-4d97-b73b-22b71c7154e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552165982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3552165982
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2198363133
Short name T687
Test name
Test status
Simulation time 526583573 ps
CPU time 4.64 seconds
Started Jul 25 05:51:48 PM PDT 24
Finished Jul 25 05:51:52 PM PDT 24
Peak memory 221816 kb
Host smart-5091074a-664a-4955-acd6-24d582386931
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198363133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2198363133
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2780370842
Short name T859
Test name
Test status
Simulation time 221357387771 ps
CPU time 478.67 seconds
Started Jul 25 05:51:51 PM PDT 24
Finished Jul 25 05:59:50 PM PDT 24
Peak memory 268904 kb
Host smart-87c054fd-7fab-430f-9ca0-4ba7dcc342ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780370842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2780370842
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.157356046
Short name T858
Test name
Test status
Simulation time 19153700023 ps
CPU time 27.71 seconds
Started Jul 25 05:51:48 PM PDT 24
Finished Jul 25 05:52:16 PM PDT 24
Peak memory 217256 kb
Host smart-d5f65eb4-98a8-4caf-b19d-cd28f1da11c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157356046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.157356046
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2858113066
Short name T376
Test name
Test status
Simulation time 1419179418 ps
CPU time 8.58 seconds
Started Jul 25 05:51:50 PM PDT 24
Finished Jul 25 05:51:59 PM PDT 24
Peak memory 217176 kb
Host smart-ad332b6d-f3cd-4dd1-81dd-80b926375fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858113066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2858113066
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1882037227
Short name T412
Test name
Test status
Simulation time 899466684 ps
CPU time 2.8 seconds
Started Jul 25 05:51:48 PM PDT 24
Finished Jul 25 05:51:51 PM PDT 24
Peak memory 217100 kb
Host smart-7c074b14-e826-4bff-8116-d65af2e2fcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882037227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1882037227
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.902892969
Short name T1009
Test name
Test status
Simulation time 44516716 ps
CPU time 0.69 seconds
Started Jul 25 05:51:49 PM PDT 24
Finished Jul 25 05:51:50 PM PDT 24
Peak memory 206808 kb
Host smart-1612cd6b-d87a-4867-adf8-bab5ccbfa3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902892969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.902892969
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.356294016
Short name T522
Test name
Test status
Simulation time 111401108 ps
CPU time 2.68 seconds
Started Jul 25 05:51:51 PM PDT 24
Finished Jul 25 05:51:54 PM PDT 24
Peak memory 224816 kb
Host smart-aa89752d-4b8b-4905-bc9f-39aebdc32b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356294016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.356294016
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4279117920
Short name T286
Test name
Test status
Simulation time 114630649 ps
CPU time 0.75 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:00 PM PDT 24
Peak memory 205488 kb
Host smart-b9362508-2e2e-4acb-ab05-a67a35d6f6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279117920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4279117920
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1189985529
Short name T704
Test name
Test status
Simulation time 1855194486 ps
CPU time 3.59 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:00 PM PDT 24
Peak memory 225376 kb
Host smart-cf7122f1-d006-4f63-9d5c-820c35ff8319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189985529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1189985529
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3054399373
Short name T969
Test name
Test status
Simulation time 69716073 ps
CPU time 0.81 seconds
Started Jul 25 05:51:46 PM PDT 24
Finished Jul 25 05:51:47 PM PDT 24
Peak memory 207632 kb
Host smart-8c1a435f-ef56-4810-9b6e-b4ecb535d043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054399373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3054399373
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1179755955
Short name T1022
Test name
Test status
Simulation time 18898150 ps
CPU time 0.72 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:51:58 PM PDT 24
Peak memory 216688 kb
Host smart-dfb3a206-b642-4b9a-8008-6554716b3324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179755955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1179755955
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2169998460
Short name T94
Test name
Test status
Simulation time 18395090039 ps
CPU time 115.22 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:53:55 PM PDT 24
Peak memory 273712 kb
Host smart-1e84c026-d69c-4f9a-9431-01927d2cc9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169998460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2169998460
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.373280171
Short name T252
Test name
Test status
Simulation time 133316093547 ps
CPU time 384.81 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:58:23 PM PDT 24
Peak memory 274520 kb
Host smart-68c125ff-2203-4b3b-8742-a576f09d61b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373280171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.373280171
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1413448823
Short name T475
Test name
Test status
Simulation time 6330247696 ps
CPU time 20.67 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:18 PM PDT 24
Peak memory 241912 kb
Host smart-9956ff90-3af7-4a49-a377-45afeba14d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413448823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1413448823
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2970042595
Short name T180
Test name
Test status
Simulation time 93042029842 ps
CPU time 173.35 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:54:51 PM PDT 24
Peak memory 250080 kb
Host smart-b761e6c0-0a17-44a7-b8e8-e46c52a08cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970042595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2970042595
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2329025202
Short name T713
Test name
Test status
Simulation time 964415045 ps
CPU time 13.17 seconds
Started Jul 25 05:51:56 PM PDT 24
Finished Jul 25 05:52:09 PM PDT 24
Peak memory 225472 kb
Host smart-a35b246a-d33e-41ff-ab26-8c9745e2a973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329025202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2329025202
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.180971486
Short name T485
Test name
Test status
Simulation time 5257011132 ps
CPU time 32.76 seconds
Started Jul 25 05:51:59 PM PDT 24
Finished Jul 25 05:52:32 PM PDT 24
Peak memory 241632 kb
Host smart-158ca9cd-f1e7-4909-88d8-e6bd83c55dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180971486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.180971486
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.672589984
Short name T409
Test name
Test status
Simulation time 130929951 ps
CPU time 2.4 seconds
Started Jul 25 05:51:45 PM PDT 24
Finished Jul 25 05:51:48 PM PDT 24
Peak memory 233336 kb
Host smart-2603cc8d-1b07-4ac1-ac3c-7b226787afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672589984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.672589984
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1996813370
Short name T915
Test name
Test status
Simulation time 1473167872 ps
CPU time 6.04 seconds
Started Jul 25 05:51:50 PM PDT 24
Finished Jul 25 05:51:56 PM PDT 24
Peak memory 225472 kb
Host smart-0da99326-be7a-463d-b9af-14d12393ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996813370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1996813370
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1434030271
Short name T371
Test name
Test status
Simulation time 209195016 ps
CPU time 4.2 seconds
Started Jul 25 05:52:00 PM PDT 24
Finished Jul 25 05:52:05 PM PDT 24
Peak memory 220096 kb
Host smart-3e5fbffc-2484-4677-95f5-0cde32e25ff3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1434030271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1434030271
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3925630278
Short name T19
Test name
Test status
Simulation time 109105546 ps
CPU time 1.16 seconds
Started Jul 25 05:51:58 PM PDT 24
Finished Jul 25 05:51:59 PM PDT 24
Peak memory 207784 kb
Host smart-a23305fb-52c1-448b-b8ce-c0f2ecd1135f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925630278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3925630278
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4180501076
Short name T546
Test name
Test status
Simulation time 2124734003 ps
CPU time 11.75 seconds
Started Jul 25 05:51:47 PM PDT 24
Finished Jul 25 05:51:59 PM PDT 24
Peak memory 217192 kb
Host smart-542f1ee4-b19d-4524-83b2-2d96272706dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180501076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4180501076
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.321369902
Short name T987
Test name
Test status
Simulation time 1231898691 ps
CPU time 5.13 seconds
Started Jul 25 05:51:48 PM PDT 24
Finished Jul 25 05:51:53 PM PDT 24
Peak memory 217160 kb
Host smart-5af67e04-dc47-464c-b710-19f5598e6361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321369902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.321369902
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.913719773
Short name T384
Test name
Test status
Simulation time 1132280842 ps
CPU time 4.38 seconds
Started Jul 25 05:51:47 PM PDT 24
Finished Jul 25 05:51:51 PM PDT 24
Peak memory 217128 kb
Host smart-6647e973-8bfb-431a-8e77-7a840856e458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913719773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.913719773
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3491748979
Short name T410
Test name
Test status
Simulation time 14004081 ps
CPU time 0.71 seconds
Started Jul 25 05:51:49 PM PDT 24
Finished Jul 25 05:51:50 PM PDT 24
Peak memory 206264 kb
Host smart-829f271e-ab3b-4b6e-9e74-b451fb1faa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491748979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3491748979
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1387311036
Short name T404
Test name
Test status
Simulation time 44040127001 ps
CPU time 30.45 seconds
Started Jul 25 05:51:57 PM PDT 24
Finished Jul 25 05:52:27 PM PDT 24
Peak memory 233732 kb
Host smart-93171634-17e4-46fd-984b-537ef254503b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387311036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1387311036
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.87808247
Short name T568
Test name
Test status
Simulation time 45331452 ps
CPU time 0.68 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:16 PM PDT 24
Peak memory 205500 kb
Host smart-529d6f0c-42f7-4c06-8ba6-665dbf887a7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87808247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.87808247
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.139596613
Short name T681
Test name
Test status
Simulation time 1317708756 ps
CPU time 7.02 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:48:25 PM PDT 24
Peak memory 233676 kb
Host smart-157abc64-7ea0-48a4-ac46-769c8a962f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139596613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.139596613
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4152940684
Short name T733
Test name
Test status
Simulation time 106481911 ps
CPU time 0.77 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:16 PM PDT 24
Peak memory 206584 kb
Host smart-2ca7e9b6-64d1-4a8f-b17a-15a700598428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152940684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4152940684
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.810304112
Short name T204
Test name
Test status
Simulation time 27334984561 ps
CPU time 209.29 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:51:46 PM PDT 24
Peak memory 253396 kb
Host smart-5845a2b4-c95b-4392-8c43-8a5a1413d82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810304112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.810304112
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1412699930
Short name T806
Test name
Test status
Simulation time 7046313542 ps
CPU time 124.39 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:50:20 PM PDT 24
Peak memory 253836 kb
Host smart-f9c8c296-fa9e-48b8-b72e-5d9923ee4caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412699930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1412699930
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3928933971
Short name T861
Test name
Test status
Simulation time 33228119540 ps
CPU time 388.52 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:54:46 PM PDT 24
Peak memory 274504 kb
Host smart-dfdd93ba-cdca-4661-8af3-c2dfbe528aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928933971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3928933971
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.26616380
Short name T916
Test name
Test status
Simulation time 896428159 ps
CPU time 4.89 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:20 PM PDT 24
Peak memory 225424 kb
Host smart-5c72726e-f16f-4ae5-a7a3-9dee2a2a665e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26616380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.26616380
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2344420370
Short name T1015
Test name
Test status
Simulation time 45048843549 ps
CPU time 76.46 seconds
Started Jul 25 05:48:19 PM PDT 24
Finished Jul 25 05:49:35 PM PDT 24
Peak memory 241844 kb
Host smart-5af883b6-5d9f-46b7-98f7-eb10021200a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344420370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2344420370
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2103330725
Short name T630
Test name
Test status
Simulation time 6400969881 ps
CPU time 13.23 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:27 PM PDT 24
Peak memory 225536 kb
Host smart-fb20fcaf-8d98-4323-b527-f818486dbb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103330725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2103330725
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1174786721
Short name T189
Test name
Test status
Simulation time 12464734185 ps
CPU time 51.45 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:49:09 PM PDT 24
Peak memory 249980 kb
Host smart-05d1eff5-0880-48a1-ba41-9471f3f966da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174786721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1174786721
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.950685488
Short name T620
Test name
Test status
Simulation time 53112165 ps
CPU time 1.06 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 217412 kb
Host smart-779b9379-61f5-4510-9699-bdb47bd7982a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950685488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.950685488
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.813011271
Short name T87
Test name
Test status
Simulation time 21897833819 ps
CPU time 17.94 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:48:35 PM PDT 24
Peak memory 241324 kb
Host smart-09261e50-d612-4925-9120-85a257d1690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813011271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
813011271
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3968024722
Short name T695
Test name
Test status
Simulation time 559675624 ps
CPU time 2.42 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 225440 kb
Host smart-93c0d964-29c5-42f0-b016-3b4ff28865bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968024722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3968024722
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.613975302
Short name T364
Test name
Test status
Simulation time 319827045 ps
CPU time 3.82 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 221640 kb
Host smart-124bf108-ed64-4e88-b77f-ee275c268e7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613975302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.613975302
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1600086182
Short name T603
Test name
Test status
Simulation time 1627474108 ps
CPU time 27.54 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 233668 kb
Host smart-d971ee58-becc-4f71-a6dc-9921899743f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600086182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1600086182
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2021585095
Short name T900
Test name
Test status
Simulation time 17326852 ps
CPU time 0.75 seconds
Started Jul 25 05:48:21 PM PDT 24
Finished Jul 25 05:48:22 PM PDT 24
Peak memory 206376 kb
Host smart-c6a85ca4-475c-476e-8c2b-9745ba87b6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021585095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2021585095
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.4131839376
Short name T673
Test name
Test status
Simulation time 548694534 ps
CPU time 3.39 seconds
Started Jul 25 05:48:14 PM PDT 24
Finished Jul 25 05:48:17 PM PDT 24
Peak memory 217096 kb
Host smart-d1261e42-4b81-4e3e-a2c3-af2938f287d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131839376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.4131839376
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.912933466
Short name T882
Test name
Test status
Simulation time 177293731 ps
CPU time 1.56 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 217112 kb
Host smart-5c79bfc3-0550-427c-960f-d252b50f339f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912933466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.912933466
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4065483844
Short name T820
Test name
Test status
Simulation time 222137340 ps
CPU time 0.89 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:17 PM PDT 24
Peak memory 206748 kb
Host smart-b0656d5a-7d84-4284-9f55-117a9c2fd04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065483844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4065483844
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2582395792
Short name T422
Test name
Test status
Simulation time 2365429404 ps
CPU time 9.1 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:48:26 PM PDT 24
Peak memory 233664 kb
Host smart-8777de77-52de-473c-9038-02402829db37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582395792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2582395792
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.116714939
Short name T491
Test name
Test status
Simulation time 14216598 ps
CPU time 0.74 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:16 PM PDT 24
Peak memory 206060 kb
Host smart-3027f47f-c447-4cb4-834a-a6c4473c1f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116714939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.116714939
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2386345375
Short name T966
Test name
Test status
Simulation time 141787983 ps
CPU time 2.2 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:16 PM PDT 24
Peak memory 224044 kb
Host smart-4cbca69d-35b2-46f6-ba28-626675c27801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386345375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2386345375
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3938869786
Short name T500
Test name
Test status
Simulation time 44148969 ps
CPU time 0.8 seconds
Started Jul 25 05:48:17 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 207296 kb
Host smart-a5945ac0-128e-458e-9c14-b07f30226c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938869786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3938869786
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.279208466
Short name T242
Test name
Test status
Simulation time 91527820165 ps
CPU time 650.59 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:59:07 PM PDT 24
Peak memory 262304 kb
Host smart-d4e59d28-ffae-48a8-aa6b-2382a3fc1ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279208466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.279208466
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1380205978
Short name T216
Test name
Test status
Simulation time 114192758159 ps
CPU time 285.04 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:53:01 PM PDT 24
Peak memory 250156 kb
Host smart-acc01a5f-7152-4d3b-abfd-20ed69fe8443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380205978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1380205978
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2805041822
Short name T185
Test name
Test status
Simulation time 3634148003 ps
CPU time 80.45 seconds
Started Jul 25 05:48:12 PM PDT 24
Finished Jul 25 05:49:33 PM PDT 24
Peak memory 258324 kb
Host smart-e80bca6f-0f1b-460e-8755-dfc5e78764bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805041822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2805041822
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.975219845
Short name T440
Test name
Test status
Simulation time 1613798214 ps
CPU time 28.71 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 233680 kb
Host smart-2f5ec5f3-13d3-4b98-84db-e4f1c9125eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975219845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.975219845
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2343667199
Short name T44
Test name
Test status
Simulation time 22871403300 ps
CPU time 209.64 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:51:45 PM PDT 24
Peak memory 254660 kb
Host smart-f3a5eb67-a80d-4698-b8f7-09da6f8519cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343667199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2343667199
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3467025607
Short name T499
Test name
Test status
Simulation time 44130479 ps
CPU time 2.92 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:19 PM PDT 24
Peak memory 233628 kb
Host smart-adaf4bc9-3b4a-4925-8251-f0d7c897a9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467025607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3467025607
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.625880071
Short name T506
Test name
Test status
Simulation time 1885500156 ps
CPU time 15.43 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 225480 kb
Host smart-555680ce-3344-4c8c-a2b5-8be9cb9e741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625880071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.625880071
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.266792484
Short name T37
Test name
Test status
Simulation time 27455862 ps
CPU time 1.06 seconds
Started Jul 25 05:48:18 PM PDT 24
Finished Jul 25 05:48:19 PM PDT 24
Peak memory 217436 kb
Host smart-0f04acff-761a-4ac1-b456-ddc5c20e7aab
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266792484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.266792484
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3298925011
Short name T754
Test name
Test status
Simulation time 14458170017 ps
CPU time 11.97 seconds
Started Jul 25 05:48:18 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 225496 kb
Host smart-3a99eb9f-e39f-42c3-967d-6ca0a07bf594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298925011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3298925011
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3164222747
Short name T219
Test name
Test status
Simulation time 267213706 ps
CPU time 3.52 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:20 PM PDT 24
Peak memory 225384 kb
Host smart-6b1a9b6a-6dd3-4b47-80a3-7acacadd5e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164222747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3164222747
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2078458840
Short name T925
Test name
Test status
Simulation time 701641764 ps
CPU time 4.35 seconds
Started Jul 25 05:48:19 PM PDT 24
Finished Jul 25 05:48:24 PM PDT 24
Peak memory 221312 kb
Host smart-4e791036-c880-4c05-81ea-5e3ac9bedb79
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2078458840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2078458840
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1790463914
Short name T993
Test name
Test status
Simulation time 6025674269 ps
CPU time 28.89 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 217220 kb
Host smart-ff985f28-0ff3-499b-acd1-9808ecffee45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790463914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1790463914
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3526406280
Short name T696
Test name
Test status
Simulation time 1794685394 ps
CPU time 7.53 seconds
Started Jul 25 05:48:19 PM PDT 24
Finished Jul 25 05:48:26 PM PDT 24
Peak memory 217232 kb
Host smart-d0c62dc9-cd44-4648-9ff8-939ac97d0472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526406280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3526406280
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1125676131
Short name T606
Test name
Test status
Simulation time 381782521 ps
CPU time 2.04 seconds
Started Jul 25 05:48:15 PM PDT 24
Finished Jul 25 05:48:18 PM PDT 24
Peak memory 217164 kb
Host smart-f867b986-f1c0-421a-be16-b1228b2407e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125676131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1125676131
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1523258842
Short name T498
Test name
Test status
Simulation time 29291332 ps
CPU time 0.89 seconds
Started Jul 25 05:48:18 PM PDT 24
Finished Jul 25 05:48:19 PM PDT 24
Peak memory 207816 kb
Host smart-85833bad-f304-4d7e-8ff5-69b657bb637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523258842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1523258842
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.739400443
Short name T891
Test name
Test status
Simulation time 53138137 ps
CPU time 2.28 seconds
Started Jul 25 05:48:16 PM PDT 24
Finished Jul 25 05:48:19 PM PDT 24
Peak memory 225008 kb
Host smart-98eb3bdd-b44b-4683-b23e-a1f6bca39d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739400443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.739400443
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2506454712
Short name T875
Test name
Test status
Simulation time 21322310 ps
CPU time 0.71 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:29 PM PDT 24
Peak memory 205504 kb
Host smart-85cb381b-9d99-4b31-96b3-097fb9c0d48e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506454712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
506454712
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1332900719
Short name T570
Test name
Test status
Simulation time 1157349589 ps
CPU time 4.4 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 225400 kb
Host smart-6b19121a-0c3a-49ac-9646-18ea191993c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332900719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1332900719
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.4282940337
Short name T420
Test name
Test status
Simulation time 21124655 ps
CPU time 0.84 seconds
Started Jul 25 05:48:13 PM PDT 24
Finished Jul 25 05:48:14 PM PDT 24
Peak memory 207188 kb
Host smart-84a06875-2b9e-4506-b6bf-d6cfe439210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282940337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.4282940337
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3217770691
Short name T4
Test name
Test status
Simulation time 590105529 ps
CPU time 10.63 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:48:37 PM PDT 24
Peak memory 237364 kb
Host smart-1c88931c-6d12-4c39-b36d-5c4755d8d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217770691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3217770691
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.4220909802
Short name T354
Test name
Test status
Simulation time 66782223190 ps
CPU time 125.27 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 268624 kb
Host smart-b4a63026-ba7b-4e16-b00a-aa85af08128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220909802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.4220909802
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1681196508
Short name T751
Test name
Test status
Simulation time 7403389584 ps
CPU time 58.24 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:49:24 PM PDT 24
Peak memory 235564 kb
Host smart-35253b1c-db2a-40ef-842b-2d8a169d1676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681196508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1681196508
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3432957178
Short name T741
Test name
Test status
Simulation time 981576527 ps
CPU time 6.39 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:31 PM PDT 24
Peak memory 225452 kb
Host smart-b385e4a4-6cc3-4b55-894f-9dfade2e46b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432957178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3432957178
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3968745765
Short name T936
Test name
Test status
Simulation time 1009131722 ps
CPU time 7.22 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:33 PM PDT 24
Peak memory 225408 kb
Host smart-b803159b-f628-45de-b78d-ed94413ba9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968745765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3968745765
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3440986851
Short name T828
Test name
Test status
Simulation time 1835918306 ps
CPU time 7 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:36 PM PDT 24
Peak memory 233552 kb
Host smart-863347d5-2712-4f0f-b316-c3a764d89957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440986851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3440986851
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.363506431
Short name T471
Test name
Test status
Simulation time 647451141 ps
CPU time 5.31 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:33 PM PDT 24
Peak memory 225428 kb
Host smart-195087ca-553e-4a36-a879-06b7eda35712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363506431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.363506431
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4185732321
Short name T36
Test name
Test status
Simulation time 141588478 ps
CPU time 1.13 seconds
Started Jul 25 05:48:19 PM PDT 24
Finished Jul 25 05:48:20 PM PDT 24
Peak memory 217348 kb
Host smart-8779fd38-37e1-42df-ac34-d18bd74e29c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185732321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4185732321
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1426324096
Short name T625
Test name
Test status
Simulation time 10232648489 ps
CPU time 9.45 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 225460 kb
Host smart-f808fbb7-58d5-442c-9ab8-d1f21d651f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426324096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1426324096
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1081230183
Short name T1010
Test name
Test status
Simulation time 5409954920 ps
CPU time 15.64 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 233688 kb
Host smart-a87239d5-4ef9-4b3e-a512-bc499a4ed5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081230183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1081230183
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.972257180
Short name T340
Test name
Test status
Simulation time 469515853 ps
CPU time 6.99 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:48:33 PM PDT 24
Peak memory 223896 kb
Host smart-8e1f5f0f-936d-48a9-9c94-e884c3b59dea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972257180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.972257180
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1632903142
Short name T685
Test name
Test status
Simulation time 31670181645 ps
CPU time 47.3 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:49:14 PM PDT 24
Peak memory 225528 kb
Host smart-15dfc05d-3aeb-4fde-b28b-2634b0d7bf8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632903142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1632903142
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.64580907
Short name T856
Test name
Test status
Simulation time 840611668 ps
CPU time 7.88 seconds
Started Jul 25 05:48:23 PM PDT 24
Finished Jul 25 05:48:31 PM PDT 24
Peak memory 218600 kb
Host smart-6f344c55-bca2-4ca0-940c-10cbfc10c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64580907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.64580907
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2635623016
Short name T438
Test name
Test status
Simulation time 13493679450 ps
CPU time 7.27 seconds
Started Jul 25 05:48:30 PM PDT 24
Finished Jul 25 05:48:37 PM PDT 24
Peak memory 217204 kb
Host smart-53880d77-ec51-4c6c-b590-dcdbe526c243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635623016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2635623016
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3772312208
Short name T303
Test name
Test status
Simulation time 178889854 ps
CPU time 3.47 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:31 PM PDT 24
Peak memory 217152 kb
Host smart-0e607ef4-e4dc-4286-8a0c-4aa0df35d4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772312208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3772312208
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4077864234
Short name T892
Test name
Test status
Simulation time 218274165 ps
CPU time 0.75 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 206740 kb
Host smart-79eaff26-3ead-4a68-9b0c-31a13a524e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077864234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4077864234
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2253970242
Short name T221
Test name
Test status
Simulation time 8912736277 ps
CPU time 9.55 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:37 PM PDT 24
Peak memory 225512 kb
Host smart-7466f6e6-cd91-48f8-9f72-dec20b4915c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253970242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2253970242
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1898445602
Short name T604
Test name
Test status
Simulation time 49915866 ps
CPU time 0.72 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:26 PM PDT 24
Peak memory 206376 kb
Host smart-72762caa-3028-4d68-96b2-5288fe16f30d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898445602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
898445602
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1442632837
Short name T490
Test name
Test status
Simulation time 1129315967 ps
CPU time 3.13 seconds
Started Jul 25 05:48:29 PM PDT 24
Finished Jul 25 05:48:32 PM PDT 24
Peak memory 233576 kb
Host smart-2d2de4fe-8bbe-4386-a2f8-b6140760efe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442632837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1442632837
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.460657587
Short name T1008
Test name
Test status
Simulation time 289412362 ps
CPU time 0.81 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 207288 kb
Host smart-4cd68a42-bb0c-4e9b-b550-dd8f6b8635b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460657587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.460657587
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3096632203
Short name T621
Test name
Test status
Simulation time 75244904959 ps
CPU time 260.16 seconds
Started Jul 25 05:48:24 PM PDT 24
Finished Jul 25 05:52:44 PM PDT 24
Peak memory 250024 kb
Host smart-3c8f254b-9ccd-4784-b42d-33923ed4f752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096632203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3096632203
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1763069561
Short name T250
Test name
Test status
Simulation time 49126237285 ps
CPU time 308.09 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:53:39 PM PDT 24
Peak memory 266556 kb
Host smart-bb73cfef-143a-4dd5-b119-4afb0925174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763069561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1763069561
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1538939039
Short name T129
Test name
Test status
Simulation time 6895694421 ps
CPU time 96.65 seconds
Started Jul 25 05:48:24 PM PDT 24
Finished Jul 25 05:50:00 PM PDT 24
Peak memory 258364 kb
Host smart-7f9d0e23-e467-4f81-bbd3-1413e5dee0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538939039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1538939039
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1877404711
Short name T961
Test name
Test status
Simulation time 1589355116 ps
CPU time 12.34 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:48:43 PM PDT 24
Peak memory 238660 kb
Host smart-48dde316-5869-4e2e-beac-3bb4190cbb27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877404711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1877404711
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1692284289
Short name T898
Test name
Test status
Simulation time 46368466 ps
CPU time 0.74 seconds
Started Jul 25 05:48:23 PM PDT 24
Finished Jul 25 05:48:24 PM PDT 24
Peak memory 216660 kb
Host smart-296aec87-0499-414b-b74d-33f8548d9d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692284289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1692284289
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3601401479
Short name T707
Test name
Test status
Simulation time 136242462 ps
CPU time 2.53 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 225380 kb
Host smart-f874c172-2d06-4e05-9ef8-75a963f9627d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601401479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3601401479
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1114458703
Short name T446
Test name
Test status
Simulation time 473795535 ps
CPU time 5.13 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 233644 kb
Host smart-ab6166a8-ab83-4c76-8d5d-2e371925bcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114458703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1114458703
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1286638410
Short name T314
Test name
Test status
Simulation time 15314899 ps
CPU time 1.05 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:48:32 PM PDT 24
Peak memory 217420 kb
Host smart-fe583c21-1daf-4661-bac8-12db2981a024
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286638410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1286638410
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3887364266
Short name T938
Test name
Test status
Simulation time 7230584970 ps
CPU time 20.42 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:48 PM PDT 24
Peak memory 233660 kb
Host smart-351c3754-9009-405f-b6c9-dbe7da565c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887364266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3887364266
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3807143402
Short name T989
Test name
Test status
Simulation time 4366554849 ps
CPU time 7.74 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:33 PM PDT 24
Peak memory 233740 kb
Host smart-bd0d44d4-2388-4bbb-871c-72e27d2ec502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807143402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3807143402
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1249772622
Short name T1012
Test name
Test status
Simulation time 3472200944 ps
CPU time 12.01 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 223988 kb
Host smart-cb6090f5-34e7-4ea8-9424-9e753579d0cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1249772622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1249772622
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2927325386
Short name T571
Test name
Test status
Simulation time 1481772705 ps
CPU time 29.72 seconds
Started Jul 25 05:48:24 PM PDT 24
Finished Jul 25 05:48:54 PM PDT 24
Peak memory 250432 kb
Host smart-c278a101-0925-4561-814c-63afa808c01b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927325386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2927325386
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2495844983
Short name T269
Test name
Test status
Simulation time 1813327901 ps
CPU time 21.87 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:49 PM PDT 24
Peak memory 217444 kb
Host smart-948f4b70-ebff-4ca0-860d-1af1daa868d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495844983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2495844983
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2567199657
Short name T77
Test name
Test status
Simulation time 1301363857 ps
CPU time 6.45 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:34 PM PDT 24
Peak memory 217188 kb
Host smart-72f84636-8a44-4961-a738-747cc8da8161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567199657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2567199657
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3188057296
Short name T582
Test name
Test status
Simulation time 1272625784 ps
CPU time 4.58 seconds
Started Jul 25 05:48:23 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 217156 kb
Host smart-43dd28bc-a3a6-4f26-9d52-2d862f9ee2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188057296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3188057296
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.56887789
Short name T449
Test name
Test status
Simulation time 117526219 ps
CPU time 1.06 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 207732 kb
Host smart-8aff8bd6-6537-4a32-9930-4f376f324cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56887789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.56887789
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.785175237
Short name T68
Test name
Test status
Simulation time 1173504323 ps
CPU time 4.26 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:29 PM PDT 24
Peak memory 225440 kb
Host smart-d6231adf-c02e-448e-995c-fec5b5d93c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785175237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.785175237
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1859964177
Short name T959
Test name
Test status
Simulation time 14649436 ps
CPU time 0.76 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:28 PM PDT 24
Peak memory 205500 kb
Host smart-a03f45a0-08e3-455a-8d8d-a2bf18f9a60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859964177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
859964177
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2429013779
Short name T744
Test name
Test status
Simulation time 2200964375 ps
CPU time 12.5 seconds
Started Jul 25 05:48:30 PM PDT 24
Finished Jul 25 05:48:42 PM PDT 24
Peak memory 225452 kb
Host smart-9bf9b5ab-4c25-482d-98a3-a68e8e3975b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429013779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2429013779
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2958050149
Short name T481
Test name
Test status
Simulation time 65113295 ps
CPU time 0.77 seconds
Started Jul 25 05:48:30 PM PDT 24
Finished Jul 25 05:48:31 PM PDT 24
Peak memory 207584 kb
Host smart-33dbc57a-8d85-4e6f-bea9-7f713fa05256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958050149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2958050149
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1491430686
Short name T182
Test name
Test status
Simulation time 1185993197 ps
CPU time 9.35 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 225464 kb
Host smart-7a7c2b47-965f-4258-8436-91d931a387b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491430686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1491430686
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3332981291
Short name T745
Test name
Test status
Simulation time 14028859093 ps
CPU time 69.8 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:49:35 PM PDT 24
Peak memory 253952 kb
Host smart-2f80b41a-6288-43f3-93f3-bfeb430ea67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332981291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3332981291
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3155074503
Short name T227
Test name
Test status
Simulation time 6059463236 ps
CPU time 81.42 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:49:48 PM PDT 24
Peak memory 255848 kb
Host smart-3e6d11e8-36e9-4b01-b7aa-dc525441641c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155074503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3155074503
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1679376638
Short name T896
Test name
Test status
Simulation time 44570488 ps
CPU time 3.22 seconds
Started Jul 25 05:48:26 PM PDT 24
Finished Jul 25 05:48:29 PM PDT 24
Peak memory 233584 kb
Host smart-bf6e498b-518b-465a-a2fc-0ccb77a22787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679376638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1679376638
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.227013783
Short name T832
Test name
Test status
Simulation time 710361281 ps
CPU time 10.41 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:38 PM PDT 24
Peak memory 233672 kb
Host smart-67a6a8ce-7175-49cc-9ebc-970fe5e15c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227013783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
227013783
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3379010031
Short name T669
Test name
Test status
Simulation time 78057340 ps
CPU time 3.45 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 225444 kb
Host smart-f75263a3-667c-4bee-b153-1f9a2299b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379010031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3379010031
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3357425433
Short name T367
Test name
Test status
Simulation time 9559916165 ps
CPU time 78.69 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:49:43 PM PDT 24
Peak memory 241520 kb
Host smart-3daf91b8-d66c-4dd1-8ed4-49cef9cb28f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357425433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3357425433
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4071938072
Short name T965
Test name
Test status
Simulation time 59417597 ps
CPU time 1.12 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:48:32 PM PDT 24
Peak memory 217392 kb
Host smart-1793b5d2-5137-4cb3-b699-7be7bd60c062
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071938072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4071938072
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2205721817
Short name T612
Test name
Test status
Simulation time 2078847783 ps
CPU time 5.67 seconds
Started Jul 25 05:48:30 PM PDT 24
Finished Jul 25 05:48:36 PM PDT 24
Peak memory 233620 kb
Host smart-4a48db71-c7e1-4f89-9588-c1996be649e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205721817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2205721817
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3168075215
Short name T946
Test name
Test status
Simulation time 4338157859 ps
CPU time 5.75 seconds
Started Jul 25 05:48:24 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 241256 kb
Host smart-a5ea00b4-c43e-4584-87ac-dd106459f5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168075215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3168075215
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.267054395
Short name T1007
Test name
Test status
Simulation time 2133032413 ps
CPU time 18.58 seconds
Started Jul 25 05:48:25 PM PDT 24
Finished Jul 25 05:48:44 PM PDT 24
Peak memory 221212 kb
Host smart-b893a2e1-2dc4-4e12-b7b8-8fc00213670b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=267054395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.267054395
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1002302096
Short name T162
Test name
Test status
Simulation time 11069288688 ps
CPU time 104.25 seconds
Started Jul 25 05:48:31 PM PDT 24
Finished Jul 25 05:50:16 PM PDT 24
Peak memory 241948 kb
Host smart-352501ef-a58e-4c3b-af3d-daa8a2df34a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002302096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1002302096
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.645330866
Short name T918
Test name
Test status
Simulation time 771238424 ps
CPU time 5.58 seconds
Started Jul 25 05:48:29 PM PDT 24
Finished Jul 25 05:48:35 PM PDT 24
Peak memory 217120 kb
Host smart-51893162-d221-41a0-88f6-9fccf9ad6373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645330866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.645330866
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.588558093
Short name T729
Test name
Test status
Simulation time 3788473877 ps
CPU time 10.6 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:39 PM PDT 24
Peak memory 217240 kb
Host smart-70165876-7db7-432b-bc5e-6ae0b0828ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588558093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.588558093
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2055074348
Short name T344
Test name
Test status
Simulation time 37072401 ps
CPU time 1.18 seconds
Started Jul 25 05:48:28 PM PDT 24
Finished Jul 25 05:48:30 PM PDT 24
Peak memory 208724 kb
Host smart-ba895e3c-3816-4a08-be37-36befeab15b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055074348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2055074348
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1691887817
Short name T445
Test name
Test status
Simulation time 247085591 ps
CPU time 0.85 seconds
Started Jul 25 05:48:21 PM PDT 24
Finished Jul 25 05:48:22 PM PDT 24
Peak memory 206732 kb
Host smart-43b770b4-7f0b-4ae7-a09a-b8edba840769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691887817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1691887817
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.2112095447
Short name T486
Test name
Test status
Simulation time 577406853 ps
CPU time 2.3 seconds
Started Jul 25 05:48:27 PM PDT 24
Finished Jul 25 05:48:29 PM PDT 24
Peak memory 223868 kb
Host smart-c0992710-b770-4d3e-ae14-2d643bd89c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112095447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2112095447
Directory /workspace/9.spi_device_upload/latest
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