Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2447084	1			T1	1		T3	1		T4	102
all_values[1]	2447084	1			T1	1		T3	1		T4	102
all_values[2]	2447084	1			T1	1		T3	1		T4	102
all_values[3]	2447084	1			T1	1		T3	1		T4	102
all_values[4]	2447084	1			T1	1		T3	1		T4	102
all_values[5]	2447084	1			T1	1		T3	1		T4	102
all_values[6]	2447084	1			T1	1		T3	1		T4	102
all_values[7]	2447084	1			T1	1		T3	1		T4	102

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19425539

1

T1

8

T3

8

T4

816

auto[1]

151133

1

T6

32

T14

103994

T15

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19551301

1

T1

8

T3

8

T4

816

auto[1]

25371

1

T6

34

T7

214

T8

44

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2434947	1			T1	1		T3	1		T4	102
all_values[0]	auto[0]	auto[1]	11613	1			T6	3		T7	125		T8	31
all_values[0]	auto[1]	auto[0]	321	1			T6	3		T16	5		T18	5
all_values[0]	auto[1]	auto[1]	203	1			T6	3		T16	2		T18	3
all_values[1]	auto[0]	auto[0]	2407978	1			T1	1		T3	1		T4	102
all_values[1]	auto[0]	auto[1]	7963	1			T7	69		T8	13		T11	59
all_values[1]	auto[1]	auto[0]	30839	1			T6	6		T14	25904		T16	4
all_values[1]	auto[1]	auto[1]	304	1			T6	3		T14	95		T16	2
all_values[2]	auto[0]	auto[0]	2412553	1			T1	1		T3	1		T4	102
all_values[2]	auto[0]	auto[1]	3162	1			T6	4		T7	20		T11	33
all_values[2]	auto[1]	auto[0]	31176	1			T14	25991		T15	1		T16	4
all_values[2]	auto[1]	auto[1]	193	1			T6	1		T14	7		T16	2
all_values[3]	auto[0]	auto[0]	2440306	1			T1	1		T3	1		T4	102
all_values[3]	auto[0]	auto[1]	228	1			T6	2		T14	1		T16	2
all_values[3]	auto[1]	auto[0]	6369	1			T15	4		T16	1		T18	4
all_values[3]	auto[1]	auto[1]	181	1			T6	3		T15	1		T16	1
all_values[4]	auto[0]	auto[0]	2410832	1			T1	1		T3	1		T4	102
all_values[4]	auto[0]	auto[1]	212	1			T6	5		T14	1		T140	2
all_values[4]	auto[1]	auto[0]	35866	1			T6	1		T14	25996		T15	2
all_values[4]	auto[1]	auto[1]	174	1			T6	1		T14	2		T16	1
all_values[5]	auto[0]	auto[0]	2443373	1			T1	1		T3	1		T4	102
all_values[5]	auto[0]	auto[1]	181	1			T6	1		T15	1		T16	1
all_values[5]	auto[1]	auto[0]	3348	1			T6	5		T15	2		T18	4
all_values[5]	auto[1]	auto[1]	182	1			T6	1		T14	1		T15	2
all_values[6]	auto[0]	auto[0]	2412909	1			T1	1		T3	1		T4	102
all_values[6]	auto[0]	auto[1]	211	1			T14	1		T18	3		T19	12
all_values[6]	auto[1]	auto[0]	33779	1			T6	1		T14	25997		T15	1
all_values[6]	auto[1]	auto[1]	185	1			T6	2		T15	3		T16	2
all_values[7]	auto[0]	auto[0]	2438898	1			T1	1		T3	1		T4	102
all_values[7]	auto[0]	auto[1]	173	1			T6	3		T15	1		T18	1
all_values[7]	auto[1]	auto[0]	7807	1			T14	1		T15	1		T16	5
all_values[7]	auto[1]	auto[1]	206	1			T6	2		T18	2		T19	9