Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33693	1			T1	2		T3	2		T4	25
auto[SpiFlashAddrCfg]	7640	1			T3	8		T4	16		T6	19
auto[SpiFlashAddr3b]	8983	1			T3	4		T4	12		T6	43
auto[SpiFlashAddr4b]	7541	1			T4	7		T6	33		T7	35

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33031

1

T1

2

T3

14

T4

29

auto[1]

24826

1

T4

31

T6

308

T7

61

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31065

1

T1

2

T3

6

T4

29

auto[1]

26792

1

T3

8

T4

31

T6

134

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38356	1			T1	2		T3	2		T4	29
values[1]	1121	1			T4	6		T6	5		T7	7
values[2]	1438	1			T4	3		T7	9		T8	7
values[3]	1405	1			T6	13		T7	6		T8	4
values[4]	1452	1			T6	11		T7	8		T8	5
values[5]	1405	1			T4	1		T6	7		T7	6
values[6]	1431	1			T3	8		T6	4		T7	5
values[7]	1450	1			T6	3		T7	3		T8	2
values[8]	9799	1			T3	4		T4	21		T6	47

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30148

1

T1

2

T3

14

T4

60

auto[1]

27709

1

T6

406

T9

190

T11

184

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54656

1

T1

2

T3

14

T4

50

write

3201

1

T4

10

T6

11

T7

18

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18977

1

T3

8

T4

28

T6

81

valids[0x1]

38880

1

T1

2

T3

6

T4

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1494	1			T1	2		T4	1		T6	10
internal_process_ops[0x5a]	1514	1			T3	4		T4	1		T6	9
internal_process_ops[0x05]	20281	1			T4	1		T6	236		T7	16
internal_process_ops[0x35]	1553	1			T3	8		T4	1		T6	8
internal_process_ops[0x15]	1472	1			T3	2		T4	3		T6	5
internal_process_ops[0x03]	1041	1			T4	3		T6	1		T7	6
internal_process_ops[0x0b]	1103	1			T4	2		T6	5		T7	6
internal_process_ops[0x3b]	1023	1			T4	2		T6	5		T7	11
internal_process_ops[0x6b]	1070	1			T4	4		T6	1		T7	5
internal_process_ops[0xbb]	1077	1			T4	2		T6	3		T7	6
internal_process_ops[0xeb]	1072	1			T4	1		T6	3		T7	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56301

1

T1

2

T3

14

T4

57

auto[1]

1556

1

T4

3

T6

5

T7

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55586

1

T1

2

T3

14

T4

52

auto[1]

2271

1

T4

8

T6

11

T7

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9778

1

T1

2

T3

2

T4

14

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6066

1

T4

7

T7

11

T8

48

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2082

1

T3

8

T4

4

T7

13

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1939

1

T4

9

T7

14

T8

9

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2418

1

T3

4

T4

3

T7

20

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2279

1

T4

6

T7

16

T8

13

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2109

1

T4

3

T7

14

T8

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1824

1

T4

4

T7

16

T8

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

133

1

T7

5

T44

2

T156

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

73

1

T7

2

T8

1

T14

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

76

1

T4

4

T8

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

88

1

T41

1

T43

3

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

142

1

T4

2

T8

1

T14

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T7

4

T36

1

T43

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T37

1

T157

3

T17

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

127

1

T4

1

T41

1

T43

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

130

1

T4

1

T8

1

T43

7

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T4

2

T7

1

T14

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T14

1

T36

1

T41

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

120

1

T7

1

T8

5

T14

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

138

1

T7

2

T14

1

T41

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T8

1

T14

1

T158

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

77

1

T8

2

T14

1

T44

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T7

3

T40

4

T42

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10277

1

T6

50

T9

114

T11

64

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6810

1

T6

255

T9

8

T11

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1425

1

T6

9

T9

18

T11

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1397

1

T6

10

T9

11

T11

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1840

1

T6

21

T9

7

T11

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1669

1

T6

18

T9

8

T11

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1420

1

T6

14

T9

6

T11

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1323

1

T6

18

T9

4

T11

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

104

1

T6

1

T26

3

T73

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T6

2

T11

2

T14

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

104

1

T6

2

T9

1

T11

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

81

1

T6

1

T14

1

T72

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

91

1

T14

1

T72

2

T73

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

89

1

T11

1

T73

2

T74

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

101

1

T11

1

T72

1

T74

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T14

1

T26

1

T73

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T6

1

T9

3

T11

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

95

1

T9

3

T11

2

T26

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

79

1

T6

1

T9

2

T28

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T6

2

T72

2

T73

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T9

1

T73

3

T74

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

131

1

T9

2

T11

1

T26

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

112

1

T6

1

T9

2

T11

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

105

1

T11

1

T72

1

T73

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3844	1			T4	11		T7	31		T8	16
auto[0]	values[0]	valids[0x1]	15009	1			T1	2		T3	2		T4	18
auto[0]	values[1]	valids[0x1]	600	1			T4	6		T7	7		T8	1
auto[0]	values[2]	valids[0x0]	568	1			T4	3		T7	9		T8	6
auto[0]	values[2]	valids[0x1]	288	1			T8	1		T14	8		T159	1
auto[0]	values[3]	valids[0x0]	553	1			T7	1		T8	2		T40	3
auto[0]	values[3]	valids[0x1]	302	1			T7	5		T8	2		T14	1
auto[0]	values[4]	valids[0x0]	552	1			T7	5		T8	2		T14	6
auto[0]	values[4]	valids[0x1]	293	1			T7	3		T8	3		T14	1
auto[0]	values[5]	valids[0x0]	562	1			T4	1		T7	6		T14	4
auto[0]	values[5]	valids[0x1]	292	1			T8	3		T14	2		T40	1
auto[0]	values[6]	valids[0x0]	526	1			T3	8		T7	4		T8	1
auto[0]	values[6]	valids[0x1]	304	1			T7	1		T8	2		T14	1
auto[0]	values[7]	valids[0x0]	552	1			T7	3		T8	2		T14	3
auto[0]	values[7]	valids[0x1]	279	1			T40	1		T159	2		T43	3
auto[0]	values[8]	valids[0x0]	3582	1			T4	13		T7	37		T8	22
auto[0]	values[8]	valids[0x1]	2042	1			T3	4		T4	8		T7	10
auto[1]	values[0]	valids[0x0]	3676	1			T6	35		T9	26		T11	31
auto[1]	values[0]	valids[0x1]	15827	1			T6	281		T9	110		T11	68
auto[1]	values[1]	valids[0x1]	521	1			T6	5		T9	4		T11	8
auto[1]	values[2]	valids[0x0]	344	1			T9	1		T11	1		T72	5
auto[1]	values[2]	valids[0x1]	238	1			T9	5		T11	2		T26	1
auto[1]	values[3]	valids[0x0]	338	1			T6	5		T9	3		T11	4
auto[1]	values[3]	valids[0x1]	212	1			T6	8		T9	2		T11	2
auto[1]	values[4]	valids[0x0]	388	1			T6	6		T9	7		T11	1
auto[1]	values[4]	valids[0x1]	219	1			T6	5		T11	2		T26	1
auto[1]	values[5]	valids[0x0]	339	1			T6	3		T11	3		T28	4
auto[1]	values[5]	valids[0x1]	212	1			T6	4		T9	2		T11	1
auto[1]	values[6]	valids[0x0]	392	1			T6	2		T9	3		T11	2
auto[1]	values[6]	valids[0x1]	209	1			T6	2		T11	4		T72	5
auto[1]	values[7]	valids[0x0]	336	1			T6	1		T9	2		T11	10
auto[1]	values[7]	valids[0x1]	283	1			T6	2		T14	4		T26	1
auto[1]	values[8]	valids[0x0]	2425	1			T6	29		T9	15		T11	30
auto[1]	values[8]	valids[0x1]	1750	1			T6	18		T9	10		T11	15