Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3401149

1

T1

2

T3

29652

T4

1039

auto[1]

27776

1

T4

259

T6

226

T7

12

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000947

1

T1

2

T3

28964

T4

141

auto[1]

2427978

1

T3

688

T4

1157

T6

6706

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	640441	1			T1	1		T3	7867		T4	310
auto[524288:1048575]	407357	1			T3	4627		T4	6		T6	1478
auto[1048576:1572863]	399509	1			T3	7885		T4	534		T6	7
auto[1572864:2097151]	411028	1			T3	2233		T4	15		T5	8009
auto[2097152:2621439]	380788	1			T3	2		T4	2		T7	1
auto[2621440:3145727]	384971	1			T3	3868		T4	2		T6	318
auto[3145728:3670015]	381642	1			T3	1693		T4	142		T5	2
auto[3670016:4194303]	423189	1			T1	1		T3	1477		T4	287

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2460328

1

T1

2

T3

788

T4

1293

auto[1]

968597

1

T3

28864

T4

5

T5

16006

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3031567

1

T1

2

T3

29652

T4

1287

auto[1]

397358

1

T4

11

T6

1860

T7

6

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	211676	1			T1	1		T3	7181		T4	38
auto[0]	auto[0]	auto[0:524287]	auto[1]	367678	1			T3	686		T4	256		T6	260
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	123753	1			T3	4627		T4	4		T6	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	234661	1			T6	4		T7	1776		T8	1643
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	87045	1			T3	7885		T4	16		T6	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	253453	1			T4	298		T8	256		T11	13
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	104414	1			T3	2232		T4	6		T5	8009
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	263939	1			T3	1		T6	1581		T7	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	112939	1			T3	2		T4	2		T7	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	216001	1			T8	1		T11	2		T14	1589
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	98078	1			T3	3868		T7	6		T8	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	224374	1			T7	1		T8	2617		T9	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	137487	1			T3	1692		T4	7		T5	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	199071	1			T3	1		T4	128		T6	177
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	114533	1			T1	1		T3	1477		T4	17
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	259482	1			T4	261		T6	2751		T7	2385
auto[0]	auto[1]	auto[0:524287]	auto[0]	692	1			T11	6		T14	1		T36	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	56395	1			T7	5		T11	3		T36	2940
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1672	1			T4	2		T6	7		T8	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	44920	1			T6	1453		T8	1		T11	319
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	554	1			T6	1		T11	1		T14	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53649	1			T6	5		T9	1944		T11	1210
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	523	1			T4	4		T6	1		T8	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	39673	1			T11	1		T36	88		T158	1119
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	779	1			T11	1		T14	1		T28	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	47759	1			T14	1		T28	204		T44	1476
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	562	1			T6	7		T7	1		T9	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	58608	1			T6	258		T9	3030		T14	2860
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1853	1			T6	1		T9	1		T14	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40386	1			T6	1		T14	1		T193	771
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	586	1			T6	1		T9	1		T14	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	43954	1			T6	1		T9	128		T14	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	499	1			T4	16		T6	2		T7	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2927	1			T6	62		T36	19		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	281	1			T7	1		T8	2		T11	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1567	1			T8	4		T11	1		T44	29
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	413	1			T4	6		T11	5		T14	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3039	1			T4	214		T11	3		T14	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	329	1			T6	1		T7	5		T8	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1756	1			T6	9		T7	2		T8	27
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	414	1			T8	1		T11	2		T14	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2486	1			T8	10		T11	3		T14	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	419	1			T4	2		T7	1		T8	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2423	1			T8	2		T40	329		T44	97
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	397	1			T4	7		T6	2		T7	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1960	1			T6	26		T36	5		T44	35
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	436	1			T4	9		T8	2		T14	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3637	1			T8	15		T14	1		T40	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	91	1			T11	3		T36	1		T41	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	483	1			T11	2		T36	7		T43	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	66	1			T6	2		T8	1		T43	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	437	1			T6	9		T8	5		T43	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	95	1			T14	1		T43	1		T72	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	1261	1			T14	1		T43	2		T72	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	71	1			T4	5		T11	1		T17	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	323	1			T11	1		T17	1		T187	186
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	58	1			T14	1		T44	3		T72	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	352	1			T14	2		T44	65		T72	31
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	89	1			T6	2		T43	2		T72	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	418	1			T6	51		T43	5		T72	48
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	73	1			T6	1		T193	3		T205	8
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	415	1			T6	43		T193	67		T17	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T6	1		T14	1		T73	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	491	1			T6	15		T14	5		T73	20

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2043455	1			T1	2		T3	788		T4	1033
auto[0]	auto[0]	auto[1]	965129	1			T3	28864		T5	16006		T6	4
auto[0]	auto[1]	auto[0]	389771	1			T4	6		T6	1735		T7	6
auto[0]	auto[1]	auto[1]	2794	1			T6	1		T36	1		T72	4
auto[1]	auto[0]	auto[0]	22430	1			T4	250		T6	102		T7	11
auto[1]	auto[0]	auto[1]	553	1			T4	4		T7	1		T8	2
auto[1]	auto[1]	auto[0]	4672	1			T4	4		T6	123		T8	6
auto[1]	auto[1]	auto[1]	121	1			T4	1		T6	1		T11	1