Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2447084	1			T1	1		T3	1		T4	102
all_pins[1]	2447084	1			T1	1		T3	1		T4	102
all_pins[2]	2447084	1			T1	1		T3	1		T4	102
all_pins[3]	2447084	1			T1	1		T3	1		T4	102
all_pins[4]	2447084	1			T1	1		T3	1		T4	102
all_pins[5]	2447084	1			T1	1		T3	1		T4	102
all_pins[6]	2447084	1			T1	1		T3	1		T4	102
all_pins[7]	2447084	1			T1	1		T3	1		T4	102

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19541356	1			T1	8		T3	8		T4	816
values[0x1]	35316	1			T6	16		T14	26080		T15	6
transitions[0x0=>0x1]	34823	1			T6	11		T14	26072		T15	4
transitions[0x1=>0x0]	34835	1			T6	11		T14	26072		T15	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2446881	1			T1	1		T3	1		T4	102
all_pins[0]	values[0x1]	203	1			T6	3		T16	2		T18	3
all_pins[0]	transitions[0x0=>0x1]	148	1			T6	1		T18	2		T19	1
all_pins[0]	transitions[0x1=>0x0]	260	1			T6	1		T14	101		T20	1
all_pins[1]	values[0x0]	2446769	1			T1	1		T3	1		T4	102
all_pins[1]	values[0x1]	315	1			T6	3		T14	101		T16	2
all_pins[1]	transitions[0x0=>0x1]	262	1			T6	3		T14	93		T18	1
all_pins[1]	transitions[0x1=>0x0]	142	1			T6	1		T18	5		T19	2
all_pins[2]	values[0x0]	2446889	1			T1	1		T3	1		T4	102
all_pins[2]	values[0x1]	195	1			T6	1		T14	8		T16	2
all_pins[2]	transitions[0x0=>0x1]	157	1			T6	1		T14	8		T16	2
all_pins[2]	transitions[0x1=>0x0]	143	1			T6	3		T15	1		T16	1
all_pins[3]	values[0x0]	2446903	1			T1	1		T3	1		T4	102
all_pins[3]	values[0x1]	181	1			T6	3		T15	1		T16	1
all_pins[3]	transitions[0x0=>0x1]	151	1			T6	3		T15	1		T18	2
all_pins[3]	transitions[0x1=>0x0]	144	1			T6	1		T14	2		T18	2
all_pins[4]	values[0x0]	2446910	1			T1	1		T3	1		T4	102
all_pins[4]	values[0x1]	174	1			T6	1		T14	2		T16	1
all_pins[4]	transitions[0x0=>0x1]	137	1			T6	1		T14	2		T16	1
all_pins[4]	transitions[0x1=>0x0]	385	1			T6	1		T14	1		T15	2
all_pins[5]	values[0x0]	2446662	1			T1	1		T3	1		T4	102
all_pins[5]	values[0x1]	422	1			T6	1		T14	1		T15	2
all_pins[5]	transitions[0x0=>0x1]	244	1			T14	1		T16	1		T18	3
all_pins[5]	transitions[0x1=>0x0]	33442	1			T6	1		T14	25968		T15	1
all_pins[6]	values[0x0]	2413464	1			T1	1		T3	1		T4	102
all_pins[6]	values[0x1]	33620	1			T6	2		T14	25968		T15	3
all_pins[6]	transitions[0x0=>0x1]	33577	1			T14	25968		T15	3		T16	2
all_pins[6]	transitions[0x1=>0x0]	163	1			T19	9		T20	1		T21	5
all_pins[7]	values[0x0]	2446878	1			T1	1		T3	1		T4	102
all_pins[7]	values[0x1]	206	1			T6	2		T18	2		T19	9
all_pins[7]	transitions[0x0=>0x1]	147	1			T6	2		T18	2		T19	8
all_pins[7]	transitions[0x1=>0x0]	156	1			T6	3		T16	2		T18	3