Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17268

1

T1

2

T3

14

T4

29

auto[1]

12880

1

T4

31

T7

61

T8

82

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3887	1			T7	20		T36	20		T110	16
values[1]	3857	1			T7	41		T36	20		T44	184
values[2]	3389	1			T4	20		T45	4		T40	20
values[3]	3760	1			T1	2		T8	76		T14	22
values[4]	3641	1			T3	14		T7	22		T8	53
values[5]	3837	1			T8	23		T14	50		T40	20
values[6]	3943	1			T4	20		T7	67		T8	21
values[7]	3834	1			T4	20		T7	22		T14	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3608	1			T1	2		T8	108		T14	22
values[1]	3831	1			T4	20		T7	41		T36	74
values[2]	4037	1			T40	20		T43	24		T44	40
values[3]	3792	1			T7	21		T8	21		T14	23
values[4]	4223	1			T3	14		T45	4		T14	25
values[5]	4445	1			T4	20		T7	62		T8	23
values[6]	3200	1			T7	48		T8	21		T24	16
values[7]	3012	1			T4	20		T14	29		T36	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	266	1			T159	8		T41	14		T38	8
auto[0]	values[0]	values[1]	286	1			T15	12		T223	12		T221	14
auto[0]	values[0]	values[2]	252	1			T15	11		T186	8		T17	13
auto[0]	values[0]	values[3]	253	1			T205	8		T46	12		T224	4
auto[0]	values[0]	values[4]	223	1			T157	4		T195	11		T66	5
auto[0]	values[0]	values[5]	328	1			T7	10		T44	17		T225	4
auto[0]	values[0]	values[6]	240	1			T110	16		T226	8		T203	66
auto[0]	values[0]	values[7]	258	1			T36	12		T43	15		T227	6
auto[0]	values[1]	values[0]	204	1			T36	9		T203	15		T185	5
auto[0]	values[1]	values[1]	275	1			T7	24		T44	7		T15	11
auto[0]	values[1]	values[2]	521	1			T44	26		T190	20		T184	15
auto[0]	values[1]	values[3]	270	1			T37	12		T172	11		T195	25
auto[0]	values[1]	values[4]	409	1			T37	14		T184	75		T185	9
auto[0]	values[1]	values[5]	172	1			T44	16		T131	8		T228	14
auto[0]	values[1]	values[6]	151	1			T212	12		T30	12		T132	10
auto[0]	values[1]	values[7]	246	1			T44	60		T172	9		T229	6
auto[0]	values[2]	values[0]	242	1			T230	6		T46	45		T195	19
auto[0]	values[2]	values[1]	242	1			T231	4		T194	6		T46	16
auto[0]	values[2]	values[2]	221	1			T40	12		T181	11		T186	25
auto[0]	values[2]	values[3]	428	1			T208	12		T157	67		T172	30
auto[0]	values[2]	values[4]	239	1			T45	4		T41	13		T43	15
auto[0]	values[2]	values[5]	369	1			T4	9		T37	16		T157	37
auto[0]	values[2]	values[6]	121	1			T232	17		T178	10		T233	16
auto[0]	values[2]	values[7]	255	1			T158	12		T157	15		T203	21
auto[0]	values[3]	values[0]	204	1			T1	2		T8	41		T14	14
auto[0]	values[3]	values[1]	231	1			T172	15		T18	19		T234	6
auto[0]	values[3]	values[2]	396	1			T172	16		T132	14		T219	7
auto[0]	values[3]	values[3]	301	1			T8	12		T43	9		T44	14
auto[0]	values[3]	values[4]	459	1			T15	12		T235	174		T236	10
auto[0]	values[3]	values[5]	277	1			T44	11		T182	7		T205	15
auto[0]	values[3]	values[6]	309	1			T43	12		T192	12		T31	18
auto[0]	values[3]	values[7]	190	1			T182	15		T15	13		T17	16
auto[0]	values[4]	values[0]	334	1			T8	8		T15	10		T237	4
auto[0]	values[4]	values[1]	225	1			T36	14		T43	12		T238	2
auto[0]	values[4]	values[2]	304	1			T43	11		T37	12		T46	13
auto[0]	values[4]	values[3]	188	1			T17	29		T202	6		T30	11
auto[0]	values[4]	values[4]	313	1			T3	14		T14	13		T44	5
auto[0]	values[4]	values[5]	223	1			T7	16		T40	11		T17	6
auto[0]	values[4]	values[6]	196	1			T88	8		T17	11		T195	7
auto[0]	values[4]	values[7]	238	1			T157	11		T132	10		T219	10
auto[0]	values[5]	values[0]	247	1			T156	60		T84	10		T239	18
auto[0]	values[5]	values[1]	339	1			T37	8		T38	10		T205	10
auto[0]	values[5]	values[2]	236	1			T205	9		T18	12		T201	14
auto[0]	values[5]	values[3]	216	1			T181	16		T172	18		T46	8
auto[0]	values[5]	values[4]	162	1			T240	2		T172	13		T205	12
auto[0]	values[5]	values[5]	566	1			T8	14		T40	11		T44	62
auto[0]	values[5]	values[6]	188	1			T14	10		T212	43		T185	10
auto[0]	values[5]	values[7]	254	1			T14	16		T15	30		T157	7
auto[0]	values[6]	values[0]	349	1			T158	14		T43	7		T182	16
auto[0]	values[6]	values[1]	285	1			T157	22		T217	10		T179	11
auto[0]	values[6]	values[2]	257	1			T157	12		T83	10		T18	10
auto[0]	values[6]	values[3]	196	1			T7	17		T41	15		T44	59
auto[0]	values[6]	values[4]	250	1			T181	21		T54	4		T195	11
auto[0]	values[6]	values[5]	300	1			T7	11		T14	15		T43	15
auto[0]	values[6]	values[6]	348	1			T7	17		T8	16		T24	16
auto[0]	values[6]	values[7]	310	1			T4	8		T40	9		T157	11
auto[0]	values[7]	values[0]	265	1			T89	8		T17	9		T241	18
auto[0]	values[7]	values[1]	245	1			T4	12		T36	12		T242	18
auto[0]	values[7]	values[2]	253	1			T181	14		T243	4		T207	22
auto[0]	values[7]	values[3]	239	1			T14	9		T244	6		T17	10
auto[0]	values[7]	values[4]	334	1			T44	17		T15	13		T30	9
auto[0]	values[7]	values[5]	212	1			T37	13		T245	8		T22	13
auto[0]	values[7]	values[6]	236	1			T7	16		T44	11		T246	14
auto[0]	values[7]	values[7]	122	1			T181	18		T186	6		T38	16
auto[1]	values[0]	values[0]	121	1			T159	12		T41	6		T38	12
auto[1]	values[0]	values[1]	372	1			T15	8		T221	9		T46	22
auto[1]	values[0]	values[2]	141	1			T15	14		T186	12		T17	11
auto[1]	values[0]	values[3]	256	1			T205	12		T46	12		T66	12
auto[1]	values[0]	values[4]	172	1			T157	16		T195	9		T66	17
auto[1]	values[0]	values[5]	345	1			T7	10		T44	6		T46	6
auto[1]	values[0]	values[6]	232	1			T203	128		T66	7		T199	7
auto[1]	values[0]	values[7]	142	1			T36	8		T43	5		T247	6
auto[1]	values[1]	values[0]	224	1			T36	11		T203	9		T185	61
auto[1]	values[1]	values[1]	212	1			T7	17		T44	52		T15	9
auto[1]	values[1]	values[2]	265	1			T44	14		T184	8		T192	33
auto[1]	values[1]	values[3]	120	1			T37	9		T172	9		T195	9
auto[1]	values[1]	values[4]	404	1			T37	6		T184	8		T185	97
auto[1]	values[1]	values[5]	119	1			T44	4		T66	31		T220	10
auto[1]	values[1]	values[6]	104	1			T212	20		T30	12		T132	10
auto[1]	values[1]	values[7]	161	1			T44	5		T172	11		T185	10
auto[1]	values[2]	values[0]	75	1			T46	6		T195	14		T173	9
auto[1]	values[2]	values[1]	134	1			T46	7		T132	10		T199	15
auto[1]	values[2]	values[2]	229	1			T40	8		T181	9		T186	15
auto[1]	values[2]	values[3]	324	1			T157	13		T172	30		T46	23
auto[1]	values[2]	values[4]	148	1			T41	7		T43	8		T248	8
auto[1]	values[2]	values[5]	174	1			T4	11		T37	4		T157	5
auto[1]	values[2]	values[6]	73	1			T198	10		T232	7		T178	10
auto[1]	values[2]	values[7]	115	1			T158	8		T157	10		T203	9
auto[1]	values[3]	values[0]	135	1			T8	14		T14	8		T182	5
auto[1]	values[3]	values[1]	100	1			T172	5		T18	3		T84	14
auto[1]	values[3]	values[2]	214	1			T172	4		T132	6		T219	17
auto[1]	values[3]	values[3]	240	1			T8	9		T43	22		T44	55
auto[1]	values[3]	values[4]	196	1			T15	8		T46	8		T212	13
auto[1]	values[3]	values[5]	207	1			T44	40		T182	13		T249	18
auto[1]	values[3]	values[6]	168	1			T43	8		T192	21		T31	5
auto[1]	values[3]	values[7]	133	1			T182	5		T15	8		T17	4
auto[1]	values[4]	values[0]	308	1			T8	45		T15	11		T250	2
auto[1]	values[4]	values[1]	177	1			T36	20		T43	11		T173	13
auto[1]	values[4]	values[2]	160	1			T43	13		T37	8		T46	12
auto[1]	values[4]	values[3]	139	1			T17	17		T30	9		T251	11
auto[1]	values[4]	values[4]	217	1			T14	12		T44	35		T15	16
auto[1]	values[4]	values[5]	178	1			T7	6		T40	9		T17	14
auto[1]	values[4]	values[6]	279	1			T17	9		T195	13		T252	9
auto[1]	values[4]	values[7]	162	1			T157	35		T132	10		T219	10
auto[1]	values[5]	values[0]	121	1			T84	10		T253	10		T254	13
auto[1]	values[5]	values[1]	216	1			T37	14		T38	25		T205	10
auto[1]	values[5]	values[2]	194	1			T205	11		T18	9		T201	6
auto[1]	values[5]	values[3]	236	1			T181	4		T172	2		T46	12
auto[1]	values[5]	values[4]	207	1			T172	7		T205	8		T66	19
auto[1]	values[5]	values[5]	321	1			T8	9		T40	9		T44	11
auto[1]	values[5]	values[6]	148	1			T14	11		T212	11		T209	20
auto[1]	values[5]	values[7]	186	1			T14	13		T15	10		T157	13
auto[1]	values[6]	values[0]	167	1			T158	6		T42	8		T43	19
auto[1]	values[6]	values[1]	231	1			T157	22		T179	9		T180	7
auto[1]	values[6]	values[2]	237	1			T157	8		T18	17		T247	13
auto[1]	values[6]	values[3]	87	1			T7	4		T41	5		T44	11
auto[1]	values[6]	values[4]	200	1			T181	27		T195	9		T173	11
auto[1]	values[6]	values[5]	348	1			T7	9		T14	10		T43	5
auto[1]	values[6]	values[6]	262	1			T7	9		T8	5		T41	15
auto[1]	values[6]	values[7]	116	1			T4	12		T40	11		T255	4
auto[1]	values[7]	values[0]	346	1			T130	18		T17	11		T173	13
auto[1]	values[7]	values[1]	261	1			T4	8		T36	28		T205	9
auto[1]	values[7]	values[2]	157	1			T181	6		T256	18		T177	7
auto[1]	values[7]	values[3]	299	1			T14	14		T17	12		T257	16
auto[1]	values[7]	values[4]	290	1			T44	111		T15	7		T30	11
auto[1]	values[7]	values[5]	306	1			T37	9		T22	16		T195	14
auto[1]	values[7]	values[6]	145	1			T7	6		T44	9		T195	41
auto[1]	values[7]	values[7]	124	1			T181	3		T186	14		T38	4